; -------------------------------------------------------------------------------- ; @Title: J7VCL On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2024-12-17 KRZ ; @Manufacturer: TI - Texas Instruments ; @Doc: Generated (TRACE32, build: 175345.), based on: J7200_DRA821.xml (CCS 20.0.0) ; @Core: Cortex-A72, Cortex-R5F, Cortex-M3 ; @Chip: DRA821 ; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perj7vcl.per 18779 2024-12-17 13:47:43Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="CORTEXM3") tree.close "Core Registers (Cortex-M3)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 11. group 0x10--0x1b line.long 0x00 "SYST_CSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" ;group 0x14++0x03 line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" ;group 0x18++0x03 line.long 0x08 "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value" rgroup 0x1c++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" textline " " rgroup 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M" textline " " abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M3" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group 0xd04--0xd17 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set" bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending" hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field" ;group 0xd08++0x03 line.long 0x04 "VTOR,Vector Table Offset Register" bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM" hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field" ;group 0xd0c++0x03 line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset" ;group 0xd10++0x03 line.long 0x0c "SCR,System Control Register" bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" ;group 0xd14++0x03 line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" group 0xd18--0xd23 line.long 0x00 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x04 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x08 "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" group 0xd24++0x3 line.long 0x00 "SHCSR,System Handler Control and State Register" bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled" bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled" bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced" bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced" bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced" textline " " bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active" bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active" textline " " bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" textline " " bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group 0xd28--0xd3b line.byte 0x0 "MMFSR,Memory Manage Fault Status Register" bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error" bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error" textline " " bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error" bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error" ;group 0xd29++0x00 line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid" bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error" bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error" textline " " bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error" bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error" bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error" ;group 0xd2a++0x01 line.word 0x02 "USAFAULT,Usage Fault Status Register" bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error" bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error" bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error" textline " " bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error" bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error" ;group 0xd2c++0x03 line.long 0x04 "HFSR,Hard Fault Status Register" bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error" bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error" bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error" ;group 0xd30++0x03 line.long 0x08 "DFSR,Debug Fault Status Register" bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted" bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched" textline " " bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested" ;group 0xd34++0x03 line.long 0xc "MMFAR,Memory Manage Fault Address Register" ;group 0xd38++0x03 line.long 0x10 "BFAR,Bus Fault Address Register" wgroup 0xf00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end tree "CoreSight Identification Registers" width 6. rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000) group 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" textline " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001) group 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled" bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" textline " " bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step" bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" textline " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0) group 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" textline " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001) group 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step" bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" textline " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif wgroup 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..." group 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" textline " " bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" textline " " bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group 0x00--0x27 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" ;group 0x04++0x03 line.long 0x04 "FP_REMAP,Flash Patch Remap Register" hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field" ;group 0x08++0x03 line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" tree "Coresight Management Registers" rgroup 0xfd0--0xfff line.long 0x00 "PID4,Peripheral ID4" line.long 0x04 "PID5,Peripheral ID5" line.long 0x08 "PID6,Peripheral ID6" line.long 0x0c "PID7,Peripheral ID7" line.long 0x10 "PID0,Peripheral ID0" line.long 0x14 "PID1,Peripheral ID1" line.long 0x18 "PID2,Peripheral ID2" line.long 0x1c "PID3,Peripheral ID3" line.long 0x20 "CID0,Component ID0" line.long 0x24 "CID1,Component ID1" line.long 0x28 "CID2,Component ID2" line.long 0x2c "CID3,Component ID3" tree.end else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group 0x00--0x1B line.long 0x00 "DWT_CTRL,DWT Control Register" bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled" bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled" bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled" bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28" bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10" bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled" ;group 0x04++0x03 line.long 0x04 "DWT_CYCCNT,Cycle Count register" ;group 0x08++0x03 line.long 0x08 "DWT_CPICNT,DWT CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" ;group 0x0c++0x03 line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" ;group 0x10++0x03 line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" ;group 0x14++0x03 line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" ;group 0x18++0x03 line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" group.long 0x24++0x03 line.long 0x00 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x03 line.long 0x00 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x44++0x03 line.long 0x00 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." endif if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00) group.long 0x38++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." else group.long 0x38++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." endif if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00) group.long 0x48++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." else group.long 0x48++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." endif if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00) group.long 0x58++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." else group.long 0x58++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." endif tree "Coresight Management Registers" rgroup 0xfd0--0xfff line.long 0x00 "PID4,Peripheral ID4" line.long 0x04 "PID5,Peripheral ID5" line.long 0x08 "PID6,Peripheral ID6" line.long 0x0c "PID7,Peripheral ID7" line.long 0x10 "PID0,Peripheral ID1" line.long 0x14 "PID1,Peripheral ID2" line.long 0x18 "PID2,Peripheral ID3" line.long 0x1c "PID3,Peripheral ID4" line.long 0x20 "CID0,Component ID0" line.long 0x24 "CID1,Component ID1" line.long 0x28 "CID2,Component ID2" line.long 0x2c "CID3,Component ID3" tree.end else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXR5F") tree "Core Registers (Cortex-R5F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x00++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup.long c15:0x500++0x00 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system" textline " " hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..." bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c15:0x020++0x00 line.long 0x00 "ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x120++0x00 line.long 0x00 "ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x220++0x00 line.long 0x00 "ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x320++0x00 line.long 0x00 "ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x420++0x00 line.long 0x00 "ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup.long c15:0x210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c15:0x310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x02f++0x00 line.long 0x00 "BO1R,Build Options 1 Register" hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM" bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented" textline " " bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented" group.long c15:0x12f++0x00 line.long 0x00 "BO2R,Build Options 2 Register" bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2" bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included" textline " " bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No" bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No" textline " " bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection" bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..." textline " " bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No" bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No" textline " " bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions" bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No" textline " " bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No" bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No" textline " " bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes" bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No" textline " " bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC" bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..." textline " " bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No" bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes" textline " " bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes" bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes" textline " " bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes" group.long c15:0x72f++0x00 line.long 0x00 "POR,Pin Options Register" bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High" bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High" textline " " bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High" bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High" textline " " bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x101++0x00 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..." textline " " bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable" bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable" bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable" textline " " group.long c15:0x0f++0x00 line.long 0x00 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x000b++0x00 line.long 0x00 "SPCR,Slave Port Control Register" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x05++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x15++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x06++0x00 line.long 0x00 "DFAR,Data Fault Address Register" textline " " group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group.long c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group.long c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group.long c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group.long c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" width 0x08 tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RBAR12,Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RSER12,Region Size and Enable Register 12" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RACR12,Region Access Control Register 12" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RBAR13,Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RSER13,Region Size and Enable Register 13" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RACR13,Region Access Control Register 13" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RBAR14,Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RSER14,Region Size and Enable Register 14" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RACR14,Region Access Control Register 14" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RBAR15,Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RSER15,Region Size and Enable Register 15" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RACR15,Region Access Control Register 15" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" textline " " group.long c15:0x10f++0x00 line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x20f++0x00 line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x30f++0x00 line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000++0x00 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" group.long c15:0x5f++0x00 line.long 0x00 "IADCR,Invalidate All Data Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" group.long c15:0xef++0x00 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes" textline " " bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree "Validation Registers" group.long c15:0x01f++0x00 line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x11f++0x00 line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x21f++0x00 line.long 0x00 "RESR,nVAL Reset Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x31f++0x00 line.long 0x00 "RESR,VAL Debug Request Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" group.long c15:0x41f++0x00 line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x51f++0x00 line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x61f++0x00 line.long 0x00 "RECR,nVAL Reset Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x71f++0x00 line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" tree.end tree.end width 11. width 18. tree "Debug Registers" tree "Processor Identifier Registers" rgroup.long c14:832.++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup.long c14:833.++0x00 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup.long c14:834.++0x00 line.long 0x00 "TCMTR,TCM Type Register" group.long c14:835.++0x00 line.long 0x00 "AMIDR,Alias of MIDR" rgroup.long c14:836.++0x00 line.long 0x00 "MPUTR,MPU Type Register" rgroup.long c14:837.++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" group.long c14:838.++0x00 line.long 0x00 "AMIDR0,Alias of MIDR" group.long c14:839.++0x00 line.long 0x00 "AMIDR1,Alias of MIDR" rgroup.long c14:840.++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c14:841.++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c14:842.++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c14:843.++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c14:844.++0x00 line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c14:845.++0x00 line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c14:846.++0x00 line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c14:847.++0x00 line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c14:848.++0x00 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:849.++0x00 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c14:850.++0x00 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:851.++0x00 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c14:852.++0x00 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c14:853.++0x00 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 15. tree "Coresight Management Registers" group.long c14:960.++0x00 line.long 0x00 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration" group.long c14:1000.++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set" group.long c14:1001.++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes" textline " " bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked" rgroup.long c14:1006.++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register" bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled" rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" tree.end textline " " width 12. rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" textline " " bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High" textline " " hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" group.long c14:34.++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" textline " " bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled" hgroup.long c14:32.++0x0 hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register" in group.long c14:35.++0x00 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group.long c14:10.++0x0 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes" bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes" textline " " bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" textline " " bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" textline " " rgroup.long c14:193.++0x0 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented" group.long c14:196.++0x0 line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register" bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held" textline " " bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested" bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" tree.end width 7. tree "Breakpoint Registers" group.long c14:64.++0x0 line.long 0x00 "BVR0,Breakpoint Value 0 Register" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group.long c14:80.++0x0 line.long 0x00 "BCR0,Breakpoint Control 0 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:65.++0x0 line.long 0x00 "BVR1,Breakpoint Value 1 Register" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group.long c14:81.++0x0 line.long 0x00 "BCR1,Breakpoint Control 1 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:66.++0x0 line.long 0x00 "BVR2,Breakpoint Value 2 Register" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group.long c14:82.++0x0 line.long 0x00 "BCR2,Breakpoint Control 2 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:67.++0x0 line.long 0x00 "BVR3,Breakpoint Value 3 Register" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group.long c14:83.++0x0 line.long 0x00 "BCR3,Breakpoint Control 3 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:68.++0x0 line.long 0x00 "BVR4,Breakpoint Value 4 Register" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group.long c14:84.++0x0 line.long 0x00 "BCR4,Breakpoint Control 4 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:69.++0x0 line.long 0x00 "BVR5,Breakpoint Value 5 Register" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group.long c14:85.++0x0 line.long 0x00 "BCR5,Breakpoint Control 5 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:70.++0x0 line.long 0x00 "BVR6,Breakpoint Value 6 Register" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group.long c14:86.++0x0 line.long 0x00 "BCR6,Breakpoint Control 6 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:71.++0x0 line.long 0x00 "BVR7,Breakpoint Value 7 Register" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group.long c14:87.++0x0 line.long 0x00 "BCR7,Breakpoint Control 7 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.long c14:96.++0x0 line.long 0x00 "WVR0,Watchpoint Value 0 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:112.++0x0 line.long 0x00 "WCR0,Watchpoint Control 0 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:97.++0x0 line.long 0x00 "WVR1,Watchpoint Value 1 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:113.++0x0 line.long 0x00 "WCR1,Watchpoint Control 1 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:98.++0x0 line.long 0x00 "WVR2,Watchpoint Value 2 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:114.++0x0 line.long 0x00 "WCR2,Watchpoint Control 2 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:99.++0x0 line.long 0x00 "WVR3,Watchpoint Value 3 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:115.++0x0 line.long 0x00 "WCR3,Watchpoint Control 3 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:100.++0x0 line.long 0x00 "WVR4,Watchpoint Value 4 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:116.++0x0 line.long 0x00 "WCR4,Watchpoint Control 4 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:101.++0x0 line.long 0x00 "WVR5,Watchpoint Value 5 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:117.++0x0 line.long 0x00 "WCR5,Watchpoint Control 5 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:102.++0x0 line.long 0x00 "WVR6,Watchpoint Value 6 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:118.++0x0 line.long 0x00 "WCR6,Watchpoint Control 6 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:103.++0x0 line.long 0x00 "WVR7,Watchpoint Value 7 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:119.++0x0 line.long 0x00 "WCR7,Watchpoint Control 7 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:6.++0x0 line.long 0x00 "WFAR ,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction" tree.end width 11. AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXA72") tree "Core Registers (Cortex-A72)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.quad 0x00 "MIDR_EL1,Main ID Register" hexmask.quad.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer code" bitfld.quad 0x00 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.quad.word 0x00 4.--15. 1. "PARTNUM,Primary Part Number" bitfld.quad 0x00 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.quad spr:0x30005++0x00 line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" newline bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.quad 0x00 0.--1. "CPU_ID,CPU ID" "1,2,3,4" rgroup.quad spr:0x30006++0x0 line.quad 0x00 "REVIDR_EL1,Revision ID Register" rgroup.quad spr:0x30014++0x00 line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,ACTLR/AIFSR/ADFSR,?..." newline bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,2 levels,?..." bitfld.quad 0x00 8.--11. "OS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30015++0x00 line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "BPRED,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Not required,?..." bitfld.quad 0x00 24.--27. "L1TSTCLN,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "L1UNI,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "L1HVD,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "L1UNISW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "L1HVDSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1UNIVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HVDVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad spr:0x30016++0x00 line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.quad 0x00 28.--31. "HWACCFLG,Hardware Access Flag Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "WFISTALL,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MEMBARR,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "UNITLB,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "HVDTLB,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "L1HVDRNG,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1HVDBG,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HVDFG,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad spr:0x30017++0x00 line.quad 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3" bitfld.quad 0x00 28.--31. "SUPERSEC,Supersection support" "Supported,?..." bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.quad 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "CMSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "CMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.quad 0x00 "ID_MMFR4_EL1,ID_MMFR4_EL1" bitfld.quad 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." rgroup.quad spr:0x30020++0x00 line.quad 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.quad 0x00 24.--27. "DIVIDE,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "DEBUG,Debug Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "COPROC,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "CMPBRANCH,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BITFIELD,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "BITCOUNT,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "SWAP,Swap Instructions Support" "Not supported,?..." rgroup.quad spr:0x30021++0x00 line.quad 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.quad 0x00 28.--31. "JAZELLE,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "INTERWORK,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "IMMEDIATE,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "IFTHEN,If Then Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "EXTEND,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "EXCEPT_AR,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "EXCEPT,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "ENDIAN,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30022++0x00 line.quad 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2" bitfld.quad 0x00 28.--31. "REVERSAL,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "PSR_AR,PSR Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MULTU,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "MULTS,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "MULT,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "MULTIACCESSINT,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "MEMHINT,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "LOADSTORE,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30023++0x00 line.quad 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3" bitfld.quad 0x00 28.--31. "THUMBEE,Thumb-EE Extensions Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "TRUENOP,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "THUMBCOPY,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TABBRANCH,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SYNCHPRIM,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "SVC,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "SIMD,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SATURATE,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30024++0x00 line.quad 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4" bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "PSR_M,PSR_M Instructions Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "SYNCHPRIM_FRAC,Synchronization Primitive instructions" "Supported,?..." newline bitfld.quad 0x00 16.--19. "BARRIER,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SMC,SMC Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "WRITEBACK,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "WITHSHIFTS,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "UNPRIV,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30025++0x00 line.quad 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5" bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2, SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1, SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." rgroup.quad spr:0x30010++0x00 line.quad 0x00 "ID_PFR0_EL1,Processor Feature Register 0" bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad spr:0x30011++0x00 line.quad 0x00 "ID_PFR1_EL1,Processor Feature Register 1" bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "V,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "S,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,Support for the GIC System register interface" "Not supported,GICv3 supported,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3,EL3 exception handling" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 8.--11. "EL2,EL2 exception handling" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "EL1,EL1 exception handling" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 0.--3. "EL0,EL0 exception handling" "Reserved,Reserved,Implemented,?..." rgroup.quad spr:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,PMUv3,?..." bitfld.quad 0x00 20.--23. "MPROFDBG,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.quad 0x00 16.--19. "MMAPTRC,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "COPTRC,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "MMAPDBG,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "COPSDBG,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "COPDBG,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,PMUv3,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug v8-A,?..." rgroup.quad spr:0x339C6++0x0 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.quad 0x00 30. "CH,Chain" "Not implemented,Implemented" bitfld.quad 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.quad 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.quad 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.quad 0x00 25. "DA,Bus access" "Not implemented,Implemented" newline bitfld.quad 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.quad 0x00 19. "MA,Data memory access" "Not implemented,Implemented" newline bitfld.quad 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.quad 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.quad 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.quad 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.quad 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.quad 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.quad 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.quad 0x00 9. "ET,Exception taken" "Not implemented,Implemented" bitfld.quad 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.quad 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.quad 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.quad 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.quad spr:0x33007++0x00 line.quad 0x00 "DCZID_EL0,Data Cache Zero ID" bitfld.quad 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.quad 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.quad spr:0x30030++0x00 "Media and VFP Feature registers" line.quad 0x00 "MVFR0_EL1,Media and VFP Feature Register 0/EL1" bitfld.quad 0x00 28.--31. "FPROUND,Indicates the rounding modes supported by the floating-point hardware" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "FPSHVEC,Indicates the hardware support for floating-point short vectors" "Not supported,?..." bitfld.quad 0x00 20.--23. "FPSQRT,Indicates the hardware support for floating-point square root operations" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "FPDIVIDE,Indicates the hardware support for floating-point divide operations" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "FPTRAP,Indicates whether the floating-point hardware implementation supports exception trapping" "Not supported,?..." bitfld.quad 0x00 8.--11. "FPDP,Indicates the hardware support for floating-point double-precision operations" "Reserved,Reserved,VFPv3 or greater,?..." newline bitfld.quad 0x00 4.--7. "FPSP,Indicates the hardware support for floating-point single-precision operations" "Reserved,Reserved,VFPv3 or greater,?..." bitfld.quad 0x00 0.--3. "SIMDREG,Indicates support for the Advanced SIMD register bank" "Reserved,Reserved,32x64-bit,?..." rgroup.quad spr:0x30031++0x00 line.quad 0x00 "MVFR1_EL1,Media and VFP Feature Register 1/EL1" bitfld.quad 0x00 28.--31. "SIMDFMAC,Indicates whether Advanced SIMD or floating-point supports fused multiply accumulate operations" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "FPHP,Indicates whether floating-point supports half-precision floating-point conversion operations" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "SIMDHP,Indicates whether Advanced SIMD supports half-precision floating-point conversion operations" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "SIMDSP,Indicates whether Advanced SIMD supports single-precision floating-point operations" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SIMDINT,Indicates whether Advanced SIMD supports integer operations" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "SIMDLS,Indicates whether Advanced SIMD supports load/store instructions" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "FPDNAN,Indicates whether the floating-point hardware implementation supports only the Default NaN mode" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "FPFTZ,Indicates whether the floating-point hardware implementation supports only the Flush-to-Zero mode of operation" "Reserved,Supported,?..." rgroup.quad spr:0x30032++0x00 line.quad 0x00 "MVFR2_EL1,Media and VFP Feature Register 2/EL1" bitfld.quad 0x00 4.--7. "FPMISC,Indicates support for miscellaneous floating-point features. Supported = Selection/Conversion to Integer with Directed Rounding/Round to Integral Floating-point/MaxNum/MinNum" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SIMDMISC,Indicates support for miscellaneous Advanced SIMD features. Supported = Selection/Conversion to Integer with Directed Rounding/Round to Integral Floating-point/MaxNum/MinNum" "Reserved,Reserved,Reserved,Supported,?..." group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Thread Pointer/ID Register" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Thread Pointer/ID Register" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Thread Pointer/ID Register" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Thread Pointer/ID Register" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Thread Pointer/ID Register" tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.quad 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPMRCGEA,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 62. "FPNMRCGEA,Force processor non-memory-system RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 61. "FPDIERCGEA,Force processor Decode and Integer Execute idle RCG enables active" "Not forced,Forced" bitfld.quad 0x00 60. "FPDRCGEA,Force processor Dispatch idle RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/st and DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" newline bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" newline bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "ECDAFEMP,Enable contention detection and fast exclusive monitor path" "Disabled,Enabled" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" newline bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" newline bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 46. "DML1DTLBM,Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss" "No,Yes" newline bitfld.quad 0x00 45. "Dl1DCWT,Disable L1-DCache way tracker" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 43. "DVABHWPREF,Disable the Load/Store hardware prefetcher from using VA to cross page boundaries" "No,Yes" bitfld.quad 0x00 42. "DPREFREQRUT,Disable prefetch requests from ReadUnique transactions" "No,Yes" newline bitfld.quad 0x00 41. "ESHWSHAEP,Enables snoop hazard while waiting for second half of atomic exclusive pair" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 requests,1 request,2 requests,3 requests" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "16 requests,18 requests,20 requests,22 requests" bitfld.quad 0x00 6. "SMPEN,Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the first memory error" group.quad spr:0x34101++0x0 line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.quad 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled" group.quad spr:0x36101++0x0 line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.quad 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled" group.quad spr:0x30102++0x00 line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.quad 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap EL0/EL1,Trap EL0,Trap EL0/EL1,No trap" group.quad spr:0x36110++0x0 line.quad 0x00 "SCR_EL3,Secure Configuration Register" bitfld.quad 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.quad 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled" newline bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.quad 0x00 3. "EA,External Abort and SError Interrupt Routing" "Not to EL3,To EL3" newline bitfld.quad 0x00 2. "FIQ,Physical FIQ Routing" "Not to EL3,To EL3" bitfld.quad 0x00 1. "IRQ,Physical IRQ Routing" "Not to EL3,To EL3" newline bitfld.quad 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers 1 (EL3)" tree.open "Exception Syndrome Registers" if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 15. "UNASE,Unattributable System Error" "Attributable,Unattributable" newline bitfld.quad 0x00 14. "UNCSE,Uncontainable System Error" "Containable,Uncontainable" bitfld.quad 0x00 0.--1. "SES,System Error Source" "Decode,ECC,Slave," elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x5C000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1. "IS,Additional information about the SError interrupt" elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x5C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined" elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1. "IS,Additional information about the SError interrupt" elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif tree.end newline if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting intermediate physical address" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" rgroup.quad spr:0x30C10++0x00 line.quad 0x00 "ISR_EL1,Interrupt Status Register" bitfld.quad 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.quad 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" bitfld.quad 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.quad spr:0x36C02++0x00 line.quad 0x00 "RMR_EL3,Reset Management Register" bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address" rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]" group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID registers" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID registers" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID registers" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID registers" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID registers" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.quad 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade - determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,Reserved,Reserved" newline bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB" newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,16 KB,Reserved" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associatedwith translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memoryregion addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.quad 0x00 14.--15. "TGO,TTBR0_EL3 granule size" "4 KB,64 KB,16 KB,Reserved" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associatedwith translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memoryregion addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34300++0x00 line.quad 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.quad 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device,?..." newline hexmask.quad 0x00 12.--43. 0x1000 "PA[43:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.q(spr:0x30740))&0x01)==0x00)&&(((per.q(spr:0x30740))&0xF000000000000000)==(0x1000000000000000||0x2000000000000000||0x3000000000000000||0x5000000000000000||0x6000000000000000||0x7000000000000000))) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--43. 0x1000 "PA[43:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x1000 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st level,Synchronous parity error on memory access on translation table walk/2nd level,Synchronous parity error on memory access on translation table walk/3rd level,Reserved,Alignment fault,Debug event,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" tree.end newline group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad spr:0x34000++0x0 line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register" group.quad spr:0x34005++0x00 line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Highest level affinity field" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.quad 0x00 28. "TDZ,Traps DC ZVA instruction" "Disabled,Enabled" bitfld.quad 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.quad 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.quad 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.quad 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" bitfld.quad 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "Not aborted,Aborted" newline bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" newline bitfld.quad 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" bitfld.quad 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.quad 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" group.quad spr:0x34111++0x00 line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.quad spr:0x36131++0x00 line.quad 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.quad 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpointregisters disabled" "No,Yes" bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.quad 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad spr:0x34112++0x00 line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad spr:0x36112++0x00 line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad spr:0x34113++0x00 line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.quad 0x00 16. "TEEE,Trap T32EE" "Not supported,?..." bitfld.quad 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.quad 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" newline bitfld.quad 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" bitfld.quad 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" bitfld.quad 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" newline bitfld.quad 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" bitfld.quad 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.quad 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" newline bitfld.quad 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" bitfld.quad 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" bitfld.quad 0x00 4. "T4,Trap to Hypervisor mode Non-secure priv 4" "No effect,Trap" newline bitfld.quad 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.quad 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" bitfld.quad 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" newline bitfld.quad 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (((per.q(spr:0x34212))&0xC000)==0x0000) group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Outer Shareable,Inner Shareable,?..." newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Level 2,Level 1,Level 0,?..." newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Outer Shareable,Inner Shareable,?..." newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Level 3,Level 2,Level 1,?..." newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting intermediate physical address" tree.end tree "Cache Control and Configuration" rgroup.quad spr:0x33001++0x00 line.quad 0x00 "CTR_EL0,Cache Type Register" bitfld.quad 0x0 29.--31. "FORMAT,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 14.--15. "L1IP,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical" bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..." group.quad spr:0x32000++0x0 line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register" bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" rgroup.quad spr:0x31001++0x0 line.quad 0x00 "CLIDR_EL1,Cache Level ID Register" bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.quad 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.quad 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.quad 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.quad 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..." rgroup.quad spr:0x31000++0x0 line.quad 0x00 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,Supported" bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.quad.word 0x00 13.--27. 1. 1. "NUMSETS,Number of Sets" hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOCIATIVITY,Associativity" newline bitfld.quad 0x00 0.--2. "LINESIZE,Line Size" "16 bytes,32bytes,64 bytes,128 bytes,?..." tree "Level 1 memory system" group.quad spr:0x30F10++0x00 line.quad 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register" group.quad spr:0x30F11++0x00 line.quad 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register" group.quad spr:0x30F12++0x00 line.quad 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register" group.quad spr:0x30F13++0x00 line.quad 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register" group.quad spr:0x30F14++0x00 line.quad 0x00 "DL1DATA4_EL1,Data L1 Data 3 Register" group.quad spr:0x30F00++0x00 line.quad 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register" group.quad spr:0x30F01++0x00 line.quad 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register" group.quad spr:0x30F02++0x00 line.quad 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register" group.quad spr:0x30F03++0x00 line.quad 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register" tree.end tree "Level 2 memory system" group.quad spr:0x31B02++0x0 line.quad 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.quad 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "Reset,No reset" bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.quad 0x00 23. "L2CP,L2 cache ECC protection" "Not supported,Supported" newline rbitfld.quad 0x00 22. "L1CECCPP,L1 Cache ECC and Parity protection" "Not supported,Supported" bitfld.quad 0x00 21. "ECCPPEN,ECC and parity enable" "Disabled,Enabled" bitfld.quad 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" newline rbitfld.quad 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" rbitfld.quad 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.quad 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1 present,2 present,?..." newline bitfld.quad 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.quad 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" newline bitfld.quad 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,6 cycles,6 cycles" group.quad spr:0x31B03++0x0 line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.quad 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad spr:0x31F00++0x00 line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.quad 0x00 30.--31. "L2PLRUIP,Select the L2 PLRU insertion point" "MRU/LRU,MRU,3/4 LRU,LRU" bitfld.quad 0x00 29. "L2RPLCPOL,Select the L2 cache replacement policy" "PLRU,Pseudo random" bitfld.quad 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" newline bitfld.quad 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.quad 0x00 26. "FL2GICRCGEA,Force L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.quad 0x00 25. "ESIAA,Enable single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.quad 0x00 24. "L2PLRUMD,Disable PLRU dynamic insertion and update policy" "No,Yes" bitfld.quad 0x00 23. "DACPMUWLUT,Disable ACP MakeUnique and WriteLineUnique transactions" "No,Yes" bitfld.quad 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.quad 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.quad 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.quad 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.quad 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.quad 0x00 14. "EUCE,Enable UniqueClean evictions with data" "Disabled,Enabled" bitfld.quad 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" newline bitfld.quad 0x00 12. "DPSHO,Disable set hazard optimization against prefetch entries" "No,Yes" bitfld.quad 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.quad 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.quad 0x00 9. "DWHOBBRRQ,Disable set/way hazard optimization on back to back reads from the same CPU targeting the same set" "No,Yes" bitfld.quad 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.quad 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" newline bitfld.quad 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" bitfld.quad 0x00 5. "DSWHOWWM,Disables set/way hazard optimization for WBNA/WT memory" "No,Yes" bitfld.quad 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" newline bitfld.quad 0x00 3. "DCEPTE,Disable clean/evict push to external" "No,Yes" bitfld.quad 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.quad 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.quad 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" tree.end tree.end tree "System Performance Monitor" group.quad spr:0x339C0++0x00 line.quad 0x00 "PMCR_EL0,Performance Monitor Control Register" hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.quad 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.quad 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad spr:0x339C1++0x00 line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register " bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad spr:0x339C2++0x00 line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled/No effect,Enabled/Disable" newline eventfld.quad 0x00 5. "P5,Event Counter 5 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 4. "P4,Event Counter 4 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 3. "P3,Event Counter 3 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.quad 0x00 2. "P2,Event Counter 2 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 1. "P1,Event Counter 1 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 0. "P0,Event Counter 0 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339C3++0x00 line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.quad 0x00 5. "P5,Event Counter 5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 4. "P4,Event Counter 4 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 3. "P3,Event Counter 3 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.quad 0x00 2. "P2,Event Counter 2 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 1. "P1,Event Counter 1 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 0. "P0,Event Counter 0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" wgroup.quad spr:0x339C4++0x00 line.quad 0x00 "PMSWINC_EL0,Performance Monitors Software Increment Register" bitfld.quad 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.quad 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.quad 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.quad 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.quad 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.quad 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad spr:0x339C5++0x00 line.quad 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,%d..." tree.open "Common Event Identification Registers" group.quad spr:0x339c6++0x00 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.quad 0x00 30. "CH,Chain" "Not implemented,Implemented" newline bitfld.quad 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.quad 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.quad 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.quad 0x00 25. "BA,Bus access" "Not implemented,Implemented" bitfld.quad 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.quad 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.quad 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.quad 0x00 19. "MA,Data memory access" "Not implemented,Implemented" bitfld.quad 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.quad 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.quad 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.quad 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.quad 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.quad 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.quad 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.quad 0x00 9. "ET,Exception taken" "Not implemented,Implemented" newline bitfld.quad 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.quad 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.quad 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.quad 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" group.quad spr:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" group.quad spr:0x339D2++0x00 line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad spr:0x339E0++0x00 line.quad 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.quad 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad spr:0x309E1++0x00 line.quad 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" newline bitfld.quad 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad spr:0x309E2++0x00 line.quad 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" eventfld.quad 0x00 31. "C,PMCCNTR enable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.quad 0x00 5. "P5,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 4. "P4,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 3. "P3,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.quad 0x00 2. "P2,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 1. "P1,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 0. "P0,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339E3++0x00 line.quad 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" group.quad spr:(0x33E80+0x0)++0x00 line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad spr:(0x33EC0+0x0)++0x00 line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x1)++0x00 line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad spr:(0x33EC0+0x1)++0x00 line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x2)++0x00 line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad spr:(0x33EC0+0x2)++0x00 line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x3)++0x00 line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad spr:(0x33EC0+0x3)++0x00 line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x4)++0x00 line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad spr:(0x33EC0+0x4)++0x00 line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x5)++0x00 line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad spr:(0x33EC0+0x5)++0x00 line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33EF7++0x00 line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad spr:0x33E00++0x00 line.quad 0x00 "CNTFRQ_EL0,Counter Frequency Register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register" group.quad spr:0x30E10++0x00 line.quad 0x00 "CNTKCTL_EL1,Timer PL1 Control Register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad spr:0x33E20++0x00 line.quad 0x00 "CNTP_TVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E21++0x00 line.quad 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E30++0x00 line.quad 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register" group.quad spr:0x33E31++0x00 line.quad 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register" group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad spr:0x34E20++0x00 line.quad 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register" group.quad spr:0x34E21++0x00 line.quad 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register" group.quad spr:0x37E20++0x00 line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register" group.quad spr:0x37E21++0x00 line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Active Priorities 0 Register 0" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Active Priorities 1 Register 0" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Control Registers for EL1" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,Supported" bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.quad 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Control Registers for EL3" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,Supported" bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interruptidentifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "RM,Routing Modifier" "Normal,Special values" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,EOI mode for interrupts handledat non-secure EL1 and EL2" "0,1" bitfld.quad 0x00 3. "EOIMODE_EL1S,EOI mode for interrupts handled at secure EL1" "0,1" bitfld.quad 0x00 2. "EOIMODE_EL3,EOI mode for interrupts handled at EL3" "0,1" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Non-secure accesses to GICC_BPR allowed." "Not allowed,Allowed" bitfld.quad 0x00 0. "CBPR_EL1S,Secure EL1 accesses to ICC_BPR1 allowed" "Not allowed,Allowed" wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0_EL1 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1_EL1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" hgroup.quad spr:0x30C80++0x00 hide.quad 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.quad 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad spr:0x30CC6++0x00 line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad spr:0x30CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad spr:0x36CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad spr:0x30460++0x00 line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad spr:0x30CB3++0x00 line.quad 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.quad spr:0x30CC5++0x00 line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad spr:0x34C95++0x00 line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad spr:0x36CC5++0x00 line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" group.quad spr:0x34C80++0x00 line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Register 0-0" rgroup.quad spr:0x34CB3++0x00 line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad spr:0x34CB5++0x00 line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.quad 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.quad 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.quad 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.quad 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.quad spr:0x34CB0++0x00 line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((per.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad spr:0x34CB2++0x00 line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.quad 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.quad 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.quad 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad spr:0x34CB7++0x00 line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.quad 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.quad 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.quad 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.quad 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.quad spr:0x34C94++0x00 line.quad 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register" rgroup.quad spr:0x34CB1++0x00 line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.quad 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad spr:0x23010++0x00 line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad spr:0x20020++0x00 line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable Register" bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" hexmask.quad.long 0x00 32.--63. 1. "HW,HighWord - Write/read DTRRX/DTRTX value without changing RXfull/TXfull" hexmask.quad.long 0x00 0.--31. 1. "LW,LowWord - Write/read DTRTX/DTRRX value without changing TXfull/RXfull" hgroup.quad spr:0x23050++0x00 hide.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" in wgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad spr:0x24070++0x00 line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Disabled,Enabled" newline bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Disabled,Enabled" newline bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Disabled,Enabled" group.quad spr:0x20002++0x00 line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" if (((per.q(spr:0x20114)&0x02)==0x00)) group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" rbitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full" rbitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full" newline rbitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High" rbitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High" newline rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTdis" "0,1,2,3" rbitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High" newline bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" rbitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "Disabled,Enabled" newline bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" else group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full" newline bitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High" bitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High" newline bitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTdis" "0,1,2,3" bitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High" newline bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "Disabled,Enabled" newline bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" endif group.quad spr:0x20032++0x00 line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad spr:0x20062++0x00 line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--43. 0x10 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad spr:0x20104++0x00 line.quad 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad spr:0x20114++0x00 line.quad 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Implemented,?..." group.quad spr:0x20134++0x00 line.quad 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad spr:0x20144++0x00 line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad spr:0x20786++0x00 line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set" newline bitfld.quad 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.quad 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad spr:0x20796++0x00 line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" if (((per.q(spr:0x207e6))&0xAA)==0xAA) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0xA8) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0xA2) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0xA0) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x8A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x88) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x82) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x80) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x2A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x28) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x22) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x20) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x0A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x08) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x02) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x00) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" endif group.quad spr:0x33450++0x00 line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x0))&0x400000)==0x400000) group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x0))&0x800000)==0x800000) group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 1" if (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x10))&0x400000)==0x400000) group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x10))&0x800000)==0x800000) group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 2" if (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x20))&0x400000)==0x400000) group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x20))&0x800000)==0x800000) group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 3" if (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x30))&0x400000)==0x400000) group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x30))&0x800000)==0x800000) group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 4" if (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x40))&0x400000)==0x400000) group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x40))&0x800000)==0x800000) group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 5" if (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x50))&0x400000)==0x400000) group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x50))&0x800000)==0x800000) group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree.end tree "Watchpoint Control Registers" tree "Watchpoint 0" group.quad spr:(0x20006+0x0)++0x00 line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 1" group.quad spr:(0x20006+0x10)++0x00 line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 2" group.quad spr:(0x20006+0x20)++0x00 line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 3" group.quad spr:(0x20006+0x30)++0x00 line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number" bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.long c15:0x0300++0x00 line.long 0x00 "TLBTR,TLB Type Register" bitfld.long 0x00 0. "NU,Not Unified. Indicates whether the implementation has a unified TLB" "Unified," rgroup.long c15:0x0500++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largery independent,Very interdependent" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.long 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" rgroup.long c15:0x0600++0x00 line.long 0x00 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,ACTLR/AIFSR/ADFSR,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,ID_MMFR4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Not supported,Supported,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,PMUv3,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline rgroup.long c15:0x6C9++0x00 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "CH,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.long 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "BA,Bus access" "Not implemented,Implemented" newline bitfld.long 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "MA,Data memory access" "Not implemented,Implemented" newline bitfld.long 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.long 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "ET,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.long 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" tree.end tree "System Control and Configuration" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" else group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" endif group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPMRCGEA,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 62. "FPNMRCGEA,Force processor non-memory-system RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 61. "FPDIERCGEA,Force processor Decode and Integer Execute idle RCG enables active" "Not forced,Forced" bitfld.quad 0x00 60. "FPDRCGEA,Force processor Dispatch idle RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/st and DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" newline bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" newline bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "ECDAFEMP,Enable contention detection and fast exclusive monitor path" "Disabled,Enabled" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" newline bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" newline bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 46. "DML1DTLBM,Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss" "No,Yes" newline bitfld.quad 0x00 45. "Dl1DCWT,Disable L1-DCache way tracker" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 43. "DVABHWPREF,Disable the Load/Store hardware prefetcher from using VA to cross page boundaries" "No,Yes" bitfld.quad 0x00 42. "DPREFREQRUT,Disable prefetch requests from ReadUnique transactions" "No,Yes" newline bitfld.quad 0x00 41. "ESHWSHAEP,Enable snoop hazard while waiting for second half of atomic exclusive pair" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 requests,1 request,2 requests,3 requests" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "16 requests,18 requests,20 requests,22 requests" bitfld.quad 0x00 6. "SMPEN,Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the first memory error" group.long c15:0x0101++0x00 line.long 0x00 "ACTLR,Auxiliary Control Register" group.long c15:0x0201++0x00 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 28. "TRCDIS,Disable CP14 access to trace registers" "No," newline bitfld.long 0x00 22.--23. "CP11,Coprocesor access control" "Denied,EL1 or higher,Reserved,Full" bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" group.long c15:0x0011++0x00 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" rgroup.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" rgroup.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.long 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[43:32],Periphbase[43:32]" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" tree.end tree "Memory Management Unit" group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Enable" "Not implemented," bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,AArch32 CP15 barrier enable" "Disabled,Enabled" bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0002))&0x02)==0x02)) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB0,Translation table base 0 address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" newline bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0002))&0x02)==0x00)) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB0,Translation table base 0 address" bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base 0 address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base 0 address" endif if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0102))&0x02)==0x02)) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base 1 Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base 1 address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" newline bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0102))&0x02)==0x00)) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base 1 address" bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base 0 address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base 0 address" endif if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR0/TTBR1 ASID field" "TTBR0,TTBR1" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" endif if (((per.l(c15:0x4202))&0x07)==0x00) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x01) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x02) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x03) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x04) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x05) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x06) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Outer Non-cacheable,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 8.--9. "IRGN0, ,Inner cacheability attribute, Normal memory" "Inner Non-cacheable,Inner Write-Back Write-Allocate Cacheable,Inner Write-Through Cacheable,Inner Write-Back no Write-Allocate Cacheable" hexmask.long.byte 0x00 0.--2. 0x1 "T0SZ, ,Size offset of the memory region addressed by HTTBR" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x0)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "No,Yes" newline bitfld.long 0x00 9. "NS,Non-secure" "No,Yes" bitfld.long 0x00 7. "SH,Shareable attribute for the region" "No,Yes" newline bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Strongly-ordered,Reserved,Device,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate" newline bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate" newline bitfld.long 0x00 1. "SS,Supersection" "Disabled,Enabled" newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x1)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline newline newline bitfld.long 0x00 6. "FS[5],Fault status bit - External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 1.--5. "FS[0:4],Fault status bit - Fault source" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external abort/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external abort on translation table walk/1st level,Permission/1st level,Sync. external abort on translation table walk/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external abort,Reserved,Async. parity error on memory access,Sync. parity error on memory access,Reserved,Reserved,Sync. parity error on translation table walk/1st level,Reserved,Sync. parity error on translation table walk/2nd level,?..." newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x1)==0x0)) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes" bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline newline newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address/0th level,Address/1st level,Address/2nd level,Address/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. ext. abort,Async. external abort,Reserved,Reserved,Sync. ext. abort/0th level,Sync. ext. abort/1st level,Sync. ext. abort/2nd level,Sync. ext. abort/3rd level,Sync. parity error on memory access,Async. parity error on memory access,Reserved,Reserved,Reserved,Sync. parity error on translation table walk/0th level,Sync. parity error on translation table walk/1st level,Sync. parity error on translation table walk/2nd level,Sync. parity error on translation table walk/3rd level,Reserved,Alignment,Debug event,?..." newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x002A++0x00 hide.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x012A++0x00 hide.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x402A++0x00 hide.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x412A++0x00 hide.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" endif if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x002A++0x00 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Non-shareable,Shareable" bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Non-shareable,Shareable" newline bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Non-shareable,Shareable" bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Non-shareable,Shareable" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." group.long c15:0x012A++0x00 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" else hgroup.long c15:0x002A++0x00 hide.long 0x00 "PRRR,Primary Region Remap Register" hgroup.long c15:0x012A++0x00 hide.long 0x00 "NMRR,Normal Memory Remap Register" group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" endif tree.end tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x00 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,AArch32 CP15 barrier enable" "Disabled,Enabled" bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR access control" "Disabled,Enabled" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full" newline bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted" newline bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" newline bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x00 20. "TTA,Trap Trace Access" "Not supported," newline bitfld.long 0x00 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x00 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" newline bitfld.long 0x00 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" newline bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" newline bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" newline bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" newline bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" newline bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" newline bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" rgroup.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" if (((per.l(c15:0x4202))&0x07)==0x00) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x01) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x02) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x03) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x04) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x05) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x06) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" if (((per.l(c15:0x4212))&0x0F)==0x00) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x01) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x02) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x03) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x04) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x05) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x06) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x07) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x08) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 22.--47. 0x40 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x09) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 21.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0A) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 20.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0B) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 19.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0C) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 18.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0D) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 17.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0E) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 16.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 15.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "2nd level,1st level,," newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" if (((per.l(c15:0x4025))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.l(c15:0x4025))&0xFC000000)==0x04000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.l(c15:0x4025))&0xFC000000)==(0x0C000000||0x14000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x54000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.l(c15:0x4025))&0xFC000000)==0x60000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.long 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.l(c15:0x4025))&0xFC800000)==(0xA0800000||0xB0800000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.l(c15:0x4025))&0xFC800000)==(0xA0000000||0xB0000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.l(c15:0x4025))&0xFD000000)==0xBD000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 15. "UNASE,Unattributable System Error" "Attributable,Unattributable" newline bitfld.long 0x00 14. "UNCSE,Uncontainable System Error" "Containable,Uncontainable" bitfld.long 0x00 0.--1. "SES,System Error Source" "Decode,ECC,Slave," elif (((per.l(c15:0x4025))&0xFD000000)==0xBC000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.l(c15:0x4025))&0xFC000000)==(0xC0000000||0xC4000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xC8000000||0xCC000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xD0000000||0xD4000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xE0000000||0xF0000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA,Bits [39:12] of the faulting intermediate physical address" group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,Reserved,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." newline bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." newline bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." rgroup.long c15:0x1700++0x0 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported," bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." group.long c15:0x2000++0x00 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" group.long c15:0x041F++0x00 line.long 0x00 "DL1DATA4,Data L1 Data 4 Register" group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x030F++0x00 line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register" wgroup.long c15:0x04F++0x00 line.long 0x00 "RAMINDEX,RAM Index Operation Register" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM identifier" bitfld.long 0x00 18.--21. "WAY,Indicates the way of the RAM that is being accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the RAM that is being accessed" tree.end tree "Level 2 memory system" group.long c15:0x1209++0x00 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "Reset,No reset" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.long 0x00 23. "L2CP,L2 cache ECC protection" "Not supported,Supported" newline rbitfld.long 0x00 22. "L1CECCPP,L1 Cache ECC and Parity protection" "Not supported,Supported" bitfld.long 0x00 21. "ECCPPEN,ECC and parity enable" "Disabled,Enabled" bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1 present,2 present,?..." newline bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" newline bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,6 cycles,6 cycles" group.long c15:0x1309++0x00 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2PLRUIP,Select the L2 PLRU insertion point" "MRU/LRU,MRU,3/4 LRU,LRU" bitfld.long 0x00 29. "L2RPLCPOL,Select the L2 cache replacement policy" "PLRU,Pseudo random" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" newline bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.long 0x00 26. "FL2GICRCGEA,Force L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.long 0x00 25. "ESIAA,Enable single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.long 0x00 24. "L2PLRUMD,Disable PLRU dynamic insertion and update policy" "No,Yes" bitfld.long 0x00 23. "DACPMUWLU,Disable ACP MakeUnique and WriteLineUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enable UniqueClean evictions with data" "Disabled,Enabled" bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" newline bitfld.long 0x00 12. "DPSHO,Disable set hazard optimization against prefetch entries" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.long 0x00 9. "DWHOBBRRQ,Disable set/way hazard optimization on back to back reads from the same CPU targeting the same set" "No,Yes" bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" newline bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" bitfld.long 0x00 5. "DSWHOWWM,Disables set/way hazard optimization for WBNA/WT memory" "No,Yes" bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" newline bitfld.long 0x00 3. "DCEPTE,Disable clean/evict push to external" "No,Yes" bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" tree.end tree.end tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline eventfld.long 0x00 5. "P5,Event Counter 5 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Event Counter 2 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 5. "P5,PMN5 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 4. "P4,PMN4 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 3. "P3,PMN3 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 2. "P2,PMN2 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 1. "P1,PMN1 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 0. "P0,PMN0 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" bitfld.long 0x00 5. "EVENT[5],Value of 5 event counter" "0,1" bitfld.long 0x00 4. "EVENT[4],Value of 4 event counter" "0,1" bitfld.long 0x00 3. "EVENT[3],Value of 3 event counter" "0,1" newline bitfld.long 0x00 2. "EVENT[2],Value of 2 event counter" "0,1" bitfld.long 0x00 1. "EVENT[1],Value of 1 event counter" "0,1" bitfld.long 0x00 0. "EVENT[0],Value of 0 event counter" "0,1" newline group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access." rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Highest Prioity Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Highest Prioity Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Interrupt Controller Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Register 0-0" bitfld.long 0x00 31. "P31,Group 0 interrupt active priority 31" "0,1" bitfld.long 0x00 30. "P30,Group 0 interrupt active priority 30" "0,1" bitfld.long 0x00 29. "P29,Group 0 interrupt active priority 29" "0,1" bitfld.long 0x00 28. "P28,Group 0 interrupt active priority 28" "0,1" newline bitfld.long 0x00 27. "P27,Group 0 interrupt active priority 27" "0,1" bitfld.long 0x00 26. "P26,Group 0 interrupt active priority 26" "0,1" bitfld.long 0x00 25. "P25,Group 0 interrupt active priority 25" "0,1" bitfld.long 0x00 24. "P24,Group 0 interrupt active priority 24" "0,1" newline bitfld.long 0x00 23. "P23,Group 0 interrupt active priority 23" "0,1" bitfld.long 0x00 22. "P22,Group 0 interrupt active priority 22" "0,1" bitfld.long 0x00 21. "P21,Group 0 interrupt active priority 21" "0,1" bitfld.long 0x00 20. "P20,Group 0 interrupt active priority 20" "0,1" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active priority 19" "0,1" bitfld.long 0x00 18. "P18,Group 0 interrupt active priority 18" "0,1" bitfld.long 0x00 17. "P17,Group 0 interrupt active priority 17" "0,1" bitfld.long 0x00 16. "P16,Group 0 interrupt active priority 16" "0,1" newline bitfld.long 0x00 15. "P15,Group 0 interrupt active priority 15" "0,1" bitfld.long 0x00 14. "P14,Group 0 interrupt active priority 14" "0,1" bitfld.long 0x00 13. "P13,Group 0 interrupt active priority 13" "0,1" bitfld.long 0x00 12. "P12,Group 0 interrupt active priority 12" "0,1" newline bitfld.long 0x00 11. "P11,Group 0 interrupt active priority 11" "0,1" bitfld.long 0x00 10. "P10,Group 0 interrupt active priority 10" "0,1" bitfld.long 0x00 9. "P9,Group 0 interrupt active priority 9" "0,1" bitfld.long 0x00 8. "P8,Group 0 interrupt active priority 8" "0,1" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active priority 7" "0,1" bitfld.long 0x00 6. "P6,Group 0 interrupt active priority 6" "0,1" bitfld.long 0x00 5. "P5,Group 0 interrupt active priority 5" "0,1" bitfld.long 0x00 4. "P4,Group 0 interrupt active priority 4" "0,1" newline bitfld.long 0x00 3. "P3,Group 0 interrupt active priority 3" "0,1" bitfld.long 0x00 2. "P2,Group 0 interrupt active priority 2" "0,1" bitfld.long 0x00 1. "P1,Group 0 interrupt active priority 1" "0,1" bitfld.long 0x00 0. "P0,Group 0 interrupt active priority 0" "0,1" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Register 1-0" bitfld.long 0x00 31. "P31,Group 1 interrupt active priority 31" "0,1" bitfld.long 0x00 30. "P30,Group 1 interrupt active priority 30" "0,1" bitfld.long 0x00 29. "P29,Group 1 interrupt active priority 29" "0,1" bitfld.long 0x00 28. "P28,Group 1 interrupt active priority 28" "0,1" newline bitfld.long 0x00 27. "P27,Group 1 interrupt active priority 27" "0,1" bitfld.long 0x00 26. "P26,Group 1 interrupt active priority 26" "0,1" bitfld.long 0x00 25. "P25,Group 1 interrupt active priority 25" "0,1" bitfld.long 0x00 24. "P24,Group 1 interrupt active priority 24" "0,1" newline bitfld.long 0x00 23. "P23,Group 1 interrupt active priority 23" "0,1" bitfld.long 0x00 22. "P22,Group 1 interrupt active priority 22" "0,1" bitfld.long 0x00 21. "P21,Group 1 interrupt active priority 21" "0,1" bitfld.long 0x00 20. "P20,Group 1 interrupt active priority 20" "0,1" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active priority 19" "0,1" bitfld.long 0x00 18. "P18,Group 1 interrupt active priority 18" "0,1" bitfld.long 0x00 17. "P17,Group 1 interrupt active priority 17" "0,1" bitfld.long 0x00 16. "P16,Group 1 interrupt active priority 16" "0,1" newline bitfld.long 0x00 15. "P15,Group 1 interrupt active priority 15" "0,1" bitfld.long 0x00 14. "P14,Group 1 interrupt active priority 14" "0,1" bitfld.long 0x00 13. "P13,Group 1 interrupt active priority 13" "0,1" bitfld.long 0x00 12. "P12,Group 1 interrupt active priority 12" "0,1" newline bitfld.long 0x00 11. "P11,Group 1 interrupt active priority 11" "0,1" bitfld.long 0x00 10. "P10,Group 1 interrupt active priority 10" "0,1" bitfld.long 0x00 9. "P9,Group 1 interrupt active priority 9" "0,1" bitfld.long 0x00 8. "P8,Group 1 interrupt active priority 8" "0,1" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active priority 7" "0,1" bitfld.long 0x00 6. "P6,Group 1 interrupt active priority 6" "0,1" bitfld.long 0x00 5. "P5,Group 1 interrupt active priority 5" "0,1" bitfld.long 0x00 4. "P4,Group 1 interrupt active priority 4" "0,1" newline bitfld.long 0x00 3. "P3,Group 1 interrupt active priority 3" "0,1" bitfld.long 0x00 2. "P2,Group 1 interrupt active priority 2" "0,1" bitfld.long 0x00 1. "P1,Group 1 interrupt active priority 1" "0,1" bitfld.long 0x00 0. "P0,Group 1 interrupt active priority 0" "0,1" tree.end newline rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x459C++0x00 line.long 0x00 "ICH_SRE,Hypervisor System Register" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..." bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..." newline bitfld.long 0x0 16.--19. "VERSION,Debug Architecture Version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8,?..." bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not implemented" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Reserved,Implemented" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" hgroup.long c14:0x0050++0x0 hide.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)" in group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 22.--23. "INTDIS,Used for save/restore of EDSCR.INTdis" "0,1,2,3" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" newline bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" newline bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" newline bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." wgroup.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" group.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)" group.long c14:0x0687++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" if (((per.l(c14:0x06E7))&0xAA)==0xAA) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0xA8) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0xA2) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0xA0) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x8A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x88) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x82) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x80) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x2A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x28) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x22) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x20) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x0A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x08) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x02) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x00) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" endif rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" ",,No offset,?..." rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" ",Supported,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad 0x0 12.--47. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x0 0.--1. "VALID,ROM table address valid" "Not valid,,,Valid" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else hgroup.long c14:0x0260++0x00 hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Power down,Emulate" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x0)++0x0 hide.long 0x00 "DBGBVR0,Breakpoint Value Register" else group.long c14:(0x0400+0x0)++0x0 line.long 0x00 "DBGBVR0,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x0)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 1" if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x10)++0x0 hide.long 0x00 "DBGBVR1,Breakpoint Value Register" else group.long c14:(0x0400+0x10)++0x0 line.long 0x00 "DBGBVR1,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x10)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 2" if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x20)++0x0 hide.long 0x00 "DBGBVR2,Breakpoint Value Register" else group.long c14:(0x0400+0x20)++0x0 line.long 0x00 "DBGBVR2,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x20)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 3" if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x30)++0x0 hide.long 0x00 "DBGBVR3,Breakpoint Value Register" else group.long c14:(0x0400+0x30)++0x0 line.long 0x00 "DBGBVR3,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x30)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 4" if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x40)++0x0 hide.long 0x00 "DBGBVR4,Breakpoint Value Register" else group.long c14:(0x0400+0x40)++0x0 line.long 0x00 "DBGBVR4,Breakpoint ContextID Register" endif if (((per.l(c14:(0x500+0x40)))&0x800000)==0x800000) group.long c14:(0x0101+0x40)++0x0 line.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VAMID,VMID value for comparison" else hgroup.long c14:(0x0101+0x40)++0x0 hide.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register" endif group.long c14:(0x0500+0x40)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 5" if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x50)++0x0 hide.long 0x00 "DBGBVR5,Breakpoint Value Register" else group.long c14:(0x0400+0x50)++0x0 line.long 0x00 "DBGBVR5,Breakpoint ContextID Register" endif if (((per.l(c14:(0x500+0x50)))&0x800000)==0x800000) group.long c14:(0x0101+0x50)++0x0 line.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VAMID,VMID value for comparison" else hgroup.long c14:(0x0101+0x50)++0x0 hide.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register" endif group.long c14:(0x0500+0x50)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree.end tree "Watchpoint Control Registers" tree "Watchpoint 0" group.long c14:(0x0600+0x0)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 1" group.long c14:(0x0600+0x10)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 2" group.long c14:(0x0600+0x20)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 3" group.long c14:(0x0600+0x30)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP tree.open "Interrupt Controller (GIC-500)" AUTOINDENT.PUSH AUTOINDENT.OFF base COMP.BASE("GICD",-1.) width 17. tree "Distributor Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 6. " DS ,Disable Security" "No,Yes" textline " " bitfld.long 0x00 5. " ARE_NS ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_S ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLEGRP1S ,Enable Secure Group 1 interrupts" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_NS ,Affinity Routing Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1A ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Reserved,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported" bitfld.long 0x00 24. " A3V ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported" bitfld.long 0x00 19.--23. " IDBITS ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." textline " " bitfld.long 0x00 17. " LPIS ,Indicates whether the implementation supports LPIs" "Not supported,Supported" bitfld.long 0x00 16. " MBIS ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--4. " ITLN ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000) wgroup.long 0x40++0x03 line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" wgroup.long 0x48++0x03 line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50)) wgroup.long 0x50++0x03 line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58)) wgroup.long 0x58++0x03 line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)" endif else hgroup.long 0x40++0x03 hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hgroup.long 0x48++0x03 hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register" hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register" endif width 17. tree "Group Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080)) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x0080++0x03 hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x00E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x00F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 24. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0100++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0200++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0300++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x400++0x03 hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hgroup.long 0x404++0x03 hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hgroup.long 0x408++0x03 hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hgroup.long 0x40C++0x03 hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hgroup.long 0x410++0x03 hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hgroup.long 0x414++0x03 hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hgroup.long 0x418++0x03 hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hgroup.long 0x41C++0x03 hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" else group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 19. tree "Interrupt Targets Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1) hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SGI)" "Level,Edge" group.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (PPI)" "Level,Edge" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 17. tree "Interrupt Group Modifier Registers" hgroup.long 0x0D00++0x03 hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)) group.long 0x0D04++0x03 line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" bitfld.long 0x00 31. " GMB63 ,Group Modifier Bit 63" "0,1" bitfld.long 0x00 30. " GMB62 ,Group Modifier Bit 62" "0,1" bitfld.long 0x00 29. " GMB61 ,Group Modifier Bit 61" "0,1" textline " " bitfld.long 0x00 28. " GMB60 ,Group Modifier Bit 60" "0,1" bitfld.long 0x00 27. " GMB59 ,Group Modifier Bit 59" "0,1" bitfld.long 0x00 26. " GMB58 ,Group Modifier Bit 58" "0,1" textline " " bitfld.long 0x00 25. " GMB57 ,Group Modifier Bit 57" "0,1" bitfld.long 0x00 24. " GMB56 ,Group Modifier Bit 56" "0,1" bitfld.long 0x00 23. " GMB55 ,Group Modifier Bit 55" "0,1" textline " " bitfld.long 0x00 22. " GMB54 ,Group Modifier Bit 54" "0,1" bitfld.long 0x00 21. " GMB53 ,Group Modifier Bit 53" "0,1" bitfld.long 0x00 20. " GMB52 ,Group Modifier Bit 52" "0,1" textline " " bitfld.long 0x00 19. " GMB51 ,Group Modifier Bit 51" "0,1" bitfld.long 0x00 18. " GMB50 ,Group Modifier Bit 50" "0,1" bitfld.long 0x00 17. " GMB49 ,Group Modifier Bit 49" "0,1" textline " " bitfld.long 0x00 16. " GMB48 ,Group Modifier Bit 48" "0,1" bitfld.long 0x00 15. " GMB47 ,Group Modifier Bit 47" "0,1" bitfld.long 0x00 14. " GMB46 ,Group Modifier Bit 46" "0,1" textline " " bitfld.long 0x00 13. " GMB45 ,Group Modifier Bit 45" "0,1" bitfld.long 0x00 12. " GMB44 ,Group Modifier Bit 44" "0,1" bitfld.long 0x00 11. " GMB43 ,Group Modifier Bit 43" "0,1" textline " " bitfld.long 0x00 10. " GMB42 ,Group Modifier Bit 42" "0,1" bitfld.long 0x00 9. " GMB41 ,Group Modifier Bit 41" "0,1" bitfld.long 0x00 8. " GMB40 ,Group Modifier Bit 40" "0,1" textline " " bitfld.long 0x00 7. " GMB39 ,Group Modifier Bit 39" "0,1" bitfld.long 0x00 6. " GMB38 ,Group Modifier Bit 38" "0,1" bitfld.long 0x00 5. " GMB37 ,Group Modifier Bit 37" "0,1" textline " " bitfld.long 0x00 4. " GMB36 ,Group Modifier Bit 36" "0,1" bitfld.long 0x00 3. " GMB35 ,Group Modifier Bit 35" "0,1" bitfld.long 0x00 2. " GMB34 ,Group Modifier Bit 34" "0,1" textline " " bitfld.long 0x00 1. " GMB33 ,Group Modifier Bit 33" "0,1" bitfld.long 0x00 0. " GMB32 ,Group Modifier Bit 32" "0,1" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)) group.long 0x0D08++0x03 line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" bitfld.long 0x00 31. " GMB95 ,Group Modifier Bit 95" "0,1" bitfld.long 0x00 30. " GMB94 ,Group Modifier Bit 94" "0,1" bitfld.long 0x00 29. " GMB93 ,Group Modifier Bit 93" "0,1" textline " " bitfld.long 0x00 28. " GMB92 ,Group Modifier Bit 92" "0,1" bitfld.long 0x00 27. " GMB91 ,Group Modifier Bit 91" "0,1" bitfld.long 0x00 26. " GMB90 ,Group Modifier Bit 90" "0,1" textline " " bitfld.long 0x00 25. " GMB89 ,Group Modifier Bit 89" "0,1" bitfld.long 0x00 24. " GMB88 ,Group Modifier Bit 88" "0,1" bitfld.long 0x00 23. " GMB87 ,Group Modifier Bit 87" "0,1" textline " " bitfld.long 0x00 22. " GMB86 ,Group Modifier Bit 86" "0,1" bitfld.long 0x00 21. " GMB85 ,Group Modifier Bit 85" "0,1" bitfld.long 0x00 20. " GMB84 ,Group Modifier Bit 84" "0,1" textline " " bitfld.long 0x00 19. " GMB83 ,Group Modifier Bit 83" "0,1" bitfld.long 0x00 18. " GMB82 ,Group Modifier Bit 82" "0,1" bitfld.long 0x00 17. " GMB81 ,Group Modifier Bit 81" "0,1" textline " " bitfld.long 0x00 16. " GMB80 ,Group Modifier Bit 80" "0,1" bitfld.long 0x00 15. " GMB79 ,Group Modifier Bit 79" "0,1" bitfld.long 0x00 14. " GMB78 ,Group Modifier Bit 78" "0,1" textline " " bitfld.long 0x00 13. " GMB77 ,Group Modifier Bit 77" "0,1" bitfld.long 0x00 12. " GMB76 ,Group Modifier Bit 76" "0,1" bitfld.long 0x00 11. " GMB75 ,Group Modifier Bit 75" "0,1" textline " " bitfld.long 0x00 10. " GMB74 ,Group Modifier Bit 74" "0,1" bitfld.long 0x00 9. " GMB73 ,Group Modifier Bit 73" "0,1" bitfld.long 0x00 8. " GMB72 ,Group Modifier Bit 72" "0,1" textline " " bitfld.long 0x00 7. " GMB71 ,Group Modifier Bit 71" "0,1" bitfld.long 0x00 6. " GMB70 ,Group Modifier Bit 70" "0,1" bitfld.long 0x00 5. " GMB69 ,Group Modifier Bit 69" "0,1" textline " " bitfld.long 0x00 4. " GMB68 ,Group Modifier Bit 68" "0,1" bitfld.long 0x00 3. " GMB67 ,Group Modifier Bit 67" "0,1" bitfld.long 0x00 2. " GMB66 ,Group Modifier Bit 66" "0,1" textline " " bitfld.long 0x00 1. " GMB65 ,Group Modifier Bit 65" "0,1" bitfld.long 0x00 0. " GMB64 ,Group Modifier Bit 64" "0,1" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)) group.long 0x0D0C++0x03 line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1" bitfld.long 0x00 30. " GMB126 ,Group Modifier Bit 126" "0,1" bitfld.long 0x00 29. " GMB125 ,Group Modifier Bit 125" "0,1" textline " " bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1" bitfld.long 0x00 27. " GMB123 ,Group Modifier Bit 123" "0,1" bitfld.long 0x00 26. " GMB122 ,Group Modifier Bit 122" "0,1" textline " " bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1" bitfld.long 0x00 24. " GMB120 ,Group Modifier Bit 120" "0,1" bitfld.long 0x00 23. " GMB119 ,Group Modifier Bit 119" "0,1" textline " " bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1" bitfld.long 0x00 21. " GMB117 ,Group Modifier Bit 117" "0,1" bitfld.long 0x00 20. " GMB116 ,Group Modifier Bit 116" "0,1" textline " " bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1" bitfld.long 0x00 18. " GMB114 ,Group Modifier Bit 114" "0,1" bitfld.long 0x00 17. " GMB113 ,Group Modifier Bit 113" "0,1" textline " " bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1" bitfld.long 0x00 15. " GMB111 ,Group Modifier Bit 111" "0,1" bitfld.long 0x00 14. " GMB110 ,Group Modifier Bit 110" "0,1" textline " " bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1" bitfld.long 0x00 12. " GMB108 ,Group Modifier Bit 108" "0,1" bitfld.long 0x00 11. " GMB107 ,Group Modifier Bit 107" "0,1" textline " " bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1" bitfld.long 0x00 9. " GMB105 ,Group Modifier Bit 105" "0,1" bitfld.long 0x00 8. " GMB104 ,Group Modifier Bit 104" "0,1" textline " " bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1" bitfld.long 0x00 6. " GMB102 ,Group Modifier Bit 102" "0,1" bitfld.long 0x00 5. " GMB101 ,Group Modifier Bit 101" "0,1" textline " " bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1" bitfld.long 0x00 3. " GMB99 ,Group Modifier Bit 99" "0,1" bitfld.long 0x00 2. " GMB98 ,Group Modifier Bit 98" "0,1" textline " " bitfld.long 0x00 1. " GMB97 ,Group Modifier Bit 97" "0,1" bitfld.long 0x00 0. " GMB96 ,Group Modifier Bit 96" "0,1" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)) group.long 0x0D10++0x03 line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1" bitfld.long 0x00 30. " GMB158 ,Group Modifier Bit 158" "0,1" bitfld.long 0x00 29. " GMB157 ,Group Modifier Bit 157" "0,1" textline " " bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1" bitfld.long 0x00 27. " GMB155 ,Group Modifier Bit 155" "0,1" bitfld.long 0x00 26. " GMB154 ,Group Modifier Bit 154" "0,1" textline " " bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1" bitfld.long 0x00 24. " GMB152 ,Group Modifier Bit 152" "0,1" bitfld.long 0x00 23. " GMB151 ,Group Modifier Bit 151" "0,1" textline " " bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1" bitfld.long 0x00 21. " GMB149 ,Group Modifier Bit 149" "0,1" bitfld.long 0x00 20. " GMB148 ,Group Modifier Bit 148" "0,1" textline " " bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1" bitfld.long 0x00 18. " GMB146 ,Group Modifier Bit 146" "0,1" bitfld.long 0x00 17. " GMB145 ,Group Modifier Bit 145" "0,1" textline " " bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1" bitfld.long 0x00 15. " GMB143 ,Group Modifier Bit 143" "0,1" bitfld.long 0x00 14. " GMB142 ,Group Modifier Bit 142" "0,1" textline " " bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1" bitfld.long 0x00 12. " GMB140 ,Group Modifier Bit 140" "0,1" bitfld.long 0x00 11. " GMB139 ,Group Modifier Bit 139" "0,1" textline " " bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1" bitfld.long 0x00 9. " GMB137 ,Group Modifier Bit 137" "0,1" bitfld.long 0x00 8. " GMB136 ,Group Modifier Bit 136" "0,1" textline " " bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1" bitfld.long 0x00 6. " GMB134 ,Group Modifier Bit 134" "0,1" bitfld.long 0x00 5. " GMB133 ,Group Modifier Bit 133" "0,1" textline " " bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1" bitfld.long 0x00 3. " GMB131 ,Group Modifier Bit 131" "0,1" bitfld.long 0x00 2. " GMB130 ,Group Modifier Bit 130" "0,1" textline " " bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1" bitfld.long 0x00 0. " GMB128 ,Group Modifier Bit 128" "0,1" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)) group.long 0x0D14++0x03 line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1" bitfld.long 0x00 30. " GMB190 ,Group Modifier Bit 190" "0,1" bitfld.long 0x00 29. " GMB189 ,Group Modifier Bit 189" "0,1" textline " " bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1" bitfld.long 0x00 27. " GMB187 ,Group Modifier Bit 187" "0,1" bitfld.long 0x00 26. " GMB186 ,Group Modifier Bit 186" "0,1" textline " " bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1" bitfld.long 0x00 24. " GMB184 ,Group Modifier Bit 184" "0,1" bitfld.long 0x00 23. " GMB183 ,Group Modifier Bit 183" "0,1" textline " " bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1" bitfld.long 0x00 21. " GMB181 ,Group Modifier Bit 181" "0,1" bitfld.long 0x00 20. " GMB180 ,Group Modifier Bit 180" "0,1" textline " " bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1" bitfld.long 0x00 18. " GMB178 ,Group Modifier Bit 178" "0,1" bitfld.long 0x00 17. " GMB177 ,Group Modifier Bit 177" "0,1" textline " " bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1" bitfld.long 0x00 15. " GMB175 ,Group Modifier Bit 175" "0,1" bitfld.long 0x00 14. " GMB174 ,Group Modifier Bit 174" "0,1" textline " " bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1" bitfld.long 0x00 12. " GMB172 ,Group Modifier Bit 172" "0,1" bitfld.long 0x00 11. " GMB171 ,Group Modifier Bit 171" "0,1" textline " " bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1" bitfld.long 0x00 9. " GMB169 ,Group Modifier Bit 169" "0,1" bitfld.long 0x00 8. " GMB168 ,Group Modifier Bit 168" "0,1" textline " " bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1" bitfld.long 0x00 6. " GMB166 ,Group Modifier Bit 166" "0,1" bitfld.long 0x00 5. " GMB165 ,Group Modifier Bit 165" "0,1" textline " " bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1" bitfld.long 0x00 3. " GMB163 ,Group Modifier Bit 163" "0,1" bitfld.long 0x00 2. " GMB162 ,Group Modifier Bit 162" "0,1" textline " " bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1" bitfld.long 0x00 0. " GMB160 ,Group Modifier Bit 160" "0,1" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)) group.long 0x0D18++0x03 line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1" bitfld.long 0x00 30. " GMB222 ,Group Modifier Bit 222" "0,1" bitfld.long 0x00 29. " GMB221 ,Group Modifier Bit 221" "0,1" textline " " bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1" bitfld.long 0x00 27. " GMB219 ,Group Modifier Bit 219" "0,1" bitfld.long 0x00 26. " GMB218 ,Group Modifier Bit 218" "0,1" textline " " bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1" bitfld.long 0x00 24. " GMB216 ,Group Modifier Bit 216" "0,1" bitfld.long 0x00 23. " GMB215 ,Group Modifier Bit 215" "0,1" textline " " bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1" bitfld.long 0x00 21. " GMB213 ,Group Modifier Bit 213" "0,1" bitfld.long 0x00 20. " GMB212 ,Group Modifier Bit 212" "0,1" textline " " bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1" bitfld.long 0x00 18. " GMB210 ,Group Modifier Bit 210" "0,1" bitfld.long 0x00 17. " GMB209 ,Group Modifier Bit 209" "0,1" textline " " bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1" bitfld.long 0x00 15. " GMB207 ,Group Modifier Bit 207" "0,1" bitfld.long 0x00 14. " GMB206 ,Group Modifier Bit 206" "0,1" textline " " bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1" bitfld.long 0x00 12. " GMB204 ,Group Modifier Bit 204" "0,1" bitfld.long 0x00 11. " GMB203 ,Group Modifier Bit 203" "0,1" textline " " bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1" bitfld.long 0x00 9. " GMB201 ,Group Modifier Bit 201" "0,1" bitfld.long 0x00 8. " GMB200 ,Group Modifier Bit 200" "0,1" textline " " bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1" bitfld.long 0x00 6. " GMB198 ,Group Modifier Bit 198" "0,1" bitfld.long 0x00 5. " GMB197 ,Group Modifier Bit 197" "0,1" textline " " bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1" bitfld.long 0x00 3. " GMB195 ,Group Modifier Bit 195" "0,1" bitfld.long 0x00 2. " GMB194 ,Group Modifier Bit 194" "0,1" textline " " bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1" bitfld.long 0x00 0. " GMB192 ,Group Modifier Bit 192" "0,1" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)) group.long 0x0D1C++0x03 line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1" bitfld.long 0x00 30. " GMB254 ,Group Modifier Bit 254" "0,1" bitfld.long 0x00 29. " GMB253 ,Group Modifier Bit 253" "0,1" textline " " bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1" bitfld.long 0x00 27. " GMB251 ,Group Modifier Bit 251" "0,1" bitfld.long 0x00 26. " GMB250 ,Group Modifier Bit 250" "0,1" textline " " bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1" bitfld.long 0x00 24. " GMB248 ,Group Modifier Bit 248" "0,1" bitfld.long 0x00 23. " GMB247 ,Group Modifier Bit 247" "0,1" textline " " bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1" bitfld.long 0x00 21. " GMB245 ,Group Modifier Bit 245" "0,1" bitfld.long 0x00 20. " GMB244 ,Group Modifier Bit 244" "0,1" textline " " bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1" bitfld.long 0x00 18. " GMB242 ,Group Modifier Bit 242" "0,1" bitfld.long 0x00 17. " GMB241 ,Group Modifier Bit 241" "0,1" textline " " bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1" bitfld.long 0x00 15. " GMB239 ,Group Modifier Bit 239" "0,1" bitfld.long 0x00 14. " GMB238 ,Group Modifier Bit 238" "0,1" textline " " bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1" bitfld.long 0x00 12. " GMB236 ,Group Modifier Bit 236" "0,1" bitfld.long 0x00 11. " GMB235 ,Group Modifier Bit 235" "0,1" textline " " bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1" bitfld.long 0x00 9. " GMB233 ,Group Modifier Bit 233" "0,1" bitfld.long 0x00 8. " GMB232 ,Group Modifier Bit 232" "0,1" textline " " bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1" bitfld.long 0x00 6. " GMB230 ,Group Modifier Bit 230" "0,1" bitfld.long 0x00 5. " GMB229 ,Group Modifier Bit 229" "0,1" textline " " bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1" bitfld.long 0x00 3. " GMB227 ,Group Modifier Bit 227" "0,1" bitfld.long 0x00 2. " GMB226 ,Group Modifier Bit 226" "0,1" textline " " bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1" bitfld.long 0x00 0. " GMB224 ,Group Modifier Bit 224" "0,1" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)) group.long 0x0D20++0x03 line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1" bitfld.long 0x00 30. " GMB286 ,Group Modifier Bit 286" "0,1" bitfld.long 0x00 29. " GMB285 ,Group Modifier Bit 285" "0,1" textline " " bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1" bitfld.long 0x00 27. " GMB283 ,Group Modifier Bit 283" "0,1" bitfld.long 0x00 26. " GMB282 ,Group Modifier Bit 282" "0,1" textline " " bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1" bitfld.long 0x00 24. " GMB280 ,Group Modifier Bit 280" "0,1" bitfld.long 0x00 23. " GMB279 ,Group Modifier Bit 279" "0,1" textline " " bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1" bitfld.long 0x00 21. " GMB277 ,Group Modifier Bit 277" "0,1" bitfld.long 0x00 20. " GMB276 ,Group Modifier Bit 276" "0,1" textline " " bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1" bitfld.long 0x00 18. " GMB274 ,Group Modifier Bit 274" "0,1" bitfld.long 0x00 17. " GMB273 ,Group Modifier Bit 273" "0,1" textline " " bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1" bitfld.long 0x00 15. " GMB271 ,Group Modifier Bit 271" "0,1" bitfld.long 0x00 14. " GMB270 ,Group Modifier Bit 270" "0,1" textline " " bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1" bitfld.long 0x00 12. " GMB268 ,Group Modifier Bit 268" "0,1" bitfld.long 0x00 11. " GMB267 ,Group Modifier Bit 267" "0,1" textline " " bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1" bitfld.long 0x00 9. " GMB265 ,Group Modifier Bit 265" "0,1" bitfld.long 0x00 8. " GMB264 ,Group Modifier Bit 264" "0,1" textline " " bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1" bitfld.long 0x00 6. " GMB262 ,Group Modifier Bit 262" "0,1" bitfld.long 0x00 5. " GMB261 ,Group Modifier Bit 261" "0,1" textline " " bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1" bitfld.long 0x00 3. " GMB259 ,Group Modifier Bit 259" "0,1" bitfld.long 0x00 2. " GMB258 ,Group Modifier Bit 258" "0,1" textline " " bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1" bitfld.long 0x00 0. " GMB256 ,Group Modifier Bit 256" "0,1" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)) group.long 0x0D24++0x03 line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1" bitfld.long 0x00 30. " GMB318 ,Group Modifier Bit 318" "0,1" bitfld.long 0x00 29. " GMB317 ,Group Modifier Bit 317" "0,1" textline " " bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1" bitfld.long 0x00 27. " GMB315 ,Group Modifier Bit 315" "0,1" bitfld.long 0x00 26. " GMB314 ,Group Modifier Bit 314" "0,1" textline " " bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1" bitfld.long 0x00 24. " GMB312 ,Group Modifier Bit 312" "0,1" bitfld.long 0x00 23. " GMB311 ,Group Modifier Bit 311" "0,1" textline " " bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1" bitfld.long 0x00 21. " GMB309 ,Group Modifier Bit 309" "0,1" bitfld.long 0x00 20. " GMB308 ,Group Modifier Bit 308" "0,1" textline " " bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1" bitfld.long 0x00 18. " GMB306 ,Group Modifier Bit 306" "0,1" bitfld.long 0x00 17. " GMB305 ,Group Modifier Bit 305" "0,1" textline " " bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1" bitfld.long 0x00 15. " GMB303 ,Group Modifier Bit 303" "0,1" bitfld.long 0x00 14. " GMB302 ,Group Modifier Bit 302" "0,1" textline " " bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1" bitfld.long 0x00 12. " GMB300 ,Group Modifier Bit 300" "0,1" bitfld.long 0x00 11. " GMB299 ,Group Modifier Bit 299" "0,1" textline " " bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1" bitfld.long 0x00 9. " GMB297 ,Group Modifier Bit 297" "0,1" bitfld.long 0x00 8. " GMB296 ,Group Modifier Bit 296" "0,1" textline " " bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1" bitfld.long 0x00 6. " GMB294 ,Group Modifier Bit 294" "0,1" bitfld.long 0x00 5. " GMB293 ,Group Modifier Bit 293" "0,1" textline " " bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1" bitfld.long 0x00 3. " GMB291 ,Group Modifier Bit 291" "0,1" bitfld.long 0x00 2. " GMB290 ,Group Modifier Bit 290" "0,1" textline " " bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1" bitfld.long 0x00 0. " GMB288 ,Group Modifier Bit 288" "0,1" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)) group.long 0x0D28++0x03 line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1" bitfld.long 0x00 30. " GMB350 ,Group Modifier Bit 350" "0,1" bitfld.long 0x00 29. " GMB349 ,Group Modifier Bit 349" "0,1" textline " " bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1" bitfld.long 0x00 27. " GMB347 ,Group Modifier Bit 347" "0,1" bitfld.long 0x00 26. " GMB346 ,Group Modifier Bit 346" "0,1" textline " " bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1" bitfld.long 0x00 24. " GMB344 ,Group Modifier Bit 344" "0,1" bitfld.long 0x00 23. " GMB343 ,Group Modifier Bit 343" "0,1" textline " " bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1" bitfld.long 0x00 21. " GMB341 ,Group Modifier Bit 341" "0,1" bitfld.long 0x00 20. " GMB340 ,Group Modifier Bit 340" "0,1" textline " " bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1" bitfld.long 0x00 18. " GMB338 ,Group Modifier Bit 338" "0,1" bitfld.long 0x00 17. " GMB337 ,Group Modifier Bit 337" "0,1" textline " " bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1" bitfld.long 0x00 15. " GMB335 ,Group Modifier Bit 335" "0,1" bitfld.long 0x00 14. " GMB334 ,Group Modifier Bit 334" "0,1" textline " " bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1" bitfld.long 0x00 12. " GMB332 ,Group Modifier Bit 332" "0,1" bitfld.long 0x00 11. " GMB331 ,Group Modifier Bit 331" "0,1" textline " " bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1" bitfld.long 0x00 9. " GMB329 ,Group Modifier Bit 329" "0,1" bitfld.long 0x00 8. " GMB328 ,Group Modifier Bit 328" "0,1" textline " " bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1" bitfld.long 0x00 6. " GMB326 ,Group Modifier Bit 326" "0,1" bitfld.long 0x00 5. " GMB325 ,Group Modifier Bit 325" "0,1" textline " " bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1" bitfld.long 0x00 3. " GMB323 ,Group Modifier Bit 323" "0,1" bitfld.long 0x00 2. " GMB322 ,Group Modifier Bit 322" "0,1" textline " " bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1" bitfld.long 0x00 0. " GMB320 ,Group Modifier Bit 320" "0,1" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)) group.long 0x0D2C++0x03 line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1" bitfld.long 0x00 30. " GMB382 ,Group Modifier Bit 382" "0,1" bitfld.long 0x00 29. " GMB381 ,Group Modifier Bit 381" "0,1" textline " " bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1" bitfld.long 0x00 27. " GMB379 ,Group Modifier Bit 379" "0,1" bitfld.long 0x00 26. " GMB378 ,Group Modifier Bit 378" "0,1" textline " " bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1" bitfld.long 0x00 24. " GMB376 ,Group Modifier Bit 376" "0,1" bitfld.long 0x00 23. " GMB375 ,Group Modifier Bit 375" "0,1" textline " " bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1" bitfld.long 0x00 21. " GMB373 ,Group Modifier Bit 373" "0,1" bitfld.long 0x00 20. " GMB372 ,Group Modifier Bit 372" "0,1" textline " " bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1" bitfld.long 0x00 18. " GMB370 ,Group Modifier Bit 370" "0,1" bitfld.long 0x00 17. " GMB369 ,Group Modifier Bit 369" "0,1" textline " " bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1" bitfld.long 0x00 15. " GMB367 ,Group Modifier Bit 367" "0,1" bitfld.long 0x00 14. " GMB366 ,Group Modifier Bit 366" "0,1" textline " " bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1" bitfld.long 0x00 12. " GMB364 ,Group Modifier Bit 364" "0,1" bitfld.long 0x00 11. " GMB363 ,Group Modifier Bit 363" "0,1" textline " " bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1" bitfld.long 0x00 9. " GMB361 ,Group Modifier Bit 361" "0,1" bitfld.long 0x00 8. " GMB360 ,Group Modifier Bit 360" "0,1" textline " " bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1" bitfld.long 0x00 6. " GMB358 ,Group Modifier Bit 358" "0,1" bitfld.long 0x00 5. " GMB357 ,Group Modifier Bit 357" "0,1" textline " " bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1" bitfld.long 0x00 3. " GMB355 ,Group Modifier Bit 355" "0,1" bitfld.long 0x00 2. " GMB354 ,Group Modifier Bit 354" "0,1" textline " " bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1" bitfld.long 0x00 0. " GMB352 ,Group Modifier Bit 352" "0,1" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)) group.long 0x0D30++0x03 line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1" bitfld.long 0x00 30. " GMB414 ,Group Modifier Bit 414" "0,1" bitfld.long 0x00 29. " GMB413 ,Group Modifier Bit 413" "0,1" textline " " bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1" bitfld.long 0x00 27. " GMB411 ,Group Modifier Bit 411" "0,1" bitfld.long 0x00 26. " GMB410 ,Group Modifier Bit 410" "0,1" textline " " bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1" bitfld.long 0x00 24. " GMB408 ,Group Modifier Bit 408" "0,1" bitfld.long 0x00 23. " GMB407 ,Group Modifier Bit 407" "0,1" textline " " bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1" bitfld.long 0x00 21. " GMB405 ,Group Modifier Bit 405" "0,1" bitfld.long 0x00 20. " GMB404 ,Group Modifier Bit 404" "0,1" textline " " bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1" bitfld.long 0x00 18. " GMB402 ,Group Modifier Bit 402" "0,1" bitfld.long 0x00 17. " GMB401 ,Group Modifier Bit 401" "0,1" textline " " bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1" bitfld.long 0x00 15. " GMB399 ,Group Modifier Bit 399" "0,1" bitfld.long 0x00 14. " GMB398 ,Group Modifier Bit 398" "0,1" textline " " bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1" bitfld.long 0x00 12. " GMB396 ,Group Modifier Bit 396" "0,1" bitfld.long 0x00 11. " GMB395 ,Group Modifier Bit 395" "0,1" textline " " bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1" bitfld.long 0x00 9. " GMB393 ,Group Modifier Bit 393" "0,1" bitfld.long 0x00 8. " GMB392 ,Group Modifier Bit 392" "0,1" textline " " bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1" bitfld.long 0x00 6. " GMB390 ,Group Modifier Bit 390" "0,1" bitfld.long 0x00 5. " GMB389 ,Group Modifier Bit 389" "0,1" textline " " bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1" bitfld.long 0x00 3. " GMB387 ,Group Modifier Bit 387" "0,1" bitfld.long 0x00 2. " GMB386 ,Group Modifier Bit 386" "0,1" textline " " bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1" bitfld.long 0x00 0. " GMB384 ,Group Modifier Bit 384" "0,1" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)) group.long 0x0D34++0x03 line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1" bitfld.long 0x00 30. " GMB446 ,Group Modifier Bit 446" "0,1" bitfld.long 0x00 29. " GMB445 ,Group Modifier Bit 445" "0,1" textline " " bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1" bitfld.long 0x00 27. " GMB443 ,Group Modifier Bit 443" "0,1" bitfld.long 0x00 26. " GMB442 ,Group Modifier Bit 442" "0,1" textline " " bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1" bitfld.long 0x00 24. " GMB440 ,Group Modifier Bit 440" "0,1" bitfld.long 0x00 23. " GMB439 ,Group Modifier Bit 439" "0,1" textline " " bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1" bitfld.long 0x00 21. " GMB437 ,Group Modifier Bit 437" "0,1" bitfld.long 0x00 20. " GMB436 ,Group Modifier Bit 436" "0,1" textline " " bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1" bitfld.long 0x00 18. " GMB434 ,Group Modifier Bit 434" "0,1" bitfld.long 0x00 17. " GMB433 ,Group Modifier Bit 433" "0,1" textline " " bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1" bitfld.long 0x00 15. " GMB431 ,Group Modifier Bit 431" "0,1" bitfld.long 0x00 14. " GMB430 ,Group Modifier Bit 430" "0,1" textline " " bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1" bitfld.long 0x00 12. " GMB428 ,Group Modifier Bit 428" "0,1" bitfld.long 0x00 11. " GMB427 ,Group Modifier Bit 427" "0,1" textline " " bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1" bitfld.long 0x00 9. " GMB425 ,Group Modifier Bit 425" "0,1" bitfld.long 0x00 8. " GMB424 ,Group Modifier Bit 424" "0,1" textline " " bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1" bitfld.long 0x00 6. " GMB422 ,Group Modifier Bit 422" "0,1" bitfld.long 0x00 5. " GMB421 ,Group Modifier Bit 421" "0,1" textline " " bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1" bitfld.long 0x00 3. " GMB419 ,Group Modifier Bit 419" "0,1" bitfld.long 0x00 2. " GMB418 ,Group Modifier Bit 418" "0,1" textline " " bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1" bitfld.long 0x00 0. " GMB416 ,Group Modifier Bit 416" "0,1" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)) group.long 0x0D38++0x03 line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1" bitfld.long 0x00 30. " GMB478 ,Group Modifier Bit 478" "0,1" bitfld.long 0x00 29. " GMB477 ,Group Modifier Bit 477" "0,1" textline " " bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1" bitfld.long 0x00 27. " GMB475 ,Group Modifier Bit 475" "0,1" bitfld.long 0x00 26. " GMB474 ,Group Modifier Bit 474" "0,1" textline " " bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1" bitfld.long 0x00 24. " GMB472 ,Group Modifier Bit 472" "0,1" bitfld.long 0x00 23. " GMB471 ,Group Modifier Bit 471" "0,1" textline " " bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1" bitfld.long 0x00 21. " GMB469 ,Group Modifier Bit 469" "0,1" bitfld.long 0x00 20. " GMB468 ,Group Modifier Bit 468" "0,1" textline " " bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1" bitfld.long 0x00 18. " GMB466 ,Group Modifier Bit 466" "0,1" bitfld.long 0x00 17. " GMB465 ,Group Modifier Bit 465" "0,1" textline " " bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1" bitfld.long 0x00 15. " GMB463 ,Group Modifier Bit 463" "0,1" bitfld.long 0x00 14. " GMB462 ,Group Modifier Bit 462" "0,1" textline " " bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1" bitfld.long 0x00 12. " GMB460 ,Group Modifier Bit 460" "0,1" bitfld.long 0x00 11. " GMB459 ,Group Modifier Bit 459" "0,1" textline " " bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1" bitfld.long 0x00 9. " GMB457 ,Group Modifier Bit 457" "0,1" bitfld.long 0x00 8. " GMB456 ,Group Modifier Bit 456" "0,1" textline " " bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1" bitfld.long 0x00 6. " GMB454 ,Group Modifier Bit 454" "0,1" bitfld.long 0x00 5. " GMB453 ,Group Modifier Bit 453" "0,1" textline " " bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1" bitfld.long 0x00 3. " GMB451 ,Group Modifier Bit 451" "0,1" bitfld.long 0x00 2. " GMB450 ,Group Modifier Bit 450" "0,1" textline " " bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1" bitfld.long 0x00 0. " GMB448 ,Group Modifier Bit 448" "0,1" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)) group.long 0x0D3C++0x03 line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1" bitfld.long 0x00 30. " GMB510 ,Group Modifier Bit 510" "0,1" bitfld.long 0x00 29. " GMB509 ,Group Modifier Bit 509" "0,1" textline " " bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1" bitfld.long 0x00 27. " GMB507 ,Group Modifier Bit 507" "0,1" bitfld.long 0x00 26. " GMB506 ,Group Modifier Bit 506" "0,1" textline " " bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1" bitfld.long 0x00 24. " GMB504 ,Group Modifier Bit 504" "0,1" bitfld.long 0x00 23. " GMB503 ,Group Modifier Bit 503" "0,1" textline " " bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1" bitfld.long 0x00 21. " GMB501 ,Group Modifier Bit 501" "0,1" bitfld.long 0x00 20. " GMB500 ,Group Modifier Bit 500" "0,1" textline " " bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1" bitfld.long 0x00 18. " GMB498 ,Group Modifier Bit 498" "0,1" bitfld.long 0x00 17. " GMB497 ,Group Modifier Bit 497" "0,1" textline " " bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1" bitfld.long 0x00 15. " GMB495 ,Group Modifier Bit 495" "0,1" bitfld.long 0x00 14. " GMB494 ,Group Modifier Bit 494" "0,1" textline " " bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1" bitfld.long 0x00 12. " GMB492 ,Group Modifier Bit 492" "0,1" bitfld.long 0x00 11. " GMB491 ,Group Modifier Bit 491" "0,1" textline " " bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1" bitfld.long 0x00 9. " GMB489 ,Group Modifier Bit 489" "0,1" bitfld.long 0x00 8. " GMB488 ,Group Modifier Bit 488" "0,1" textline " " bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1" bitfld.long 0x00 6. " GMB486 ,Group Modifier Bit 486" "0,1" bitfld.long 0x00 5. " GMB485 ,Group Modifier Bit 485" "0,1" textline " " bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1" bitfld.long 0x00 3. " GMB483 ,Group Modifier Bit 483" "0,1" bitfld.long 0x00 2. " GMB482 ,Group Modifier Bit 482" "0,1" textline " " bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1" bitfld.long 0x00 0. " GMB480 ,Group Modifier Bit 480" "0,1" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x0D40++0x03 line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1" bitfld.long 0x00 30. " GMB542 ,Group Modifier Bit 542" "0,1" bitfld.long 0x00 29. " GMB541 ,Group Modifier Bit 541" "0,1" textline " " bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1" bitfld.long 0x00 27. " GMB539 ,Group Modifier Bit 539" "0,1" bitfld.long 0x00 26. " GMB538 ,Group Modifier Bit 538" "0,1" textline " " bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1" bitfld.long 0x00 24. " GMB536 ,Group Modifier Bit 536" "0,1" bitfld.long 0x00 23. " GMB535 ,Group Modifier Bit 535" "0,1" textline " " bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1" bitfld.long 0x00 21. " GMB533 ,Group Modifier Bit 533" "0,1" bitfld.long 0x00 20. " GMB532 ,Group Modifier Bit 532" "0,1" textline " " bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1" bitfld.long 0x00 18. " GMB530 ,Group Modifier Bit 530" "0,1" bitfld.long 0x00 17. " GMB529 ,Group Modifier Bit 529" "0,1" textline " " bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1" bitfld.long 0x00 15. " GMB527 ,Group Modifier Bit 527" "0,1" bitfld.long 0x00 14. " GMB526 ,Group Modifier Bit 526" "0,1" textline " " bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1" bitfld.long 0x00 12. " GMB524 ,Group Modifier Bit 524" "0,1" bitfld.long 0x00 11. " GMB523 ,Group Modifier Bit 523" "0,1" textline " " bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1" bitfld.long 0x00 9. " GMB521 ,Group Modifier Bit 521" "0,1" bitfld.long 0x00 8. " GMB520 ,Group Modifier Bit 520" "0,1" textline " " bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1" bitfld.long 0x00 6. " GMB518 ,Group Modifier Bit 518" "0,1" bitfld.long 0x00 5. " GMB517 ,Group Modifier Bit 517" "0,1" textline " " bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1" bitfld.long 0x00 3. " GMB515 ,Group Modifier Bit 515" "0,1" bitfld.long 0x00 2. " GMB514 ,Group Modifier Bit 514" "0,1" textline " " bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1" bitfld.long 0x00 0. " GMB512 ,Group Modifier Bit 512" "0,1" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x0D44++0x03 line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1" bitfld.long 0x00 30. " GMB574 ,Group Modifier Bit 574" "0,1" bitfld.long 0x00 29. " GMB573 ,Group Modifier Bit 573" "0,1" textline " " bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1" bitfld.long 0x00 27. " GMB571 ,Group Modifier Bit 571" "0,1" bitfld.long 0x00 26. " GMB570 ,Group Modifier Bit 570" "0,1" textline " " bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1" bitfld.long 0x00 24. " GMB568 ,Group Modifier Bit 568" "0,1" bitfld.long 0x00 23. " GMB567 ,Group Modifier Bit 567" "0,1" textline " " bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1" bitfld.long 0x00 21. " GMB565 ,Group Modifier Bit 565" "0,1" bitfld.long 0x00 20. " GMB564 ,Group Modifier Bit 564" "0,1" textline " " bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1" bitfld.long 0x00 18. " GMB562 ,Group Modifier Bit 562" "0,1" bitfld.long 0x00 17. " GMB561 ,Group Modifier Bit 561" "0,1" textline " " bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1" bitfld.long 0x00 15. " GMB559 ,Group Modifier Bit 559" "0,1" bitfld.long 0x00 14. " GMB558 ,Group Modifier Bit 558" "0,1" textline " " bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1" bitfld.long 0x00 12. " GMB556 ,Group Modifier Bit 556" "0,1" bitfld.long 0x00 11. " GMB555 ,Group Modifier Bit 555" "0,1" textline " " bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1" bitfld.long 0x00 9. " GMB553 ,Group Modifier Bit 553" "0,1" bitfld.long 0x00 8. " GMB552 ,Group Modifier Bit 552" "0,1" textline " " bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1" bitfld.long 0x00 6. " GMB550 ,Group Modifier Bit 550" "0,1" bitfld.long 0x00 5. " GMB549 ,Group Modifier Bit 549" "0,1" textline " " bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1" bitfld.long 0x00 3. " GMB547 ,Group Modifier Bit 547" "0,1" bitfld.long 0x00 2. " GMB546 ,Group Modifier Bit 546" "0,1" textline " " bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1" bitfld.long 0x00 0. " GMB544 ,Group Modifier Bit 544" "0,1" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x0D48++0x03 line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1" bitfld.long 0x00 30. " GMB606 ,Group Modifier Bit 606" "0,1" bitfld.long 0x00 29. " GMB605 ,Group Modifier Bit 605" "0,1" textline " " bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1" bitfld.long 0x00 27. " GMB603 ,Group Modifier Bit 603" "0,1" bitfld.long 0x00 26. " GMB602 ,Group Modifier Bit 602" "0,1" textline " " bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1" bitfld.long 0x00 24. " GMB600 ,Group Modifier Bit 600" "0,1" bitfld.long 0x00 23. " GMB599 ,Group Modifier Bit 599" "0,1" textline " " bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1" bitfld.long 0x00 21. " GMB597 ,Group Modifier Bit 597" "0,1" bitfld.long 0x00 20. " GMB596 ,Group Modifier Bit 596" "0,1" textline " " bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1" bitfld.long 0x00 18. " GMB594 ,Group Modifier Bit 594" "0,1" bitfld.long 0x00 17. " GMB593 ,Group Modifier Bit 593" "0,1" textline " " bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1" bitfld.long 0x00 15. " GMB591 ,Group Modifier Bit 591" "0,1" bitfld.long 0x00 14. " GMB590 ,Group Modifier Bit 590" "0,1" textline " " bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1" bitfld.long 0x00 12. " GMB588 ,Group Modifier Bit 588" "0,1" bitfld.long 0x00 11. " GMB587 ,Group Modifier Bit 587" "0,1" textline " " bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1" bitfld.long 0x00 9. " GMB585 ,Group Modifier Bit 585" "0,1" bitfld.long 0x00 8. " GMB584 ,Group Modifier Bit 584" "0,1" textline " " bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1" bitfld.long 0x00 6. " GMB582 ,Group Modifier Bit 582" "0,1" bitfld.long 0x00 5. " GMB581 ,Group Modifier Bit 581" "0,1" textline " " bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1" bitfld.long 0x00 3. " GMB579 ,Group Modifier Bit 579" "0,1" bitfld.long 0x00 2. " GMB578 ,Group Modifier Bit 578" "0,1" textline " " bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1" bitfld.long 0x00 0. " GMB576 ,Group Modifier Bit 576" "0,1" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x0D4C++0x03 line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1" bitfld.long 0x00 30. " GMB638 ,Group Modifier Bit 638" "0,1" bitfld.long 0x00 29. " GMB637 ,Group Modifier Bit 637" "0,1" textline " " bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1" bitfld.long 0x00 27. " GMB635 ,Group Modifier Bit 635" "0,1" bitfld.long 0x00 26. " GMB634 ,Group Modifier Bit 634" "0,1" textline " " bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1" bitfld.long 0x00 24. " GMB632 ,Group Modifier Bit 632" "0,1" bitfld.long 0x00 23. " GMB631 ,Group Modifier Bit 631" "0,1" textline " " bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1" bitfld.long 0x00 21. " GMB629 ,Group Modifier Bit 629" "0,1" bitfld.long 0x00 20. " GMB628 ,Group Modifier Bit 628" "0,1" textline " " bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1" bitfld.long 0x00 18. " GMB626 ,Group Modifier Bit 626" "0,1" bitfld.long 0x00 17. " GMB625 ,Group Modifier Bit 625" "0,1" textline " " bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1" bitfld.long 0x00 15. " GMB623 ,Group Modifier Bit 623" "0,1" bitfld.long 0x00 14. " GMB622 ,Group Modifier Bit 622" "0,1" textline " " bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1" bitfld.long 0x00 12. " GMB620 ,Group Modifier Bit 620" "0,1" bitfld.long 0x00 11. " GMB619 ,Group Modifier Bit 619" "0,1" textline " " bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1" bitfld.long 0x00 9. " GMB617 ,Group Modifier Bit 617" "0,1" bitfld.long 0x00 8. " GMB616 ,Group Modifier Bit 616" "0,1" textline " " bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1" bitfld.long 0x00 6. " GMB614 ,Group Modifier Bit 614" "0,1" bitfld.long 0x00 5. " GMB613 ,Group Modifier Bit 613" "0,1" textline " " bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1" bitfld.long 0x00 3. " GMB611 ,Group Modifier Bit 611" "0,1" bitfld.long 0x00 2. " GMB610 ,Group Modifier Bit 610" "0,1" textline " " bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1" bitfld.long 0x00 0. " GMB608 ,Group Modifier Bit 608" "0,1" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x0D50++0x03 line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1" bitfld.long 0x00 30. " GMB670 ,Group Modifier Bit 670" "0,1" bitfld.long 0x00 29. " GMB669 ,Group Modifier Bit 669" "0,1" textline " " bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1" bitfld.long 0x00 27. " GMB667 ,Group Modifier Bit 667" "0,1" bitfld.long 0x00 26. " GMB666 ,Group Modifier Bit 666" "0,1" textline " " bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1" bitfld.long 0x00 24. " GMB664 ,Group Modifier Bit 664" "0,1" bitfld.long 0x00 23. " GMB663 ,Group Modifier Bit 663" "0,1" textline " " bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1" bitfld.long 0x00 21. " GMB661 ,Group Modifier Bit 661" "0,1" bitfld.long 0x00 20. " GMB660 ,Group Modifier Bit 660" "0,1" textline " " bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1" bitfld.long 0x00 18. " GMB658 ,Group Modifier Bit 658" "0,1" bitfld.long 0x00 17. " GMB657 ,Group Modifier Bit 657" "0,1" textline " " bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1" bitfld.long 0x00 15. " GMB655 ,Group Modifier Bit 655" "0,1" bitfld.long 0x00 14. " GMB654 ,Group Modifier Bit 654" "0,1" textline " " bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1" bitfld.long 0x00 12. " GMB652 ,Group Modifier Bit 652" "0,1" bitfld.long 0x00 11. " GMB651 ,Group Modifier Bit 651" "0,1" textline " " bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1" bitfld.long 0x00 9. " GMB649 ,Group Modifier Bit 649" "0,1" bitfld.long 0x00 8. " GMB648 ,Group Modifier Bit 648" "0,1" textline " " bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1" bitfld.long 0x00 6. " GMB646 ,Group Modifier Bit 646" "0,1" bitfld.long 0x00 5. " GMB645 ,Group Modifier Bit 645" "0,1" textline " " bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1" bitfld.long 0x00 3. " GMB643 ,Group Modifier Bit 643" "0,1" bitfld.long 0x00 2. " GMB642 ,Group Modifier Bit 642" "0,1" textline " " bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1" bitfld.long 0x00 0. " GMB640 ,Group Modifier Bit 640" "0,1" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x0D54++0x03 line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1" bitfld.long 0x00 30. " GMB702 ,Group Modifier Bit 702" "0,1" bitfld.long 0x00 29. " GMB701 ,Group Modifier Bit 701" "0,1" textline " " bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1" bitfld.long 0x00 27. " GMB699 ,Group Modifier Bit 699" "0,1" bitfld.long 0x00 26. " GMB698 ,Group Modifier Bit 698" "0,1" textline " " bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1" bitfld.long 0x00 24. " GMB696 ,Group Modifier Bit 696" "0,1" bitfld.long 0x00 23. " GMB695 ,Group Modifier Bit 695" "0,1" textline " " bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1" bitfld.long 0x00 21. " GMB693 ,Group Modifier Bit 693" "0,1" bitfld.long 0x00 20. " GMB692 ,Group Modifier Bit 692" "0,1" textline " " bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1" bitfld.long 0x00 18. " GMB690 ,Group Modifier Bit 690" "0,1" bitfld.long 0x00 17. " GMB689 ,Group Modifier Bit 689" "0,1" textline " " bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1" bitfld.long 0x00 15. " GMB687 ,Group Modifier Bit 687" "0,1" bitfld.long 0x00 14. " GMB686 ,Group Modifier Bit 686" "0,1" textline " " bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1" bitfld.long 0x00 12. " GMB684 ,Group Modifier Bit 684" "0,1" bitfld.long 0x00 11. " GMB683 ,Group Modifier Bit 683" "0,1" textline " " bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1" bitfld.long 0x00 9. " GMB681 ,Group Modifier Bit 681" "0,1" bitfld.long 0x00 8. " GMB680 ,Group Modifier Bit 680" "0,1" textline " " bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1" bitfld.long 0x00 6. " GMB678 ,Group Modifier Bit 678" "0,1" bitfld.long 0x00 5. " GMB677 ,Group Modifier Bit 677" "0,1" textline " " bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1" bitfld.long 0x00 3. " GMB675 ,Group Modifier Bit 675" "0,1" bitfld.long 0x00 2. " GMB674 ,Group Modifier Bit 674" "0,1" textline " " bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1" bitfld.long 0x00 0. " GMB672 ,Group Modifier Bit 672" "0,1" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x0D58++0x03 line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1" bitfld.long 0x00 30. " GMB734 ,Group Modifier Bit 734" "0,1" bitfld.long 0x00 29. " GMB733 ,Group Modifier Bit 733" "0,1" textline " " bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1" bitfld.long 0x00 27. " GMB731 ,Group Modifier Bit 731" "0,1" bitfld.long 0x00 26. " GMB730 ,Group Modifier Bit 730" "0,1" textline " " bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1" bitfld.long 0x00 24. " GMB728 ,Group Modifier Bit 728" "0,1" bitfld.long 0x00 23. " GMB727 ,Group Modifier Bit 727" "0,1" textline " " bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1" bitfld.long 0x00 21. " GMB725 ,Group Modifier Bit 725" "0,1" bitfld.long 0x00 20. " GMB724 ,Group Modifier Bit 724" "0,1" textline " " bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1" bitfld.long 0x00 18. " GMB722 ,Group Modifier Bit 722" "0,1" bitfld.long 0x00 17. " GMB721 ,Group Modifier Bit 721" "0,1" textline " " bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1" bitfld.long 0x00 15. " GMB719 ,Group Modifier Bit 719" "0,1" bitfld.long 0x00 14. " GMB718 ,Group Modifier Bit 718" "0,1" textline " " bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1" bitfld.long 0x00 12. " GMB716 ,Group Modifier Bit 716" "0,1" bitfld.long 0x00 11. " GMB715 ,Group Modifier Bit 715" "0,1" textline " " bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1" bitfld.long 0x00 9. " GMB713 ,Group Modifier Bit 713" "0,1" bitfld.long 0x00 8. " GMB712 ,Group Modifier Bit 712" "0,1" textline " " bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1" bitfld.long 0x00 6. " GMB710 ,Group Modifier Bit 710" "0,1" bitfld.long 0x00 5. " GMB709 ,Group Modifier Bit 709" "0,1" textline " " bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1" bitfld.long 0x00 3. " GMB707 ,Group Modifier Bit 707" "0,1" bitfld.long 0x00 2. " GMB706 ,Group Modifier Bit 706" "0,1" textline " " bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1" bitfld.long 0x00 0. " GMB704 ,Group Modifier Bit 704" "0,1" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x0D5C++0x03 line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1" bitfld.long 0x00 30. " GMB766 ,Group Modifier Bit 766" "0,1" bitfld.long 0x00 29. " GMB765 ,Group Modifier Bit 765" "0,1" textline " " bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1" bitfld.long 0x00 27. " GMB763 ,Group Modifier Bit 763" "0,1" bitfld.long 0x00 26. " GMB762 ,Group Modifier Bit 762" "0,1" textline " " bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1" bitfld.long 0x00 24. " GMB760 ,Group Modifier Bit 760" "0,1" bitfld.long 0x00 23. " GMB759 ,Group Modifier Bit 759" "0,1" textline " " bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1" bitfld.long 0x00 21. " GMB757 ,Group Modifier Bit 757" "0,1" bitfld.long 0x00 20. " GMB756 ,Group Modifier Bit 756" "0,1" textline " " bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1" bitfld.long 0x00 18. " GMB754 ,Group Modifier Bit 754" "0,1" bitfld.long 0x00 17. " GMB753 ,Group Modifier Bit 753" "0,1" textline " " bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1" bitfld.long 0x00 15. " GMB751 ,Group Modifier Bit 751" "0,1" bitfld.long 0x00 14. " GMB750 ,Group Modifier Bit 750" "0,1" textline " " bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1" bitfld.long 0x00 12. " GMB748 ,Group Modifier Bit 748" "0,1" bitfld.long 0x00 11. " GMB747 ,Group Modifier Bit 747" "0,1" textline " " bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1" bitfld.long 0x00 9. " GMB745 ,Group Modifier Bit 745" "0,1" bitfld.long 0x00 8. " GMB744 ,Group Modifier Bit 744" "0,1" textline " " bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1" bitfld.long 0x00 6. " GMB742 ,Group Modifier Bit 742" "0,1" bitfld.long 0x00 5. " GMB741 ,Group Modifier Bit 741" "0,1" textline " " bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1" bitfld.long 0x00 3. " GMB739 ,Group Modifier Bit 739" "0,1" bitfld.long 0x00 2. " GMB738 ,Group Modifier Bit 738" "0,1" textline " " bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1" bitfld.long 0x00 0. " GMB736 ,Group Modifier Bit 736" "0,1" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x0D60++0x03 line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1" bitfld.long 0x00 30. " GMB798 ,Group Modifier Bit 798" "0,1" bitfld.long 0x00 29. " GMB797 ,Group Modifier Bit 797" "0,1" textline " " bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1" bitfld.long 0x00 27. " GMB795 ,Group Modifier Bit 795" "0,1" bitfld.long 0x00 26. " GMB794 ,Group Modifier Bit 794" "0,1" textline " " bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1" bitfld.long 0x00 24. " GMB792 ,Group Modifier Bit 792" "0,1" bitfld.long 0x00 23. " GMB791 ,Group Modifier Bit 791" "0,1" textline " " bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1" bitfld.long 0x00 21. " GMB789 ,Group Modifier Bit 789" "0,1" bitfld.long 0x00 20. " GMB788 ,Group Modifier Bit 788" "0,1" textline " " bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1" bitfld.long 0x00 18. " GMB786 ,Group Modifier Bit 786" "0,1" bitfld.long 0x00 17. " GMB785 ,Group Modifier Bit 785" "0,1" textline " " bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1" bitfld.long 0x00 15. " GMB783 ,Group Modifier Bit 783" "0,1" bitfld.long 0x00 14. " GMB782 ,Group Modifier Bit 782" "0,1" textline " " bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1" bitfld.long 0x00 12. " GMB780 ,Group Modifier Bit 780" "0,1" bitfld.long 0x00 11. " GMB779 ,Group Modifier Bit 779" "0,1" textline " " bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1" bitfld.long 0x00 9. " GMB777 ,Group Modifier Bit 777" "0,1" bitfld.long 0x00 8. " GMB776 ,Group Modifier Bit 776" "0,1" textline " " bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1" bitfld.long 0x00 6. " GMB774 ,Group Modifier Bit 774" "0,1" bitfld.long 0x00 5. " GMB773 ,Group Modifier Bit 773" "0,1" textline " " bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1" bitfld.long 0x00 3. " GMB771 ,Group Modifier Bit 771" "0,1" bitfld.long 0x00 2. " GMB770 ,Group Modifier Bit 770" "0,1" textline " " bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1" bitfld.long 0x00 0. " GMB768 ,Group Modifier Bit 768" "0,1" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x0D64++0x03 line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1" bitfld.long 0x00 30. " GMB830 ,Group Modifier Bit 830" "0,1" bitfld.long 0x00 29. " GMB829 ,Group Modifier Bit 829" "0,1" textline " " bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1" bitfld.long 0x00 27. " GMB827 ,Group Modifier Bit 827" "0,1" bitfld.long 0x00 26. " GMB826 ,Group Modifier Bit 826" "0,1" textline " " bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1" bitfld.long 0x00 24. " GMB824 ,Group Modifier Bit 824" "0,1" bitfld.long 0x00 23. " GMB823 ,Group Modifier Bit 823" "0,1" textline " " bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1" bitfld.long 0x00 21. " GMB821 ,Group Modifier Bit 821" "0,1" bitfld.long 0x00 20. " GMB820 ,Group Modifier Bit 820" "0,1" textline " " bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1" bitfld.long 0x00 18. " GMB818 ,Group Modifier Bit 818" "0,1" bitfld.long 0x00 17. " GMB817 ,Group Modifier Bit 817" "0,1" textline " " bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1" bitfld.long 0x00 15. " GMB815 ,Group Modifier Bit 815" "0,1" bitfld.long 0x00 14. " GMB814 ,Group Modifier Bit 814" "0,1" textline " " bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1" bitfld.long 0x00 12. " GMB812 ,Group Modifier Bit 812" "0,1" bitfld.long 0x00 11. " GMB811 ,Group Modifier Bit 811" "0,1" textline " " bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1" bitfld.long 0x00 9. " GMB809 ,Group Modifier Bit 809" "0,1" bitfld.long 0x00 8. " GMB808 ,Group Modifier Bit 808" "0,1" textline " " bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1" bitfld.long 0x00 6. " GMB806 ,Group Modifier Bit 806" "0,1" bitfld.long 0x00 5. " GMB805 ,Group Modifier Bit 805" "0,1" textline " " bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1" bitfld.long 0x00 3. " GMB803 ,Group Modifier Bit 803" "0,1" bitfld.long 0x00 2. " GMB802 ,Group Modifier Bit 802" "0,1" textline " " bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1" bitfld.long 0x00 0. " GMB800 ,Group Modifier Bit 800" "0,1" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A)) group.long 0x0D68++0x03 line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1" bitfld.long 0x00 30. " GMB862 ,Group Modifier Bit 862" "0,1" bitfld.long 0x00 29. " GMB861 ,Group Modifier Bit 861" "0,1" textline " " bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1" bitfld.long 0x00 27. " GMB859 ,Group Modifier Bit 859" "0,1" bitfld.long 0x00 26. " GMB858 ,Group Modifier Bit 858" "0,1" textline " " bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1" bitfld.long 0x00 24. " GMB856 ,Group Modifier Bit 856" "0,1" bitfld.long 0x00 23. " GMB855 ,Group Modifier Bit 855" "0,1" textline " " bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1" bitfld.long 0x00 21. " GMB853 ,Group Modifier Bit 853" "0,1" bitfld.long 0x00 20. " GMB852 ,Group Modifier Bit 852" "0,1" textline " " bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1" bitfld.long 0x00 18. " GMB850 ,Group Modifier Bit 850" "0,1" bitfld.long 0x00 17. " GMB849 ,Group Modifier Bit 849" "0,1" textline " " bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1" bitfld.long 0x00 15. " GMB847 ,Group Modifier Bit 847" "0,1" bitfld.long 0x00 14. " GMB846 ,Group Modifier Bit 846" "0,1" textline " " bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1" bitfld.long 0x00 12. " GMB844 ,Group Modifier Bit 844" "0,1" bitfld.long 0x00 11. " GMB843 ,Group Modifier Bit 843" "0,1" textline " " bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1" bitfld.long 0x00 9. " GMB841 ,Group Modifier Bit 841" "0,1" bitfld.long 0x00 8. " GMB840 ,Group Modifier Bit 840" "0,1" textline " " bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1" bitfld.long 0x00 6. " GMB838 ,Group Modifier Bit 838" "0,1" bitfld.long 0x00 5. " GMB837 ,Group Modifier Bit 837" "0,1" textline " " bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1" bitfld.long 0x00 3. " GMB835 ,Group Modifier Bit 835" "0,1" bitfld.long 0x00 2. " GMB834 ,Group Modifier Bit 834" "0,1" textline " " bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1" bitfld.long 0x00 0. " GMB832 ,Group Modifier Bit 832" "0,1" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x0D6C++0x03 line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1" bitfld.long 0x00 30. " GMB894 ,Group Modifier Bit 894" "0,1" bitfld.long 0x00 29. " GMB893 ,Group Modifier Bit 893" "0,1" textline " " bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1" bitfld.long 0x00 27. " GMB891 ,Group Modifier Bit 891" "0,1" bitfld.long 0x00 26. " GMB890 ,Group Modifier Bit 890" "0,1" textline " " bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1" bitfld.long 0x00 24. " GMB888 ,Group Modifier Bit 888" "0,1" bitfld.long 0x00 23. " GMB887 ,Group Modifier Bit 887" "0,1" textline " " bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1" bitfld.long 0x00 21. " GMB885 ,Group Modifier Bit 885" "0,1" bitfld.long 0x00 20. " GMB884 ,Group Modifier Bit 884" "0,1" textline " " bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1" bitfld.long 0x00 18. " GMB882 ,Group Modifier Bit 882" "0,1" bitfld.long 0x00 17. " GMB881 ,Group Modifier Bit 881" "0,1" textline " " bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1" bitfld.long 0x00 15. " GMB879 ,Group Modifier Bit 879" "0,1" bitfld.long 0x00 14. " GMB878 ,Group Modifier Bit 878" "0,1" textline " " bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1" bitfld.long 0x00 12. " GMB876 ,Group Modifier Bit 876" "0,1" bitfld.long 0x00 11. " GMB875 ,Group Modifier Bit 875" "0,1" textline " " bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1" bitfld.long 0x00 9. " GMB873 ,Group Modifier Bit 873" "0,1" bitfld.long 0x00 8. " GMB872 ,Group Modifier Bit 872" "0,1" textline " " bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1" bitfld.long 0x00 6. " GMB870 ,Group Modifier Bit 870" "0,1" bitfld.long 0x00 5. " GMB869 ,Group Modifier Bit 869" "0,1" textline " " bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1" bitfld.long 0x00 3. " GMB867 ,Group Modifier Bit 867" "0,1" bitfld.long 0x00 2. " GMB866 ,Group Modifier Bit 866" "0,1" textline " " bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1" bitfld.long 0x00 0. " GMB864 ,Group Modifier Bit 864" "0,1" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x0D70++0x03 line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1" bitfld.long 0x00 30. " GMB926 ,Group Modifier Bit 926" "0,1" bitfld.long 0x00 29. " GMB925 ,Group Modifier Bit 925" "0,1" textline " " bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1" bitfld.long 0x00 27. " GMB923 ,Group Modifier Bit 923" "0,1" bitfld.long 0x00 26. " GMB922 ,Group Modifier Bit 922" "0,1" textline " " bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1" bitfld.long 0x00 24. " GMB920 ,Group Modifier Bit 920" "0,1" bitfld.long 0x00 23. " GMB919 ,Group Modifier Bit 919" "0,1" textline " " bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1" bitfld.long 0x00 21. " GMB917 ,Group Modifier Bit 917" "0,1" bitfld.long 0x00 20. " GMB916 ,Group Modifier Bit 916" "0,1" textline " " bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1" bitfld.long 0x00 18. " GMB914 ,Group Modifier Bit 914" "0,1" bitfld.long 0x00 17. " GMB913 ,Group Modifier Bit 913" "0,1" textline " " bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1" bitfld.long 0x00 15. " GMB911 ,Group Modifier Bit 911" "0,1" bitfld.long 0x00 14. " GMB910 ,Group Modifier Bit 910" "0,1" textline " " bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1" bitfld.long 0x00 12. " GMB908 ,Group Modifier Bit 908" "0,1" bitfld.long 0x00 11. " GMB907 ,Group Modifier Bit 907" "0,1" textline " " bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1" bitfld.long 0x00 9. " GMB905 ,Group Modifier Bit 905" "0,1" bitfld.long 0x00 8. " GMB904 ,Group Modifier Bit 904" "0,1" textline " " bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1" bitfld.long 0x00 6. " GMB902 ,Group Modifier Bit 902" "0,1" bitfld.long 0x00 5. " GMB901 ,Group Modifier Bit 901" "0,1" textline " " bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1" bitfld.long 0x00 3. " GMB899 ,Group Modifier Bit 899" "0,1" bitfld.long 0x00 2. " GMB898 ,Group Modifier Bit 898" "0,1" textline " " bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1" bitfld.long 0x00 0. " GMB896 ,Group Modifier Bit 896" "0,1" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x0D74++0x03 line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1" bitfld.long 0x00 30. " GMB958 ,Group Modifier Bit 958" "0,1" bitfld.long 0x00 29. " GMB957 ,Group Modifier Bit 957" "0,1" textline " " bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1" bitfld.long 0x00 27. " GMB955 ,Group Modifier Bit 955" "0,1" bitfld.long 0x00 26. " GMB954 ,Group Modifier Bit 954" "0,1" textline " " bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1" bitfld.long 0x00 24. " GMB952 ,Group Modifier Bit 952" "0,1" bitfld.long 0x00 23. " GMB951 ,Group Modifier Bit 951" "0,1" textline " " bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1" bitfld.long 0x00 21. " GMB949 ,Group Modifier Bit 949" "0,1" bitfld.long 0x00 20. " GMB948 ,Group Modifier Bit 948" "0,1" textline " " bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1" bitfld.long 0x00 18. " GMB946 ,Group Modifier Bit 946" "0,1" bitfld.long 0x00 17. " GMB945 ,Group Modifier Bit 945" "0,1" textline " " bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1" bitfld.long 0x00 15. " GMB943 ,Group Modifier Bit 943" "0,1" bitfld.long 0x00 14. " GMB942 ,Group Modifier Bit 942" "0,1" textline " " bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1" bitfld.long 0x00 12. " GMB940 ,Group Modifier Bit 940" "0,1" bitfld.long 0x00 11. " GMB939 ,Group Modifier Bit 939" "0,1" textline " " bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1" bitfld.long 0x00 9. " GMB937 ,Group Modifier Bit 937" "0,1" bitfld.long 0x00 8. " GMB936 ,Group Modifier Bit 936" "0,1" textline " " bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1" bitfld.long 0x00 6. " GMB934 ,Group Modifier Bit 934" "0,1" bitfld.long 0x00 5. " GMB933 ,Group Modifier Bit 933" "0,1" textline " " bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1" bitfld.long 0x00 3. " GMB931 ,Group Modifier Bit 931" "0,1" bitfld.long 0x00 2. " GMB930 ,Group Modifier Bit 930" "0,1" textline " " bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1" bitfld.long 0x00 0. " GMB928 ,Group Modifier Bit 928" "0,1" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x0D78++0x03 line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1" bitfld.long 0x00 30. " GMB990 ,Group Modifier Bit 990" "0,1" bitfld.long 0x00 29. " GMB989 ,Group Modifier Bit 989" "0,1" textline " " bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1" bitfld.long 0x00 27. " GMB987 ,Group Modifier Bit 987" "0,1" bitfld.long 0x00 26. " GMB986 ,Group Modifier Bit 986" "0,1" textline " " bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1" bitfld.long 0x00 24. " GMB984 ,Group Modifier Bit 984" "0,1" bitfld.long 0x00 23. " GMB983 ,Group Modifier Bit 983" "0,1" textline " " bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1" bitfld.long 0x00 21. " GMB981 ,Group Modifier Bit 981" "0,1" bitfld.long 0x00 20. " GMB980 ,Group Modifier Bit 980" "0,1" textline " " bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1" bitfld.long 0x00 18. " GMB978 ,Group Modifier Bit 978" "0,1" bitfld.long 0x00 17. " GMB977 ,Group Modifier Bit 977" "0,1" textline " " bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1" bitfld.long 0x00 15. " GMB975 ,Group Modifier Bit 975" "0,1" bitfld.long 0x00 14. " GMB974 ,Group Modifier Bit 974" "0,1" textline " " bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1" bitfld.long 0x00 12. " GMB972 ,Group Modifier Bit 972" "0,1" bitfld.long 0x00 11. " GMB971 ,Group Modifier Bit 971" "0,1" textline " " bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1" bitfld.long 0x00 9. " GMB969 ,Group Modifier Bit 969" "0,1" bitfld.long 0x00 8. " GMB968 ,Group Modifier Bit 968" "0,1" textline " " bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1" bitfld.long 0x00 6. " GMB966 ,Group Modifier Bit 966" "0,1" bitfld.long 0x00 5. " GMB965 ,Group Modifier Bit 965" "0,1" textline " " bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1" bitfld.long 0x00 3. " GMB963 ,Group Modifier Bit 963" "0,1" bitfld.long 0x00 2. " GMB962 ,Group Modifier Bit 962" "0,1" textline " " bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1" bitfld.long 0x00 0. " GMB960 ,Group Modifier Bit 960" "0,1" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" endif tree.end width 14. tree "Non-secure Access Control Registers" hgroup.long 0x0E00++0x03 hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0" hgroup.long 0xE04++0x03 hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08))) group.long 0xE08++0x03 line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" bitfld.long 0x00 30.--31. " NS_ACCESS47 ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS46 ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS45 ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS44 ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS43 ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS42 ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS41 ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS40 ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS39 ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS38 ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS37 ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS36 ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS35 ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS34 ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS33 ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS32 ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE08++0x03 hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C))) group.long 0xE0C++0x03 line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" bitfld.long 0x00 30.--31. " NS_ACCESS63 ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS62 ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS61 ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS60 ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS59 ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS58 ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS57 ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS56 ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS55 ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS54 ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS53 ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS52 ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS51 ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS50 ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS49 ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS48 ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE0C++0x03 hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10))) group.long 0xE10++0x03 line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" bitfld.long 0x00 30.--31. " NS_ACCESS79 ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS78 ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS77 ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS76 ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS75 ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS74 ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS73 ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS72 ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS71 ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS70 ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS69 ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS68 ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS67 ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS66 ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS65 ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS64 ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE10++0x03 hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14))) group.long 0xE14++0x03 line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" bitfld.long 0x00 30.--31. " NS_ACCESS95 ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS94 ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS93 ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS92 ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS91 ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS90 ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS89 ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS88 ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS87 ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS86 ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS85 ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS84 ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS83 ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS82 ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS81 ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS80 ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE14++0x03 hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18))) group.long 0xE18++0x03 line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS99 ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS98 ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS97 ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS96 ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE18++0x03 hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C))) group.long 0xE1C++0x03 line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE1C++0x03 hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20))) group.long 0xE20++0x03 line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE20++0x03 hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24))) group.long 0xE24++0x03 line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE24++0x03 hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28))) group.long 0xE28++0x03 line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE28++0x03 hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C))) group.long 0xE2C++0x03 line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE2C++0x03 hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30))) group.long 0xE30++0x03 line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE30++0x03 hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34))) group.long 0xE34++0x03 line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE34++0x03 hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38))) group.long 0xE38++0x03 line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE38++0x03 hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C))) group.long 0xE3C++0x03 line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE3C++0x03 hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40))) group.long 0xE40++0x03 line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE40++0x03 hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44))) group.long 0xE44++0x03 line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE44++0x03 hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48))) group.long 0xE48++0x03 line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE48++0x03 hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C))) group.long 0xE4C++0x03 line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE4C++0x03 hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50))) group.long 0xE50++0x03 line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE50++0x03 hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54))) group.long 0xE54++0x03 line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE54++0x03 hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58))) group.long 0xE58++0x03 line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE58++0x03 hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C))) group.long 0xE5C++0x03 line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE5C++0x03 hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60))) group.long 0xE60++0x03 line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE60++0x03 hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64))) group.long 0xE64++0x03 line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE64++0x03 hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68))) group.long 0xE68++0x03 line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE68++0x03 hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C))) group.long 0xE6C++0x03 line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE6C++0x03 hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70))) group.long 0xE70++0x03 line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE70++0x03 hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74))) group.long 0xE74++0x03 line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE74++0x03 hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78))) group.long 0xE78++0x03 line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE78++0x03 hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C))) group.long 0xE7C++0x03 line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE7C++0x03 hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80))) group.long 0xE80++0x03 line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE80++0x03 hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84))) group.long 0xE84++0x03 line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE84++0x03 hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88))) group.long 0xE88++0x03 line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE88++0x03 hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C))) group.long 0xE8C++0x03 line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE8C++0x03 hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90))) group.long 0xE90++0x03 line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE90++0x03 hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94))) group.long 0xE94++0x03 line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE94++0x03 hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98))) group.long 0xE98++0x03 line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE98++0x03 hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C))) group.long 0xE9C++0x03 line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE9C++0x03 hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0))) group.long 0xEA0++0x03 line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA0++0x03 hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4))) group.long 0xEA4++0x03 line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA4++0x03 hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8))) group.long 0xEA8++0x03 line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA8++0x03 hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC))) group.long 0xEAC++0x03 line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEAC++0x03 hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0))) group.long 0xEB0++0x03 line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB0++0x03 hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4))) group.long 0xEB4++0x03 line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB4++0x03 hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8))) group.long 0xEB8++0x03 line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB8++0x03 hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC))) group.long 0xEBC++0x03 line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEBC++0x03 hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0))) group.long 0xEC0++0x03 line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC0++0x03 hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4))) group.long 0xEC4++0x03 line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC4++0x03 hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8))) group.long 0xEC8++0x03 line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC8++0x03 hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC))) group.long 0xECC++0x03 line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xECC++0x03 hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0))) group.long 0xED0++0x03 line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED0++0x03 hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4))) group.long 0xED4++0x03 line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED4++0x03 hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8))) group.long 0xED8++0x03 line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED8++0x03 hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC))) group.long 0xEDC++0x03 line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEDC++0x03 hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0))) group.long 0xEE0++0x03 line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE0++0x03 hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4))) group.long 0xEE4++0x03 line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE4++0x03 hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8))) group.long 0xEE8++0x03 line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE8++0x03 hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC))) group.long 0xEEC++0x03 line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEEC++0x03 hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0))) group.long 0xEF0++0x03 line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF0++0x03 hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4))) group.long 0xEF4++0x03 line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF4++0x03 hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0F00++0x03 hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" hgroup.long 0xF10++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" hgroup.long 0xF14++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" hgroup.long 0xF18++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" hgroup.long 0xF1C++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" hgroup.long 0xF20++0x03 hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" hgroup.long 0xF24++0x03 hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" hgroup.long 0xF28++0x03 hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" hgroup.long 0xF2C++0x03 hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" group.long 0xF10++0x03 line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" group.long 0xF14++0x03 line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" group.long 0xF18++0x03 line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" group.long 0xF1C++0x03 line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" group.long 0xF20++0x03 line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" group.long 0xF24++0x03 line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" group.long 0xF28++0x03 line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" group.long 0xF2C++0x03 line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 22. tree "Implementation Defined Test Registers" rgroup.long 0xC000++0x03 line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR" bitfld.long 0x00 31. " SRWP ,Super Register Write Pending" "Not pending,Pending" wgroup.long 0xC004++0x03 line.long 0x00 "GICD_ERRTESTR,Error Test Register" bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High" bitfld.long 0x00 0. " ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High" textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) rgroup.long 0xC084++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " SPIS63 ,SPI Status Bit 63" "Low,High" bitfld.long 0x00 30. " SPIS62 ,SPI Status Bit 62" "Low,High" bitfld.long 0x00 29. " SPIS61 ,SPI Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " SPIS60 ,SPI Status Bit 60" "Low,High" bitfld.long 0x00 27. " SPIS59 ,SPI Status Bit 59" "Low,High" bitfld.long 0x00 26. " SPIS58 ,SPI Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " SPIS57 ,SPI Status Bit 57" "Low,High" bitfld.long 0x00 24. " SPIS56 ,SPI Status Bit 56" "Low,High" bitfld.long 0x00 23. " SPIS55 ,SPI Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " SPIS54 ,SPI Status Bit 54" "Low,High" bitfld.long 0x00 21. " SPIS53 ,SPI Status Bit 53" "Low,High" bitfld.long 0x00 20. " SPIS52 ,SPI Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " SPIS51 ,SPI Status Bit 51" "Low,High" bitfld.long 0x00 18. " SPIS50 ,SPI Status Bit 50" "Low,High" bitfld.long 0x00 17. " SPIS49 ,SPI Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " SPIS48 ,SPI Status Bit 48" "Low,High" bitfld.long 0x00 15. " SPIS47 ,SPI Status Bit 47" "Low,High" bitfld.long 0x00 14. " SPIS46 ,SPI Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " SPIS45 ,SPI Status Bit 45" "Low,High" bitfld.long 0x00 12. " SPIS44 ,SPI Status Bit 44" "Low,High" bitfld.long 0x00 11. " SPIS43 ,SPI Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " SPIS42 ,SPI Status Bit 42" "Low,High" bitfld.long 0x00 9. " SPIS41 ,SPI Status Bit 41" "Low,High" bitfld.long 0x00 8. " SPIS40 ,SPI Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " SPIS39 ,SPI Status Bit 39" "Low,High" bitfld.long 0x00 6. " SPIS38 ,SPI Status Bit 38" "Low,High" bitfld.long 0x00 5. " SPIS37 ,SPI Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " SPIS36 ,SPI Status Bit 36" "Low,High" bitfld.long 0x00 3. " SPIS35 ,SPI Status Bit 35" "Low,High" bitfld.long 0x00 2. " SPIS34 ,SPI Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " SPIS33 ,SPI Status Bit 33" "Low,High" bitfld.long 0x00 0. " SPIS32 ,SPI Status Bit 32" "Low,High" else hgroup.long 0xC084++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) rgroup.long 0xC088++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " SPIS95 ,SPI Status Bit 95" "Low,High" bitfld.long 0x00 30. " SPIS94 ,SPI Status Bit 94" "Low,High" bitfld.long 0x00 29. " SPIS93 ,SPI Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " SPIS92 ,SPI Status Bit 92" "Low,High" bitfld.long 0x00 27. " SPIS91 ,SPI Status Bit 91" "Low,High" bitfld.long 0x00 26. " SPIS90 ,SPI Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " SPIS89 ,SPI Status Bit 89" "Low,High" bitfld.long 0x00 24. " SPIS88 ,SPI Status Bit 88" "Low,High" bitfld.long 0x00 23. " SPIS87 ,SPI Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " SPIS86 ,SPI Status Bit 86" "Low,High" bitfld.long 0x00 21. " SPIS85 ,SPI Status Bit 85" "Low,High" bitfld.long 0x00 20. " SPIS84 ,SPI Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " SPIS83 ,SPI Status Bit 83" "Low,High" bitfld.long 0x00 18. " SPIS82 ,SPI Status Bit 82" "Low,High" bitfld.long 0x00 17. " SPIS81 ,SPI Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " SPIS80 ,SPI Status Bit 80" "Low,High" bitfld.long 0x00 15. " SPIS79 ,SPI Status Bit 79" "Low,High" bitfld.long 0x00 14. " SPIS78 ,SPI Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " SPIS77 ,SPI Status Bit 77" "Low,High" bitfld.long 0x00 12. " SPIS76 ,SPI Status Bit 76" "Low,High" bitfld.long 0x00 11. " SPIS75 ,SPI Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " SPIS74 ,SPI Status Bit 74" "Low,High" bitfld.long 0x00 9. " SPIS73 ,SPI Status Bit 73" "Low,High" bitfld.long 0x00 8. " SPIS72 ,SPI Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " SPIS71 ,SPI Status Bit 71" "Low,High" bitfld.long 0x00 6. " SPIS70 ,SPI Status Bit 70" "Low,High" bitfld.long 0x00 5. " SPIS69 ,SPI Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " SPIS68 ,SPI Status Bit 68" "Low,High" bitfld.long 0x00 3. " SPIS67 ,SPI Status Bit 67" "Low,High" bitfld.long 0x00 2. " SPIS66 ,SPI Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " SPIS65 ,SPI Status Bit 65" "Low,High" bitfld.long 0x00 0. " SPIS64 ,SPI Status Bit 64" "Low,High" else hgroup.long 0xC088++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) rgroup.long 0xC08C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High" bitfld.long 0x00 30. " SPIS126 ,SPI Status Bit 126" "Low,High" bitfld.long 0x00 29. " SPIS125 ,SPI Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High" bitfld.long 0x00 27. " SPIS123 ,SPI Status Bit 123" "Low,High" bitfld.long 0x00 26. " SPIS122 ,SPI Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High" bitfld.long 0x00 24. " SPIS120 ,SPI Status Bit 120" "Low,High" bitfld.long 0x00 23. " SPIS119 ,SPI Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High" bitfld.long 0x00 21. " SPIS117 ,SPI Status Bit 117" "Low,High" bitfld.long 0x00 20. " SPIS116 ,SPI Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High" bitfld.long 0x00 18. " SPIS114 ,SPI Status Bit 114" "Low,High" bitfld.long 0x00 17. " SPIS113 ,SPI Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High" bitfld.long 0x00 15. " SPIS111 ,SPI Status Bit 111" "Low,High" bitfld.long 0x00 14. " SPIS110 ,SPI Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High" bitfld.long 0x00 12. " SPIS108 ,SPI Status Bit 108" "Low,High" bitfld.long 0x00 11. " SPIS107 ,SPI Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High" bitfld.long 0x00 9. " SPIS105 ,SPI Status Bit 105" "Low,High" bitfld.long 0x00 8. " SPIS104 ,SPI Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High" bitfld.long 0x00 6. " SPIS102 ,SPI Status Bit 102" "Low,High" bitfld.long 0x00 5. " SPIS101 ,SPI Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High" bitfld.long 0x00 3. " SPIS99 ,SPI Status Bit 99" "Low,High" bitfld.long 0x00 2. " SPIS98 ,SPI Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " SPIS97 ,SPI Status Bit 97" "Low,High" bitfld.long 0x00 0. " SPIS96 ,SPI Status Bit 96" "Low,High" else hgroup.long 0xC08C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) rgroup.long 0xC090++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High" bitfld.long 0x00 30. " SPIS158 ,SPI Status Bit 158" "Low,High" bitfld.long 0x00 29. " SPIS157 ,SPI Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High" bitfld.long 0x00 27. " SPIS155 ,SPI Status Bit 155" "Low,High" bitfld.long 0x00 26. " SPIS154 ,SPI Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High" bitfld.long 0x00 24. " SPIS152 ,SPI Status Bit 152" "Low,High" bitfld.long 0x00 23. " SPIS151 ,SPI Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High" bitfld.long 0x00 21. " SPIS149 ,SPI Status Bit 149" "Low,High" bitfld.long 0x00 20. " SPIS148 ,SPI Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High" bitfld.long 0x00 18. " SPIS146 ,SPI Status Bit 146" "Low,High" bitfld.long 0x00 17. " SPIS145 ,SPI Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High" bitfld.long 0x00 15. " SPIS143 ,SPI Status Bit 143" "Low,High" bitfld.long 0x00 14. " SPIS142 ,SPI Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High" bitfld.long 0x00 12. " SPIS140 ,SPI Status Bit 140" "Low,High" bitfld.long 0x00 11. " SPIS139 ,SPI Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High" bitfld.long 0x00 9. " SPIS137 ,SPI Status Bit 137" "Low,High" bitfld.long 0x00 8. " SPIS136 ,SPI Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High" bitfld.long 0x00 6. " SPIS134 ,SPI Status Bit 134" "Low,High" bitfld.long 0x00 5. " SPIS133 ,SPI Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High" bitfld.long 0x00 3. " SPIS131 ,SPI Status Bit 131" "Low,High" bitfld.long 0x00 2. " SPIS130 ,SPI Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High" bitfld.long 0x00 0. " SPIS128 ,SPI Status Bit 128" "Low,High" else hgroup.long 0xC090++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) rgroup.long 0xC094++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High" bitfld.long 0x00 30. " SPIS190 ,SPI Status Bit 190" "Low,High" bitfld.long 0x00 29. " SPIS189 ,SPI Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High" bitfld.long 0x00 27. " SPIS187 ,SPI Status Bit 187" "Low,High" bitfld.long 0x00 26. " SPIS186 ,SPI Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High" bitfld.long 0x00 24. " SPIS184 ,SPI Status Bit 184" "Low,High" bitfld.long 0x00 23. " SPIS183 ,SPI Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High" bitfld.long 0x00 21. " SPIS181 ,SPI Status Bit 181" "Low,High" bitfld.long 0x00 20. " SPIS180 ,SPI Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High" bitfld.long 0x00 18. " SPIS178 ,SPI Status Bit 178" "Low,High" bitfld.long 0x00 17. " SPIS177 ,SPI Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High" bitfld.long 0x00 15. " SPIS175 ,SPI Status Bit 175" "Low,High" bitfld.long 0x00 14. " SPIS174 ,SPI Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High" bitfld.long 0x00 12. " SPIS172 ,SPI Status Bit 172" "Low,High" bitfld.long 0x00 11. " SPIS171 ,SPI Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High" bitfld.long 0x00 9. " SPIS169 ,SPI Status Bit 169" "Low,High" bitfld.long 0x00 8. " SPIS168 ,SPI Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High" bitfld.long 0x00 6. " SPIS166 ,SPI Status Bit 166" "Low,High" bitfld.long 0x00 5. " SPIS165 ,SPI Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High" bitfld.long 0x00 3. " SPIS163 ,SPI Status Bit 163" "Low,High" bitfld.long 0x00 2. " SPIS162 ,SPI Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High" bitfld.long 0x00 0. " SPIS160 ,SPI Status Bit 160" "Low,High" else hgroup.long 0xC094++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) rgroup.long 0xC098++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High" bitfld.long 0x00 30. " SPIS222 ,SPI Status Bit 222" "Low,High" bitfld.long 0x00 29. " SPIS221 ,SPI Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High" bitfld.long 0x00 27. " SPIS219 ,SPI Status Bit 219" "Low,High" bitfld.long 0x00 26. " SPIS218 ,SPI Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High" bitfld.long 0x00 24. " SPIS216 ,SPI Status Bit 216" "Low,High" bitfld.long 0x00 23. " SPIS215 ,SPI Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High" bitfld.long 0x00 21. " SPIS213 ,SPI Status Bit 213" "Low,High" bitfld.long 0x00 20. " SPIS212 ,SPI Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High" bitfld.long 0x00 18. " SPIS210 ,SPI Status Bit 210" "Low,High" bitfld.long 0x00 17. " SPIS209 ,SPI Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High" bitfld.long 0x00 15. " SPIS207 ,SPI Status Bit 207" "Low,High" bitfld.long 0x00 14. " SPIS206 ,SPI Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High" bitfld.long 0x00 12. " SPIS204 ,SPI Status Bit 204" "Low,High" bitfld.long 0x00 11. " SPIS203 ,SPI Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High" bitfld.long 0x00 9. " SPIS201 ,SPI Status Bit 201" "Low,High" bitfld.long 0x00 8. " SPIS200 ,SPI Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High" bitfld.long 0x00 6. " SPIS198 ,SPI Status Bit 198" "Low,High" bitfld.long 0x00 5. " SPIS197 ,SPI Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High" bitfld.long 0x00 3. " SPIS195 ,SPI Status Bit 195" "Low,High" bitfld.long 0x00 2. " SPIS194 ,SPI Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High" bitfld.long 0x00 0. " SPIS192 ,SPI Status Bit 192" "Low,High" else hgroup.long 0xC098++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) rgroup.long 0xC09C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High" bitfld.long 0x00 30. " SPIS254 ,SPI Status Bit 254" "Low,High" bitfld.long 0x00 29. " SPIS253 ,SPI Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High" bitfld.long 0x00 27. " SPIS251 ,SPI Status Bit 251" "Low,High" bitfld.long 0x00 26. " SPIS250 ,SPI Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High" bitfld.long 0x00 24. " SPIS248 ,SPI Status Bit 248" "Low,High" bitfld.long 0x00 23. " SPIS247 ,SPI Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High" bitfld.long 0x00 21. " SPIS245 ,SPI Status Bit 245" "Low,High" bitfld.long 0x00 20. " SPIS244 ,SPI Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High" bitfld.long 0x00 18. " SPIS242 ,SPI Status Bit 242" "Low,High" bitfld.long 0x00 17. " SPIS241 ,SPI Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High" bitfld.long 0x00 15. " SPIS239 ,SPI Status Bit 239" "Low,High" bitfld.long 0x00 14. " SPIS238 ,SPI Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High" bitfld.long 0x00 12. " SPIS236 ,SPI Status Bit 236" "Low,High" bitfld.long 0x00 11. " SPIS235 ,SPI Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High" bitfld.long 0x00 9. " SPIS233 ,SPI Status Bit 233" "Low,High" bitfld.long 0x00 8. " SPIS232 ,SPI Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High" bitfld.long 0x00 6. " SPIS230 ,SPI Status Bit 230" "Low,High" bitfld.long 0x00 5. " SPIS229 ,SPI Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High" bitfld.long 0x00 3. " SPIS227 ,SPI Status Bit 227" "Low,High" bitfld.long 0x00 2. " SPIS226 ,SPI Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High" bitfld.long 0x00 0. " SPIS224 ,SPI Status Bit 224" "Low,High" else hgroup.long 0xC09C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) rgroup.long 0xC0A0++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High" bitfld.long 0x00 30. " SPIS286 ,SPI Status Bit 286" "Low,High" bitfld.long 0x00 29. " SPIS285 ,SPI Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High" bitfld.long 0x00 27. " SPIS283 ,SPI Status Bit 283" "Low,High" bitfld.long 0x00 26. " SPIS282 ,SPI Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High" bitfld.long 0x00 24. " SPIS280 ,SPI Status Bit 280" "Low,High" bitfld.long 0x00 23. " SPIS279 ,SPI Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High" bitfld.long 0x00 21. " SPIS277 ,SPI Status Bit 277" "Low,High" bitfld.long 0x00 20. " SPIS276 ,SPI Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High" bitfld.long 0x00 18. " SPIS274 ,SPI Status Bit 274" "Low,High" bitfld.long 0x00 17. " SPIS273 ,SPI Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High" bitfld.long 0x00 15. " SPIS271 ,SPI Status Bit 271" "Low,High" bitfld.long 0x00 14. " SPIS270 ,SPI Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High" bitfld.long 0x00 12. " SPIS268 ,SPI Status Bit 268" "Low,High" bitfld.long 0x00 11. " SPIS267 ,SPI Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High" bitfld.long 0x00 9. " SPIS265 ,SPI Status Bit 265" "Low,High" bitfld.long 0x00 8. " SPIS264 ,SPI Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High" bitfld.long 0x00 6. " SPIS262 ,SPI Status Bit 262" "Low,High" bitfld.long 0x00 5. " SPIS261 ,SPI Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High" bitfld.long 0x00 3. " SPIS259 ,SPI Status Bit 259" "Low,High" bitfld.long 0x00 2. " SPIS258 ,SPI Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High" bitfld.long 0x00 0. " SPIS256 ,SPI Status Bit 256" "Low,High" else hgroup.long 0xC0A0++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) rgroup.long 0xC0A4++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High" bitfld.long 0x00 30. " SPIS318 ,SPI Status Bit 318" "Low,High" bitfld.long 0x00 29. " SPIS317 ,SPI Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High" bitfld.long 0x00 27. " SPIS315 ,SPI Status Bit 315" "Low,High" bitfld.long 0x00 26. " SPIS314 ,SPI Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High" bitfld.long 0x00 24. " SPIS312 ,SPI Status Bit 312" "Low,High" bitfld.long 0x00 23. " SPIS311 ,SPI Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High" bitfld.long 0x00 21. " SPIS309 ,SPI Status Bit 309" "Low,High" bitfld.long 0x00 20. " SPIS308 ,SPI Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High" bitfld.long 0x00 18. " SPIS306 ,SPI Status Bit 306" "Low,High" bitfld.long 0x00 17. " SPIS305 ,SPI Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High" bitfld.long 0x00 15. " SPIS303 ,SPI Status Bit 303" "Low,High" bitfld.long 0x00 14. " SPIS302 ,SPI Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High" bitfld.long 0x00 12. " SPIS300 ,SPI Status Bit 300" "Low,High" bitfld.long 0x00 11. " SPIS299 ,SPI Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High" bitfld.long 0x00 9. " SPIS297 ,SPI Status Bit 297" "Low,High" bitfld.long 0x00 8. " SPIS296 ,SPI Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High" bitfld.long 0x00 6. " SPIS294 ,SPI Status Bit 294" "Low,High" bitfld.long 0x00 5. " SPIS293 ,SPI Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High" bitfld.long 0x00 3. " SPIS291 ,SPI Status Bit 291" "Low,High" bitfld.long 0x00 2. " SPIS290 ,SPI Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High" bitfld.long 0x00 0. " SPIS288 ,SPI Status Bit 288" "Low,High" else hgroup.long 0xC0A4++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) rgroup.long 0xC0A8++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High" bitfld.long 0x00 30. " SPIS350 ,SPI Status Bit 350" "Low,High" bitfld.long 0x00 29. " SPIS349 ,SPI Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High" bitfld.long 0x00 27. " SPIS347 ,SPI Status Bit 347" "Low,High" bitfld.long 0x00 26. " SPIS346 ,SPI Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High" bitfld.long 0x00 24. " SPIS344 ,SPI Status Bit 344" "Low,High" bitfld.long 0x00 23. " SPIS343 ,SPI Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High" bitfld.long 0x00 21. " SPIS341 ,SPI Status Bit 341" "Low,High" bitfld.long 0x00 20. " SPIS340 ,SPI Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High" bitfld.long 0x00 18. " SPIS338 ,SPI Status Bit 338" "Low,High" bitfld.long 0x00 17. " SPIS337 ,SPI Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High" bitfld.long 0x00 15. " SPIS335 ,SPI Status Bit 335" "Low,High" bitfld.long 0x00 14. " SPIS334 ,SPI Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High" bitfld.long 0x00 12. " SPIS332 ,SPI Status Bit 332" "Low,High" bitfld.long 0x00 11. " SPIS331 ,SPI Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High" bitfld.long 0x00 9. " SPIS329 ,SPI Status Bit 329" "Low,High" bitfld.long 0x00 8. " SPIS328 ,SPI Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High" bitfld.long 0x00 6. " SPIS326 ,SPI Status Bit 326" "Low,High" bitfld.long 0x00 5. " SPIS325 ,SPI Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High" bitfld.long 0x00 3. " SPIS323 ,SPI Status Bit 323" "Low,High" bitfld.long 0x00 2. " SPIS322 ,SPI Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High" bitfld.long 0x00 0. " SPIS320 ,SPI Status Bit 320" "Low,High" else hgroup.long 0xC0A8++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) rgroup.long 0xC0AC++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High" bitfld.long 0x00 30. " SPIS382 ,SPI Status Bit 382" "Low,High" bitfld.long 0x00 29. " SPIS381 ,SPI Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High" bitfld.long 0x00 27. " SPIS379 ,SPI Status Bit 379" "Low,High" bitfld.long 0x00 26. " SPIS378 ,SPI Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High" bitfld.long 0x00 24. " SPIS376 ,SPI Status Bit 376" "Low,High" bitfld.long 0x00 23. " SPIS375 ,SPI Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High" bitfld.long 0x00 21. " SPIS373 ,SPI Status Bit 373" "Low,High" bitfld.long 0x00 20. " SPIS372 ,SPI Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High" bitfld.long 0x00 18. " SPIS370 ,SPI Status Bit 370" "Low,High" bitfld.long 0x00 17. " SPIS369 ,SPI Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High" bitfld.long 0x00 15. " SPIS367 ,SPI Status Bit 367" "Low,High" bitfld.long 0x00 14. " SPIS366 ,SPI Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High" bitfld.long 0x00 12. " SPIS364 ,SPI Status Bit 364" "Low,High" bitfld.long 0x00 11. " SPIS363 ,SPI Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High" bitfld.long 0x00 9. " SPIS361 ,SPI Status Bit 361" "Low,High" bitfld.long 0x00 8. " SPIS360 ,SPI Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High" bitfld.long 0x00 6. " SPIS358 ,SPI Status Bit 358" "Low,High" bitfld.long 0x00 5. " SPIS357 ,SPI Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High" bitfld.long 0x00 3. " SPIS355 ,SPI Status Bit 355" "Low,High" bitfld.long 0x00 2. " SPIS354 ,SPI Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High" bitfld.long 0x00 0. " SPIS352 ,SPI Status Bit 352" "Low,High" else hgroup.long 0xC0AC++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) rgroup.long 0xC0B0++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High" bitfld.long 0x00 30. " SPIS414 ,SPI Status Bit 414" "Low,High" bitfld.long 0x00 29. " SPIS413 ,SPI Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High" bitfld.long 0x00 27. " SPIS411 ,SPI Status Bit 411" "Low,High" bitfld.long 0x00 26. " SPIS410 ,SPI Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High" bitfld.long 0x00 24. " SPIS408 ,SPI Status Bit 408" "Low,High" bitfld.long 0x00 23. " SPIS407 ,SPI Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High" bitfld.long 0x00 21. " SPIS405 ,SPI Status Bit 405" "Low,High" bitfld.long 0x00 20. " SPIS404 ,SPI Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High" bitfld.long 0x00 18. " SPIS402 ,SPI Status Bit 402" "Low,High" bitfld.long 0x00 17. " SPIS401 ,SPI Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High" bitfld.long 0x00 15. " SPIS399 ,SPI Status Bit 399" "Low,High" bitfld.long 0x00 14. " SPIS398 ,SPI Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High" bitfld.long 0x00 12. " SPIS396 ,SPI Status Bit 396" "Low,High" bitfld.long 0x00 11. " SPIS395 ,SPI Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High" bitfld.long 0x00 9. " SPIS393 ,SPI Status Bit 393" "Low,High" bitfld.long 0x00 8. " SPIS392 ,SPI Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High" bitfld.long 0x00 6. " SPIS390 ,SPI Status Bit 390" "Low,High" bitfld.long 0x00 5. " SPIS389 ,SPI Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High" bitfld.long 0x00 3. " SPIS387 ,SPI Status Bit 387" "Low,High" bitfld.long 0x00 2. " SPIS386 ,SPI Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High" bitfld.long 0x00 0. " SPIS384 ,SPI Status Bit 384" "Low,High" else hgroup.long 0xC0B0++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) rgroup.long 0xC0B4++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High" bitfld.long 0x00 30. " SPIS446 ,SPI Status Bit 446" "Low,High" bitfld.long 0x00 29. " SPIS445 ,SPI Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High" bitfld.long 0x00 27. " SPIS443 ,SPI Status Bit 443" "Low,High" bitfld.long 0x00 26. " SPIS442 ,SPI Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High" bitfld.long 0x00 24. " SPIS440 ,SPI Status Bit 440" "Low,High" bitfld.long 0x00 23. " SPIS439 ,SPI Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High" bitfld.long 0x00 21. " SPIS437 ,SPI Status Bit 437" "Low,High" bitfld.long 0x00 20. " SPIS436 ,SPI Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High" bitfld.long 0x00 18. " SPIS434 ,SPI Status Bit 434" "Low,High" bitfld.long 0x00 17. " SPIS433 ,SPI Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High" bitfld.long 0x00 15. " SPIS431 ,SPI Status Bit 431" "Low,High" bitfld.long 0x00 14. " SPIS430 ,SPI Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High" bitfld.long 0x00 12. " SPIS428 ,SPI Status Bit 428" "Low,High" bitfld.long 0x00 11. " SPIS427 ,SPI Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High" bitfld.long 0x00 9. " SPIS425 ,SPI Status Bit 425" "Low,High" bitfld.long 0x00 8. " SPIS424 ,SPI Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High" bitfld.long 0x00 6. " SPIS422 ,SPI Status Bit 422" "Low,High" bitfld.long 0x00 5. " SPIS421 ,SPI Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High" bitfld.long 0x00 3. " SPIS419 ,SPI Status Bit 419" "Low,High" bitfld.long 0x00 2. " SPIS418 ,SPI Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High" bitfld.long 0x00 0. " SPIS416 ,SPI Status Bit 416" "Low,High" else hgroup.long 0xC0B4++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) rgroup.long 0xC0B8++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High" bitfld.long 0x00 30. " SPIS478 ,SPI Status Bit 478" "Low,High" bitfld.long 0x00 29. " SPIS477 ,SPI Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High" bitfld.long 0x00 27. " SPIS475 ,SPI Status Bit 475" "Low,High" bitfld.long 0x00 26. " SPIS474 ,SPI Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High" bitfld.long 0x00 24. " SPIS472 ,SPI Status Bit 472" "Low,High" bitfld.long 0x00 23. " SPIS471 ,SPI Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High" bitfld.long 0x00 21. " SPIS469 ,SPI Status Bit 469" "Low,High" bitfld.long 0x00 20. " SPIS468 ,SPI Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High" bitfld.long 0x00 18. " SPIS466 ,SPI Status Bit 466" "Low,High" bitfld.long 0x00 17. " SPIS465 ,SPI Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High" bitfld.long 0x00 15. " SPIS463 ,SPI Status Bit 463" "Low,High" bitfld.long 0x00 14. " SPIS462 ,SPI Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High" bitfld.long 0x00 12. " SPIS460 ,SPI Status Bit 460" "Low,High" bitfld.long 0x00 11. " SPIS459 ,SPI Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High" bitfld.long 0x00 9. " SPIS457 ,SPI Status Bit 457" "Low,High" bitfld.long 0x00 8. " SPIS456 ,SPI Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High" bitfld.long 0x00 6. " SPIS454 ,SPI Status Bit 454" "Low,High" bitfld.long 0x00 5. " SPIS453 ,SPI Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High" bitfld.long 0x00 3. " SPIS451 ,SPI Status Bit 451" "Low,High" bitfld.long 0x00 2. " SPIS450 ,SPI Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High" bitfld.long 0x00 0. " SPIS448 ,SPI Status Bit 448" "Low,High" else hgroup.long 0xC0B8++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) rgroup.long 0xC0BC++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High" bitfld.long 0x00 30. " SPIS510 ,SPI Status Bit 510" "Low,High" bitfld.long 0x00 29. " SPIS509 ,SPI Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High" bitfld.long 0x00 27. " SPIS507 ,SPI Status Bit 507" "Low,High" bitfld.long 0x00 26. " SPIS506 ,SPI Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High" bitfld.long 0x00 24. " SPIS504 ,SPI Status Bit 504" "Low,High" bitfld.long 0x00 23. " SPIS503 ,SPI Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High" bitfld.long 0x00 21. " SPIS501 ,SPI Status Bit 501" "Low,High" bitfld.long 0x00 20. " SPIS500 ,SPI Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High" bitfld.long 0x00 18. " SPIS498 ,SPI Status Bit 498" "Low,High" bitfld.long 0x00 17. " SPIS497 ,SPI Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High" bitfld.long 0x00 15. " SPIS495 ,SPI Status Bit 495" "Low,High" bitfld.long 0x00 14. " SPIS494 ,SPI Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High" bitfld.long 0x00 12. " SPIS492 ,SPI Status Bit 492" "Low,High" bitfld.long 0x00 11. " SPIS491 ,SPI Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High" bitfld.long 0x00 9. " SPIS489 ,SPI Status Bit 489" "Low,High" bitfld.long 0x00 8. " SPIS488 ,SPI Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High" bitfld.long 0x00 6. " SPIS486 ,SPI Status Bit 486" "Low,High" bitfld.long 0x00 5. " SPIS485 ,SPI Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High" bitfld.long 0x00 3. " SPIS483 ,SPI Status Bit 483" "Low,High" bitfld.long 0x00 2. " SPIS482 ,SPI Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High" bitfld.long 0x00 0. " SPIS480 ,SPI Status Bit 480" "Low,High" else hgroup.long 0xC0BC++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) rgroup.long 0xC0C0++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High" bitfld.long 0x00 30. " SPIS542 ,SPI Status Bit 542" "Low,High" bitfld.long 0x00 29. " SPIS541 ,SPI Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High" bitfld.long 0x00 27. " SPIS539 ,SPI Status Bit 539" "Low,High" bitfld.long 0x00 26. " SPIS538 ,SPI Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High" bitfld.long 0x00 24. " SPIS536 ,SPI Status Bit 536" "Low,High" bitfld.long 0x00 23. " SPIS535 ,SPI Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High" bitfld.long 0x00 21. " SPIS533 ,SPI Status Bit 533" "Low,High" bitfld.long 0x00 20. " SPIS532 ,SPI Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High" bitfld.long 0x00 18. " SPIS530 ,SPI Status Bit 530" "Low,High" bitfld.long 0x00 17. " SPIS529 ,SPI Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High" bitfld.long 0x00 15. " SPIS527 ,SPI Status Bit 527" "Low,High" bitfld.long 0x00 14. " SPIS526 ,SPI Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High" bitfld.long 0x00 12. " SPIS524 ,SPI Status Bit 524" "Low,High" bitfld.long 0x00 11. " SPIS523 ,SPI Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High" bitfld.long 0x00 9. " SPIS521 ,SPI Status Bit 521" "Low,High" bitfld.long 0x00 8. " SPIS520 ,SPI Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High" bitfld.long 0x00 6. " SPIS518 ,SPI Status Bit 518" "Low,High" bitfld.long 0x00 5. " SPIS517 ,SPI Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High" bitfld.long 0x00 3. " SPIS515 ,SPI Status Bit 515" "Low,High" bitfld.long 0x00 2. " SPIS514 ,SPI Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High" bitfld.long 0x00 0. " SPIS512 ,SPI Status Bit 512" "Low,High" else hgroup.long 0xC0C0++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) rgroup.long 0xC0C4++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High" bitfld.long 0x00 30. " SPIS574 ,SPI Status Bit 574" "Low,High" bitfld.long 0x00 29. " SPIS573 ,SPI Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High" bitfld.long 0x00 27. " SPIS571 ,SPI Status Bit 571" "Low,High" bitfld.long 0x00 26. " SPIS570 ,SPI Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High" bitfld.long 0x00 24. " SPIS568 ,SPI Status Bit 568" "Low,High" bitfld.long 0x00 23. " SPIS567 ,SPI Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High" bitfld.long 0x00 21. " SPIS565 ,SPI Status Bit 565" "Low,High" bitfld.long 0x00 20. " SPIS564 ,SPI Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High" bitfld.long 0x00 18. " SPIS562 ,SPI Status Bit 562" "Low,High" bitfld.long 0x00 17. " SPIS561 ,SPI Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High" bitfld.long 0x00 15. " SPIS559 ,SPI Status Bit 559" "Low,High" bitfld.long 0x00 14. " SPIS558 ,SPI Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High" bitfld.long 0x00 12. " SPIS556 ,SPI Status Bit 556" "Low,High" bitfld.long 0x00 11. " SPIS555 ,SPI Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High" bitfld.long 0x00 9. " SPIS553 ,SPI Status Bit 553" "Low,High" bitfld.long 0x00 8. " SPIS552 ,SPI Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High" bitfld.long 0x00 6. " SPIS550 ,SPI Status Bit 550" "Low,High" bitfld.long 0x00 5. " SPIS549 ,SPI Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High" bitfld.long 0x00 3. " SPIS547 ,SPI Status Bit 547" "Low,High" bitfld.long 0x00 2. " SPIS546 ,SPI Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High" bitfld.long 0x00 0. " SPIS544 ,SPI Status Bit 544" "Low,High" else hgroup.long 0xC0C4++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) rgroup.long 0xC0C8++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High" bitfld.long 0x00 30. " SPIS606 ,SPI Status Bit 606" "Low,High" bitfld.long 0x00 29. " SPIS605 ,SPI Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High" bitfld.long 0x00 27. " SPIS603 ,SPI Status Bit 603" "Low,High" bitfld.long 0x00 26. " SPIS602 ,SPI Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High" bitfld.long 0x00 24. " SPIS600 ,SPI Status Bit 600" "Low,High" bitfld.long 0x00 23. " SPIS599 ,SPI Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High" bitfld.long 0x00 21. " SPIS597 ,SPI Status Bit 597" "Low,High" bitfld.long 0x00 20. " SPIS596 ,SPI Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High" bitfld.long 0x00 18. " SPIS594 ,SPI Status Bit 594" "Low,High" bitfld.long 0x00 17. " SPIS593 ,SPI Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High" bitfld.long 0x00 15. " SPIS591 ,SPI Status Bit 591" "Low,High" bitfld.long 0x00 14. " SPIS590 ,SPI Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High" bitfld.long 0x00 12. " SPIS588 ,SPI Status Bit 588" "Low,High" bitfld.long 0x00 11. " SPIS587 ,SPI Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High" bitfld.long 0x00 9. " SPIS585 ,SPI Status Bit 585" "Low,High" bitfld.long 0x00 8. " SPIS584 ,SPI Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High" bitfld.long 0x00 6. " SPIS582 ,SPI Status Bit 582" "Low,High" bitfld.long 0x00 5. " SPIS581 ,SPI Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High" bitfld.long 0x00 3. " SPIS579 ,SPI Status Bit 579" "Low,High" bitfld.long 0x00 2. " SPIS578 ,SPI Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High" bitfld.long 0x00 0. " SPIS576 ,SPI Status Bit 576" "Low,High" else hgroup.long 0xC0C8++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) rgroup.long 0xC0CC++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High" bitfld.long 0x00 30. " SPIS638 ,SPI Status Bit 638" "Low,High" bitfld.long 0x00 29. " SPIS637 ,SPI Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High" bitfld.long 0x00 27. " SPIS635 ,SPI Status Bit 635" "Low,High" bitfld.long 0x00 26. " SPIS634 ,SPI Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High" bitfld.long 0x00 24. " SPIS632 ,SPI Status Bit 632" "Low,High" bitfld.long 0x00 23. " SPIS631 ,SPI Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High" bitfld.long 0x00 21. " SPIS629 ,SPI Status Bit 629" "Low,High" bitfld.long 0x00 20. " SPIS628 ,SPI Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High" bitfld.long 0x00 18. " SPIS626 ,SPI Status Bit 626" "Low,High" bitfld.long 0x00 17. " SPIS625 ,SPI Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High" bitfld.long 0x00 15. " SPIS623 ,SPI Status Bit 623" "Low,High" bitfld.long 0x00 14. " SPIS622 ,SPI Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High" bitfld.long 0x00 12. " SPIS620 ,SPI Status Bit 620" "Low,High" bitfld.long 0x00 11. " SPIS619 ,SPI Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High" bitfld.long 0x00 9. " SPIS617 ,SPI Status Bit 617" "Low,High" bitfld.long 0x00 8. " SPIS616 ,SPI Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High" bitfld.long 0x00 6. " SPIS614 ,SPI Status Bit 614" "Low,High" bitfld.long 0x00 5. " SPIS613 ,SPI Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High" bitfld.long 0x00 3. " SPIS611 ,SPI Status Bit 611" "Low,High" bitfld.long 0x00 2. " SPIS610 ,SPI Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High" bitfld.long 0x00 0. " SPIS608 ,SPI Status Bit 608" "Low,High" else hgroup.long 0xC0CC++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) rgroup.long 0xC0D0++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High" bitfld.long 0x00 30. " SPIS670 ,SPI Status Bit 670" "Low,High" bitfld.long 0x00 29. " SPIS669 ,SPI Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High" bitfld.long 0x00 27. " SPIS667 ,SPI Status Bit 667" "Low,High" bitfld.long 0x00 26. " SPIS666 ,SPI Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High" bitfld.long 0x00 24. " SPIS664 ,SPI Status Bit 664" "Low,High" bitfld.long 0x00 23. " SPIS663 ,SPI Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High" bitfld.long 0x00 21. " SPIS661 ,SPI Status Bit 661" "Low,High" bitfld.long 0x00 20. " SPIS660 ,SPI Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High" bitfld.long 0x00 18. " SPIS658 ,SPI Status Bit 658" "Low,High" bitfld.long 0x00 17. " SPIS657 ,SPI Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High" bitfld.long 0x00 15. " SPIS655 ,SPI Status Bit 655" "Low,High" bitfld.long 0x00 14. " SPIS654 ,SPI Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High" bitfld.long 0x00 12. " SPIS652 ,SPI Status Bit 652" "Low,High" bitfld.long 0x00 11. " SPIS651 ,SPI Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High" bitfld.long 0x00 9. " SPIS649 ,SPI Status Bit 649" "Low,High" bitfld.long 0x00 8. " SPIS648 ,SPI Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High" bitfld.long 0x00 6. " SPIS646 ,SPI Status Bit 646" "Low,High" bitfld.long 0x00 5. " SPIS645 ,SPI Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High" bitfld.long 0x00 3. " SPIS643 ,SPI Status Bit 643" "Low,High" bitfld.long 0x00 2. " SPIS642 ,SPI Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High" bitfld.long 0x00 0. " SPIS640 ,SPI Status Bit 640" "Low,High" else hgroup.long 0xC0D0++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) rgroup.long 0xC0D4++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High" bitfld.long 0x00 30. " SPIS702 ,SPI Status Bit 702" "Low,High" bitfld.long 0x00 29. " SPIS701 ,SPI Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High" bitfld.long 0x00 27. " SPIS699 ,SPI Status Bit 699" "Low,High" bitfld.long 0x00 26. " SPIS698 ,SPI Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High" bitfld.long 0x00 24. " SPIS696 ,SPI Status Bit 696" "Low,High" bitfld.long 0x00 23. " SPIS695 ,SPI Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High" bitfld.long 0x00 21. " SPIS693 ,SPI Status Bit 693" "Low,High" bitfld.long 0x00 20. " SPIS692 ,SPI Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High" bitfld.long 0x00 18. " SPIS690 ,SPI Status Bit 690" "Low,High" bitfld.long 0x00 17. " SPIS689 ,SPI Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High" bitfld.long 0x00 15. " SPIS687 ,SPI Status Bit 687" "Low,High" bitfld.long 0x00 14. " SPIS686 ,SPI Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High" bitfld.long 0x00 12. " SPIS684 ,SPI Status Bit 684" "Low,High" bitfld.long 0x00 11. " SPIS683 ,SPI Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High" bitfld.long 0x00 9. " SPIS681 ,SPI Status Bit 681" "Low,High" bitfld.long 0x00 8. " SPIS680 ,SPI Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High" bitfld.long 0x00 6. " SPIS678 ,SPI Status Bit 678" "Low,High" bitfld.long 0x00 5. " SPIS677 ,SPI Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High" bitfld.long 0x00 3. " SPIS675 ,SPI Status Bit 675" "Low,High" bitfld.long 0x00 2. " SPIS674 ,SPI Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High" bitfld.long 0x00 0. " SPIS672 ,SPI Status Bit 672" "Low,High" else hgroup.long 0xC0D4++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) rgroup.long 0xC0D8++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High" bitfld.long 0x00 30. " SPIS734 ,SPI Status Bit 734" "Low,High" bitfld.long 0x00 29. " SPIS733 ,SPI Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High" bitfld.long 0x00 27. " SPIS731 ,SPI Status Bit 731" "Low,High" bitfld.long 0x00 26. " SPIS730 ,SPI Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High" bitfld.long 0x00 24. " SPIS728 ,SPI Status Bit 728" "Low,High" bitfld.long 0x00 23. " SPIS727 ,SPI Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High" bitfld.long 0x00 21. " SPIS725 ,SPI Status Bit 725" "Low,High" bitfld.long 0x00 20. " SPIS724 ,SPI Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High" bitfld.long 0x00 18. " SPIS722 ,SPI Status Bit 722" "Low,High" bitfld.long 0x00 17. " SPIS721 ,SPI Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High" bitfld.long 0x00 15. " SPIS719 ,SPI Status Bit 719" "Low,High" bitfld.long 0x00 14. " SPIS718 ,SPI Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High" bitfld.long 0x00 12. " SPIS716 ,SPI Status Bit 716" "Low,High" bitfld.long 0x00 11. " SPIS715 ,SPI Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High" bitfld.long 0x00 9. " SPIS713 ,SPI Status Bit 713" "Low,High" bitfld.long 0x00 8. " SPIS712 ,SPI Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High" bitfld.long 0x00 6. " SPIS710 ,SPI Status Bit 710" "Low,High" bitfld.long 0x00 5. " SPIS709 ,SPI Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High" bitfld.long 0x00 3. " SPIS707 ,SPI Status Bit 707" "Low,High" bitfld.long 0x00 2. " SPIS706 ,SPI Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High" bitfld.long 0x00 0. " SPIS704 ,SPI Status Bit 704" "Low,High" else hgroup.long 0xC0D8++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) rgroup.long 0xC0DC++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High" bitfld.long 0x00 30. " SPIS766 ,SPI Status Bit 766" "Low,High" bitfld.long 0x00 29. " SPIS765 ,SPI Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High" bitfld.long 0x00 27. " SPIS763 ,SPI Status Bit 763" "Low,High" bitfld.long 0x00 26. " SPIS762 ,SPI Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High" bitfld.long 0x00 24. " SPIS760 ,SPI Status Bit 760" "Low,High" bitfld.long 0x00 23. " SPIS759 ,SPI Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High" bitfld.long 0x00 21. " SPIS757 ,SPI Status Bit 757" "Low,High" bitfld.long 0x00 20. " SPIS756 ,SPI Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High" bitfld.long 0x00 18. " SPIS754 ,SPI Status Bit 754" "Low,High" bitfld.long 0x00 17. " SPIS753 ,SPI Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High" bitfld.long 0x00 15. " SPIS751 ,SPI Status Bit 751" "Low,High" bitfld.long 0x00 14. " SPIS750 ,SPI Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High" bitfld.long 0x00 12. " SPIS748 ,SPI Status Bit 748" "Low,High" bitfld.long 0x00 11. " SPIS747 ,SPI Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High" bitfld.long 0x00 9. " SPIS745 ,SPI Status Bit 745" "Low,High" bitfld.long 0x00 8. " SPIS744 ,SPI Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High" bitfld.long 0x00 6. " SPIS742 ,SPI Status Bit 742" "Low,High" bitfld.long 0x00 5. " SPIS741 ,SPI Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High" bitfld.long 0x00 3. " SPIS739 ,SPI Status Bit 739" "Low,High" bitfld.long 0x00 2. " SPIS738 ,SPI Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High" bitfld.long 0x00 0. " SPIS736 ,SPI Status Bit 736" "Low,High" else hgroup.long 0xC0DC++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) rgroup.long 0xC0E0++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High" bitfld.long 0x00 30. " SPIS798 ,SPI Status Bit 798" "Low,High" bitfld.long 0x00 29. " SPIS797 ,SPI Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High" bitfld.long 0x00 27. " SPIS795 ,SPI Status Bit 795" "Low,High" bitfld.long 0x00 26. " SPIS794 ,SPI Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High" bitfld.long 0x00 24. " SPIS792 ,SPI Status Bit 792" "Low,High" bitfld.long 0x00 23. " SPIS791 ,SPI Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High" bitfld.long 0x00 21. " SPIS789 ,SPI Status Bit 789" "Low,High" bitfld.long 0x00 20. " SPIS788 ,SPI Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High" bitfld.long 0x00 18. " SPIS786 ,SPI Status Bit 786" "Low,High" bitfld.long 0x00 17. " SPIS785 ,SPI Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High" bitfld.long 0x00 15. " SPIS783 ,SPI Status Bit 783" "Low,High" bitfld.long 0x00 14. " SPIS782 ,SPI Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High" bitfld.long 0x00 12. " SPIS780 ,SPI Status Bit 780" "Low,High" bitfld.long 0x00 11. " SPIS779 ,SPI Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High" bitfld.long 0x00 9. " SPIS777 ,SPI Status Bit 777" "Low,High" bitfld.long 0x00 8. " SPIS776 ,SPI Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High" bitfld.long 0x00 6. " SPIS774 ,SPI Status Bit 774" "Low,High" bitfld.long 0x00 5. " SPIS773 ,SPI Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High" bitfld.long 0x00 3. " SPIS771 ,SPI Status Bit 771" "Low,High" bitfld.long 0x00 2. " SPIS770 ,SPI Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High" bitfld.long 0x00 0. " SPIS768 ,SPI Status Bit 768" "Low,High" else hgroup.long 0xC0E0++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) rgroup.long 0xC0E4++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High" bitfld.long 0x00 30. " SPIS830 ,SPI Status Bit 830" "Low,High" bitfld.long 0x00 29. " SPIS829 ,SPI Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High" bitfld.long 0x00 27. " SPIS827 ,SPI Status Bit 827" "Low,High" bitfld.long 0x00 26. " SPIS826 ,SPI Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High" bitfld.long 0x00 24. " SPIS824 ,SPI Status Bit 824" "Low,High" bitfld.long 0x00 23. " SPIS823 ,SPI Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High" bitfld.long 0x00 21. " SPIS821 ,SPI Status Bit 821" "Low,High" bitfld.long 0x00 20. " SPIS820 ,SPI Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High" bitfld.long 0x00 18. " SPIS818 ,SPI Status Bit 818" "Low,High" bitfld.long 0x00 17. " SPIS817 ,SPI Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High" bitfld.long 0x00 15. " SPIS815 ,SPI Status Bit 815" "Low,High" bitfld.long 0x00 14. " SPIS814 ,SPI Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High" bitfld.long 0x00 12. " SPIS812 ,SPI Status Bit 812" "Low,High" bitfld.long 0x00 11. " SPIS811 ,SPI Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High" bitfld.long 0x00 9. " SPIS809 ,SPI Status Bit 809" "Low,High" bitfld.long 0x00 8. " SPIS808 ,SPI Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High" bitfld.long 0x00 6. " SPIS806 ,SPI Status Bit 806" "Low,High" bitfld.long 0x00 5. " SPIS805 ,SPI Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High" bitfld.long 0x00 3. " SPIS803 ,SPI Status Bit 803" "Low,High" bitfld.long 0x00 2. " SPIS802 ,SPI Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High" bitfld.long 0x00 0. " SPIS800 ,SPI Status Bit 800" "Low,High" else hgroup.long 0xC0E4++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) rgroup.long 0xC0E8++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High" bitfld.long 0x00 30. " SPIS862 ,SPI Status Bit 862" "Low,High" bitfld.long 0x00 29. " SPIS861 ,SPI Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High" bitfld.long 0x00 27. " SPIS859 ,SPI Status Bit 859" "Low,High" bitfld.long 0x00 26. " SPIS858 ,SPI Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High" bitfld.long 0x00 24. " SPIS856 ,SPI Status Bit 856" "Low,High" bitfld.long 0x00 23. " SPIS855 ,SPI Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High" bitfld.long 0x00 21. " SPIS853 ,SPI Status Bit 853" "Low,High" bitfld.long 0x00 20. " SPIS852 ,SPI Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High" bitfld.long 0x00 18. " SPIS850 ,SPI Status Bit 850" "Low,High" bitfld.long 0x00 17. " SPIS849 ,SPI Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High" bitfld.long 0x00 15. " SPIS847 ,SPI Status Bit 847" "Low,High" bitfld.long 0x00 14. " SPIS846 ,SPI Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High" bitfld.long 0x00 12. " SPIS844 ,SPI Status Bit 844" "Low,High" bitfld.long 0x00 11. " SPIS843 ,SPI Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High" bitfld.long 0x00 9. " SPIS841 ,SPI Status Bit 841" "Low,High" bitfld.long 0x00 8. " SPIS840 ,SPI Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High" bitfld.long 0x00 6. " SPIS838 ,SPI Status Bit 838" "Low,High" bitfld.long 0x00 5. " SPIS837 ,SPI Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High" bitfld.long 0x00 3. " SPIS835 ,SPI Status Bit 835" "Low,High" bitfld.long 0x00 2. " SPIS834 ,SPI Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High" bitfld.long 0x00 0. " SPIS832 ,SPI Status Bit 832" "Low,High" else hgroup.long 0xC0E8++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) rgroup.long 0xC0EC++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High" bitfld.long 0x00 30. " SPIS894 ,SPI Status Bit 894" "Low,High" bitfld.long 0x00 29. " SPIS893 ,SPI Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High" bitfld.long 0x00 27. " SPIS891 ,SPI Status Bit 891" "Low,High" bitfld.long 0x00 26. " SPIS890 ,SPI Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High" bitfld.long 0x00 24. " SPIS888 ,SPI Status Bit 888" "Low,High" bitfld.long 0x00 23. " SPIS887 ,SPI Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High" bitfld.long 0x00 21. " SPIS885 ,SPI Status Bit 885" "Low,High" bitfld.long 0x00 20. " SPIS884 ,SPI Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High" bitfld.long 0x00 18. " SPIS882 ,SPI Status Bit 882" "Low,High" bitfld.long 0x00 17. " SPIS881 ,SPI Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High" bitfld.long 0x00 15. " SPIS879 ,SPI Status Bit 879" "Low,High" bitfld.long 0x00 14. " SPIS878 ,SPI Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High" bitfld.long 0x00 12. " SPIS876 ,SPI Status Bit 876" "Low,High" bitfld.long 0x00 11. " SPIS875 ,SPI Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High" bitfld.long 0x00 9. " SPIS873 ,SPI Status Bit 873" "Low,High" bitfld.long 0x00 8. " SPIS872 ,SPI Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High" bitfld.long 0x00 6. " SPIS870 ,SPI Status Bit 870" "Low,High" bitfld.long 0x00 5. " SPIS869 ,SPI Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High" bitfld.long 0x00 3. " SPIS867 ,SPI Status Bit 867" "Low,High" bitfld.long 0x00 2. " SPIS866 ,SPI Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High" bitfld.long 0x00 0. " SPIS864 ,SPI Status Bit 864" "Low,High" else hgroup.long 0xC0EC++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) rgroup.long 0xC0F0++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High" bitfld.long 0x00 30. " SPIS926 ,SPI Status Bit 926" "Low,High" bitfld.long 0x00 29. " SPIS925 ,SPI Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High" bitfld.long 0x00 27. " SPIS923 ,SPI Status Bit 923" "Low,High" bitfld.long 0x00 26. " SPIS922 ,SPI Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High" bitfld.long 0x00 24. " SPIS920 ,SPI Status Bit 920" "Low,High" bitfld.long 0x00 23. " SPIS919 ,SPI Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High" bitfld.long 0x00 21. " SPIS917 ,SPI Status Bit 917" "Low,High" bitfld.long 0x00 20. " SPIS916 ,SPI Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High" bitfld.long 0x00 18. " SPIS914 ,SPI Status Bit 914" "Low,High" bitfld.long 0x00 17. " SPIS913 ,SPI Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High" bitfld.long 0x00 15. " SPIS911 ,SPI Status Bit 911" "Low,High" bitfld.long 0x00 14. " SPIS910 ,SPI Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High" bitfld.long 0x00 12. " SPIS908 ,SPI Status Bit 908" "Low,High" bitfld.long 0x00 11. " SPIS907 ,SPI Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High" bitfld.long 0x00 9. " SPIS905 ,SPI Status Bit 905" "Low,High" bitfld.long 0x00 8. " SPIS904 ,SPI Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High" bitfld.long 0x00 6. " SPIS902 ,SPI Status Bit 902" "Low,High" bitfld.long 0x00 5. " SPIS901 ,SPI Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High" bitfld.long 0x00 3. " SPIS899 ,SPI Status Bit 899" "Low,High" bitfld.long 0x00 2. " SPIS898 ,SPI Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High" bitfld.long 0x00 0. " SPIS896 ,SPI Status Bit 896" "Low,High" else hgroup.long 0xC0F0++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) rgroup.long 0xC0F4++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High" bitfld.long 0x00 30. " SPIS958 ,SPI Status Bit 958" "Low,High" bitfld.long 0x00 29. " SPIS957 ,SPI Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High" bitfld.long 0x00 27. " SPIS955 ,SPI Status Bit 955" "Low,High" bitfld.long 0x00 26. " SPIS954 ,SPI Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High" bitfld.long 0x00 24. " SPIS952 ,SPI Status Bit 952" "Low,High" bitfld.long 0x00 23. " SPIS951 ,SPI Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High" bitfld.long 0x00 21. " SPIS949 ,SPI Status Bit 949" "Low,High" bitfld.long 0x00 20. " SPIS948 ,SPI Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High" bitfld.long 0x00 18. " SPIS946 ,SPI Status Bit 946" "Low,High" bitfld.long 0x00 17. " SPIS945 ,SPI Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High" bitfld.long 0x00 15. " SPIS943 ,SPI Status Bit 943" "Low,High" bitfld.long 0x00 14. " SPIS942 ,SPI Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High" bitfld.long 0x00 12. " SPIS940 ,SPI Status Bit 940" "Low,High" bitfld.long 0x00 11. " SPIS939 ,SPI Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High" bitfld.long 0x00 9. " SPIS937 ,SPI Status Bit 937" "Low,High" bitfld.long 0x00 8. " SPIS936 ,SPI Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High" bitfld.long 0x00 6. " SPIS934 ,SPI Status Bit 934" "Low,High" bitfld.long 0x00 5. " SPIS933 ,SPI Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High" bitfld.long 0x00 3. " SPIS931 ,SPI Status Bit 931" "Low,High" bitfld.long 0x00 2. " SPIS930 ,SPI Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High" bitfld.long 0x00 0. " SPIS928 ,SPI Status Bit 928" "Low,High" else hgroup.long 0xC0F4++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) rgroup.long 0xC0F8++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High" bitfld.long 0x00 30. " SPIS990 ,SPI Status Bit 990" "Low,High" bitfld.long 0x00 29. " SPIS989 ,SPI Status Bit 989" "Low,High" textline " " bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High" bitfld.long 0x00 27. " SPIS987 ,SPI Status Bit 987" "Low,High" bitfld.long 0x00 26. " SPIS986 ,SPI Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High" bitfld.long 0x00 24. " SPIS984 ,SPI Status Bit 984" "Low,High" bitfld.long 0x00 23. " SPIS983 ,SPI Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High" bitfld.long 0x00 21. " SPIS981 ,SPI Status Bit 981" "Low,High" bitfld.long 0x00 20. " SPIS980 ,SPI Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High" bitfld.long 0x00 18. " SPIS978 ,SPI Status Bit 978" "Low,High" bitfld.long 0x00 17. " SPIS977 ,SPI Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High" bitfld.long 0x00 15. " SPIS975 ,SPI Status Bit 975" "Low,High" bitfld.long 0x00 14. " SPIS974 ,SPI Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High" bitfld.long 0x00 12. " SPIS972 ,SPI Status Bit 972" "Low,High" bitfld.long 0x00 11. " SPIS971 ,SPI Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High" bitfld.long 0x00 9. " SPIS969 ,SPI Status Bit 969" "Low,High" bitfld.long 0x00 8. " SPIS968 ,SPI Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High" bitfld.long 0x00 6. " SPIS966 ,SPI Status Bit 966" "Low,High" bitfld.long 0x00 5. " SPIS965 ,SPI Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High" bitfld.long 0x00 3. " SPIS963 ,SPI Status Bit 963" "Low,High" bitfld.long 0x00 2. " SPIS962 ,SPI Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High" bitfld.long 0x00 0. " SPIS960 ,SPI Status Bit 960" "Low,High" else hgroup.long 0xC0F8++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B base (COMP.BASE("GICD",-1.)+0x20000) width 24. tree "Interrupt Translation Service" group.long 0x00++0x03 line.long 0x00 "GITS_CTLR,ITS Control Register" rbitfld.long 0x00 31. " QUIESCENT ,Indicates completion of all ITS operations" "Not quiescent,Quiescent" bitfld.long 0x00 0. " ENABLED ,Controls whether the ITS is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" else rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.quad 0x80++0x07 line.quad 0x00 "GITS_CBASER,The command queue control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated" bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the base physical address of the command queue" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of 4KB pages of physical memory allocated to the command queue minus one" group.quad 0x88++0x7 line.quad 0x00 "GITS_CWRITER,The command queue write pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " RETRY ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted" group.quad 0x90++0x07 line.quad 0x00 "GITS_CREADR,The command queue read pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " STALLED ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00) group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." else group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one" endif textline " " wgroup.long 0xC000++0x03 line.long 0x00 "GITS_TRKCTLR,Tracking Control Register" bitfld.long 0x00 1. " LPI_TRACK ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture" bitfld.long 0x00 0. " CACHE_COUNT_RESET ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset" if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 6. " PID_OUT_OF_RANGE ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1" bitfld.long 0x00 5. " TARGET_OUT_OF_RANGE ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1" textline " " bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" textline " " bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" else rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC008++0x03 line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" hexmask.long.tbyte 0x00 0.--19. 1. " LPI_DID ,The Device ID for the interrupt that was tracked" else hgroup.long 0xC008++0x03 hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC00C++0x03 line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_PID ,The ID after translation for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC00C++0x03 hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC010++0x03 line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_ID ,The ID before translation of the interrupt that was tracked" else hgroup.long 0xC010++0x03 hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC014++0x03 line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" hexmask.long.byte 0x00 0.--6. 1. " LPI_TARGET_CORE ,The target core for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC014++0x03 hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" endif rgroup.long 0xC018++0x03 line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " ITE_CACHE_HITS ,Number of hits in the ITE cache" hexmask.long.word 0x00 0.--15. 1. " ITE_CACHE_MISSES ,Number of misses in the ITE cache" rgroup.long 0xC01C++0x03 line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " LPI_CACHE_HITS ,Number of hits in the LPI cache" hexmask.long.word 0x00 0.--15. 1. " LPI_CACHE_MISSES ,Number of misses in the LPI cache" rgroup.long 0xFFE0++0x03 line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" textline " " bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GITS_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GITS_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GITS_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GITS_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " base (COMP.BASE("GICD",-1.)+0x20000)+0x10000 if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01) wgroup.long 0x40++0x03 line.long 0x00 "GITS_TRANSLATER,ITS Translation Register" else hgroup.long 0x40++0x03 hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register" endif tree.end width 0x0B base COMP.BASE("GICR",-1.) width 17. tree "Redistributor Interface" tree "Control Registers" if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register" hexmask.quad.byte 0x00 56.--63. 1. " AFF3 ,Affinity level 3 value for the Redistributor" hexmask.quad.byte 0x00 48.--55. 1. " AFF2 ,Affinity level 2 value for the Redistributor" hexmask.quad.byte 0x00 40.--47. 1. " AFF1 ,Affinity level 1 value for the Redistributor" textline " " hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0 value for the Redistributor" bitfld.quad 0x00 24.--25. " COMMONLPIAFF ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,A unique identifier for the PE" textline " " bitfld.quad 0x00 5. " DPGS ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported" bitfld.quad 0x00 4. " LAST ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest" bitfld.quad 0x00 3. " DIRECTLPI ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported" textline " " bitfld.quad 0x00 0. " PLPIS ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014)))) group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Power Management Control Register" bitfld.long 0x00 31. " QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent" bitfld.long 0x00 2. " CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent" bitfld.long 0x00 1. " PROCESSORASLEEP ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes" textline " " bitfld.long 0x00 0. " SLEEP ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes" textline " " else hgroup.long 0x0014++0x03 hide.long 0x00 "GICR_WAKER,Power Management Control Register" endif group.quad 0x070++0x07 line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..." bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 0.--4. " IDBITS ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address" group.quad 0x78++0x07 line.quad 0x00 "GICR_PENDBASER,LPI pending table base register" bitfld.quad 0x00 62. " PTZ ,Pending Table Zero" "Not zero,Zero" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" textline " " hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " tree.end tree "SGI and PPI Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080)) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x10080++0x03 hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif textline " " width 24. group.long 0x10100++0x03 line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" textline " " width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " textline " " rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " width 18. if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00)) group.long 0x10D00++0x03 line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1" bitfld.long 0x00 30. " GMB30 ,Group Modifier Bit 30" "0,1" bitfld.long 0x00 29. " GMB29 ,Group Modifier Bit 29" "0,1" textline " " bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1" bitfld.long 0x00 27. " GMB27 ,Group Modifier Bit 27" "0,1" bitfld.long 0x00 26. " GMB26 ,Group Modifier Bit 26" "0,1" textline " " bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1" bitfld.long 0x00 24. " GMB24 ,Group Modifier Bit 24" "0,1" bitfld.long 0x00 23. " GMB23 ,Group Modifier Bit 23" "0,1" textline " " bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1" bitfld.long 0x00 21. " GMB21 ,Group Modifier Bit 21" "0,1" bitfld.long 0x00 20. " GMB20 ,Group Modifier Bit 20" "0,1" textline " " bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1" bitfld.long 0x00 18. " GMB18 ,Group Modifier Bit 18" "0,1" bitfld.long 0x00 17. " GMB17 ,Group Modifier Bit 17" "0,1" textline " " bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1" bitfld.long 0x00 15. " GMB15 ,Group Modifier Bit 15" "0,1" bitfld.long 0x00 14. " GMB14 ,Group Modifier Bit 14" "0,1" textline " " bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1" bitfld.long 0x00 12. " GMB12 ,Group Modifier Bit 12" "0,1" bitfld.long 0x00 11. " GMB11 ,Group Modifier Bit 11" "0,1" textline " " bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1" bitfld.long 0x00 9. " GMB9 ,Group Modifier Bit 9" "0,1" bitfld.long 0x00 8. " GMB8 ,Group Modifier Bit 8" "0,1" textline " " bitfld.long 0x00 7. " GMB7 ,Group Modifier Bit 7" "0,1" bitfld.long 0x00 6. " GMB6 ,Group Modifier Bit 6" "0,1" bitfld.long 0x00 5. " GMB5 ,Group Modifier Bit 5" "0,1" textline " " bitfld.long 0x00 4. " GMB4 ,Group Modifier Bit 4" "0,1" bitfld.long 0x00 3. " GMB3 ,Group Modifier Bit 3" "0,1" bitfld.long 0x00 2. " GMB2 ,Group Modifier Bit 2" "0,1" textline " " bitfld.long 0x00 1. " GMB1 ,Group Modifier Bit 1" "0,1" bitfld.long 0x00 0. " GMB0 ,Group Modifier Bit 0" "0,1" textline " " else hgroup.long 0x10D00++0x03 hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00)) group.long 0x10E00++0x03 line.long 0x00 "GICR_NSACR,Non-secure Access Control Register" bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 28.--29. " NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 26.--27. " NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 22.--23. " NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 20.--21. " NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 18.--19. " NS_ACCESS9 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 16.--17. " NS_ACCESS8 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 14.--15. " NS_ACCESS7 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 12.--13. " NS_ACCESS6 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 10.--11. " NS_ACCESS5 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 8.--9. " NS_ACCESS4 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 6.--7. " NS_ACCESS3 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 4.--5. " NS_ACCESS2 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 2.--3. " NS_ACCESS1 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 0.--1. " NS_ACCESS0 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..." textline " " else hgroup.long 0x10E00++0x03 hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register" textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x1C000++0x03 line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register" bitfld.long 0x00 31. " CPU_AS ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High" bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1" bitfld.long 0x00 1. " ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1" rgroup.long 0x1C080++0x03 line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 31. " PPI31S ,Actual status of the PPI31 input signal" "Low,High" bitfld.long 0x00 30. " PPI30S ,Actual status of the PPI30 input signal" "Low,High" bitfld.long 0x00 29. " PPI29S ,Actual status of the PPI29 input signal" "Low,High" textline " " bitfld.long 0x00 28. " PPI28S ,Actual status of the PPI28 input signal" "Low,High" bitfld.long 0x00 27. " PPI27S ,Actual status of the PPI27 input signal" "Low,High" bitfld.long 0x00 26. " PPI26S ,Actual status of the PPI26 input signal" "Low,High" textline " " bitfld.long 0x00 25. " PPI25S ,Actual status of the PPI25 input signal" "Low,High" bitfld.long 0x00 24. " PPI24S ,Actual status of the PPI24 input signal" "Low,High" bitfld.long 0x00 23. " PPI23S ,Actual status of the PPI23 input signal" "Low,High" textline " " bitfld.long 0x00 22. " PPI22S ,Actual status of the PPI22 input signal" "Low,High" bitfld.long 0x00 21. " PPI21S ,Actual status of the PPI21 input signal" "Low,High" bitfld.long 0x00 20. " PPI20S ,Actual status of the PPI20 input signal" "Low,High" textline " " bitfld.long 0x00 19. " PPI19S ,Actual status of the PPI19 input signal" "Low,High" bitfld.long 0x00 18. " PPI18S ,Actual status of the PPI18 input signal" "Low,High" bitfld.long 0x00 17. " PPI17S ,Actual status of the PPI17 input signal" "Low,High" textline " " bitfld.long 0x00 16. " PPI16S ,Actual status of the PPI16 input signal" "Low,High" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B sif COMP.AVAILABLE("GICC") base COMP.BASE("GICC",-1.) width 14. tree "CPU Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.))) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" textline " " bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" endif textline " " group.long 0x04++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x08++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x0C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x10++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x20++0x03 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in wgroup.long 0x24++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x2C++0x03 line.long 0x00 "GICC_STATUSR,CPU Interface Status Register" bitfld.long 0x00 4. " ASV ,Attempted security violation" "Not detected,Detected" bitfld.long 0x00 3. " WROD ,Write to an RO location" "Not detected,Detected" bitfld.long 0x00 2. " RWOD ,Read of a WO location" "Not detected,Detected" textline " " bitfld.long 0x00 1. " WRD ,Write to a reserved location" "Not detected,Detected" bitfld.long 0x00 0. " RRD ,Read of a reserved location" "Not detected,Detected" group.long 0xD0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register 0" group.long 0xD4++0x03 line.long 0x00 "GICC_APR1,Active Priorities Register 1" group.long 0xD8++0x03 line.long 0x00 "GICC_APR2,Active Priorities Register 2" group.long 0xDC++0x03 line.long 0x00 "GICC_APR3,Active Priorities Register 3" group.long 0xE0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0" group.long 0xE4++0x03 line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1" group.long 0xE8++0x03 line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2" group.long 0xEC++0x03 line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3" rgroup.long 0xFC++0x03 line.long 0x00 "GICC_IIDR,CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..." bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICH") base COMP.BASE("GICH",-1.) width 13. tree "Virtual CPU Control Interface" group.long 0x00++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,Virtual CPU interface Enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GICH_VTR,Virtual Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 23.--25. " IDBITS ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..." textline " " bitfld.long 0x00 22. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. " A3V ,Affinity 3 valid" "Invalid,Valid" bitfld.long 0x00 0.--4. " LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x08++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. " VPMR ,Virtual priority mask" bitfld.long 0x00 21.--23. " VBPR0 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VBPR1 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. " VEOIM ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" textline " " bitfld.long 0x00 4. " VCBPR ,Virtual Common Binary Point Register" "ABPR,BPR" bitfld.long 0x00 3. " VFIQEN ,Virtual FIQ enable" "Disabled,Enabled" bitfld.long 0x00 2. " VACKCTL ,Virtual AckCtl" "INTID=1022,INTID=corresponding" bitfld.long 0x00 1. " VENG1 ,Virtual interrupt enable for group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VENG0 ,Virtual interrupt enable for group 0" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 6. " VGRP1E ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 5. " VGRP0D ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 4. " VGRP0E ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 1. " U ,Underflow maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 0. " EOI ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted" rgroup.long 0x20++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x30++0x03 line.long 0x00 "GICH_ELRSR0,Empty List register Status Register" bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,Status bit for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,Status bit for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,Status bit for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,Status bit for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,Status bit for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,Status bit for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,Status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,Status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,Status bit for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,Status bit for List register 0" "No interrupt,Interrupt" textline " " group.long 0xF0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF4++0x03 line.long 0x00 "GICH_APR1,Active Priorities Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF8++0x03 line.long 0x00 "GICH_APR2,Active Priorities Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "GICH_APR3,Active Priorities Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x110++0x03 line.long 0x00 "GICH_LR4,List Register 4" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x114++0x03 line.long 0x00 "GICH_LR5,List Register 5" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x118++0x03 line.long 0x00 "GICH_LR6,List Register 6" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x11C++0x03 line.long 0x00 "GICH_LR7,List Register 7" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x120++0x03 line.long 0x00 "GICH_LR8,List Register 8" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x124++0x03 line.long 0x00 "GICH_LR9,List Register 9" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x128++0x03 line.long 0x00 "GICH_LR10,List Register 10" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x12C++0x03 line.long 0x00 "GICH_LR11,List Register 11" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x130++0x03 line.long 0x00 "GICH_LR12,List Register 12" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x134++0x03 line.long 0x00 "GICH_LR13,List Register 13" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x138++0x03 line.long 0x00 "GICH_LR14,List Register 14" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICV") base COMP.BASE("GICV",-1.) width 14. tree "Virtual CPU Interface" group.long 0x00++0x03 line.long 0x00 "GICV_CTLR,VM Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 4. " CBPR ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,FIQ Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for the virtual CPU interface" group.long 0x08++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x0C++0x03 line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x10++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x03 line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x24++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" textline "" group.long 0xD0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD4++0x03 line.long 0x00 "GICV_APR1,VM Active Priority Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD8++0x03 line.long 0x00 "GICV_APR2,VM Active Priority Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "GICV_APR3,VM Active Priority Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " rgroup.long 0xFC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" ",,,GICv3,?..." hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif width 0x0B AUTOINDENT.POP tree.end tree.end endif tree "ARMSS_VIC_CFG" base ad:0xFF80000 rgroup.long 0x0++0x27 line.long 0x0 "R5FSS_VIM_PID,This register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." line.long 0x4 "R5FSS_VIM_INFO,This contains information about the configuration of the R5FSS_VIM." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Indicates the number of interrupts supported by the VIM." line.long 0x8 "R5FSS_VIM_PRIIRQ,This register contains the number of the highest priority pending IRQ." bitfld.long 0x8 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x8 16.--19. 1. "PRI,This field indicates the priority of the pending IRQ interrupt." hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x8 0.--9. 1. "NUM,This field indicates the interrupt number of the pending IRQ interrupt with the highest priority." line.long 0xC "R5FSS_VIM_PRIFIQ,This register contains the number of the highest priority pending FIQ." bitfld.long 0xC 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0xC 16.--19. 1. "PRI,This field indicates the priority of the pending FIQ interrupt." hexmask.long.byte 0xC 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0xC 0.--9. 1. "NUM,This field indicates the interrupt number of the pending FIQ interrupt with the highest priority." line.long 0x10 "R5FSS_VIM_IRQGSTS,This register indicates which groups of interrupts have pending. unmasked IRQ interrupts." hexmask.long 0x10 0.--31. 1. "STS,This field indicates that one or more interrupts in group M are mapped to IRQ unmasked and pending. Bit 0 corresponds to group 0 bit 1 corresponds to group 1 etc. The interrupts associated with each group are [(M*32)+31:M*32]" line.long 0x14 "R5FSS_VIM_FIQGSTS,This register indicates which groups of interrupts have pending. unmasked FIQ interrupts." hexmask.long 0x14 0.--31. 1. "STS,This field indicates that one or more interrupts in group M are mapped to FIQ unmasked and pending. Bit 0 corresponds to group 0 bit 1 corresponds to group 1 etc. The interrupts associated with each group are [(M*32)+31:M*32]" line.long 0x18 "R5FSS_VIM_IRQVEC,This register contains the 32-bit interrupt vector address of the currently pending IRQ." hexmask.long 0x18 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority IRQ (as indicated by the" bitfld.long 0x18 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" line.long 0x1C "R5FSS_VIM_FIQVEC,This register contains the 32-bit interrupt vector address of the currently pending FIQ." hexmask.long 0x1C 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority FIQ (as indicated by the" bitfld.long 0x1C 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" line.long 0x20 "R5FSS_VIM_ACTIRQ,This register contains the number of the active IRQ." bitfld.long 0x20 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x20 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x20 16.--19. 1. "PRI,This field indicates the priority of the active IRQ interrupt." hexmask.long.byte 0x20 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x20 0.--9. 1. "NUM,This field indicates the interrupt number of the active IRQ interrupt." line.long 0x24 "R5FSS_VIM_ACTFIQ,This register contains the number of the active FIQ." bitfld.long 0x24 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x24 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x24 16.--19. 1. "PRI,This field indicates the priority of the active FIQ interrupt." hexmask.long.byte 0x24 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x24 0.--9. 1. "NUM,This field indicates the interrupt number of the active FIQ interrupt." group.long 0x30++0x3 line.long 0x0 "R5FSS_VIM_DEDVEC,This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors." hexmask.long 0x0 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (the address must be 32-bit aligned) of an interrupt to be used if an uncorrectable double-bit error (DED) is detected in any of the interrupt vector addresses." rbitfld.long 0x0 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" group.long 0x400++0x1F line.long 0x0 "R5FSS_VIM_RAW_j,This register indicates the raw status of the events in group M. Offset = 400h + (j * 20h); where j = 0h to Fh." hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x4 "R5FSS_VIM_STS_j,This register indicates the masked status of the events in group M. Offset = 404h + (j * 20h); where j = 0h to Fh." hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status of the events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x8 "R5FSS_VIM_INTR_EN_SET_j,This register is used to enable the mask for the events in group M. Offset = 408h + (j * 20h); where j = 0h to Fh." hexmask.long 0x8 0.--31. 1. "MSK,This field is used to enable the mask of events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0xC "R5FSS_VIM_INTR_EN_CLR_j,This register is used to disable the mask for the events in group M. Offset = 40Ch + (j * 20h); where j = 0h to Fh." hexmask.long 0xC 0.--31. 1. "MSK,This field is used to disable the mask of events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x10 "R5FSS_VIM_IRQSTS_j,This register indicates the masked status of the events in Group M that are also mapped as IRQs. Offset = 410h + (j * 20h); where j = 0h to Fh." hexmask.long 0x10 0.--31. 1. "MSK,This is the masked status of the events in group M that are mapped to IRQ. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x14 "R5FSS_VIM_FIQSTS_j,This register indicates the masked status of the events in group M that are also mapped as FIQs. Offset = 414h + (j * 20h); where j = 0h to Fh." hexmask.long 0x14 0.--31. 1. "MSK,This is the masked status of the events in group M that are mapped to FIQ. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x18 "R5FSS_VIM_INTMAP_j,This register is used to map interrupts as IRQ or FIQ. Offset = 418h + (j * 20h); where j = 0h to Fh." hexmask.long 0x18 0.--31. 1. "MSK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x1C "R5FSS_VIM_INTTYPE_j,This register indicates whether an interrupt is a pulse or level source. Offset = 41Ch + (j * 20h); where j = 0h to Fh." hexmask.long 0x1C 0.--31. 1. "MSK,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." group.long 0x1000++0x3 line.long 0x0 "R5FSS_VIM_PRI_INT_j,This register is used to set the priority of interrupt Q. Offset = 1000h + (j * 4h); where j = 0h to 1FFh." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x0 0.--3. 1. "VAL,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration." group.long 0x2000++0x3 line.long 0x0 "R5FSS_VIM_VEC_INT_j,This register contains the vector address associated with interrupt Q. Offset = 2000h + (j * 4h); where j = 0h to 1FFh." hexmask.long 0x0 2.--31. 1. "VAL,These are the upper 30 bits of the 32-bit vector address associated with interrupt Q. It is the address that will be reflected in the" rbitfld.long 0x0 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" tree.end tree "ATL0_REG" base ad:0x31F0000 rgroup.long 0x0++0x3 line.long 0x0 "ATL_REVISION,Return to the . The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL" bitfld.long 0x0 8.--10. "MAJOR,Major" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor" group.long 0x200++0x3 line.long 0x0 "ATL0_PPMR,Return to the . The PPM register is used by the Audio re-timing code. The DAC over-sampling clock will slow down or speed up by the PPM written to bits [8:0]." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "PPM_SD" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "PPM_SET,This is the" rgroup.long 0x204++0x3 line.long 0x0 "ATL0_BBSR,Return to the . The measuring circuit produces a 16-bit Sample Count. Its inputs are the Audio IIS Word Select (AWS) and the Baseband IIS Word Select (BWS) from their respective MCASP pins. The sample count is a read-only register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SMP_CNT,This is the" group.long 0x208++0x3 line.long 0x0 "ATL0_ATLCR,Return to the . The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "CLK_DIV_SEL" "0,1" hexmask.long.byte 0x0 0.--4. 1. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" group.long 0x210++0xF line.long 0x0 "ATL0_SWEN,Return to the . The software enable register is used to enable/disable the ATL." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes." "0,1" line.long 0x4 "ATL0_BWSMUX,Return to the . The Baseband IIS Word Select mux select control register" hexmask.long 0x4 4.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "SELECT,BWS input select:" line.long 0x8 "ATL0_AWSMUX,Return to the . The Audio IIS Word Select mux select control register" hexmask.long 0x8 4.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--3. 1. "SELECT,AWS input select:" line.long 0xC "ATL0_PCLKMUX,Return to the . ATL core input clock mux select control register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "SELECT,ATL" "0,1" group.long 0x280++0x3 line.long 0x0 "ATL1_PPMR,Return to the . The PPM register is used by the Audio re-timing code. The DAC over-sampling clock will slow down or speed up by the PPM written to bits [8:0]." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "PPM_SD" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "PPM_SET,This is the" rgroup.long 0x284++0x3 line.long 0x0 "ATL1_BBSR,Return to the . The measuring circuit produces a 16-bit Sample Count. Its inputs are the Audio IIS Word Select (AWS) and the Baseband IIS Word Select (BWS) from their respective MCASP pins. The sample count is a read-only register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SMP_CNT,This is the" group.long 0x288++0x3 line.long 0x0 "ATL1_ATLCR,Return to the . The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "CLK_DIV_SEL" "0,1" hexmask.long.byte 0x0 0.--4. 1. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" group.long 0x290++0xF line.long 0x0 "ATL1_SWEN,Return to the . The software enable register is used to enable/disable the ATL." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes." "0,1" line.long 0x4 "ATL1_BWSMUX,Return to the . The Baseband IIS Word Select mux select control register" hexmask.long 0x4 4.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "SELECT,BWS input select:" line.long 0x8 "ATL1_AWSMUX,Return to the . The Audio IIS Word Select mux select control register" hexmask.long 0x8 4.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--3. 1. "SELECT,AWS input select:" line.long 0xC "ATL1_PCLKMUX,Return to the . ATL core input clock mux select control register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "SELECT,Non-functional" "0,1" group.long 0x300++0x3 line.long 0x0 "ATL2_PPMR,Return to the . The PPM register is used by the Audio re-timing code. The DAC over-sampling clock will slow down or speed up by the PPM written to bits [8:0]." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "PPM_SD" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "PPM_SET,This is the" rgroup.long 0x304++0x3 line.long 0x0 "ATL2_BBSR,Return to the . The measuring circuit produces a 16-bit Sample Count. Its inputs are the Audio IIS Word Select (AWS) and the Baseband IIS Word Select (BWS) from their respective MCASP pins. The sample count is a read-only register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SMP_CNT,This is the" group.long 0x308++0x3 line.long 0x0 "ATL2_ATLCR,Return to the . The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "CLK_DIV_SEL" "0,1" hexmask.long.byte 0x0 0.--4. 1. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" group.long 0x310++0xF line.long 0x0 "ATL2_SWEN,Return to the . The software enable register is used to enable/disable the ATL." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes." "0,1" line.long 0x4 "ATL2_BWSMUX,Return to the . The Baseband IIS Word Select mux select control register" hexmask.long 0x4 4.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "SELECT,BWS input select:" line.long 0x8 "ATL2_AWSMUX,Return to the . The Audio IIS Word Select mux select control register" hexmask.long 0x8 4.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--3. 1. "SELECT,AWS input select:" line.long 0xC "ATL2_PCLKMUX,Return to the . ATL core input clock mux select control register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "SELECT,Non-functional" "0,1" group.long 0x380++0x3 line.long 0x0 "ATL3_PPMR,Return to the . The PPM register is used by the Audio re-timing code. The DAC over-sampling clock will slow down or speed up by the PPM written to bits [8:0]." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "PPM_SD" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "PPM_SET,This is the" rgroup.long 0x384++0x3 line.long 0x0 "ATL3_BBSR,Return to the . The measuring circuit produces a 16-bit Sample Count. Its inputs are the Audio IIS Word Select (AWS) and the Baseband IIS Word Select (BWS) from their respective MCASP pins. The sample count is a read-only register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SMP_CNT,This is the" group.long 0x388++0x3 line.long 0x0 "ATL3_ATLCR,Return to the . The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "CLK_DIV_SEL" "0,1" hexmask.long.byte 0x0 0.--4. 1. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" group.long 0x390++0xF line.long 0x0 "ATL3_SWEN,Return to the . The software enable register is used to enable/disable the ATL." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes." "0,1" line.long 0x4 "ATL3_BWSMUX,Return to the . The Baseband IIS Word Select mux select control register" hexmask.long 0x4 4.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "SELECT,BWS input select:" line.long 0x8 "ATL3_AWSMUX,Return to the . The Audio IIS Word Select mux select control register" hexmask.long 0x8 4.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--3. 1. "SELECT,AWS input select:" line.long 0xC "ATL3_PCLKMUX,Return to the . ATL core input clock mux select control register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "SELECT,Non-functional" "0,1" tree.end tree "CBASS" base ad:0x0 tree "CBASS_DATADEBUG0_ERR" base ad:0x2A6000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_DATADEBUG0_GLB" base ad:0x45B20800 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_FW0_ERR" base ad:0xB8000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_HC2_0_ERR" base ad:0x2A3000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_HC2_0_GLB" base ad:0x45B22800 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_HC_CFG0_ERR" base ad:0x2A9000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_HC_CFG0_GLB" base ad:0x45B21000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_INFRA0_ERR" base ad:0xB0000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_INFRA0_GLB" base ad:0x45B0C000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_INFRA_NON_SAFE0_ERR" base ad:0xB4000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_INFRA_NON_SAFE0_GLB" base ad:0x45B24000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_IPPHY0_ERR" base ad:0x2AF000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_IPPHY0_GLB" base ad:0x45B21400 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_IPPHY_SAFE0_ERR" base ad:0x2A4000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_IPPHY_SAFE0_GLB" base ad:0x45B24400 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_MCASP_G0_0_ERR" base ad:0x2AA000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_MCASP_G0_0_GLB" base ad:0x45B21800 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_RC0_ERR" base ad:0x2AC000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_RC0_GLB" base ad:0x45B22000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS_RC_CFG0_ERR" base ad:0x2AD000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "CBASS_RC_CFG0_GLB" base ad:0x45B22400 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree "CMPEVENT_INTRTR0_INTR_ROUTER_CFG" base ad:0xA30000 rgroup.long 0x0++0x3 line.long 0x0 "CMPEVT_INTRTR0_PID,Peripheral identification register. Uniquely identifies the module and its specific revision." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "CMPEVT_INTRTR0_MUXCNTL_y,Event mux control register. Offset = 4h + (y * 4h); where y = 0h to Fh." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "INT_ENABLE,Enable for event output N" "0,1" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Mux control for event output N" tree.end tree "COMPUTE_CLUSTER" base ad:0x0 tree "COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR" base ad:0x4D20010000 rgroup.long 0x0++0x3 line.long 0x0 "A72SS_CLUSTER_ECC_REV,IP revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "A72SS_CLUSTER_ECC_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "A72SS_CLUSTER_ECC_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator" group.long 0x3C++0xB line.long 0x0 "A72SS_CLUSTER_ECC_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "A72SS_CLUSTER_ECC_SEC_STATUS_REG0,SEC interrupt status register 0." bitfld.long 0x4 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x8 "A72SS_CLUSTER_ECC_SEC_STATUS_REG1,SEC interrupt status register 1." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_PEND,Interrupt pending status for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x8 8. "VBUSP_CFG_M2M_M2M_VBUSS_PEND,Interrupt pending status for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x8 7. "VBUSP_CFG_M2M_DST_VBUSS_PEND,Interrupt pending status for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x8 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND,Interrupt pending status for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x8 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x8 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 0. "EDC_CTRL_ECCAGGR_COREPAC_PEND,Interrupt pending status for edc_ctrl_eccaggr_corepac_pend" "0,1" group.long 0x80++0x7 line.long 0x0 "A72SS_CLUSTER_ECC_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." bitfld.long 0x0 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x4 "A72SS_CLUSTER_ECC_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_SET,Interrupt enable set for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 8. "VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET,Interrupt enable set for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET,Interrupt enable set for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt enable set for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x4 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET,Interrupt enable set for edc_ctrl_eccaggr_corepac_pend" "0,1" group.long 0xC0++0x7 line.long 0x0 "A72SS_CLUSTER_ECC_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." bitfld.long 0x0 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x4 "A72SS_CLUSTER_ECC_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_CLR,Interrupt enable clear for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 8. "VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt enable clear for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR,Interrupt enable clear for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt enable clear for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x4 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR,Interrupt enable clear for edc_ctrl_eccaggr_corepac_pend" "0,1" group.long 0x13C++0xB line.long 0x0 "A72SS_CLUSTER_ECC_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "A72SS_CLUSTER_ECC_DED_STATUS_REG0,DED interrupt status register 0." bitfld.long 0x4 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x8 "A72SS_CLUSTER_ECC_DED_STATUS_REG1,DED interrupt status register 1." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_PEND,Interrupt pending status for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x8 8. "VBUSP_CFG_M2M_M2M_VBUSS_PEND,Interrupt pending status for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x8 7. "VBUSP_CFG_M2M_DST_VBUSS_PEND,Interrupt pending status for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x8 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND,Interrupt pending status for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x8 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x8 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_PEND,Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x8 0. "EDC_CTRL_ECCAGGR_COREPAC_PEND,Interrupt pending status for edc_ctrl_eccaggr_corepac_pend" "0,1" group.long 0x180++0x7 line.long 0x0 "A72SS_CLUSTER_ECC_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." bitfld.long 0x0 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x4 "A72SS_CLUSTER_ECC_DED_ENABLE_SET_REG1,DED interrupt enable set register 1." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED" newline bitfld.long 0x4 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_SET,Interrupt enable set for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 8. "VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET,Interrupt enable set for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET,Interrupt enable set for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt enable set for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x4 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_SET,Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr_corepac_pend" "0,1" group.long 0x1C0++0x7 line.long 0x0 "A72SS_CLUSTER_ECC_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." bitfld.long 0x0 31. "L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_incl_plru_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 30. "L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_incl_plru_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 29. "L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_dirty_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 28. "L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_dirty_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 27. "L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 26. "L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_snp_tag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_snp_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_snp_tag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for l2_snp_tag_spram_bank0_ecc_svbus_pend" "0,1" line.long 0x4 "A72SS_CLUSTER_ECC_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 9. "VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_CLR,Interrupt enable clear for vbusp_cfg_dst_m2p_dst_busecc_pend" "0,1" newline bitfld.long 0x4 8. "VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR,Interrupt enable clear for vbusp_cfg_m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 7. "VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR,Interrupt enable clear for vbusp_cfg_m2m_dst_vbuss_pend" "0,1" newline bitfld.long 0x4 6. "VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt enable clear for vbusp_cfg_dst_m2p_src_busecc_pend" "0,1" newline bitfld.long 0x4 5. "A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend" "0,1" newline bitfld.long 0x4 4. "A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 3. "A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 2. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR,Interrupt enable clear for edc_ctrl_eccaggr_corepac_pend" "0,1" group.long 0x200++0xF line.long 0x0 "A72SS_CLUSTER_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "A72SS_CLUSTER_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "A72SS_CLUSTER_ECC_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "A72SS_CLUSTER_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR" base ad:0x4D20014000 rgroup.long 0x0++0x3 line.long 0x0 "A72SS_CORE0_ECC_REV,IP revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "A72SS_CORE0_ECC_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "A72SS_CORE0_ECC_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator" group.long 0x3C++0x7 line.long 0x0 "A72SS_CORE0_ECC_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "A72SS_CORE0_ECC_SEC_STATUS_REG0,SEC interrupt status register 0." hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 24. "EDC_CTRL_ECCAGGR_CPU0_PEND,Interrupt pending status for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x4 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x4 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x4 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x4 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "A72SS_CORE0_ECC_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU0_ENABLE_SET,Interrupt enable set for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x0 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "A72SS_CORE0_ECC_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU0_ENABLE_CLR,Interrupt enable clear for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x0 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "A72SS_CORE0_ECC_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "A72SS_CORE0_ECC_DED_STATUS_REG0,DED interrupt status register 0." hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 24. "EDC_CTRL_ECCAGGR_CPU0_PEND,Interrupt pending status for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x4 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x4 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x4 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x4 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "A72SS_CORE0_ECC_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU0_ENABLE_SET,Interrupt enable set for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x0 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "A72SS_CORE0_ECC_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU0_ENABLE_CLR,Interrupt enable clear for edc_ctrl_eccaggr_cpu0_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 22. "CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 20. "CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 18. "CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 16. "CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x0 14. "CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 12. "CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 10. "CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 8. "CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 6. "CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 4. "CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 2. "CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 0. "CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu0_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x200++0xF line.long 0x0 "A72SS_CORE0_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "A72SS_CORE0_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "A72SS_CORE0_ECC_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "A72SS_CORE0_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR" base ad:0x4D20018000 rgroup.long 0x0++0x3 line.long 0x0 "A72SS_CORE1_ECC_REV,IP revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "A72SS_CORE1_ECC_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "A72SS_CORE1_ECC_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator" group.long 0x3C++0x7 line.long 0x0 "A72SS_CORE1_ECC_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "A72SS_CORE1_ECC_SEC_STATUS_REG0,SEC interrupt status register 0." hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 24. "EDC_CTRL_ECCAGGR_CPU1_PEND,Interrupt pending status for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x4 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x4 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x4 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x4 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "A72SS_CORE1_ECC_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU1_ENABLE_SET,Interrupt enable set for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x0 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "A72SS_CORE1_ECC_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU1_ENABLE_CLR,Interrupt enable clear for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x0 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "A72SS_CORE1_ECC_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "A72SS_CORE1_ECC_DED_STATUS_REG0,DED interrupt status register 0." hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 24. "EDC_CTRL_ECCAGGR_CPU1_PEND,Interrupt pending status for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x4 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x4 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x4 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x4 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x4 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x4 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt pending status for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "A72SS_CORE1_ECC_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU1_ENABLE_SET,Interrupt enable set for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x0 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt enable set for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "A72SS_CORE1_ECC_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "EDC_CTRL_ECCAGGR_CPU1_ENABLE_CLR,Interrupt enable clear for edc_ctrl_eccaggr_cpu1_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_l2_tlb_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 22. "CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_l2_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_l2_tlb_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 20. "CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_l2_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_tag_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 18. "CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_tag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 16. "CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank7_ecc_svbus_pend" "0,1" bitfld.long 0x0 14. "CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 12. "CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 10. "CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 8. "CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_ls_data_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_tag_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 6. "CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_tag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank5_ecc_svbus_pend" "0,1" bitfld.long 0x0 4. "CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank3_ecc_svbus_pend" "0,1" bitfld.long 0x0 2. "CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank1_ecc_svbus_pend" "0,1" bitfld.long 0x0 0. "CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt enable clear for cpu1_if_data_spram_bank0_ecc_svbus_pend" "0,1" group.long 0x200++0xF line.long 0x0 "A72SS_CORE1_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "A72SS_CORE1_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "A72SS_CORE1_ECC_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "A72SS_CORE1_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "COMPUTE_CLUSTER0_CTL_CFG" base ad:0x2990000 group.long 0x0++0x3 line.long 0x0 "DDRSS_CTL_0" hexmask.long.word 0x0 16.--31. 1. "CONTROLLER_ID,Holds the controller product id number." hexmask.long.byte 0x0 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x0 8.--11. 1. "DRAM_CLASS,Defines the class of DRAM memory which is connected to the controller.7h - LPDDR3Bh - LPDDR4All other values reserved" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "START,Initiate command processing in the controller." "0,1" rgroup.long 0x4++0x17 line.long 0x0 "DDRSS_CTL_1" hexmask.long 0x0 0.--31. 1. "CONTROLLER_VERSION_0,Holds the controller version id." line.long 0x4 "DDRSS_CTL_2" hexmask.long 0x4 0.--31. 1. "CONTROLLER_VERSION_1,Holds the controller version id." line.long 0x8 "DDRSS_CTL_3" hexmask.long.byte 0x8 24.--31. 1. "READ_DATA_FIFO_DEPTH,Reports the depth of the controller core read data queue." hexmask.long.byte 0x8 18.--23. 1. "RESERVED" newline bitfld.long 0x8 16.--17. "MAX_CS_REG,Holds the maximum number of chip selects available." "0,1,2,3" hexmask.long.byte 0x8 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x8 8.--11. 1. "MAX_COL_REG,Holds the maximum width of column address in DRAMs." bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "MAX_ROW_REG,Holds the maximum width of memory address bus." line.long 0xC "DDRSS_CTL_4" hexmask.long.byte 0xC 24.--31. 1. "RESERVED" hexmask.long.byte 0xC 16.--23. 1. "WRITE_DATA_FIFO_PTR_WIDTH,Reports the width of the controller core write data latency queue pointer." newline hexmask.long.byte 0xC 8.--15. 1. "WRITE_DATA_FIFO_DEPTH,Reports the depth of the controller core write data latency queue." hexmask.long.byte 0xC 0.--7. 1. "READ_DATA_FIFO_PTR_WIDTH,Reports the width of the controller core read data queue pointer." line.long 0x10 "DDRSS_CTL_5" hexmask.long.byte 0x10 24.--31. 1. "ASYNC_CDC_STAGES,Reports the number of synchronizer delays specified for the asynchronous boundary crossings." hexmask.long.byte 0x10 16.--23. 1. "MEMCD_RMODW_FIFO_PTR_WIDTH,Reports the width of the controller core read/modify/write FIFO pointer." newline hexmask.long.word 0x10 0.--15. 1. "MEMCD_RMODW_FIFO_DEPTH,Reports the depth of the controller core read/modify/write FIFO." line.long 0x14 "DDRSS_CTL_6" hexmask.long.byte 0x14 24.--31. 1. "AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 write command processing FIFO." hexmask.long.byte 0x14 16.--23. 1. "AXI0_WR_ARRAY_LOG2_DEPTH,Reports the depth of the AXI port 0 write data array." newline hexmask.long.byte 0x14 8.--15. 1. "AXI0_RDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 read data FIFO." hexmask.long.byte 0x14 0.--7. 1. "AXI0_CMDFIFO_LOG2_DEPTH,Reports the depth of the AXI port 0 command FIFO." group.long 0x1C++0x47 line.long 0x0 "DDRSS_CTL_7" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--23. 1. "TINIT_F0,DRAM TINIT value for frequency copy 0 in cycles." line.long 0x4 "DDRSS_CTL_8" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--23. 1. "TINIT3_F0,DRAM TINIT3 value for frequency copy 0 in cycles." line.long 0x8 "DDRSS_CTL_9" hexmask.long.byte 0x8 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--23. 1. "TINIT4_F0,DRAM TINIT4 value for frequency copy 0 in cycles." line.long 0xC "DDRSS_CTL_10" hexmask.long.byte 0xC 24.--31. 1. "RESERVED" hexmask.long.tbyte 0xC 0.--23. 1. "TINIT5_F0,DRAM TINIT5 value for frequency copy 0 in cycles." line.long 0x10 "DDRSS_CTL_11" hexmask.long.byte 0x10 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x10 0.--23. 1. "TINIT_F1,DRAM TINIT value for frequency copy 1 in cycles." line.long 0x14 "DDRSS_CTL_12" hexmask.long.byte 0x14 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x14 0.--23. 1. "TINIT3_F1,DRAM TINIT3 value for frequency copy 1 in cycles." line.long 0x18 "DDRSS_CTL_13" hexmask.long.byte 0x18 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--23. 1. "TINIT4_F1,DRAM TINIT4 value for frequency copy 1 in cycles." line.long 0x1C "DDRSS_CTL_14" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x1C 0.--23. 1. "TINIT5_F1,DRAM TINIT5 value for frequency copy 1 in cycles." line.long 0x20 "DDRSS_CTL_15" hexmask.long.byte 0x20 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x20 0.--23. 1. "TINIT_F2,DRAM TINIT value for frequency copy 2 in cycles." line.long 0x24 "DDRSS_CTL_16" hexmask.long.byte 0x24 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x24 0.--23. 1. "TINIT3_F2,DRAM TINIT3 value for frequency copy 2 in cycles." line.long 0x28 "DDRSS_CTL_17" hexmask.long.byte 0x28 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x28 0.--23. 1. "TINIT4_F2,DRAM TINIT4 value for frequency copy 2 in cycles." line.long 0x2C "DDRSS_CTL_18" hexmask.long.byte 0x2C 25.--31. 1. "RESERVED" bitfld.long 0x2C 24. "NO_AUTO_MRR_INIT,Disable MRR commands during initialization." "0,1" newline hexmask.long.tbyte 0x2C 0.--23. 1. "TINIT5_F2,DRAM TINIT5 value for frequency copy 2 in cycles." line.long 0x30 "DDRSS_CTL_19" hexmask.long.byte 0x30 25.--31. 1. "RESERVED" bitfld.long 0x30 24. "ODT_VALUE,When using LPDDR4 this value will be driven out on the dfi_odt signal." "0,1" newline hexmask.long.byte 0x30 17.--23. 1. "RESERVED" bitfld.long 0x30 16. "NO_MRW_INIT,Disable MRW commands during initialization." "0,1" newline hexmask.long.byte 0x30 9.--15. 1. "RESERVED" bitfld.long 0x30 8. "DFI_INV_DATA_CS,Forces the inversion of the dfi_rddata_cs_n_X and dfi_wrdata_cs_n_X signals." "0,1" newline hexmask.long.byte 0x30 1.--7. 1. "RESERVED" rbitfld.long 0x30 0. "MRR_ERROR_STATUS,Indicates that an MRR was issued while in self-refresh." "0,1" line.long 0x34 "DDRSS_CTL_20" hexmask.long.byte 0x34 26.--31. 1. "RESERVED" bitfld.long 0x34 24.--25. "DFIBUS_FREQ_INIT,Defines the initial DFI bus frequency." "0,1,2,3" newline hexmask.long.byte 0x34 17.--23. 1. "RESERVED" bitfld.long 0x34 16. "PHY_INDEP_INIT_MODE,Enable PHY independent initailization mode commands during initialization." "0,1" newline bitfld.long 0x34 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x34 8.--13. 1. "TSREF2PHYMSTR,Specifies the minimum time after a self-refresh exit command on the DFI bus that the Controller will wait for the PHY to assert the dfi_phymstr_req signal before completing other commands." newline hexmask.long.byte 0x34 1.--7. 1. "RESERVED" bitfld.long 0x34 0. "PHY_INDEP_TRAIN_MODE,Enable PHY independent training mode commands during initialization." "0,1" line.long 0x38 "DDRSS_CTL_21" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "DFIBUS_FREQ_F2,Defines the DFI bus frequency for frequency copy 2." newline bitfld.long 0x38 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 16.--20. 1. "DFIBUS_FREQ_F1,Defines the DFI bus frequency for frequency copy 1." newline bitfld.long 0x38 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 8.--12. 1. "DFIBUS_FREQ_F0,Defines the DFI bus frequency for frequency copy 0." newline hexmask.long.byte 0x38 2.--7. 1. "RESERVED" bitfld.long 0x38 0.--1. "DFIBUS_BOOT_FREQ,Defines the DFI bus boot frequency." "0,1,2,3" line.long 0x3C "DDRSS_CTL_22" hexmask.long.word 0x3C 18.--31. 1. "RESERVED" bitfld.long 0x3C 16.--17. "FREQ_CHANGE_TYPE_F2,Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation." "0,1,2,3" newline hexmask.long.byte 0x3C 10.--15. 1. "RESERVED" bitfld.long 0x3C 8.--9. "FREQ_CHANGE_TYPE_F1,Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation." "0,1,2,3" newline hexmask.long.byte 0x3C 2.--7. 1. "RESERVED" bitfld.long 0x3C 0.--1. "FREQ_CHANGE_TYPE_F0,Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation." "0,1,2,3" line.long 0x40 "DDRSS_CTL_23" hexmask.long 0x40 0.--31. 1. "TRST_PWRON,Duration of memory reset during power-on initialization." line.long 0x44 "DDRSS_CTL_24" hexmask.long 0x44 0.--31. 1. "CKE_INACTIVE,Number of cycles after reset before CKE will be active." group.long 0x68++0x13 line.long 0x0 "DDRSS_CTL_26" hexmask.long.word 0x0 17.--31. 1. "RESERVED" bitfld.long 0x0 16. "DQS_OSC_ENABLE,Enable DQS oscillator measurement function in DRAM." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "RESERVED,Reserved" line.long 0x4 "DDRSS_CTL_27" hexmask.long.byte 0x4 24.--31. 1. "TOSCO_F0,Number of cycles for tOSCO timing parameter for frequency copy 0." hexmask.long.byte 0x4 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x4 16.--19. 1. "FUNC_VALID_CYCLES,Number of cycles to hold dfi_function_valid asserted." bitfld.long 0x4 15. "RESERVED" "0,1" newline hexmask.long.word 0x4 0.--14. 1. "DQS_OSC_PERIOD,Number of cycles to run the oscillator measurement." line.long 0x8 "DDRSS_CTL_28" hexmask.long.byte 0x8 24.--31. 1. "DQS_OSC_HIGH_THRESHOLD,Number of long counts until the high priority request is asserted for DQS Oscillator." hexmask.long.byte 0x8 16.--23. 1. "DQS_OSC_NORM_THRESHOLD,Number of long counts until the normal priority request is asserted for DQS Oscillator." newline hexmask.long.byte 0x8 8.--15. 1. "TOSCO_F2,Number of cycles for tOSCO timing parameter for frequency copy 2." hexmask.long.byte 0x8 0.--7. 1. "TOSCO_F1,Number of cycles for tOSCO timing parameter for frequency copy 1." line.long 0xC "DDRSS_CTL_29" hexmask.long.word 0xC 16.--31. 1. "OSC_VARIANCE_LIMIT,Allowed difference between base value and DQS Oscillator measurement." hexmask.long.byte 0xC 8.--15. 1. "DQS_OSC_PROMOTE_THRESHOLD,Number of long counts until a software request for the DQS Oscillator is promoted to high priority." newline hexmask.long.byte 0xC 0.--7. 1. "DQS_OSC_TIMEOUT,Number of long counts until the timeout is asserted for DQS Oscillator." line.long 0x10 "DDRSS_CTL_30" hexmask.long.byte 0x10 24.--31. 1. "RESERVED" hexmask.long.word 0x10 8.--23. 1. "OSC_BASE_VALUE_0_CS0,Base value for device 0 on chip 0." newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "DQS_OSC_REQUEST,Software request for DQS Oscillator measurement function in DRAM." "0,1" rgroup.long 0x7C++0xB line.long 0x0 "DDRSS_CTL_31" hexmask.long.word 0x0 16.--31. 1. "OSC_BASE_VALUE_2_CS0,Base value for device 2 on chip 0." hexmask.long.word 0x0 0.--15. 1. "OSC_BASE_VALUE_1_CS0,Base value for device 1 on chip 0." line.long 0x4 "DDRSS_CTL_32" hexmask.long.word 0x4 16.--31. 1. "OSC_BASE_VALUE_0_CS1,Base value for device 0 on chip 1." hexmask.long.word 0x4 0.--15. 1. "OSC_BASE_VALUE_3_CS0,Base value for device 3 on chip 0." line.long 0x8 "DDRSS_CTL_33" hexmask.long.word 0x8 16.--31. 1. "OSC_BASE_VALUE_2_CS1,Base value for device 2 on chip 1." hexmask.long.word 0x8 0.--15. 1. "OSC_BASE_VALUE_1_CS1,Base value for device 1 on chip 1." group.long 0x88++0xEB line.long 0x0 "DDRSS_CTL_34" bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long.byte 0x0 24.--30. 1. "WRLAT_F0,DRAM WRLAT value for frequency copy 0 in cycles." newline bitfld.long 0x0 23. "RESERVED" "0,1" hexmask.long.byte 0x0 16.--22. 1. "CASLAT_LIN_F0,Sets latency from read command send to data receive from/to controller for frequency copy 0." newline hexmask.long.word 0x0 0.--15. 1. "OSC_BASE_VALUE_3_CS1,Base value for device 3 on chip 1." line.long 0x4 "DDRSS_CTL_35" bitfld.long 0x4 31. "RESERVED" "0,1" hexmask.long.byte 0x4 24.--30. 1. "WRLAT_F2,DRAM WRLAT value for frequency copy 2 in cycles." newline bitfld.long 0x4 23. "RESERVED" "0,1" hexmask.long.byte 0x4 16.--22. 1. "CASLAT_LIN_F2,Sets latency from read command send to data receive from/to controller for frequency copy 2." newline bitfld.long 0x4 15. "RESERVED" "0,1" hexmask.long.byte 0x4 8.--14. 1. "WRLAT_F1,DRAM WRLAT value for frequency copy 1 in cycles." newline bitfld.long 0x4 7. "RESERVED" "0,1" hexmask.long.byte 0x4 0.--6. 1. "CASLAT_LIN_F1,Sets latency from read command send to data receive from/to controller for frequency copy 1." line.long 0x8 "DDRSS_CTL_36" hexmask.long.byte 0x8 24.--31. 1. "RESERVED" hexmask.long.byte 0x8 16.--23. 1. "TRRD_F0,DRAM TRRD value for frequency copy 0 in cycles." newline bitfld.long 0x8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "TCCD,DRAM CAS-to-CAS value in cycles." newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" bitfld.long 0x8 0.--2. "TBST_INT_INTERVAL,DRAM burst interrupt interval value in cycles." "0,1,2,3,4,5,6,7" line.long 0xC "DDRSS_CTL_37" bitfld.long 0xC 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 24.--29. 1. "TWTR_F0,DRAM TWTR value for frequency copy 0 in cycles." newline hexmask.long.byte 0xC 16.--23. 1. "TRAS_MIN_F0,DRAM TRAS_MIN value for frequency copy 0 in cycles." hexmask.long.byte 0xC 9.--15. 1. "RESERVED" newline hexmask.long.word 0xC 0.--8. 1. "TRC_F0,DRAM TRC value for frequency copy 0 in cycles." line.long 0x10 "DDRSS_CTL_38" hexmask.long.byte 0x10 24.--31. 1. "TRRD_F1,DRAM TRRD value for frequency copy 1 in cycles." hexmask.long.byte 0x10 17.--23. 1. "RESERVED" newline hexmask.long.word 0x10 8.--16. 1. "TFAW_F0,DRAM TFAW value for frequency copy 0 in cycles." hexmask.long.byte 0x10 0.--7. 1. "TRP_F0,DRAM TRP value for frequency copy 0 in cycles." line.long 0x14 "DDRSS_CTL_39" bitfld.long 0x14 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 24.--29. 1. "TWTR_F1,DRAM TWTR value for frequency copy 1 in cycles." newline hexmask.long.byte 0x14 16.--23. 1. "TRAS_MIN_F1,DRAM TRAS_MIN value for frequency copy 1 in cycles." hexmask.long.byte 0x14 9.--15. 1. "RESERVED" newline hexmask.long.word 0x14 0.--8. 1. "TRC_F1,DRAM TRC value for frequency copy 1 in cycles." line.long 0x18 "DDRSS_CTL_40" hexmask.long.byte 0x18 24.--31. 1. "TRRD_F2,DRAM TRRD value for frequency copy 2 in cycles." hexmask.long.byte 0x18 17.--23. 1. "RESERVED" newline hexmask.long.word 0x18 8.--16. 1. "TFAW_F1,DRAM TFAW value for frequency copy 1 in cycles." hexmask.long.byte 0x18 0.--7. 1. "TRP_F1,DRAM TRP value for frequency copy 1 in cycles." line.long 0x1C "DDRSS_CTL_41" bitfld.long 0x1C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x1C 24.--29. 1. "TWTR_F2,DRAM TWTR value for frequency copy 2 in cycles." newline hexmask.long.byte 0x1C 16.--23. 1. "TRAS_MIN_F2,DRAM TRAS_MIN value for frequency copy 2 in cycles." hexmask.long.byte 0x1C 9.--15. 1. "RESERVED" newline hexmask.long.word 0x1C 0.--8. 1. "TRC_F2,DRAM TRC value for frequency copy 2 in cycles." line.long 0x20 "DDRSS_CTL_42" bitfld.long 0x20 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x20 24.--29. 1. "TCCDMW,DRAM CAS-to-CAS masked write value in cycles." newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" hexmask.long.word 0x20 8.--16. 1. "TFAW_F2,DRAM TFAW value for frequency copy 2 in cycles." newline hexmask.long.byte 0x20 0.--7. 1. "TRP_F2,DRAM TRP value for frequency copy 2 in cycles." line.long 0x24 "DDRSS_CTL_43" hexmask.long.byte 0x24 24.--31. 1. "RESERVED" hexmask.long.byte 0x24 16.--23. 1. "TMOD_F0,DRAM TMOD value for frequency copy 0 in cycles." newline hexmask.long.byte 0x24 8.--15. 1. "TMRD_F0,DRAM TMRD value for frequency copy 0 in cycles." hexmask.long.byte 0x24 0.--7. 1. "TRTP_F0,DRAM TRTP value for frequency copy 0 in cycles." line.long 0x28 "DDRSS_CTL_44" bitfld.long 0x28 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 24.--28. 1. "TCKE_F0,Minimum CKE pulse width for frequency copy 0." newline hexmask.long.byte 0x28 17.--23. 1. "RESERVED" hexmask.long.tbyte 0x28 0.--16. 1. "TRAS_MAX_F0,DRAM TRAS_MAX value for frequency copy 0 in cycles." line.long 0x2C "DDRSS_CTL_45" hexmask.long.byte 0x2C 24.--31. 1. "TMOD_F1,DRAM TMOD value for frequency copy 1 in cycles." hexmask.long.byte 0x2C 16.--23. 1. "TMRD_F1,DRAM TMRD value for frequency copy 1 in cycles." newline hexmask.long.byte 0x2C 8.--15. 1. "TRTP_F1,DRAM TRTP value for frequency copy 1 in cycles." hexmask.long.byte 0x2C 0.--7. 1. "TCKESR_F0,Minimum CKE low pulse width during a self-refresh for frequency copy 0." line.long 0x30 "DDRSS_CTL_46" bitfld.long 0x30 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30 24.--28. 1. "TCKE_F1,Minimum CKE pulse width for frequency copy 1." newline hexmask.long.byte 0x30 17.--23. 1. "RESERVED" hexmask.long.tbyte 0x30 0.--16. 1. "TRAS_MAX_F1,DRAM TRAS_MAX value for frequency copy 1 in cycles." line.long 0x34 "DDRSS_CTL_47" hexmask.long.byte 0x34 24.--31. 1. "TMOD_F2,DRAM TMOD value for frequency copy 2 in cycles." hexmask.long.byte 0x34 16.--23. 1. "TMRD_F2,DRAM TMRD value for frequency copy 2 in cycles." newline hexmask.long.byte 0x34 8.--15. 1. "TRTP_F2,DRAM TRTP value for frequency copy 2 in cycles." hexmask.long.byte 0x34 0.--7. 1. "TCKESR_F1,Minimum CKE low pulse width during a self-refresh for frequency copy 1." line.long 0x38 "DDRSS_CTL_48" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "TCKE_F2,Minimum CKE pulse width for frequency copy 2." newline hexmask.long.byte 0x38 17.--23. 1. "RESERVED" hexmask.long.tbyte 0x38 0.--16. 1. "TRAS_MAX_F2,DRAM TRAS_MAX value for frequency copy 2 in cycles." line.long 0x3C "DDRSS_CTL_49" hexmask.long.byte 0x3C 27.--31. 1. "RESERVED" bitfld.long 0x3C 24.--26. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x3C 19.--23. 1. "RESERVED" bitfld.long 0x3C 16.--18. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x3C 11.--15. 1. "RESERVED" bitfld.long 0x3C 8.--10. "TPPD,DRAM TPPD value in cycles." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x3C 0.--7. 1. "TCKESR_F2,Minimum CKE low pulse width during a self-refresh for frequency copy 2." line.long 0x40 "DDRSS_CTL_50" hexmask.long.byte 0x40 24.--31. 1. "TRCD_F1,DRAM TRCD value for frequency copy 1 in cycles." hexmask.long.byte 0x40 16.--23. 1. "TWR_F0,DRAM TWR value for frequency copy 0 in cycles." newline hexmask.long.byte 0x40 8.--15. 1. "TRCD_F0,DRAM TRCD value for frequency copy 0 in cycles." hexmask.long.byte 0x40 1.--7. 1. "RESERVED" newline bitfld.long 0x40 0. "WRITEINTERP,Allow controller to interrupt a write burst to the DRAMs with a read command." "0,1" line.long 0x44 "DDRSS_CTL_51" hexmask.long.byte 0x44 28.--31. 1. "RESERVED" hexmask.long.byte 0x44 24.--27. 1. "TMRR,DRAM TMRR value in cycles." newline hexmask.long.byte 0x44 16.--23. 1. "TWR_F2,DRAM TWR value for frequency copy 2 in cycles." hexmask.long.byte 0x44 8.--15. 1. "TRCD_F2,DRAM TRCD value for frequency copy 2 in cycles." newline hexmask.long.byte 0x44 0.--7. 1. "TWR_F1,DRAM TWR value for frequency copy 1 in cycles." line.long 0x48 "DDRSS_CTL_52" bitfld.long 0x48 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x48 24.--29. 1. "TCAMRD,DRAM TCAMRD value in cycles." newline hexmask.long.byte 0x48 18.--23. 1. "RESERVED" hexmask.long.word 0x48 8.--17. 1. "TCAENT,DRAM TCAENT value in cycles." newline bitfld.long 0x48 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x48 0.--4. 1. "TCACKEL,DRAM TCACKEL value in cycles." line.long 0x4C "DDRSS_CTL_53" bitfld.long 0x4C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C 24.--28. 1. "TMRZ_F1,DRAM TMRZ value for frequency copy 1 in cycles." newline bitfld.long 0x4C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C 16.--20. 1. "TMRZ_F0,DRAM TMRZ value for frequency copy 0 in cycles." newline bitfld.long 0x4C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C 8.--12. 1. "TCACKEH,DRAM TCACKEH value in cycles." newline bitfld.long 0x4C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C 0.--4. 1. "TCAEXT,DRAM TCAEXT value in cycles." line.long 0x50 "DDRSS_CTL_54" hexmask.long.byte 0x50 25.--31. 1. "RESERVED" bitfld.long 0x50 24. "TRAS_LOCKOUT,IF the DRAM supports it this allows the controller to execute auto pre-charge commands before the TRAS_MIN parameter expires." "0,1" newline hexmask.long.byte 0x50 17.--23. 1. "RESERVED" bitfld.long 0x50 16. "CONCURRENTAP,IF the DRAM supports it this allows the controller to issue commands to other banks while a bank is in auto pre-charge." "0,1" newline hexmask.long.byte 0x50 9.--15. 1. "RESERVED" bitfld.long 0x50 8. "AP,Enable auto pre-charge mode of controller." "0,1" newline bitfld.long 0x50 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x50 0.--4. 1. "TMRZ_F2,DRAM TMRZ value for frequency copy 2 in cycles." line.long 0x54 "DDRSS_CTL_55" bitfld.long 0x54 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x54 24.--28. 1. "BSTLEN,Encoded burst length sent to DRAMs during initialization." newline hexmask.long.byte 0x54 16.--23. 1. "TDAL_F2,DRAM TDAL value for frequency copy 2 in cycles." hexmask.long.byte 0x54 8.--15. 1. "TDAL_F1,DRAM TDAL value for frequency copy 1 in cycles." newline hexmask.long.byte 0x54 0.--7. 1. "TDAL_F0,DRAM TDAL value for frequency copy 0 in cycles." line.long 0x58 "DDRSS_CTL_56" hexmask.long.byte 0x58 24.--31. 1. "TRP_AB_F0_1,DRAM TRP all bank value for frequency copy 0 in cycles for chip select 1." hexmask.long.byte 0x58 16.--23. 1. "TRP_AB_F2_0,DRAM TRP all bank value for frequency copy 2 in cycles for chip select 0." newline hexmask.long.byte 0x58 8.--15. 1. "TRP_AB_F1_0,DRAM TRP all bank value for frequency copy 1 in cycles for chip select 0." hexmask.long.byte 0x58 0.--7. 1. "TRP_AB_F0_0,DRAM TRP all bank value for frequency copy 0 in cycles for chip select 0." line.long 0x5C "DDRSS_CTL_57" hexmask.long.byte 0x5C 26.--31. 1. "RESERVED" bitfld.long 0x5C 24.--25. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x5C 17.--23. 1. "RESERVED" bitfld.long 0x5C 16. "REG_DIMM_ENABLE,Enable registered DIMM operation of the controller." "0,1" newline hexmask.long.byte 0x5C 8.--15. 1. "TRP_AB_F2_1,DRAM TRP all bank value for frequency copy 2 in cycles for chip select 1." hexmask.long.byte 0x5C 0.--7. 1. "TRP_AB_F1_1,DRAM TRP all bank value for frequency copy 1 in cycles for chip select 1." line.long 0x60 "DDRSS_CTL_58" hexmask.long.byte 0x60 25.--31. 1. "RESERVED" bitfld.long 0x60 24. "NO_MEMORY_DM,Indicates that the external DRAM does not support DM masking." "0,1" newline hexmask.long.byte 0x60 17.--23. 1. "RESERVED" bitfld.long 0x60 16. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x60 9.--15. 1. "RESERVED" bitfld.long 0x60 8. "OPTIMAL_RMODW_EN,Enables optimized RMODW logic in the controller." "0,1" newline bitfld.long 0x60 7. "RESERVED" "0,1" hexmask.long.byte 0x60 0.--6. 1. "RESERVED,Reserved" line.long 0x64 "DDRSS_CTL_59" hexmask.long.byte 0x64 27.--31. 1. "RESERVED" bitfld.long 0x64 24.--26. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x64 17.--23. 1. "RESERVED" bitfld.long 0x64 16. "TREF_ENABLE,Issue auto-refresh commands to the DRAMs at the interval defined in the TREF parameter." "0,1" newline hexmask.long.byte 0x64 9.--15. 1. "RESERVED" rbitfld.long 0x64 8. "AREF_STATUS,Indicates a SR error associated with the AREF interrupt." "0,1" newline hexmask.long.byte 0x64 1.--7. 1. "RESERVED" bitfld.long 0x64 0. "AREFRESH,Initiate auto-refresh at the end of the current burst boundary." "0,1" line.long 0x68 "DDRSS_CTL_60" hexmask.long.word 0x68 18.--31. 1. "RESERVED" hexmask.long.word 0x68 8.--17. 1. "TRFC_F0,DRAM TRFC value for frequency copy 0 in cycles." newline bitfld.long 0x68 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x68 0.--5. 1. "CS_COMPARISON_FOR_REFRESH_DEPTH,Defines the number of entries of the command queue that the refresh logic will consider for sending a refresh command." line.long 0x6C "DDRSS_CTL_61" hexmask.long.word 0x6C 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x6C 0.--19. 1. "TREF_F0,DRAM TREF value for frequency copy 0 in cycles." line.long 0x70 "DDRSS_CTL_62" hexmask.long.tbyte 0x70 10.--31. 1. "RESERVED" hexmask.long.word 0x70 0.--9. 1. "TRFC_F1,DRAM TRFC value for frequency copy 1 in cycles." line.long 0x74 "DDRSS_CTL_63" hexmask.long.word 0x74 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x74 0.--19. 1. "TREF_F1,DRAM TREF value for frequency copy 1 in cycles." line.long 0x78 "DDRSS_CTL_64" hexmask.long.tbyte 0x78 10.--31. 1. "RESERVED" hexmask.long.word 0x78 0.--9. 1. "TRFC_F2,DRAM TRFC value for frequency copy 2 in cycles." line.long 0x7C "DDRSS_CTL_65" hexmask.long.word 0x7C 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x7C 0.--19. 1. "TREF_F2,DRAM TREF value for frequency copy 2 in cycles." line.long 0x80 "DDRSS_CTL_66" hexmask.long.word 0x80 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x80 0.--19. 1. "TREF_INTERVAL,Defines the cycles between refreshes to different chip selects." line.long 0x84 "DDRSS_CTL_67" hexmask.long.byte 0x84 26.--31. 1. "RESERVED" hexmask.long.word 0x84 16.--25. 1. "TRFC_PB_F0,DRAM TRFC_PB value for frequency copy 0 in cycles." newline hexmask.long.byte 0x84 9.--15. 1. "RESERVED" bitfld.long 0x84 8. "PBR_NUMERIC_ORDER,Enables the PBR to run REFpb commands in numeric bank order (0 1 2 3 etc.) When disabled the order may be modified if supported by the memory type." "0,1" newline hexmask.long.byte 0x84 1.--7. 1. "RESERVED" bitfld.long 0x84 0. "PBR_EN,Enables the per-bank refresh feature." "0,1" line.long 0x88 "DDRSS_CTL_68" hexmask.long.byte 0x88 26.--31. 1. "RESERVED" hexmask.long.word 0x88 16.--25. 1. "TRFC_PB_F1,DRAM TRFC_PB value for frequency copy 1 in cycles." newline hexmask.long.word 0x88 0.--15. 1. "TREFI_PB_F0,DRAM TREFI_PB value for frequency copy 0 in cycles." line.long 0x8C "DDRSS_CTL_69" hexmask.long.byte 0x8C 26.--31. 1. "RESERVED" hexmask.long.word 0x8C 16.--25. 1. "TRFC_PB_F2,DRAM TRFC_PB value for frequency copy 2 in cycles." newline hexmask.long.word 0x8C 0.--15. 1. "TREFI_PB_F1,DRAM TREFI_PB value for frequency copy 1 in cycles." line.long 0x90 "DDRSS_CTL_70" hexmask.long.word 0x90 16.--31. 1. "PBR_MAX_BANK_WAIT,Defines the maximum number of cycles that the PBR module will wait for Strategy to release the target bank until the PBR will assert the inhibit and close the target bank." hexmask.long.word 0x90 0.--15. 1. "TREFI_PB_F2,DRAM TREFI_PB value for frequency copy 2 in cycles." line.long 0x94 "DDRSS_CTL_71" bitfld.long 0x94 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x94 24.--28. 1. "AREF_PBR_CONT_DIS_THRESHOLD,Sets the auto-refresh request count threshold when the PBR continuous refresh request enable will be deasserted." newline bitfld.long 0x94 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x94 16.--20. 1. "AREF_PBR_CONT_EN_THRESHOLD,Sets the auto-refresh request count threshold when the PBR continuous refresh request enable will be asserted." newline hexmask.long.byte 0x94 9.--15. 1. "RESERVED" bitfld.long 0x94 8. "PBR_CONT_REQ_EN,Enables the per-bank refresh continuous request feature." "0,1" newline hexmask.long.byte 0x94 4.--7. 1. "RESERVED" hexmask.long.byte 0x94 0.--3. 1. "PBR_BANK_SELECT_DELAY,Defines the PBR bank select to command delay the time from bank selection to when the command queue bank selection logic is guaranteed to have blocked the bank." line.long 0x98 "DDRSS_CTL_72" hexmask.long.word 0x98 16.--31. 1. "TPDEX_F1,DRAM TPDEX value for frequency copy 1 in cycles." hexmask.long.word 0x98 0.--15. 1. "TPDEX_F0,DRAM TPDEX value for frequency copy 0 in cycles." line.long 0x9C "DDRSS_CTL_73" hexmask.long.byte 0x9C 24.--31. 1. "TMRRI_F1,DRAM TMRRI value for frequency copy 1 in cycles." hexmask.long.byte 0x9C 16.--23. 1. "TMRRI_F0,DRAM TMRRI value for frequency copy 0 in cycles." newline hexmask.long.word 0x9C 0.--15. 1. "TPDEX_F2,DRAM TPDEX value for frequency copy 2 in cycles." line.long 0xA0 "DDRSS_CTL_74" bitfld.long 0xA0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA0 24.--28. 1. "TCKEHCS_F0,DRAM TCKEHCS value for frequency copy 0 in cycles." newline bitfld.long 0xA0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA0 16.--20. 1. "TCKELCS_F0,DRAM TCKELCS value for frequency copy 0 in cycles." newline bitfld.long 0xA0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA0 8.--12. 1. "TCSCKE_F0,DRAM TCSCKE value for frequency copy 0 in cycles." newline hexmask.long.byte 0xA0 0.--7. 1. "TMRRI_F2,DRAM TMRRI value for frequency copy 2 in cycles." line.long 0xA4 "DDRSS_CTL_75" bitfld.long 0xA4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA4 24.--28. 1. "TCSCKE_F1,DRAM TCSCKE value for frequency copy 1 in cycles." newline hexmask.long.byte 0xA4 17.--23. 1. "RESERVED" bitfld.long 0xA4 16. "CA_DEFAULT_VAL_F0,Defines how unused address/command bits are driven for frequency copy 0." "0,1" newline hexmask.long.byte 0xA4 12.--15. 1. "RESERVED" hexmask.long.byte 0xA4 8.--11. 1. "TZQCKE_F0,DRAM TZQCKE value for frequency copy 0 in cycles." newline bitfld.long 0xA4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA4 0.--4. 1. "TMRWCKEL_F0,DRAM TMRWCKEL value for frequency copy 0 in cycles." line.long 0xA8 "DDRSS_CTL_76" hexmask.long.byte 0xA8 28.--31. 1. "RESERVED" hexmask.long.byte 0xA8 24.--27. 1. "TZQCKE_F1,DRAM TZQCKE value for frequency copy 1 in cycles." newline bitfld.long 0xA8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA8 16.--20. 1. "TMRWCKEL_F1,DRAM TMRWCKEL value for frequency copy 1 in cycles." newline bitfld.long 0xA8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA8 8.--12. 1. "TCKEHCS_F1,DRAM TCKEHCS value for frequency copy 1 in cycles." newline bitfld.long 0xA8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA8 0.--4. 1. "TCKELCS_F1,DRAM TCKELCS value for frequency copy 1 in cycles." line.long 0xAC "DDRSS_CTL_77" bitfld.long 0xAC 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xAC 24.--28. 1. "TCKEHCS_F2,DRAM TCKEHCS value for frequency copy 2 in cycles." newline bitfld.long 0xAC 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xAC 16.--20. 1. "TCKELCS_F2,DRAM TCKELCS value for frequency copy 2 in cycles." newline bitfld.long 0xAC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xAC 8.--12. 1. "TCSCKE_F2,DRAM TCSCKE value for frequency copy 2 in cycles." newline hexmask.long.byte 0xAC 1.--7. 1. "RESERVED" bitfld.long 0xAC 0. "CA_DEFAULT_VAL_F1,Defines how unused address/command bits are driven for frequency copy 1." "0,1" line.long 0xB0 "DDRSS_CTL_78" hexmask.long.word 0xB0 17.--31. 1. "RESERVED" bitfld.long 0xB0 16. "CA_DEFAULT_VAL_F2,Defines how unused address/command bits are driven for frequency copy 2." "0,1" newline hexmask.long.byte 0xB0 12.--15. 1. "RESERVED" hexmask.long.byte 0xB0 8.--11. 1. "TZQCKE_F2,DRAM TZQCKE value for frequency copy 2 in cycles." newline bitfld.long 0xB0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB0 0.--4. 1. "TMRWCKEL_F2,DRAM TMRWCKEL value for frequency copy 2 in cycles." line.long 0xB4 "DDRSS_CTL_79" hexmask.long.word 0xB4 16.--31. 1. "TXSNR_F0,DRAM TXSNR value for frequency copy 0 in cycles." hexmask.long.word 0xB4 0.--15. 1. "TXSR_F0,DRAM TXSR value for frequency copy 0 in cycles." line.long 0xB8 "DDRSS_CTL_80" hexmask.long.word 0xB8 16.--31. 1. "TXSNR_F1,DRAM TXSNR value for frequency copy 1 in cycles." hexmask.long.word 0xB8 0.--15. 1. "TXSR_F1,DRAM TXSR value for frequency copy 1 in cycles." line.long 0xBC "DDRSS_CTL_81" hexmask.long.word 0xBC 16.--31. 1. "TXSNR_F2,DRAM TXSNR value for frequency copy 2 in cycles." hexmask.long.word 0xBC 0.--15. 1. "TXSR_F2,DRAM TXSR value for frequency copy 2 in cycles." line.long 0xC0 "DDRSS_CTL_82" hexmask.long.byte 0xC0 24.--31. 1. "TSR_F0,DRAM TSR value for frequency copy 0 in cycles." bitfld.long 0xC0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC0 16.--20. 1. "TCKCKEL_F0,DRAM TCKCKEL value for frequency copy 0 in cycles." bitfld.long 0xC0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC0 8.--12. 1. "TCKEHCMD_F0,DRAM TCKEHCMD value for frequency copy 0 in cycles." bitfld.long 0xC0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC0 0.--4. 1. "TCKELCMD_F0,DRAM TCKELCMD value for frequency copy 0 in cycles." line.long 0xC4 "DDRSS_CTL_83" bitfld.long 0xC4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC4 24.--28. 1. "TCMDCKE_F0,DRAM TCMDCKE value for frequency copy 0 in cycles." newline bitfld.long 0xC4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC4 16.--20. 1. "TCSCKEH_F0,DRAM TCSCKEH value for frequency copy 0 in cycles." newline bitfld.long 0xC4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC4 8.--12. 1. "TCKELPD_F0,DRAM TCKELPD value for frequency copy 0 in cycles." newline hexmask.long.byte 0xC4 3.--7. 1. "RESERVED" bitfld.long 0xC4 0.--2. "TESCKE_F0,DRAM TESCKE value for frequency copy 0 in cycles." "0,1,2,3,4,5,6,7" line.long 0xC8 "DDRSS_CTL_84" hexmask.long.byte 0xC8 24.--31. 1. "TSR_F1,DRAM TSR value for frequency copy 1 in cycles." bitfld.long 0xC8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 16.--20. 1. "TCKCKEL_F1,DRAM TCKCKEL value for frequency copy 1 in cycles." bitfld.long 0xC8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 8.--12. 1. "TCKEHCMD_F1,DRAM TCKEHCMD value for frequency copy 1 in cycles." bitfld.long 0xC8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 0.--4. 1. "TCKELCMD_F1,DRAM TCKELCMD value for frequency copy 1 in cycles." line.long 0xCC "DDRSS_CTL_85" bitfld.long 0xCC 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xCC 24.--28. 1. "TCMDCKE_F1,DRAM TCMDCKE value for frequency copy 1 in cycles." newline bitfld.long 0xCC 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xCC 16.--20. 1. "TCSCKEH_F1,DRAM TCSCKEH value for frequency copy 1 in cycles." newline bitfld.long 0xCC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xCC 8.--12. 1. "TCKELPD_F1,DRAM TCKELPD value for frequency copy 1 in cycles." newline hexmask.long.byte 0xCC 3.--7. 1. "RESERVED" bitfld.long 0xCC 0.--2. "TESCKE_F1,DRAM TESCKE value for frequency copy 1 in cycles." "0,1,2,3,4,5,6,7" line.long 0xD0 "DDRSS_CTL_86" hexmask.long.byte 0xD0 24.--31. 1. "TSR_F2,DRAM TSR value for frequency copy 2 in cycles." bitfld.long 0xD0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD0 16.--20. 1. "TCKCKEL_F2,DRAM TCKCKEL value for frequency copy 2 in cycles." bitfld.long 0xD0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD0 8.--12. 1. "TCKEHCMD_F2,DRAM TCKEHCMD value for frequency copy 2 in cycles." bitfld.long 0xD0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD0 0.--4. 1. "TCKELCMD_F2,DRAM TCKELCMD value for frequency copy 2 in cycles." line.long 0xD4 "DDRSS_CTL_87" bitfld.long 0xD4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD4 24.--28. 1. "TCMDCKE_F2,DRAM TCMDCKE value for frequency copy 2 in cycles." newline bitfld.long 0xD4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD4 16.--20. 1. "TCSCKEH_F2,DRAM TCSCKEH value for frequency copy 2 in cycles." newline bitfld.long 0xD4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD4 8.--12. 1. "TCKELPD_F2,DRAM TCKELPD value for frequency copy 2 in cycles." newline hexmask.long.byte 0xD4 3.--7. 1. "RESERVED" bitfld.long 0xD4 0.--2. "TESCKE_F2,DRAM TESCKE value for frequency copy 2 in cycles." "0,1,2,3,4,5,6,7" line.long 0xD8 "DDRSS_CTL_88" hexmask.long.byte 0xD8 27.--31. 1. "RESERVED" bitfld.long 0xD8 24.--26. "CKE_DELAY,Additional cycles to delay CKE for status reporting." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD8 17.--23. 1. "RESERVED" bitfld.long 0xD8 16. "ENABLE_QUICK_SREFRESH,Allow user to interrupt memory initialization to enter self-refresh mode." "0,1" newline hexmask.long.byte 0xD8 9.--15. 1. "RESERVED" bitfld.long 0xD8 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xD8 1.--7. 1. "RESERVED" bitfld.long 0xD8 0. "PWRUP_SREFRESH_EXIT,Allow powerup via self-refresh instead of full memory initialization." "0,1" line.long 0xDC "DDRSS_CTL_89" hexmask.long.byte 0xDC 25.--31. 1. "RESERVED" bitfld.long 0xDC 24. "DFS_CALVL_EN,Enables CA training during a DFS exit." "0,1" newline hexmask.long.byte 0xDC 17.--23. 1. "RESERVED" bitfld.long 0xDC 16. "DFS_ZQ_EN,Enables ZQ calibration during a DFS exit." "0,1" newline hexmask.long.byte 0xDC 10.--15. 1. "RESERVED" rbitfld.long 0xDC 8.--9. "DFS_STATUS,Holds the error associated with the DFS interrupt." "0,1,2,3" newline bitfld.long 0xDC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xDC 0.--4. 1. "RESERVED,Reserved" line.long 0xE0 "DDRSS_CTL_90" hexmask.long.word 0xE0 17.--31. 1. "RESERVED" bitfld.long 0xE0 16. "DFS_RDLVL_GATE_EN,Enables read gate training during a DFS exit." "0,1" newline hexmask.long.byte 0xE0 9.--15. 1. "RESERVED" bitfld.long 0xE0 8. "DFS_RDLVL_EN,Enables read data eye training during a DFS exit." "0,1" newline hexmask.long.byte 0xE0 1.--7. 1. "RESERVED" bitfld.long 0xE0 0. "DFS_WRLVL_EN,Enables write leveling during a DFS exit." "0,1" line.long 0xE4 "DDRSS_CTL_91" hexmask.long.word 0xE4 16.--31. 1. "DFS_PROMOTE_THRESHOLD_F1,DFS promotion number of long counts until the high priority request is asserted for frequency copy 1." hexmask.long.word 0xE4 0.--15. 1. "DFS_PROMOTE_THRESHOLD_F0,DFS promotion number of long counts until the high priority request is asserted for frequency copy 0." line.long 0xE8 "DDRSS_CTL_92" hexmask.long.byte 0xE8 27.--31. 1. "RESERVED" bitfld.long 0xE8 24.--26. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE8 19.--23. 1. "RESERVED" rbitfld.long 0xE8 16.--18. "ZQ_STATUS_LOG,Indicates what kind of ZQ command was terminated without execution that caused the ZQ status interrupt to assert." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xE8 0.--15. 1. "DFS_PROMOTE_THRESHOLD_F2,DFS promotion number of long counts until the high priority request is asserted for frequency copy 2." group.long 0x178++0x10B line.long 0x0 "DDRSS_CTL_94" hexmask.long.word 0x0 16.--31. 1. "UPD_CTRLUPD_HIGH_THRESHOLD_F0,DFI control update number of long counts until the high priority request is asserted for frequency copy 0." hexmask.long.word 0x0 0.--15. 1. "UPD_CTRLUPD_NORM_THRESHOLD_F0,DFI control update number of long counts until the normal priority request is asserted for frequency copy 0." line.long 0x4 "DDRSS_CTL_95" hexmask.long.word 0x4 16.--31. 1. "UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0,DFI control update SW promotion number of long counts until the high priority request is asserted for frequency copy 0." hexmask.long.word 0x4 0.--15. 1. "UPD_CTRLUPD_TIMEOUT_F0,DFI control update number of long counts until the timeout is asserted for frequency copy 0." line.long 0x8 "DDRSS_CTL_96" hexmask.long.word 0x8 16.--31. 1. "UPD_CTRLUPD_NORM_THRESHOLD_F1,DFI control update number of long counts until the normal priority request is asserted for frequency copy 1." hexmask.long.word 0x8 0.--15. 1. "UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0,DFI PHY update DFI promotion number of long counts until the high priority request is asserted for frequency copy 0." line.long 0xC "DDRSS_CTL_97" hexmask.long.word 0xC 16.--31. 1. "UPD_CTRLUPD_TIMEOUT_F1,DFI control update number of long counts until the timeout is asserted for frequency copy 1." hexmask.long.word 0xC 0.--15. 1. "UPD_CTRLUPD_HIGH_THRESHOLD_F1,DFI control update number of long counts until the high priority request is asserted for frequency copy 1." line.long 0x10 "DDRSS_CTL_98" hexmask.long.word 0x10 16.--31. 1. "UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1,DFI PHY update DFI promotion number of long counts until the high priority request is asserted for frequency copy 1." hexmask.long.word 0x10 0.--15. 1. "UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1,DFI control update SW promotion number of long counts until the high priority request is asserted for frequency copy 1." line.long 0x14 "DDRSS_CTL_99" hexmask.long.word 0x14 16.--31. 1. "UPD_CTRLUPD_HIGH_THRESHOLD_F2,DFI control update number of long counts until the high priority request is asserted for frequency copy 2." hexmask.long.word 0x14 0.--15. 1. "UPD_CTRLUPD_NORM_THRESHOLD_F2,DFI control update number of long counts until the normal priority request is asserted for frequency copy 2." line.long 0x18 "DDRSS_CTL_100" hexmask.long.word 0x18 16.--31. 1. "UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2,DFI control update SW promotion number of long counts until the high priority request is asserted for frequency copy 2." hexmask.long.word 0x18 0.--15. 1. "UPD_CTRLUPD_TIMEOUT_F2,DFI control update number of long counts until the timeout is asserted for frequency copy 2." line.long 0x1C "DDRSS_CTL_101" hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 0.--15. 1. "UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2,DFI PHY update DFI promotion number of long counts until the high priority request is asserted for frequency copy 2." line.long 0x20 "DDRSS_CTL_102" hexmask.long 0x20 0.--31. 1. "TDFI_PHYMSTR_MAX_F0,Defines the DFI tPHYMSTR_MAX timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for frequency copy 0." line.long 0x24 "DDRSS_CTL_103" hexmask.long 0x24 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE0_F0,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0 for frequency copy 0." line.long 0x28 "DDRSS_CTL_104" hexmask.long 0x28 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE1_F0,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1 for frequency copy 0." line.long 0x2C "DDRSS_CTL_105" hexmask.long 0x2C 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE2_F0,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2 for frequency copy 0." line.long 0x30 "DDRSS_CTL_106" hexmask.long 0x30 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE3_F0,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3 for frequency copy 0." line.long 0x34 "DDRSS_CTL_107" hexmask.long.word 0x34 16.--31. 1. "RESERVED" hexmask.long.word 0x34 0.--15. 1. "PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0,Defines the DFI(4.0 and 4.0v2) PHY master request promotion number of regular (not long) counts until the high priority request is asserted for frequency copy 0." line.long 0x38 "DDRSS_CTL_108" hexmask.long.word 0x38 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x38 0.--19. 1. "TDFI_PHYMSTR_RESP_F0,Defines the DFI tPHYMSTR_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion for frequency copy 0." line.long 0x3C "DDRSS_CTL_109" hexmask.long 0x3C 0.--31. 1. "TDFI_PHYMSTR_MAX_F1,Defines the DFI tPHYMSTR_MAX timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for frequency copy 1." line.long 0x40 "DDRSS_CTL_110" hexmask.long 0x40 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE0_F1,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0 for frequency copy 1." line.long 0x44 "DDRSS_CTL_111" hexmask.long 0x44 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE1_F1,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1 for frequency copy 1." line.long 0x48 "DDRSS_CTL_112" hexmask.long 0x48 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE2_F1,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2 for frequency copy 1." line.long 0x4C "DDRSS_CTL_113" hexmask.long 0x4C 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE3_F1,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3 for frequency copy 1." line.long 0x50 "DDRSS_CTL_114" hexmask.long.word 0x50 16.--31. 1. "RESERVED" hexmask.long.word 0x50 0.--15. 1. "PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1,Defines the DFI(4.0 and 4.0v2) PHY master request promotion number of regular (not long) counts until the high priority request is asserted for frequency copy 1." line.long 0x54 "DDRSS_CTL_115" hexmask.long.word 0x54 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x54 0.--19. 1. "TDFI_PHYMSTR_RESP_F1,Defines the DFI tPHYMSTR_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion for frequency copy 1." line.long 0x58 "DDRSS_CTL_116" hexmask.long 0x58 0.--31. 1. "TDFI_PHYMSTR_MAX_F2,Defines the DFI tPHYMSTR_MAX timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for frequency copy 2." line.long 0x5C "DDRSS_CTL_117" hexmask.long 0x5C 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE0_F2,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0 for frequency copy 2." line.long 0x60 "DDRSS_CTL_118" hexmask.long 0x60 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE1_F2,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1 for frequency copy 2." line.long 0x64 "DDRSS_CTL_119" hexmask.long 0x64 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE2_F2,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2 for frequency copy 2." line.long 0x68 "DDRSS_CTL_120" hexmask.long 0x68 0.--31. 1. "TDFI_PHYMSTR_MAX_TYPE3_F2,Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter (in DFI clocks) the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3 for frequency copy 2." line.long 0x6C "DDRSS_CTL_121" hexmask.long.word 0x6C 16.--31. 1. "RESERVED" hexmask.long.word 0x6C 0.--15. 1. "PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2,Defines the DFI(4.0 and 4.0v2) PHY master request promotion number of regular (not long) counts until the high priority request is asserted for frequency copy 2." line.long 0x70 "DDRSS_CTL_122" hexmask.long.byte 0x70 25.--31. 1. "RESERVED" bitfld.long 0x70 24. "PHYMSTR_NO_AREF,Disables refreshes during the PHY master interface sequence." "0,1" newline hexmask.long.byte 0x70 20.--23. 1. "RESERVED" hexmask.long.tbyte 0x70 0.--19. 1. "TDFI_PHYMSTR_RESP_F2,Defines the DFI tPHYMSTR_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion for frequency copy 2." line.long 0x74 "DDRSS_CTL_123" hexmask.long.word 0x74 17.--31. 1. "RESERVED" bitfld.long 0x74 16. "PHYMSTR_TRAIN_AFTER_INIT_COMPLETE,Defines how the PHY will use the PHY Master Interface for training." "0,1" newline hexmask.long.byte 0x74 9.--15. 1. "RESERVED" bitfld.long 0x74 8. "PHYMSTR_DFI_VERSION_4P0V1,Defines the version of the DFI 4.0 specification supported." "0,1" newline hexmask.long.byte 0x74 2.--7. 1. "RESERVED" rbitfld.long 0x74 0.--1. "PHYMSTR_ERROR_STATUS,Identifies the source of any DFI PHY Master Interface errors." "0,1,2,3" line.long 0x78 "DDRSS_CTL_124" hexmask.long.word 0x78 16.--31. 1. "MRR_TEMPCHK_HIGH_THRESHOLD_F0,MRR temp check number of long counts until the high priority request is asserted for frequency copy 0." hexmask.long.word 0x78 0.--15. 1. "MRR_TEMPCHK_NORM_THRESHOLD_F0,MRR temp check number of long counts until the normal priority request is asserted for frequency copy 0." line.long 0x7C "DDRSS_CTL_125" hexmask.long.word 0x7C 16.--31. 1. "MRR_TEMPCHK_NORM_THRESHOLD_F1,MRR temp check number of long counts until the normal priority request is asserted for frequency copy 1." hexmask.long.word 0x7C 0.--15. 1. "MRR_TEMPCHK_TIMEOUT_F0,MRR temp check number of long counts until the timeout is asserted for frequency copy 0." line.long 0x80 "DDRSS_CTL_126" hexmask.long.word 0x80 16.--31. 1. "MRR_TEMPCHK_TIMEOUT_F1,MRR temp check number of long counts until the timeout is asserted for frequency copy 1." hexmask.long.word 0x80 0.--15. 1. "MRR_TEMPCHK_HIGH_THRESHOLD_F1,MRR temp check number of long counts until the high priority request is asserted for frequency copy 1." line.long 0x84 "DDRSS_CTL_127" hexmask.long.word 0x84 16.--31. 1. "MRR_TEMPCHK_HIGH_THRESHOLD_F2,MRR temp check number of long counts until the high priority request is asserted for frequency copy 2." hexmask.long.word 0x84 0.--15. 1. "MRR_TEMPCHK_NORM_THRESHOLD_F2,MRR temp check number of long counts until the normal priority request is asserted for frequency copy 2." line.long 0x88 "DDRSS_CTL_128" hexmask.long.byte 0x88 27.--31. 1. "RESERVED" bitfld.long 0x88 24.--26. "PPR_COMMAND,Specifies the type of PPR command." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x88 17.--23. 1. "RESERVED" bitfld.long 0x88 16. "PPR_CONTROL,Enables the post-package repair feature." "0,1" newline hexmask.long.word 0x88 0.--15. 1. "MRR_TEMPCHK_TIMEOUT_F2,MRR temp check number of long counts until the timeout is asserted for frequency copy 2." line.long 0x8C "DDRSS_CTL_129" hexmask.long.byte 0x8C 25.--31. 1. "RESERVED" hexmask.long.tbyte 0x8C 8.--24. 1. "PPR_ROW_ADDRESS,Specifies the encoded row address to be repaired." newline hexmask.long.byte 0x8C 0.--7. 1. "PPR_COMMAND_MRW,Specifies the mode register to be used." line.long 0x90 "DDRSS_CTL_130" hexmask.long.byte 0x90 25.--31. 1. "RESERVED" bitfld.long 0x90 24. "FM_OVRIDE_CONTROL,Enables the FM Override feature." "0,1" newline hexmask.long.byte 0x90 18.--23. 1. "RESERVED" rbitfld.long 0x90 16.--17. "PPR_STATUS,Reports the status of the PPR operation." "0,1,2,3" newline hexmask.long.byte 0x90 9.--15. 1. "RESERVED" bitfld.long 0x90 8. "PPR_CS_ADDRESS,Specifies the chip select for the row to be repaired." "0,1" newline hexmask.long.byte 0x90 3.--7. 1. "RESERVED" bitfld.long 0x90 0.--2. "PPR_BANK_ADDRESS,Specifies the bank for the row to be repaired." "0,1,2,3,4,5,6,7" line.long 0x94 "DDRSS_CTL_131" hexmask.long.byte 0x94 24.--31. 1. "CKSRE_F1,Clock hold delay on self-refresh entry for frequency copy 1." hexmask.long.byte 0x94 16.--23. 1. "CKSRX_F0,Clock stable delay on self-refresh exit for frequency copy 0." newline hexmask.long.byte 0x94 8.--15. 1. "CKSRE_F0,Clock hold delay on self-refresh entry for frequency copy 0." hexmask.long.byte 0x94 2.--7. 1. "RESERVED" newline bitfld.long 0x94 0.--1. "LOWPOWER_REFRESH_ENABLE,Enable refreshes while in low power mode." "0,1,2,3" line.long 0x98 "DDRSS_CTL_132" bitfld.long 0x98 31. "RESERVED" "0,1" hexmask.long.byte 0x98 24.--30. 1. "LP_CMD,Low power software command request interface." newline hexmask.long.byte 0x98 16.--23. 1. "CKSRX_F2,Clock stable delay on self-refresh exit for frequency copy 2." hexmask.long.byte 0x98 8.--15. 1. "CKSRE_F2,Clock hold delay on self-refresh entry for frequency copy 2." newline hexmask.long.byte 0x98 0.--7. 1. "CKSRX_F1,Clock stable delay on self-refresh exit for frequency copy 1." line.long 0x9C "DDRSS_CTL_133" hexmask.long.byte 0x9C 28.--31. 1. "RESERVED" hexmask.long.byte 0x9C 24.--27. 1. "LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long with memory and controller clock gating state for frequency copy 0." newline hexmask.long.byte 0x9C 20.--23. 1. "RESERVED" hexmask.long.byte 0x9C 16.--19. 1. "LPI_SR_LONG_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long state (with or without memory clock gating) for frequency copy 0." newline hexmask.long.byte 0x9C 12.--15. 1. "RESERVED" hexmask.long.byte 0x9C 8.--11. 1. "LPI_SR_SHORT_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when LPDDR4 memory is in the self-refresh short state (with or without memory clock gating) for frequency copy 0." newline hexmask.long.byte 0x9C 4.--7. 1. "RESERVED" hexmask.long.byte 0x9C 0.--3. 1. "LPI_CTRL_IDLE_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when controller is idle for frequency copy 0." line.long 0xA0 "DDRSS_CTL_134" hexmask.long.byte 0xA0 28.--31. 1. "RESERVED" hexmask.long.byte 0xA0 24.--27. 1. "LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state for frequency copy 0." newline hexmask.long.byte 0xA0 20.--23. 1. "RESERVED" hexmask.long.byte 0xA0 16.--19. 1. "LPI_SRPD_LONG_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long state (with or without memory clock gating) for frequency copy 0." newline hexmask.long.byte 0xA0 12.--15. 1. "RESERVED" hexmask.long.byte 0xA0 8.--11. 1. "LPI_SRPD_SHORT_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down short state (with or without memory clock gating) for frequency copy 0." newline hexmask.long.byte 0xA0 4.--7. 1. "RESERVED" hexmask.long.byte 0xA0 0.--3. 1. "LPI_PD_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in any of the power-down states (with or without memory clock gating) for frequency copy 0." line.long 0xA4 "DDRSS_CTL_135" hexmask.long.byte 0xA4 28.--31. 1. "RESERVED" hexmask.long.byte 0xA4 24.--27. 1. "LPI_SR_LONG_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long state (with or without memory clock gating) for frequency copy 1." newline hexmask.long.byte 0xA4 20.--23. 1. "RESERVED" hexmask.long.byte 0xA4 16.--19. 1. "LPI_SR_SHORT_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when LPDDR4 memory is in the self-refresh short state (with or without memory clock gating) for frequency copy 1." newline hexmask.long.byte 0xA4 12.--15. 1. "RESERVED" hexmask.long.byte 0xA4 8.--11. 1. "LPI_CTRL_IDLE_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when controller is idle for frequency copy 1." newline hexmask.long.byte 0xA4 4.--7. 1. "RESERVED" hexmask.long.byte 0xA4 0.--3. 1. "LPI_TIMER_WAKEUP_F0,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when the LPI timer expires for frequency copy 0." line.long 0xA8 "DDRSS_CTL_136" hexmask.long.byte 0xA8 28.--31. 1. "RESERVED" hexmask.long.byte 0xA8 24.--27. 1. "LPI_SRPD_LONG_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long state (with or without memory clock gating) for frequency copy 1." newline hexmask.long.byte 0xA8 20.--23. 1. "RESERVED" hexmask.long.byte 0xA8 16.--19. 1. "LPI_SRPD_SHORT_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down short state (with or without memory clock gating) for frequency copy 1." newline hexmask.long.byte 0xA8 12.--15. 1. "RESERVED" hexmask.long.byte 0xA8 8.--11. 1. "LPI_PD_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in any of the power-down states (with or without memory clock gating) for frequency copy 1." newline hexmask.long.byte 0xA8 4.--7. 1. "RESERVED" hexmask.long.byte 0xA8 0.--3. 1. "LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long with memory and controller clock gating state for frequency copy 1." line.long 0xAC "DDRSS_CTL_137" hexmask.long.byte 0xAC 28.--31. 1. "RESERVED" hexmask.long.byte 0xAC 24.--27. 1. "LPI_SR_SHORT_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when LPDDR4 memory is in the self-refresh short state (with or without memory clock gating) for frequency copy 2." newline hexmask.long.byte 0xAC 20.--23. 1. "RESERVED" hexmask.long.byte 0xAC 16.--19. 1. "LPI_CTRL_IDLE_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when controller is idle for frequency copy 2." newline hexmask.long.byte 0xAC 12.--15. 1. "RESERVED" hexmask.long.byte 0xAC 8.--11. 1. "LPI_TIMER_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when the LPI timer expires for frequency copy 1." newline hexmask.long.byte 0xAC 4.--7. 1. "RESERVED" hexmask.long.byte 0xAC 0.--3. 1. "LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state for frequency copy 1." line.long 0xB0 "DDRSS_CTL_138" hexmask.long.byte 0xB0 28.--31. 1. "RESERVED" hexmask.long.byte 0xB0 24.--27. 1. "LPI_SRPD_SHORT_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down short state (with or without memory clock gating) for frequency copy 2." newline hexmask.long.byte 0xB0 20.--23. 1. "RESERVED" hexmask.long.byte 0xB0 16.--19. 1. "LPI_PD_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in any of the power-down states (with or without memory clock gating) for frequency copy 2." newline hexmask.long.byte 0xB0 12.--15. 1. "RESERVED" hexmask.long.byte 0xB0 8.--11. 1. "LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long with memory and controller clock gating state for frequency copy 2." newline hexmask.long.byte 0xB0 4.--7. 1. "RESERVED" hexmask.long.byte 0xB0 0.--3. 1. "LPI_SR_LONG_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long state (with or without memory clock gating) for frequency copy 2." line.long 0xB4 "DDRSS_CTL_139" bitfld.long 0xB4 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xB4 24.--29. 1. "LPI_WAKEUP_EN,Enables the various low power state wakeup parameters for LPI request uses." newline hexmask.long.byte 0xB4 20.--23. 1. "RESERVED" hexmask.long.byte 0xB4 16.--19. 1. "LPI_TIMER_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when the LPI timer expires for frequency copy 2." newline hexmask.long.byte 0xB4 12.--15. 1. "RESERVED" hexmask.long.byte 0xB4 8.--11. 1. "LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state for frequency copy 2." newline hexmask.long.byte 0xB4 4.--7. 1. "RESERVED" hexmask.long.byte 0xB4 0.--3. 1. "LPI_SRPD_LONG_WAKEUP_F2,Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long state (with or without memory clock gating) for frequency copy 2." line.long 0xB8 "DDRSS_CTL_140" hexmask.long.byte 0xB8 27.--31. 1. "RESERVED" bitfld.long 0xB8 24.--26. "TDFI_LP_RESP,Defines the DFI tLP_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_lp_req assertion and a dfi_lp_ack assertion." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB8 20.--23. 1. "RESERVED" hexmask.long.word 0xB8 8.--19. 1. "LPI_WAKEUP_TIMEOUT,Defines the LPI timeout time the maximum cycles between a dfi_lp_req de-assertion and a dfi_lp_ack de-assertion." newline hexmask.long.byte 0xB8 1.--7. 1. "RESERVED" bitfld.long 0xB8 0. "LPI_CTRL_REQ_EN,Enables the dfi_lpi_ctrl_req signal for the LPI." "0,1" line.long 0xBC "DDRSS_CTL_141" hexmask.long.byte 0xBC 28.--31. 1. "RESERVED" hexmask.long.byte 0xBC 24.--27. 1. "LP_AUTO_EXIT_EN,Enable auto exit from each of the low power states when a read or write command enters the command queue." newline hexmask.long.byte 0xBC 20.--23. 1. "RESERVED" hexmask.long.byte 0xBC 16.--19. 1. "LP_AUTO_ENTRY_EN,Enable auto entry into each of the low power states when the associated idle timer expires." newline bitfld.long 0xBC 15. "RESERVED" "0,1" hexmask.long.byte 0xBC 8.--14. 1. "LP_STATE_CS1,Low power state status parameter for chip select 1." newline bitfld.long 0xBC 7. "RESERVED" "0,1" hexmask.long.byte 0xBC 0.--6. 1. "LP_STATE_CS0,Low power state status parameter for chip select 0." line.long 0xC0 "DDRSS_CTL_142" hexmask.long.word 0xC0 20.--31. 1. "RESERVED" hexmask.long.word 0xC0 8.--19. 1. "LP_AUTO_PD_IDLE,Defines the idle time (in controller clocks) until the controller will automatically issue an entry into one of the power-down low power states." newline hexmask.long.byte 0xC0 3.--7. 1. "RESERVED" bitfld.long 0xC0 0.--2. "LP_AUTO_MEM_GATE_EN,Enable memory clock gating when entering a low power state via the auto low power counters." "0,1,2,3,4,5,6,7" line.long 0xC4 "DDRSS_CTL_143" hexmask.long.byte 0xC4 24.--31. 1. "LP_AUTO_SR_LONG_MC_GATE_IDLE,Defines the idle time (in long counts) until the controller will automatically issue an entry into the self-refresh long with memory and controller clock gating or self-refresh power-down long with memory and controller clock.." hexmask.long.byte 0xC4 16.--23. 1. "LP_AUTO_SR_LONG_IDLE,Defines the idle time (in long counts) until the controller will automatically issue an entry into the self-refresh long or self-refresh power-down long (with or without memory clock gating) low power states." newline hexmask.long.byte 0xC4 12.--15. 1. "RESERVED" hexmask.long.word 0xC4 0.--11. 1. "LP_AUTO_SR_SHORT_IDLE,Defines the idle time (in controller clocks) until the controller will automatically issue an entry into the self-refresh short or self-refresh power-down short (with or without memory clock gating) low power states." line.long 0xC8 "DDRSS_CTL_144" hexmask.long.word 0xC8 16.--31. 1. "HW_PROMOTE_THRESHOLD_F1,HW interface promotion number of long counts until the high priority request is asserted for frequency copy 1." hexmask.long.word 0xC8 0.--15. 1. "HW_PROMOTE_THRESHOLD_F0,HW interface promotion number of long counts until the high priority request is asserted for frequency copy 0." line.long 0xCC "DDRSS_CTL_145" hexmask.long.word 0xCC 16.--31. 1. "LPC_PROMOTE_THRESHOLD_F0,LPC promotion number of long counts until the high priority request is asserted for frequency copy 0." hexmask.long.word 0xCC 0.--15. 1. "HW_PROMOTE_THRESHOLD_F2,HW interface promotion number of long counts until the high priority request is asserted for frequency copy 2." line.long 0xD0 "DDRSS_CTL_146" hexmask.long.word 0xD0 16.--31. 1. "LPC_PROMOTE_THRESHOLD_F2,LPC promotion number of long counts until the high priority request is asserted for frequency copy 2." hexmask.long.word 0xD0 0.--15. 1. "LPC_PROMOTE_THRESHOLD_F1,LPC promotion number of long counts until the high priority request is asserted for frequency copy 1." line.long 0xD4 "DDRSS_CTL_147" hexmask.long.byte 0xD4 25.--31. 1. "RESERVED" bitfld.long 0xD4 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xD4 17.--23. 1. "RESERVED" bitfld.long 0xD4 16. "LPC_SR_PHYMSTR_EN,Enable LPC to execute a DFI PHY Master request on a self-refresh exit sequence." "0,1" newline hexmask.long.byte 0xD4 9.--15. 1. "RESERVED" bitfld.long 0xD4 8. "LPC_SR_PHYUPD_EN,Enable LPC to execute a DFI PHY update on a self-refresh exit sequence." "0,1" newline hexmask.long.byte 0xD4 1.--7. 1. "RESERVED" bitfld.long 0xD4 0. "LPC_SR_CTRLUPD_EN,Enable LPC to execute a DFI control update on a self-refresh exit sequence." "0,1" line.long 0xD8 "DDRSS_CTL_148" bitfld.long 0xD8 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xD8 24.--29. 1. "PCPCS_PD_EXIT_DEPTH,Defines the number of entries of the command queue that the PCPCS logic will consider for dynamic power-down exit decode." newline bitfld.long 0xD8 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0xD8 16.--21. 1. "PCPCS_PD_ENTER_DEPTH,Defines the number of entries of the command queue that the PCPCS logic will consider for dynamic power-down entry decode." newline hexmask.long.byte 0xD8 9.--15. 1. "RESERVED" bitfld.long 0xD8 8. "PCPCS_PD_EN,Enable dynamic PCPCS to allow chip selects to dynamically enter and exit power-down." "0,1" newline hexmask.long.byte 0xD8 1.--7. 1. "RESERVED" bitfld.long 0xD8 0. "LPC_SR_ZQ_EN,Enable LPC to execute a ZQ calibration on a self-refresh exit sequence." "0,1" line.long 0xDC "DDRSS_CTL_149" hexmask.long.byte 0xDC 25.--31. 1. "RESERVED" bitfld.long 0xDC 24. "DFS_ENABLE,Enable hardware dynamic frequency scaling." "0,1" newline hexmask.long.byte 0xDC 16.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0xDC 10.--15. 1. "RESERVED" newline bitfld.long 0xDC 8.--9. "PCPCS_PD_MASK,Disables dynamic PCPCS power-down entry/exit for particular chip selects if the PCPCS_PD_EN parameter is set." "0,1,2,3" hexmask.long.byte 0xDC 0.--7. 1. "PCPCS_PD_ENTER_TIMER,Sets the delay used by dynamic PCPCS from when the decode logic determines that a chip select has no outstanding transactions to when the power-down entry command is issued." line.long 0xE0 "DDRSS_CTL_150" hexmask.long.word 0xE0 16.--31. 1. "TDFI_INIT_COMPLETE_F0,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency copy 0 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY." hexmask.long.byte 0xE0 10.--15. 1. "RESERVED" newline hexmask.long.word 0xE0 0.--9. 1. "TDFI_INIT_START_F0,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency copy 0 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY." line.long 0xE4 "DDRSS_CTL_151" hexmask.long.word 0xE4 16.--31. 1. "TDFI_INIT_COMPLETE_F1,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency copy 1 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY." hexmask.long.byte 0xE4 10.--15. 1. "RESERVED" newline hexmask.long.word 0xE4 0.--9. 1. "TDFI_INIT_START_F1,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency copy 1 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY." line.long 0xE8 "DDRSS_CTL_152" hexmask.long.word 0xE8 16.--31. 1. "TDFI_INIT_COMPLETE_F2,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency copy 2 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY." hexmask.long.byte 0xE8 10.--15. 1. "RESERVED" newline hexmask.long.word 0xE8 0.--9. 1. "TDFI_INIT_START_F2,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency copy 2 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY." line.long 0xEC "DDRSS_CTL_153" hexmask.long.tbyte 0xEC 9.--31. 1. "RESERVED" bitfld.long 0xEC 8. "DFS_PHY_REG_WRITE_EN,Enable a register write to the PHY during a frequency change." "0,1" newline hexmask.long.byte 0xEC 2.--7. 1. "RESERVED" rbitfld.long 0xEC 0.--1. "CURRENT_REG_COPY,Indicates the current copy of timing parameters that is in use by the controller." "0,1,2,3" line.long 0xF0 "DDRSS_CTL_154" hexmask.long 0xF0 0.--31. 1. "DFS_PHY_REG_WRITE_ADDR,Register address which will be written during a frequency change." line.long 0xF4 "DDRSS_CTL_155" hexmask.long 0xF4 0.--31. 1. "DFS_PHY_REG_WRITE_DATA_F0,Register data which will be written during a frequency change for frequency copy 0." line.long 0xF8 "DDRSS_CTL_156" hexmask.long 0xF8 0.--31. 1. "DFS_PHY_REG_WRITE_DATA_F1,Register data which will be written during a frequency change for frequency copy 1." line.long 0xFC "DDRSS_CTL_157" hexmask.long 0xFC 0.--31. 1. "DFS_PHY_REG_WRITE_DATA_F2,Register data which will be written during a frequency change for frequency copy 2." line.long 0x100 "DDRSS_CTL_158" hexmask.long.byte 0x100 24.--31. 1. "RESERVED" hexmask.long.word 0x100 8.--23. 1. "DFS_PHY_REG_WRITE_WAIT,Defines the number of DFI PHY clocks that the controller will wait after issuing the register write to the PHY during a frequency change." newline hexmask.long.byte 0x100 4.--7. 1. "RESERVED" hexmask.long.byte 0x100 0.--3. 1. "DFS_PHY_REG_WRITE_MASK,Register mask which will be written during a frequency change." line.long 0x104 "DDRSS_CTL_159" hexmask.long.byte 0x104 27.--31. 1. "RESERVED" hexmask.long 0x104 0.--26. 1. "WRITE_MODEREG,Write memory mode register data to the DRAMs." line.long 0x108 "DDRSS_CTL_160" hexmask.long.byte 0x108 25.--31. 1. "RESERVED" hexmask.long.tbyte 0x108 8.--24. 1. "READ_MODEREG,Read the specified memory mode register from specified chip when start bit set." newline hexmask.long.byte 0x108 0.--7. 1. "MRW_STATUS,Write memory mode register status." rgroup.long 0x284++0x7 line.long 0x0 "DDRSS_CTL_161" hexmask.long 0x0 0.--31. 1. "PERIPHERAL_MRR_DATA_0,Data and chip returned from memory mode register read requested by the READ_MODEREG parameter." line.long 0x4 "DDRSS_CTL_162" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.word 0x4 8.--23. 1. "AUTO_TEMPCHK_VAL_0,MR4 data for all devices on chip 0 accessed by automatic MRR commands." newline hexmask.long.byte 0x4 0.--7. 1. "PERIPHERAL_MRR_DATA_1,Data and chip returned from memory mode register read requested by the READ_MODEREG parameter." group.long 0x28C++0xBB line.long 0x0 "DDRSS_CTL_163" hexmask.long.word 0x0 17.--31. 1. "RESERVED" bitfld.long 0x0 16. "DISABLE_UPDATE_TVRCG,Bypass changing for TVRCG during a DFS operation." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "AUTO_TEMPCHK_VAL_1,MR4 data for all devices on chip 1 accessed by automatic MRR commands." line.long 0x4 "DDRSS_CTL_164" hexmask.long.byte 0x4 26.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--25. 1. "TVRCG_ENABLE_F0,JEDEC TVRCG_ENABLE time." newline hexmask.long.word 0x4 2.--15. 1. "RESERVED" bitfld.long 0x4 0.--1. "MRW_DFS_UPDATE_FRC,Defines the frequency register set to use when doing a software MRW with WRITE_MODEREG bit (26)." "0,1,2,3" line.long 0x8 "DDRSS_CTL_165" hexmask.long.byte 0x8 26.--31. 1. "RESERVED" hexmask.long.word 0x8 16.--25. 1. "TFC_F0,JEDEC TFC the frequency set point switching time." newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "TVRCG_DISABLE_F0,JEDEC TVRCG_DISABLE time." line.long 0xC "DDRSS_CTL_166" hexmask.long.word 0xC 16.--31. 1. "TVREF_LONG_F0,JEDEC TVREF design will always use the long value." bitfld.long 0xC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "TCKFSPX_F0,JEDEC TCKFSPX the valid clock requirement before 1st valid command after FSP change." bitfld.long 0xC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "TCKFSPE_F0,JEDEC TCKFSPE the valid clock requirement after entering SDP change." line.long 0x10 "DDRSS_CTL_167" hexmask.long.byte 0x10 26.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--25. 1. "TVRCG_DISABLE_F1,JEDEC TVRCG_DISABLE time." newline hexmask.long.byte 0x10 10.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--9. 1. "TVRCG_ENABLE_F1,JEDEC TVRCG_ENABLE time." line.long 0x14 "DDRSS_CTL_168" bitfld.long 0x14 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 24.--28. 1. "TCKFSPX_F1,JEDEC TCKFSPX the valid clock requirement before 1st valid command after FSP change." newline bitfld.long 0x14 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 16.--20. 1. "TCKFSPE_F1,JEDEC TCKFSPE the valid clock requirement after entering SDP change." newline hexmask.long.byte 0x14 10.--15. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "TFC_F1,JEDEC TFC the frequency set point switching time." line.long 0x18 "DDRSS_CTL_169" hexmask.long.byte 0x18 26.--31. 1. "RESERVED" hexmask.long.word 0x18 16.--25. 1. "TVRCG_ENABLE_F2,JEDEC TVRCG_ENABLE time." newline hexmask.long.word 0x18 0.--15. 1. "TVREF_LONG_F1,JEDEC TVREF design will always use the long value." line.long 0x1C "DDRSS_CTL_170" hexmask.long.byte 0x1C 26.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--25. 1. "TFC_F2,JEDEC TFC the frequency set point switching time." newline hexmask.long.byte 0x1C 10.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--9. 1. "TVRCG_DISABLE_F2,JEDEC TVRCG_DISABLE time." line.long 0x20 "DDRSS_CTL_171" hexmask.long.word 0x20 16.--31. 1. "TVREF_LONG_F2,JEDEC TVREF design will always use the long value." bitfld.long 0x20 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 8.--12. 1. "TCKFSPX_F2,JEDEC TCKFSPX the valid clock requirement before 1st valid command after FSP change." bitfld.long 0x20 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 0.--4. 1. "TCKFSPE_F2,JEDEC TCKFSPE the valid clock requirement after entering SDP change." line.long 0x24 "DDRSS_CTL_172" hexmask.long.word 0x24 16.--31. 1. "MRR_PROMOTE_THRESHOLD_F1,MRR promotion number of long counts until the high priority request is asserted for frequency copy 1." hexmask.long.word 0x24 0.--15. 1. "MRR_PROMOTE_THRESHOLD_F0,MRR promotion number of long counts until the high priority request is asserted for frequency copy 0." line.long 0x28 "DDRSS_CTL_173" hexmask.long.word 0x28 16.--31. 1. "MRW_PROMOTE_THRESHOLD_F0,MRW promotion number of long counts until the high priority request is asserted for frequency copy 0." hexmask.long.word 0x28 0.--15. 1. "MRR_PROMOTE_THRESHOLD_F2,MRR promotion number of long counts until the high priority request is asserted for frequency copy 2." line.long 0x2C "DDRSS_CTL_174" hexmask.long.word 0x2C 16.--31. 1. "MRW_PROMOTE_THRESHOLD_F2,MRW promotion number of long counts until the high priority request is asserted for frequency copy 2." hexmask.long.word 0x2C 0.--15. 1. "MRW_PROMOTE_THRESHOLD_F1,MRW promotion number of long counts until the high priority request is asserted for frequency copy 1." line.long 0x30 "DDRSS_CTL_175" hexmask.long.byte 0x30 24.--31. 1. "MR2_DATA_F1_0,Data to program into memory mode register 2 for chip select 0 for frequency copy 1." hexmask.long.byte 0x30 16.--23. 1. "MR1_DATA_F1_0,Data to program into memory mode register 1 for chip select 0 for frequency copy 1." newline hexmask.long.byte 0x30 8.--15. 1. "MR2_DATA_F0_0,Data to program into memory mode register 2 for chip select 0 for frequency copy 0." hexmask.long.byte 0x30 0.--7. 1. "MR1_DATA_F0_0,Data to program into memory mode register 1 for chip select 0 for frequency copy 0." line.long 0x34 "DDRSS_CTL_176" hexmask.long.byte 0x34 24.--31. 1. "MR3_DATA_F0_0,Data to program into memory mode register 3 for chip select 0 for frequency copy 0." hexmask.long.byte 0x34 16.--23. 1. "MRSINGLE_DATA_0,Data to program into memory mode register single write to chip select 0." newline hexmask.long.byte 0x34 8.--15. 1. "MR2_DATA_F2_0,Data to program into memory mode register 2 for chip select 0 for frequency copy 2." hexmask.long.byte 0x34 0.--7. 1. "MR1_DATA_F2_0,Data to program into memory mode register 1 for chip select 0 for frequency copy 2." line.long 0x38 "DDRSS_CTL_177" hexmask.long.byte 0x38 24.--31. 1. "MR4_DATA_F1_0,Data to program into memory mode register 4 for chip select 0 for frequency copy 1." hexmask.long.byte 0x38 16.--23. 1. "MR4_DATA_F0_0,Data to program into memory mode register 4 for chip select 0 for frequency copy 0." newline hexmask.long.byte 0x38 8.--15. 1. "MR3_DATA_F2_0,Data to program into memory mode register 3 for chip select 0 for frequency copy 2." hexmask.long.byte 0x38 0.--7. 1. "MR3_DATA_F1_0,Data to program into memory mode register 3 for chip select 0 for frequency copy 1." line.long 0x3C "DDRSS_CTL_178" hexmask.long.byte 0x3C 24.--31. 1. "MR11_DATA_F1_0,Data to program into memory mode register 11 for chip select 0 for frequency copy 1." hexmask.long.byte 0x3C 16.--23. 1. "MR11_DATA_F0_0,Data to program into memory mode register 11 for chip select 0 for frequency copy 0." newline hexmask.long.byte 0x3C 8.--15. 1. "MR8_DATA_0,Data read from MR8 for chip select 0." hexmask.long.byte 0x3C 0.--7. 1. "MR4_DATA_F2_0,Data to program into memory mode register 4 for chip select 0 for frequency copy 2." line.long 0x40 "DDRSS_CTL_179" hexmask.long.byte 0x40 24.--31. 1. "MR12_DATA_F2_0,Data to program into memory mode register 12 for chip select 0." hexmask.long.byte 0x40 16.--23. 1. "MR12_DATA_F1_0,Data to program into memory mode register 12 for chip select 0." newline hexmask.long.byte 0x40 8.--15. 1. "MR12_DATA_F0_0,Data to program into memory mode register 12 for chip select 0." hexmask.long.byte 0x40 0.--7. 1. "MR11_DATA_F2_0,Data to program into memory mode register 11 for chip select 0 for frequency copy 2." line.long 0x44 "DDRSS_CTL_180" hexmask.long.byte 0x44 24.--31. 1. "MR14_DATA_F2_0,Data to program into memory mode register 14 for chip select 0." hexmask.long.byte 0x44 16.--23. 1. "MR14_DATA_F1_0,Data to program into memory mode register 14 for chip select 0." newline hexmask.long.byte 0x44 8.--15. 1. "MR14_DATA_F0_0,Data to program into memory mode register 14 for chip select 0." hexmask.long.byte 0x44 0.--7. 1. "MR13_DATA_0,Data to program into memory mode register 13 for chip select 0." line.long 0x48 "DDRSS_CTL_181" hexmask.long.byte 0x48 24.--31. 1. "MR22_DATA_F0_0,Data to program into memory mode register 22 for chip select 0." hexmask.long.byte 0x48 16.--23. 1. "MR20_DATA_0,Data read from MR20 for chip select 0." newline hexmask.long.byte 0x48 8.--15. 1. "MR17_DATA_0,Data to program into memory mode register 17 for chip select 0." hexmask.long.byte 0x48 0.--7. 1. "MR16_DATA_0,Data to program into memory mode register 16 for chip select 0." line.long 0x4C "DDRSS_CTL_182" hexmask.long.byte 0x4C 24.--31. 1. "MR2_DATA_F0_1,Data to program into memory mode register 2 for chip select 1 for frequency copy 0." hexmask.long.byte 0x4C 16.--23. 1. "MR1_DATA_F0_1,Data to program into memory mode register 1 for chip select 1 for frequency copy 0." newline hexmask.long.byte 0x4C 8.--15. 1. "MR22_DATA_F2_0,Data to program into memory mode register 22 for chip select 0." hexmask.long.byte 0x4C 0.--7. 1. "MR22_DATA_F1_0,Data to program into memory mode register 22 for chip select 0." line.long 0x50 "DDRSS_CTL_183" hexmask.long.byte 0x50 24.--31. 1. "MR2_DATA_F2_1,Data to program into memory mode register 2 for chip select 1 for frequency copy 2." hexmask.long.byte 0x50 16.--23. 1. "MR1_DATA_F2_1,Data to program into memory mode register 1 for chip select 1 for frequency copy 2." newline hexmask.long.byte 0x50 8.--15. 1. "MR2_DATA_F1_1,Data to program into memory mode register 2 for chip select 1 for frequency copy 1." hexmask.long.byte 0x50 0.--7. 1. "MR1_DATA_F1_1,Data to program into memory mode register 1 for chip select 1 for frequency copy 1." line.long 0x54 "DDRSS_CTL_184" hexmask.long.byte 0x54 24.--31. 1. "MR3_DATA_F2_1,Data to program into memory mode register 3 for chip select 1 for frequency copy 2." hexmask.long.byte 0x54 16.--23. 1. "MR3_DATA_F1_1,Data to program into memory mode register 3 for chip select 1 for frequency copy 1." newline hexmask.long.byte 0x54 8.--15. 1. "MR3_DATA_F0_1,Data to program into memory mode register 3 for chip select 1 for frequency copy 0." hexmask.long.byte 0x54 0.--7. 1. "MRSINGLE_DATA_1,Data to program into memory mode register single write to chip select 1." line.long 0x58 "DDRSS_CTL_185" hexmask.long.byte 0x58 24.--31. 1. "MR8_DATA_1,Data read from MR8 for chip select 1." hexmask.long.byte 0x58 16.--23. 1. "MR4_DATA_F2_1,Data to program into memory mode register 4 for chip select 1 for frequency copy 2." newline hexmask.long.byte 0x58 8.--15. 1. "MR4_DATA_F1_1,Data to program into memory mode register 4 for chip select 1 for frequency copy 1." hexmask.long.byte 0x58 0.--7. 1. "MR4_DATA_F0_1,Data to program into memory mode register 4 for chip select 1 for frequency copy 0." line.long 0x5C "DDRSS_CTL_186" hexmask.long.byte 0x5C 24.--31. 1. "MR12_DATA_F0_1,Data to program into memory mode register 12 for chip select 1." hexmask.long.byte 0x5C 16.--23. 1. "MR11_DATA_F2_1,Data to program into memory mode register 11 for chip select 1 for frequency copy 2." newline hexmask.long.byte 0x5C 8.--15. 1. "MR11_DATA_F1_1,Data to program into memory mode register 11 for chip select 1 for frequency copy 1." hexmask.long.byte 0x5C 0.--7. 1. "MR11_DATA_F0_1,Data to program into memory mode register 11 for chip select 1 for frequency copy 0." line.long 0x60 "DDRSS_CTL_187" hexmask.long.byte 0x60 24.--31. 1. "MR14_DATA_F0_1,Data to program into memory mode register 14 for chip select 1." hexmask.long.byte 0x60 16.--23. 1. "MR13_DATA_1,Data to program into memory mode register 13 for chip select 1." newline hexmask.long.byte 0x60 8.--15. 1. "MR12_DATA_F2_1,Data to program into memory mode register 12 for chip select 1." hexmask.long.byte 0x60 0.--7. 1. "MR12_DATA_F1_1,Data to program into memory mode register 12 for chip select 1." line.long 0x64 "DDRSS_CTL_188" hexmask.long.byte 0x64 24.--31. 1. "MR17_DATA_1,Data to program into memory mode register 17 for chip select 1." hexmask.long.byte 0x64 16.--23. 1. "MR16_DATA_1,Data to program into memory mode register 16 for chip select 1." newline hexmask.long.byte 0x64 8.--15. 1. "MR14_DATA_F2_1,Data to program into memory mode register 14 for chip select 1." hexmask.long.byte 0x64 0.--7. 1. "MR14_DATA_F1_1,Data to program into memory mode register 14 for chip select 1." line.long 0x68 "DDRSS_CTL_189" hexmask.long.byte 0x68 24.--31. 1. "MR22_DATA_F2_1,Data to program into memory mode register 22 for chip select 1." hexmask.long.byte 0x68 16.--23. 1. "MR22_DATA_F1_1,Data to program into memory mode register 22 for chip select 1." newline hexmask.long.byte 0x68 8.--15. 1. "MR22_DATA_F0_1,Data to program into memory mode register 22 for chip select 1." hexmask.long.byte 0x68 0.--7. 1. "MR20_DATA_1,Data read from MR20 for chip select 1." line.long 0x6C "DDRSS_CTL_190" hexmask.long.byte 0x6C 25.--31. 1. "RESERVED" bitfld.long 0x6C 24. "MR_FSP_DATA_VALID_F2,Indicates that at this frequency memory was trained and the associated data has been loaded into the MRx_DATA parameter(s)." "0,1" newline hexmask.long.byte 0x6C 17.--23. 1. "RESERVED" bitfld.long 0x6C 16. "MR_FSP_DATA_VALID_F1,Indicates that at this frequency memory was trained and the associated data has been loaded into the MRx_DATA parameter(s)." "0,1" newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED" bitfld.long 0x6C 8. "MR_FSP_DATA_VALID_F0,Indicates that at this frequency memory was trained and the associated data has been loaded into the MRx_DATA parameter(s)." "0,1" newline hexmask.long.byte 0x6C 0.--7. 1. "MR23_DATA,Data to program into memory mode register 23." line.long 0x70 "DDRSS_CTL_191" hexmask.long.byte 0x70 25.--31. 1. "RESERVED" bitfld.long 0x70 24. "FSP_PHY_UPDATE_MRW,Identifies the logic responsible for updating MR12 and MR14 in memory." "0,1" newline hexmask.long.byte 0x70 17.--23. 1. "RESERVED" rbitfld.long 0x70 16. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x70 9.--15. 1. "RESERVED" rbitfld.long 0x70 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x70 2.--7. 1. "RESERVED" rbitfld.long 0x70 0.--1. "RL3_SUPPORT_EN,Indicates if RL3 is supported by a connected LPDDR3 memory." "0,1,2,3" line.long 0x74 "DDRSS_CTL_192" hexmask.long.byte 0x74 25.--31. 1. "RESERVED" bitfld.long 0x74 24. "FSP_WR_CURRENT,Reports which FSP set the memory will target with write commands." "0,1" newline hexmask.long.byte 0x74 17.--23. 1. "RESERVED" bitfld.long 0x74 16. "FSP_OP_CURRENT,Reports which FSP set the memory is currently using." "0,1" newline hexmask.long.byte 0x74 9.--15. 1. "RESERVED" bitfld.long 0x74 8. "FSP_STATUS,Indicates that a DFS event caused the FSP mode registers to be updated." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RESERVED" bitfld.long 0x74 0. "DFS_ALWAYS_WRITE_FSP,Forces all FSP mode registers to be written by the controller during a DFS event." "0,1" line.long 0x78 "DDRSS_CTL_193" hexmask.long.byte 0x78 26.--31. 1. "RESERVED" bitfld.long 0x78 24.--25. "FSP1_FRC,Identifies which of the controller's frequency copy is associated with FSP1." "0,1,2,3" newline hexmask.long.byte 0x78 18.--23. 1. "RESERVED" bitfld.long 0x78 16.--17. "FSP0_FRC,Identifies which of the controller's frequency copy is associated with FSP0." "0,1,2,3" newline hexmask.long.byte 0x78 9.--15. 1. "RESERVED" bitfld.long 0x78 8. "FSP1_FRC_VALID,Specifies whether the FSP set defined in the FSP1_FRC parameter reflects the frequency used to program the FSP1 registers." "0,1" newline hexmask.long.byte 0x78 1.--7. 1. "RESERVED" bitfld.long 0x78 0. "FSP0_FRC_VALID,Specifies whether the FSP set defined in the FSP0_FRC parameter reflects the frequency used to program the FSP0 registers." "0,1" line.long 0x7C "DDRSS_CTL_194" hexmask.long.byte 0x7C 25.--31. 1. "RESERVED" bitfld.long 0x7C 24. "BIST_DATA_CHECK,Enable data checking with BIST operation." "0,1" newline bitfld.long 0x7C 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x7C 16.--21. 1. "ADDR_SPACE,Sets the number of address bits to check during BIST operation." newline hexmask.long.byte 0x7C 10.--15. 1. "RESERVED" rbitfld.long 0x7C 8.--9. "BIST_RESULT,BIST operation status (pass/fail)." "0,1,2,3" newline hexmask.long.byte 0x7C 1.--7. 1. "RESERVED" bitfld.long 0x7C 0. "BIST_GO,Initiate a BIST operation." "0,1" line.long 0x80 "DDRSS_CTL_195" hexmask.long 0x80 1.--31. 1. "RESERVED" bitfld.long 0x80 0. "BIST_ADDR_CHECK,Enable address checking with BIST operation." "0,1" line.long 0x84 "DDRSS_CTL_196" hexmask.long 0x84 0.--31. 1. "BIST_START_ADDRESS_0,Start BIST checking at this address." line.long 0x88 "DDRSS_CTL_197" hexmask.long 0x88 3.--31. 1. "RESERVED" bitfld.long 0x88 0.--2. "BIST_START_ADDRESS_1,Start BIST checking at this address." "0,1,2,3,4,5,6,7" line.long 0x8C "DDRSS_CTL_198" hexmask.long 0x8C 0.--31. 1. "BIST_DATA_MASK_0,Mask applied to data for BIST error checking." line.long 0x90 "DDRSS_CTL_199" hexmask.long 0x90 0.--31. 1. "BIST_DATA_MASK_1,Mask applied to data for BIST error checking." line.long 0x94 "DDRSS_CTL_200" hexmask.long 0x94 3.--31. 1. "RESERVED" bitfld.long 0x94 0.--2. "BIST_TEST_MODE,Sets the BIST test mode." "0,1,2,3,4,5,6,7" line.long 0x98 "DDRSS_CTL_201" hexmask.long 0x98 0.--31. 1. "BIST_DATA_PATTERN_0,Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1 2 3 or 4." line.long 0x9C "DDRSS_CTL_202" hexmask.long 0x9C 0.--31. 1. "BIST_DATA_PATTERN_1,Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1 2 3 or 4." line.long 0xA0 "DDRSS_CTL_203" hexmask.long 0xA0 0.--31. 1. "BIST_DATA_PATTERN_2,Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1 2 3 or 4." line.long 0xA4 "DDRSS_CTL_204" hexmask.long 0xA4 0.--31. 1. "BIST_DATA_PATTERN_3,Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1 2 3 or 4." line.long 0xA8 "DDRSS_CTL_205" hexmask.long.byte 0xA8 28.--31. 1. "RESERVED" hexmask.long.word 0xA8 16.--27. 1. "BIST_ERR_STOP,Defines the maximum number of error occurrences allowed prior to quitting when the BIST_TEST_MODE parameter is programmed to 1 2 or 3." newline hexmask.long.byte 0xA8 9.--15. 1. "RESERVED" rbitfld.long 0xA8 8. "BIST_RET_STATE,Indicates if BIST is in a retention wait state used when the BIST_TEST_MODE parameter is programmed to 2 or 3." "0,1" newline hexmask.long.byte 0xA8 1.--7. 1. "RESERVED" bitfld.long 0xA8 0. "BIST_RET_STATE_EXIT,Exit self-refresh or idle retention state used when the BIST_TEST_MODE parameter is programmed to 2 or 3." "0,1" line.long 0xAC "DDRSS_CTL_206,The ECC Engine block of the DDR controller is not supported." hexmask.long.byte 0xAC 27.--31. 1. "RESERVED" bitfld.long 0xAC 24.--26. "INLINE_ECC_BANK_OFFSET,Inline ECC Bank Offset defines the bank shift between data and ECC commands associated with the same sequence" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xAC 18.--23. 1. "RESERVED" bitfld.long 0xAC 16.--17. "ECC_ENABLE,ECC error checking and correcting control register." "0,1,2,3" newline hexmask.long.byte 0xAC 12.--15. 1. "RESERVED" hexmask.long.word 0xAC 0.--11. 1. "BIST_ERR_COUNT,Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is programmed to 1 2 or 3." line.long 0xB0 "DDRSS_CTL_207" hexmask.long.byte 0xB0 25.--31. 1. "RESERVED" bitfld.long 0xB0 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xB0 20.--23. 1. "RESERVED" hexmask.long.byte 0xB0 16.--19. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xB0 9.--15. 1. "RESERVED" bitfld.long 0xB0 8. "ECC_WRITE_COMBINING_EN,Allows ECC write data within a given ECC buffer to be combined across commands so that in certain cases where we see multiple ECC writes to the same ECC address the controller may end up only issuing one final ECC write command to.." "0,1" newline hexmask.long.byte 0xB0 1.--7. 1. "RESERVED" bitfld.long 0xB0 0. "ECC_READ_CACHING_EN,Allows ECC read data already in one of the ECC buffers to be used when possible in place of issuing an ECC read command to memory." "0,1" line.long 0xB4 "DDRSS_CTL_208" hexmask.long.byte 0xB4 25.--31. 1. "RESERVED" bitfld.long 0xB4 24. "ECC_WRITEBACK_EN,ECC writeback will occur on detection of single bit errors for reads." "0,1" newline hexmask.long.word 0xB4 8.--23. 1. "XOR_CHECK_BITS,Value to xor with generated ECC codes for forced write check." hexmask.long.byte 0xB4 1.--7. 1. "RESERVED" newline bitfld.long 0xB4 0. "FWC,Force a write check." "0,1" line.long 0xB8 "DDRSS_CTL_209" hexmask.long 0xB8 1.--31. 1. "RESERVED" bitfld.long 0xB8 0. "ECC_DISABLE_W_UC_ERR,Controls auto-corruption of ECC when un-correctable errors occur in R/M/W operations." "0,1" rgroup.long 0x348++0x1F line.long 0x0 "DDRSS_CTL_210" hexmask.long 0x0 0.--31. 1. "ECC_U_ADDR_0,Address of uncorrectable ECC event." line.long 0x4 "DDRSS_CTL_211" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 8.--15. 1. "ECC_U_SYND,Syndrome for uncorrectable ECC event." newline hexmask.long.byte 0x4 3.--7. 1. "RESERVED" bitfld.long 0x4 0.--2. "ECC_U_ADDR_1,Address of uncorrectable ECC event." "0,1,2,3,4,5,6,7" line.long 0x8 "DDRSS_CTL_212" hexmask.long 0x8 0.--31. 1. "ECC_U_DATA_0,Data associated with uncorrectable ECC event." line.long 0xC "DDRSS_CTL_213" hexmask.long 0xC 0.--31. 1. "ECC_U_DATA_1,Data associated with uncorrectable ECC event." line.long 0x10 "DDRSS_CTL_214" hexmask.long 0x10 0.--31. 1. "ECC_C_ADDR_0,Address of correctable ECC event." line.long 0x14 "DDRSS_CTL_215" hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "ECC_C_SYND,Syndrome for correctable ECC event." newline hexmask.long.byte 0x14 3.--7. 1. "RESERVED" bitfld.long 0x14 0.--2. "ECC_C_ADDR_1,Address of correctable ECC event." "0,1,2,3,4,5,6,7" line.long 0x18 "DDRSS_CTL_216" hexmask.long 0x18 0.--31. 1. "ECC_C_DATA_0,Data associated with correctable ECC event." line.long 0x1C "DDRSS_CTL_217" hexmask.long 0x1C 0.--31. 1. "ECC_C_DATA_1,Data associated with correctable ECC event." group.long 0x368++0x97 line.long 0x0 "DDRSS_CTL_218" bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long.word 0x0 16.--30. 1. "NON_ECC_REGION_START_ADDR_0,Set the base address of the soft-designated non-ECC region 0." newline bitfld.long 0x0 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "ECC_C_ID,Source ID associated with correctable ECC event." newline bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "ECC_U_ID,Source ID associated with the uncorrectable ECC event." line.long 0x4 "DDRSS_CTL_219" bitfld.long 0x4 31. "RESERVED" "0,1" hexmask.long.word 0x4 16.--30. 1. "NON_ECC_REGION_START_ADDR_1,Set the base address of the soft-designated non-ECC region 1." newline bitfld.long 0x4 15. "RESERVED" "0,1" hexmask.long.word 0x4 0.--14. 1. "NON_ECC_REGION_END_ADDR_0,Set the base address of the soft-designated non-ECC region 0." line.long 0x8 "DDRSS_CTL_220" bitfld.long 0x8 31. "RESERVED" "0,1" hexmask.long.word 0x8 16.--30. 1. "NON_ECC_REGION_START_ADDR_2,Set the base address of the soft-designated non-ECC region 2." newline bitfld.long 0x8 15. "RESERVED" "0,1" hexmask.long.word 0x8 0.--14. 1. "NON_ECC_REGION_END_ADDR_1,Set the base address of the soft-designated non-ECC region 1." line.long 0xC "DDRSS_CTL_221" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "ECC_SCRUB_START,ECC scrubbing control." "0,1" newline hexmask.long.byte 0xC 19.--23. 1. "RESERVED" bitfld.long 0xC 16.--18. "NON_ECC_REGION_ENABLE,Enables each soft-designated non-ECC region." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 15. "RESERVED" "0,1" hexmask.long.word 0xC 0.--14. 1. "NON_ECC_REGION_END_ADDR_2,Set the base address of the soft-designated non-ECC region 2." line.long 0x10 "DDRSS_CTL_222" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" bitfld.long 0x10 24. "ECC_SCRUB_MODE,Defines how often ECC scrubbing operations will occur." "0,1" newline hexmask.long.byte 0x10 20.--23. 1. "RESERVED" hexmask.long.word 0x10 8.--19. 1. "ECC_SCRUB_LEN,Defines the length of the ECC scrubbing read command that the controller will issue." newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" rbitfld.long 0x10 0. "ECC_SCRUB_IN_PROGRESS,Reports the scrubbing operation status." "0,1" line.long 0x14 "DDRSS_CTL_223" hexmask.long.word 0x14 16.--31. 1. "ECC_SCRUB_IDLE_CNT,The number of controller clock cycles that the scrubbing engine will wait in controller idle state before starting scrubbing operations." hexmask.long.word 0x14 0.--15. 1. "ECC_SCRUB_INTERVAL,The minimum interval between two ECC scrubbing commands in number of controller clock cycles." line.long 0x18 "DDRSS_CTL_224" hexmask.long 0x18 0.--31. 1. "ECC_SCRUB_START_ADDR_0,The starting address from where scrubbing operations will begin." line.long 0x1C "DDRSS_CTL_225" hexmask.long 0x1C 3.--31. 1. "RESERVED" bitfld.long 0x1C 0.--2. "ECC_SCRUB_START_ADDR_1,The starting address from where scrubbing operations will begin." "0,1,2,3,4,5,6,7" line.long 0x20 "DDRSS_CTL_226" hexmask.long 0x20 0.--31. 1. "ECC_SCRUB_END_ADDR_0,The end address where scrubbing operations will wrap around to the start address." line.long 0x24 "DDRSS_CTL_227" bitfld.long 0x24 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 24.--28. 1. "AREF_HIGH_THRESHOLD,AREF number of pending refreshes until the high priority request is asserted." newline bitfld.long 0x24 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--20. 1. "AREF_NORM_THRESHOLD,AREF number of pending refreshes until the normal priority request is asserted." newline bitfld.long 0x24 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 8.--12. 1. "LONG_COUNT_MASK,Reduces the length of the long counter from 1024 cycles." newline hexmask.long.byte 0x24 3.--7. 1. "RESERVED" bitfld.long 0x24 0.--2. "ECC_SCRUB_END_ADDR_1,The end address where scrubbing operations will wrap around to the start address." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_CTL_228" hexmask.long.word 0x28 20.--31. 1. "RESERVED" hexmask.long.byte 0x28 16.--19. 1. "AREF_CMD_MAX_PER_TREFI,Sets the maximum number of auto-refreshes that will be executed in a TREFI period - both normal and high priority." newline bitfld.long 0x28 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 8.--12. 1. "AREF_MAX_CREDIT,AREF number of posted refreshes until the maximum number of refresh credits has been reached." newline bitfld.long 0x28 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--4. 1. "AREF_MAX_DEFICIT,AREF number of pending refreshes until the maximum number of refreshes has been exceeded." line.long 0x2C "DDRSS_CTL_229" hexmask.long.word 0x2C 16.--31. 1. "ZQ_CALSTART_HIGH_THRESHOLD_F0,ZQ START number of long counts until the high priority request is asserted for frequency copy 0." hexmask.long.word 0x2C 0.--15. 1. "ZQ_CALSTART_NORM_THRESHOLD_F0,ZQ START number of long counts until the normal priority request is asserted for frequency copy 0." line.long 0x30 "DDRSS_CTL_230" hexmask.long.word 0x30 16.--31. 1. "ZQ_CS_NORM_THRESHOLD_F0,ZQ CS number of long counts until the normal priority request is asserted for frequency copy 0." hexmask.long.word 0x30 0.--15. 1. "ZQ_CALLATCH_HIGH_THRESHOLD_F0,ZQ LATCH number of long counts until the high priority request is asserted for frequency copy 0." line.long 0x34 "DDRSS_CTL_231" hexmask.long.word 0x34 16.--31. 1. "ZQ_CALSTART_TIMEOUT_F0,ZQ START number of long counts until the timeout is asserted for frequency copy 0." hexmask.long.word 0x34 0.--15. 1. "ZQ_CS_HIGH_THRESHOLD_F0,ZQ CS number of long counts until the high priority request is asserted for frequency copy 0." line.long 0x38 "DDRSS_CTL_232" hexmask.long.word 0x38 16.--31. 1. "ZQ_CS_TIMEOUT_F0,ZQ CS number of long counts until the timeout is asserted for frequency copy 0." hexmask.long.word 0x38 0.--15. 1. "ZQ_CALLATCH_TIMEOUT_F0,ZQ LATCH number of long counts until the timeout is asserted for frequency copy 0." line.long 0x3C "DDRSS_CTL_233" hexmask.long.word 0x3C 16.--31. 1. "ZQ_CALSTART_NORM_THRESHOLD_F1,ZQ START number of long counts until the normal priority request is asserted for frequency copy 1." hexmask.long.word 0x3C 0.--15. 1. "ZQ_PROMOTE_THRESHOLD_F0,ZQ SW promotion number of long counts until the high priority request is asserted for frequency copy 0." line.long 0x40 "DDRSS_CTL_234" hexmask.long.word 0x40 16.--31. 1. "ZQ_CALLATCH_HIGH_THRESHOLD_F1,ZQ LATCH number of long counts until the high priority request is asserted for frequency copy 1." hexmask.long.word 0x40 0.--15. 1. "ZQ_CALSTART_HIGH_THRESHOLD_F1,ZQ START number of long counts until the high priority request is asserted for frequency copy 1." line.long 0x44 "DDRSS_CTL_235" hexmask.long.word 0x44 16.--31. 1. "ZQ_CS_HIGH_THRESHOLD_F1,ZQ CS number of long counts until the high priority request is asserted for frequency copy 1." hexmask.long.word 0x44 0.--15. 1. "ZQ_CS_NORM_THRESHOLD_F1,ZQ CS number of long counts until the normal priority request is asserted for frequency copy 1." line.long 0x48 "DDRSS_CTL_236" hexmask.long.word 0x48 16.--31. 1. "ZQ_CALLATCH_TIMEOUT_F1,ZQ LATCH number of long counts until the timeout is asserted for frequency copy 1." hexmask.long.word 0x48 0.--15. 1. "ZQ_CALSTART_TIMEOUT_F1,ZQ START number of long counts until the timeout is asserted for frequency copy 1." line.long 0x4C "DDRSS_CTL_237" hexmask.long.word 0x4C 16.--31. 1. "ZQ_PROMOTE_THRESHOLD_F1,ZQ SW promotion number of long counts until the high priority request is asserted for frequency copy 1." hexmask.long.word 0x4C 0.--15. 1. "ZQ_CS_TIMEOUT_F1,ZQ CS number of long counts until the timeout is asserted for frequency copy 1." line.long 0x50 "DDRSS_CTL_238" hexmask.long.word 0x50 16.--31. 1. "ZQ_CALSTART_HIGH_THRESHOLD_F2,ZQ START number of long counts until the high priority request is asserted for frequency copy 2." hexmask.long.word 0x50 0.--15. 1. "ZQ_CALSTART_NORM_THRESHOLD_F2,ZQ START number of long counts until the normal priority request is asserted for frequency copy 2." line.long 0x54 "DDRSS_CTL_239" hexmask.long.word 0x54 16.--31. 1. "ZQ_CS_NORM_THRESHOLD_F2,ZQ CS number of long counts until the normal priority request is asserted for frequency copy 2." hexmask.long.word 0x54 0.--15. 1. "ZQ_CALLATCH_HIGH_THRESHOLD_F2,ZQ LATCH number of long counts until the high priority request is asserted for frequency copy 2." line.long 0x58 "DDRSS_CTL_240" hexmask.long.word 0x58 16.--31. 1. "ZQ_CALSTART_TIMEOUT_F2,ZQ START number of long counts until the timeout is asserted for frequency copy 2." hexmask.long.word 0x58 0.--15. 1. "ZQ_CS_HIGH_THRESHOLD_F2,ZQ CS number of long counts until the high priority request is asserted for frequency copy 2." line.long 0x5C "DDRSS_CTL_241" hexmask.long.word 0x5C 16.--31. 1. "ZQ_CS_TIMEOUT_F2,ZQ CS number of long counts until the timeout is asserted for frequency copy 2." hexmask.long.word 0x5C 0.--15. 1. "ZQ_CALLATCH_TIMEOUT_F2,ZQ LATCH number of long counts until the timeout is asserted for frequency copy 2." line.long 0x60 "DDRSS_CTL_242" hexmask.long.word 0x60 19.--31. 1. "RESERVED" bitfld.long 0x60 16.--18. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x60 0.--15. 1. "ZQ_PROMOTE_THRESHOLD_F2,ZQ SW promotion number of long counts until the high priority request is asserted for frequency copy 2." line.long 0x64 "DDRSS_CTL_243" hexmask.long.word 0x64 16.--31. 1. "WATCHDOG_THRESHOLD_BUS_ARB_F0,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 0." hexmask.long.word 0x64 0.--15. 1. "WATCHDOG_THRESHOLD_TASK_ARB_F0,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 0." line.long 0x68 "DDRSS_CTL_244" hexmask.long.word 0x68 16.--31. 1. "WATCHDOG_THRESHOLD_SPLIT_F0,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 0." hexmask.long.word 0x68 0.--15. 1. "WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 0." line.long 0x6C "DDRSS_CTL_245" hexmask.long.word 0x6C 16.--31. 1. "WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 0." hexmask.long.word 0x6C 0.--15. 1. "WATCHDOG_THRESHOLD_STRATEGY_F0,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 0." line.long 0x70 "DDRSS_CTL_246" hexmask.long.word 0x70 16.--31. 1. "WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 0." hexmask.long.word 0x70 0.--15. 1. "WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 0." line.long 0x74 "DDRSS_CTL_247" hexmask.long.word 0x74 16.--31. 1. "WATCHDOG_THRESHOLD_BUS_ARB_F1,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 1." hexmask.long.word 0x74 0.--15. 1. "WATCHDOG_THRESHOLD_TASK_ARB_F1,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 1." line.long 0x78 "DDRSS_CTL_248" hexmask.long.word 0x78 16.--31. 1. "WATCHDOG_THRESHOLD_SPLIT_F1,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 1." hexmask.long.word 0x78 0.--15. 1. "WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 1." line.long 0x7C "DDRSS_CTL_249" hexmask.long.word 0x7C 16.--31. 1. "WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 1." hexmask.long.word 0x7C 0.--15. 1. "WATCHDOG_THRESHOLD_STRATEGY_F1,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 1." line.long 0x80 "DDRSS_CTL_250" hexmask.long.word 0x80 16.--31. 1. "WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 1." hexmask.long.word 0x80 0.--15. 1. "WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 1." line.long 0x84 "DDRSS_CTL_251" hexmask.long.word 0x84 16.--31. 1. "WATCHDOG_THRESHOLD_BUS_ARB_F2,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 2." hexmask.long.word 0x84 0.--15. 1. "WATCHDOG_THRESHOLD_TASK_ARB_F2,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 2." line.long 0x88 "DDRSS_CTL_252" hexmask.long.word 0x88 16.--31. 1. "WATCHDOG_THRESHOLD_SPLIT_F2,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 2." hexmask.long.word 0x88 0.--15. 1. "WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 2." line.long 0x8C "DDRSS_CTL_253" hexmask.long.word 0x8C 16.--31. 1. "WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 2." hexmask.long.word 0x8C 0.--15. 1. "WATCHDOG_THRESHOLD_STRATEGY_F2,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 2." line.long 0x90 "DDRSS_CTL_254" hexmask.long.word 0x90 16.--31. 1. "WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 2." hexmask.long.word 0x90 0.--15. 1. "WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2,When watchdog's counter reaches this threshold it will assert an error when using frequency copy 2." line.long 0x94 "DDRSS_CTL_255" hexmask.long.word 0x94 16.--31. 1. "RESERVED" hexmask.long.byte 0x94 8.--15. 1. "WATCHDOG_DIAGNOSTIC_MODE,Used to test watchdog timers or to force a failure." newline hexmask.long.byte 0x94 0.--7. 1. "WATCHDOG_RELOAD,Forces reload to assert on all watchdog timers effectively restarting all watchdog counters and clearing any existing watchdog error assertions." rgroup.long 0x400++0x3 line.long 0x0 "DDRSS_CTL_256" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "TIMEOUT_TIMER_LOG,Reflects which timers experienced a timeout error (or had an uncleared error) when the timeout interrupt fired." group.long 0x404++0x5B line.long 0x0 "DDRSS_CTL_257" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--27. 1. "ZQCL_F0,Number of cycles needed for a ZQCL command for frequency copy 0." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--11. 1. "ZQINIT_F0,Number of cycles needed for a ZQINIT command for frequency copy 0." line.long 0x4 "DDRSS_CTL_258" hexmask.long.byte 0x4 28.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--27. 1. "TZQCAL_F0,Holds the DRAM ZQCAL value for frequency copy 0 in cycles." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--11. 1. "ZQCS_F0,Number of cycles needed for a ZQCS command for frequency copy 0." line.long 0x8 "DDRSS_CTL_259" hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.word 0x8 8.--19. 1. "ZQINIT_F1,Number of cycles needed for a ZQINIT command for frequency copy 1." newline bitfld.long 0x8 7. "RESERVED" "0,1" hexmask.long.byte 0x8 0.--6. 1. "TZQLAT_F0,Holds the DRAM ZQLAT value for frequency copy 0 in cycles." line.long 0xC "DDRSS_CTL_260" hexmask.long.byte 0xC 28.--31. 1. "RESERVED" hexmask.long.word 0xC 16.--27. 1. "ZQCS_F1,Number of cycles needed for a ZQCS command for frequency copy 1." newline hexmask.long.byte 0xC 12.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--11. 1. "ZQCL_F1,Number of cycles needed for a ZQCL command for frequency copy 1." line.long 0x10 "DDRSS_CTL_261" hexmask.long.word 0x10 23.--31. 1. "RESERVED" hexmask.long.byte 0x10 16.--22. 1. "TZQLAT_F1,Holds the DRAM ZQLAT value for frequency copy 1 in cycles." newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--11. 1. "TZQCAL_F1,Holds the DRAM ZQCAL value for frequency copy 1 in cycles." line.long 0x14 "DDRSS_CTL_262" hexmask.long.byte 0x14 28.--31. 1. "RESERVED" hexmask.long.word 0x14 16.--27. 1. "ZQCL_F2,Number of cycles needed for a ZQCL command for frequency copy 2." newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED" hexmask.long.word 0x14 0.--11. 1. "ZQINIT_F2,Number of cycles needed for a ZQINIT command for frequency copy 2." line.long 0x18 "DDRSS_CTL_263" hexmask.long.byte 0x18 28.--31. 1. "RESERVED" hexmask.long.word 0x18 16.--27. 1. "TZQCAL_F2,Holds the DRAM ZQCAL value for frequency copy 2 in cycles." newline hexmask.long.byte 0x18 12.--15. 1. "RESERVED" hexmask.long.word 0x18 0.--11. 1. "ZQCS_F2,Number of cycles needed for a ZQCS command for frequency copy 2." line.long 0x1C "DDRSS_CTL_264" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" rbitfld.long 0x1C 24. "ZQ_REQ_PENDING,Indicates that a ZQ command is currently in progress or waiting to run." "0,1" newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED" hexmask.long.byte 0x1C 16.--19. 1. "ZQ_REQ,User request to initiate a ZQ calibration." newline hexmask.long.byte 0x1C 10.--15. 1. "RESERVED" bitfld.long 0x1C 8.--9. "ZQ_SW_REQ_START_LATCH_MAP,Specifies which chip selects will simultaneously receive a ZQ start or latch command once the ZQ_REQ parameter is written with a ZQ Start or ZQ Latch command." "0,1,2,3" newline bitfld.long 0x1C 7. "RESERVED" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "TZQLAT_F2,Holds the DRAM ZQLAT value for frequency copy 2 in cycles." line.long 0x20 "DDRSS_CTL_265" hexmask.long.byte 0x20 28.--31. 1. "RESERVED" hexmask.long.word 0x20 16.--27. 1. "ZQRESET_F1,Number of cycles needed for a ZQRESET command for frequency copy 1." newline hexmask.long.byte 0x20 12.--15. 1. "RESERVED" hexmask.long.word 0x20 0.--11. 1. "ZQRESET_F0,Number of cycles needed for a ZQRESET command for frequency copy 0." line.long 0x24 "DDRSS_CTL_266" hexmask.long.byte 0x24 25.--31. 1. "RESERVED" bitfld.long 0x24 24. "ZQCS_ROTATE,For non-LPDDR4 memories selects whether a ZQCS command will calibrate just one chip select or all chip selects." "0,1" newline hexmask.long.byte 0x24 17.--23. 1. "RESERVED" bitfld.long 0x24 16. "NO_ZQ_INIT,Disable ZQ operations during initialization." "0,1" newline hexmask.long.byte 0x24 12.--15. 1. "RESERVED" hexmask.long.word 0x24 0.--11. 1. "ZQRESET_F2,Number of cycles needed for a ZQRESET command for frequency copy 2." line.long 0x28 "DDRSS_CTL_267" hexmask.long.byte 0x28 26.--31. 1. "RESERVED" bitfld.long 0x28 24.--25. "ZQ_CAL_LATCH_MAP_1,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 1 of the ZQ LATCH initialization and periodic command sequences." "0,1,2,3" newline hexmask.long.byte 0x28 18.--23. 1. "RESERVED" bitfld.long 0x28 16.--17. "ZQ_CAL_START_MAP_1,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 1 of the ZQ START initialization and periodic command sequences." "0,1,2,3" newline hexmask.long.byte 0x28 10.--15. 1. "RESERVED" bitfld.long 0x28 8.--9. "ZQ_CAL_LATCH_MAP_0,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 0 of the ZQ LATCH initialization and periodic command sequences." "0,1,2,3" newline hexmask.long.byte 0x28 2.--7. 1. "RESERVED" bitfld.long 0x28 0.--1. "ZQ_CAL_START_MAP_0,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 0 of the ZQ START initialization and periodic command sequences." "0,1,2,3" line.long 0x2C "DDRSS_CTL_268" hexmask.long.byte 0x2C 27.--31. 1. "RESERVED" bitfld.long 0x2C 24.--26. "ROW_DIFF_1,Difference between number of address pins available and number being used for chip select 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 19.--23. 1. "RESERVED" bitfld.long 0x2C 16.--18. "ROW_DIFF_0,Difference between number of address pins available and number being used for chip select 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" bitfld.long 0x2C 8.--9. "BANK_DIFF_1,Encoded number of banks on the DRAM for chip select 1." "0,1,2,3" newline hexmask.long.byte 0x2C 2.--7. 1. "RESERVED" bitfld.long 0x2C 0.--1. "BANK_DIFF_0,Encoded number of banks on the DRAM for chip select 0." "0,1,2,3" line.long 0x30 "DDRSS_CTL_269" hexmask.long.word 0x30 16.--31. 1. "CS_VAL_LOWER_0,Lower bound address for chip select 0." hexmask.long.byte 0x30 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x30 8.--11. 1. "COL_DIFF_1,Difference between number of column pins available and number being used for chip select 1." hexmask.long.byte 0x30 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x30 0.--3. 1. "COL_DIFF_0,Difference between number of column pins available and number being used for chip select 0." line.long 0x34 "DDRSS_CTL_270" hexmask.long.word 0x34 19.--31. 1. "RESERVED" bitfld.long 0x34 16.--18. "ROW_START_VAL_0,Row start value for chip select 0." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x34 0.--15. 1. "CS_VAL_UPPER_0,Upper bound address for chip select 0." line.long 0x38 "DDRSS_CTL_271" hexmask.long.word 0x38 16.--31. 1. "CS_VAL_UPPER_1,Upper bound address for chip select 1." hexmask.long.word 0x38 0.--15. 1. "CS_VAL_LOWER_1,Lower bound address for chip select 1." line.long 0x3C "DDRSS_CTL_272" hexmask.long.word 0x3C 16.--31. 1. "CS_MSK_0,Mask applied to the address decode for chip select 0." hexmask.long.byte 0x3C 10.--15. 1. "RESERVED" newline bitfld.long 0x3C 8.--9. "CS_MAP_NON_POW2,Defines which chip selects are non-power-of-2 memory sizes." "0,1,2,3" hexmask.long.byte 0x3C 3.--7. 1. "RESERVED" newline bitfld.long 0x3C 0.--2. "ROW_START_VAL_1,Row start value for chip select 1." "0,1,2,3,4,5,6,7" line.long 0x40 "DDRSS_CTL_273" bitfld.long 0x40 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 24.--28. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x40 17.--23. 1. "RESERVED" bitfld.long 0x40 16. "CS_LOWER_ADDR_EN,Enables moving the CS field to lower in the address map." "0,1" newline hexmask.long.word 0x40 0.--15. 1. "CS_MSK_1,Mask applied to the address decode for chip select 1." line.long 0x44 "DDRSS_CTL_274" hexmask.long.byte 0x44 24.--31. 1. "COMMAND_AGE_COUNT,Initial value of individual command aging counters for command aging." hexmask.long.byte 0x44 16.--23. 1. "AGE_COUNT,Initial value of master aging-rate counter for command aging." newline bitfld.long 0x44 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 8.--12. 1. "APREBIT,Location of the auto pre-charge bit in the DRAM address." newline hexmask.long.byte 0x44 1.--7. 1. "RESERVED" bitfld.long 0x44 0. "RESERVED,Reserved" "0,1" line.long 0x48 "DDRSS_CTL_275" hexmask.long.byte 0x48 25.--31. 1. "RESERVED" bitfld.long 0x48 24. "PLACEMENT_EN,Enable placement logic for command queue." "0,1" newline hexmask.long.byte 0x48 17.--23. 1. "RESERVED" bitfld.long 0x48 16. "BANK_SPLIT_EN,Enable bank splitting as a rule for command queue placement." "0,1" newline hexmask.long.byte 0x48 9.--15. 1. "RESERVED" bitfld.long 0x48 8. "ADDR_COLLISION_MPM_DIS,Disable address collision detection extension using micro page mask for command queue placement and selection." "0,1" newline hexmask.long.byte 0x48 1.--7. 1. "RESERVED" bitfld.long 0x48 0. "ADDR_CMP_EN,Enable address collision detection as a rule for command queue placement." "0,1" line.long 0x4C "DDRSS_CTL_276" hexmask.long.byte 0x4C 25.--31. 1. "RESERVED" bitfld.long 0x4C 24. "CS_SAME_EN,Enable chip select grouping when read/write grouping as a rule for command queue placement." "0,1" newline hexmask.long.byte 0x4C 17.--23. 1. "RESERVED" bitfld.long 0x4C 16. "RW_SAME_PAGE_EN,Enable page grouping when read/write grouping as a rule for command queue placement." "0,1" newline hexmask.long.byte 0x4C 9.--15. 1. "RESERVED" bitfld.long 0x4C 8. "RW_SAME_EN,Enable read/write grouping as a rule for command queue placement." "0,1" newline hexmask.long.byte 0x4C 1.--7. 1. "RESERVED" bitfld.long 0x4C 0. "PRIORITY_EN,Enable priority as a rule for command queue placement." "0,1" line.long 0x50 "DDRSS_CTL_277" hexmask.long.byte 0x50 25.--31. 1. "RESERVED" bitfld.long 0x50 24. "SWAP_EN,Enable command swapping logic in execution unit." "0,1" newline bitfld.long 0x50 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x50 16.--20. 1. "NUM_Q_ENTRIES_ACT_DISABLE,Number of queue entries in which ACT requests will be disabled." newline hexmask.long.byte 0x50 10.--15. 1. "RESERVED" bitfld.long 0x50 8.--9. "DISABLE_RW_GROUP_W_BNK_CONFLICT,Disables placement to read/write group when grouping creates a bank collision." "0,1,2,3" newline hexmask.long.byte 0x50 1.--7. 1. "RESERVED" bitfld.long 0x50 0. "W2R_SPLIT_EN,Enable splitting of commands to the same chip select from a write to a read command as a rule for command queue placement." "0,1" line.long 0x54 "DDRSS_CTL_278" hexmask.long.byte 0x54 25.--31. 1. "RESERVED" bitfld.long 0x54 24. "REDUC,Enable the half datapath feature of the controller." "0,1" newline hexmask.long.byte 0x54 18.--23. 1. "RESERVED" bitfld.long 0x54 16.--17. "CS_MAP,Defines which chip selects are active." "0,1,2,3" newline hexmask.long.byte 0x54 10.--15. 1. "RESERVED" bitfld.long 0x54 8.--9. "INHIBIT_DRAM_CMD,Inhibit command types from being executed from the command queue." "0,1,2,3" newline hexmask.long.byte 0x54 1.--7. 1. "RESERVED" bitfld.long 0x54 0. "DISABLE_RD_INTERLEAVE,Disable read data interleaving for commands from the same port regardless of the requestor ID." "0,1" line.long 0x58 "DDRSS_CTL_279" hexmask.long.word 0x58 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x58 0.--17. 1. "FAULT_FIFO_PROTECTION_EN,Enables fault fifo protection features." rgroup.long 0x460++0x3 line.long 0x0 "DDRSS_CTL_280" hexmask.long.word 0x0 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--17. 1. "FAULT_FIFO_PROTECTION_STATUS,Status of fault fifo protection modules." group.long 0x464++0x2F line.long 0x0 "DDRSS_CTL_281" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "WRITE_ADDR_CHAN_PARITY_EN,Enables parity checking on the AXI write command (address) channel." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--17. 1. "FAULT_FIFO_PROTECTION_INJECTION_EN,Triggers error injection for fault fifo protection modules." line.long 0x4 "DDRSS_CTL_282" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" bitfld.long 0x4 24. "READ_DATA_CHAN_PARITY_EN,Enables parity checking on the AXI read data channel." "0,1" newline hexmask.long.byte 0x4 17.--23. 1. "RESERVED" bitfld.long 0x4 16. "READ_ADDR_CHAN_PARITY_EN,Enables parity checking on the AXI read command (address) channel." "0,1" newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "WRITE_RESP_CHAN_PARITY_EN,Enables parity checking on the AXI write response channel." "0,1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" bitfld.long 0x4 0.--1. "WRITE_DATA_CHAN_PARITY_EN,Enables parity checking on the AXI write data channel." "0,1,2,3" line.long 0x8 "DDRSS_CTL_283" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "READ_PARITY_ERR_RRESP_EN,Enables AXI ERROR responses on the AXI read data channel for any parity errors that occurred on the read command (address) channel." "0,1" newline hexmask.long.byte 0x8 17.--23. 1. "RESERVED" bitfld.long 0x8 16. "WRITE_PARITY_ERR_BRESP_EN,Enables AXI ERROR responses on the AXI write response channel for any parity errors that occured on either the write command (address) or write data channels." "0,1" newline hexmask.long.byte 0x8 9.--15. 1. "RESERVED" bitfld.long 0x8 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x8 1.--7. 1. "RESERVED" bitfld.long 0x8 0. "RESERVED,Reserved" "0,1" line.long 0xC "DDRSS_CTL_284" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "READ_ADDR_CHAN_TRIGGER_PARITY_EN,Triggers a parity error on the AXI read command (address) channel." "0,1" newline hexmask.long.byte 0xC 17.--23. 1. "RESERVED" bitfld.long 0xC 16. "WRITE_RESP_CHAN_CORRUPT_PARITY_EN,Corrupts the parity on the AXI write response channel." "0,1" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" bitfld.long 0xC 8. "WRITE_DATA_CHAN_TRIGGER_PARITY_EN,Triggers a parity error on the AXI write data channel." "0,1" newline hexmask.long.byte 0xC 1.--7. 1. "RESERVED" bitfld.long 0xC 0. "WRITE_ADDR_CHAN_TRIGGER_PARITY_EN,Triggers a parity error on the AXI write command (address) channel." "0,1" line.long 0x10 "DDRSS_CTL_285" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" bitfld.long 0x10 24. "ENHANCED_PARITY_PROTECTION_EN,Enable byte parity implementation on addr/data channels." "0,1" newline hexmask.long.byte 0x10 17.--23. 1. "RESERVED" bitfld.long 0x10 16. "WRITE_PARITY_ERR_CORRUPT_ECC_EN,Enables corruption of ECC code if an AXI parity error is detected." "0,1" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "ECC_AXI_ERROR_RESPONSE_INHIBIT,Inhibits AXI ERROR responses when an ECC error occurs on the AXI read data channel." "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "READ_DATA_CHAN_CORRUPT_PARITY_EN,Corrupts the parity on the AXI read data channel." "0,1" line.long 0x14 "DDRSS_CTL_286" hexmask.long.byte 0x14 28.--31. 1. "RESERVED" hexmask.long.byte 0x14 24.--27. 1. "DEVICE2_BYTE0_CS0,Defines the byte location of byte0 in the memory datapath for device 2 on chip 0." newline hexmask.long.byte 0x14 20.--23. 1. "RESERVED" hexmask.long.byte 0x14 16.--19. 1. "DEVICE1_BYTE0_CS0,Defines the byte location of byte0 in the memory datapath for device 1 on chip 0." newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED" hexmask.long.byte 0x14 8.--11. 1. "DEVICE0_BYTE0_CS0,Defines the byte location of byte0 in the memory datapath for device 0 on chip 0." newline hexmask.long.byte 0x14 3.--7. 1. "RESERVED" bitfld.long 0x14 0.--2. "MEMDATA_RATIO_0,Defines the ratio of the DRAM device size on chip select 0 to the memory data width." "0,1,2,3,4,5,6,7" line.long 0x18 "DDRSS_CTL_287" hexmask.long.byte 0x18 28.--31. 1. "RESERVED" hexmask.long.byte 0x18 24.--27. 1. "DEVICE1_BYTE0_CS1,Defines the byte location of byte0 in the memory datapath for device 1 on chip 1." newline hexmask.long.byte 0x18 20.--23. 1. "RESERVED" hexmask.long.byte 0x18 16.--19. 1. "DEVICE0_BYTE0_CS1,Defines the byte location of byte0 in the memory datapath for device 0 on chip 1." newline hexmask.long.byte 0x18 11.--15. 1. "RESERVED" bitfld.long 0x18 8.--10. "MEMDATA_RATIO_1,Defines the ratio of the DRAM device size on chip select 1 to the memory data width." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 4.--7. 1. "RESERVED" hexmask.long.byte 0x18 0.--3. 1. "DEVICE3_BYTE0_CS0,Defines the byte location of byte0 in the memory datapath for device 3 on chip 0." line.long 0x1C "DDRSS_CTL_288" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" bitfld.long 0x1C 24. "IN_ORDER_ACCEPT,Forces the controller to accept commands in the order in which they are placed in the command queue." "0,1" newline bitfld.long 0x1C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 16.--20. 1. "Q_FULLNESS,Quantity that determines command queue almost full assertion(q_almost_full)." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED" hexmask.long.byte 0x1C 8.--11. 1. "DEVICE3_BYTE0_CS1,Defines the byte location of byte0 in the memory datapath for device 3 on chip 1." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED" hexmask.long.byte 0x1C 0.--3. 1. "DEVICE2_BYTE0_CS1,Defines the byte location of byte0 in the memory datapath for device 2 on chip 1." line.long 0x20 "DDRSS_CTL_289" hexmask.long.byte 0x20 25.--31. 1. "RESERVED" bitfld.long 0x20 24. "CTRLUPD_REQ_PER_AREF_EN,Enable an automatic controller-initiated update (dfi_ctrlupd_req) after every refresh." "0,1" newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" bitfld.long 0x20 16. "CTRLUPD_REQ,Assert the DFI controller-initiated update request signal dfi_ctrlupd_req." "0,1" newline hexmask.long.byte 0x20 9.--15. 1. "RESERVED" rbitfld.long 0x20 8. "CONTROLLER_BUSY,Indicator that the controller is processing a command." "0,1" newline hexmask.long.byte 0x20 2.--7. 1. "RESERVED" bitfld.long 0x20 0.--1. "WR_ORDER_REQ,Determines if the controller can re-order write commands from the same source ID and/or the same port." "0,1,2,3" line.long 0x24 "DDRSS_CTL_290" hexmask.long.byte 0x24 26.--31. 1. "RESERVED" bitfld.long 0x24 24.--25. "PREAMBLE_SUPPORT_F2,Selection of one or two cycle preamble for read and write burst transfers for frequency copy 2." "0,1,2,3" newline hexmask.long.byte 0x24 18.--23. 1. "RESERVED" bitfld.long 0x24 16.--17. "PREAMBLE_SUPPORT_F1,Selection of one or two cycle preamble for read and write burst transfers for frequency copy 1." "0,1,2,3" newline hexmask.long.byte 0x24 10.--15. 1. "RESERVED" bitfld.long 0x24 8.--9. "PREAMBLE_SUPPORT_F0,Selection of one or two cycle preamble for read and write burst transfers for frequency copy 0." "0,1,2,3" newline hexmask.long.byte 0x24 1.--7. 1. "RESERVED" bitfld.long 0x24 0. "CTRLUPD_AREF_HP_ENABLE,Enable an automatic controller-initiated update (dfi_ctrlupd_req) after every high priority refresh when executing as a subtask request." "0,1" line.long 0x28 "DDRSS_CTL_291" bitfld.long 0x28 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 24.--28. 1. "DFI_ERROR,Indicates that the DFI error flag has been asserted." newline hexmask.long.byte 0x28 17.--23. 1. "RESERVED" bitfld.long 0x28 16. "RD_DBI_EN,Enables controller support of DRAM DBI feature for read data with DDR4 devices." "0,1" newline hexmask.long.byte 0x28 9.--15. 1. "RESERVED" bitfld.long 0x28 8. "WR_DBI_EN,Enables controller support of DRAM DBI feature for write data with DDR4 devices." "0,1" newline hexmask.long.byte 0x28 1.--7. 1. "RESERVED" bitfld.long 0x28 0. "RD_PREAMBLE_TRAINING_EN,Enable read preamble training during gate training." "0,1" line.long 0x2C "DDRSS_CTL_292" hexmask.long.byte 0x2C 25.--31. 1. "RESERVED" bitfld.long 0x2C 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x2C 20.--23. 1. "RESERVED" hexmask.long.tbyte 0x2C 0.--19. 1. "DFI_ERROR_INFO,Holds the encoded DFI error type associated with the DFI_ERROR parameter assertion." rgroup.long 0x494++0x7 line.long 0x0 "DDRSS_CTL_293" hexmask.long 0x0 0.--31. 1. "INT_STATUS_0,Status of interrupt features in the controller." line.long 0x4 "DDRSS_CTL_294" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--12. 1. "INT_STATUS_1,Status of interrupt features in the controller." wgroup.long 0x49C++0x7 line.long 0x0 "DDRSS_CTL_295" hexmask.long 0x0 0.--31. 1. "INT_ACK_0,Clear mask of the INT_STATUS parameter." line.long 0x4 "DDRSS_CTL_296" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--11. 1. "INT_ACK_1,Clear mask of the INT_STATUS parameter." group.long 0x4A4++0x7 line.long 0x0 "DDRSS_CTL_297" hexmask.long 0x0 0.--31. 1. "INT_MASK_0,Mask for the controller_int signal from the INT_STATUS parameter." line.long 0x4 "DDRSS_CTL_298" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--12. 1. "INT_MASK_1,Mask for the controller_int signal from the INT_STATUS parameter." rgroup.long 0x4AC++0x37 line.long 0x0 "DDRSS_CTL_299" hexmask.long 0x0 0.--31. 1. "OUT_OF_RANGE_ADDR_0,Address of command that caused an out-of-range interrupt." line.long 0x4 "DDRSS_CTL_300" bitfld.long 0x4 31. "RESERVED" "0,1" hexmask.long.byte 0x4 24.--30. 1. "OUT_OF_RANGE_TYPE,Type of command that caused an out-of-range interrupt." newline hexmask.long.byte 0x4 20.--23. 1. "RESERVED" hexmask.long.word 0x4 8.--19. 1. "OUT_OF_RANGE_LENGTH,Length of command that caused an out-of-range interrupt." newline hexmask.long.byte 0x4 3.--7. 1. "RESERVED" bitfld.long 0x4 0.--2. "OUT_OF_RANGE_ADDR_1,Address of command that caused an out-of-range interrupt." "0,1,2,3,4,5,6,7" line.long 0x8 "DDRSS_CTL_301" hexmask.long 0x8 6.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--5. 1. "OUT_OF_RANGE_SOURCE_ID,Source ID of command that caused an out-of-range interrupt." line.long 0xC "DDRSS_CTL_302" hexmask.long 0xC 0.--31. 1. "BIST_EXP_DATA_0,Expected data on BIST error." line.long 0x10 "DDRSS_CTL_303" hexmask.long 0x10 0.--31. 1. "BIST_EXP_DATA_1,Expected data on BIST error." line.long 0x14 "DDRSS_CTL_304" hexmask.long 0x14 0.--31. 1. "BIST_EXP_DATA_2,Expected data on BIST error." line.long 0x18 "DDRSS_CTL_305" hexmask.long 0x18 0.--31. 1. "BIST_EXP_DATA_3,Expected data on BIST error." line.long 0x1C "DDRSS_CTL_306" hexmask.long 0x1C 0.--31. 1. "BIST_FAIL_DATA_0,Actual data on BIST error." line.long 0x20 "DDRSS_CTL_307" hexmask.long 0x20 0.--31. 1. "BIST_FAIL_DATA_1,Actual data on BIST error." line.long 0x24 "DDRSS_CTL_308" hexmask.long 0x24 0.--31. 1. "BIST_FAIL_DATA_2,Actual data on BIST error." line.long 0x28 "DDRSS_CTL_309" hexmask.long 0x28 0.--31. 1. "BIST_FAIL_DATA_3,Actual data on BIST error." line.long 0x2C "DDRSS_CTL_310" hexmask.long 0x2C 0.--31. 1. "BIST_FAIL_ADDR_0,Address of BIST error." line.long 0x30 "DDRSS_CTL_311" hexmask.long 0x30 3.--31. 1. "RESERVED" bitfld.long 0x30 0.--2. "BIST_FAIL_ADDR_1,Address of BIST error." "0,1,2,3,4,5,6,7" line.long 0x34 "DDRSS_CTL_312" hexmask.long 0x34 0.--31. 1. "PORT_CMD_ERROR_ADDR_0,Address of command that caused the PORT command error." group.long 0x4E4++0x107 line.long 0x0 "DDRSS_CTL_313" hexmask.long.byte 0x0 26.--31. 1. "RESERVED" bitfld.long 0x0 24.--25. "ODT_RD_MAP_CS0,Determines which chip(s) will have termination when a read occurs on chip select 0." "0,1,2,3" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED" rbitfld.long 0x0 16.--17. "PORT_CMD_ERROR_TYPE,Type of error and access type that caused the PORT command error." "0,1,2,3" newline bitfld.long 0x0 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "PORT_CMD_ERROR_ID,Source ID of command that caused the PORT command error." newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" rbitfld.long 0x0 0.--2. "PORT_CMD_ERROR_ADDR_1,Address of command that caused the PORT command error." "0,1,2,3,4,5,6,7" line.long 0x4 "DDRSS_CTL_314" hexmask.long.byte 0x4 24.--31. 1. "TODTL_2CMD_F0,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command." hexmask.long.byte 0x4 18.--23. 1. "RESERVED" newline bitfld.long 0x4 16.--17. "ODT_WR_MAP_CS1,Determines which chip(s) will have termination when a write occurs on chip select 1." "0,1,2,3" hexmask.long.byte 0x4 10.--15. 1. "RESERVED" newline bitfld.long 0x4 8.--9. "ODT_RD_MAP_CS1,Determines which chip(s) will have termination when a read occurs on chip select 1." "0,1,2,3" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 0.--1. "ODT_WR_MAP_CS0,Determines which chip(s) will have termination when a write occurs on chip select 0." "0,1,2,3" line.long 0x8 "DDRSS_CTL_315" hexmask.long.byte 0x8 28.--31. 1. "RESERVED" hexmask.long.byte 0x8 24.--27. 1. "TODTH_WR_F1,Defines the DRAM minimum ODT high time after an ODT assertion for a write command." newline hexmask.long.byte 0x8 16.--23. 1. "TODTL_2CMD_F1,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command." hexmask.long.byte 0x8 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x8 8.--11. 1. "TODTH_RD_F0,Defines the DRAM minimum ODT high time after an ODT assertion for a read command." hexmask.long.byte 0x8 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x8 0.--3. 1. "TODTH_WR_F0,Defines the DRAM minimum ODT high time after an ODT assertion for a write command." line.long 0xC "DDRSS_CTL_316" hexmask.long.byte 0xC 28.--31. 1. "RESERVED" hexmask.long.byte 0xC 24.--27. 1. "TODTH_RD_F2,Defines the DRAM minimum ODT high time after an ODT assertion for a read command." newline hexmask.long.byte 0xC 20.--23. 1. "RESERVED" hexmask.long.byte 0xC 16.--19. 1. "TODTH_WR_F2,Defines the DRAM minimum ODT high time after an ODT assertion for a write command." newline hexmask.long.byte 0xC 8.--15. 1. "TODTL_2CMD_F2,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command." hexmask.long.byte 0xC 4.--7. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--3. 1. "TODTH_RD_F1,Defines the DRAM minimum ODT high time after an ODT assertion for a read command." line.long 0x10 "DDRSS_CTL_317" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" bitfld.long 0x10 24. "EN_ODT_ASSERT_EXCEPT_RD,Enable controller to assert ODT at all times except during reads." "0,1" newline hexmask.long.byte 0x10 17.--23. 1. "RESERVED" bitfld.long 0x10 16. "ODT_EN_F2,Enable support of DRAM ODT." "0,1" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "ODT_EN_F1,Enable support of DRAM ODT." "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "ODT_EN_F0,Enable support of DRAM ODT." "0,1" line.long 0x14 "DDRSS_CTL_318" bitfld.long 0x14 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 24.--29. 1. "RD_TO_ODTH_F0,Defines the delay from a read command to ODT assertion." newline bitfld.long 0x14 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 16.--21. 1. "WR_TO_ODTH_F2,Defines the delay from a write command to ODT assertion." newline bitfld.long 0x14 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 8.--13. 1. "WR_TO_ODTH_F1,Defines the delay from a write command to ODT assertion." newline bitfld.long 0x14 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 0.--5. 1. "WR_TO_ODTH_F0,Defines the delay from a write command to ODT assertion." line.long 0x18 "DDRSS_CTL_319" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "RW2MRW_DLY_F1,Additional delay to insert between read or write and mode_reg_write." newline bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 16.--20. 1. "RW2MRW_DLY_F0,Additional delay to insert between read or write and mode_reg_write." newline bitfld.long 0x18 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x18 8.--13. 1. "RD_TO_ODTH_F2,Defines the delay from a read command to ODT assertion." newline bitfld.long 0x18 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x18 0.--5. 1. "RD_TO_ODTH_F1,Defines the delay from a read command to ODT assertion." line.long 0x1C "DDRSS_CTL_320" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "W2R_DIFFCS_DLY_F0,Additional delay to insert between writes and reads to different chip selects." newline bitfld.long 0x1C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 16.--20. 1. "R2W_DIFFCS_DLY_F0,Additional delay to insert between reads and writes to different chip selects." newline bitfld.long 0x1C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--12. 1. "R2R_DIFFCS_DLY_F0,Additional delay to insert between reads to different chip selects." newline bitfld.long 0x1C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--4. 1. "RW2MRW_DLY_F2,Additional delay to insert between read or write and mode_reg_write." line.long 0x20 "DDRSS_CTL_321" bitfld.long 0x20 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 24.--28. 1. "W2R_DIFFCS_DLY_F1,Additional delay to insert between writes and reads to different chip selects." newline bitfld.long 0x20 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 16.--20. 1. "R2W_DIFFCS_DLY_F1,Additional delay to insert between reads and writes to different chip selects." newline bitfld.long 0x20 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 8.--12. 1. "R2R_DIFFCS_DLY_F1,Additional delay to insert between reads to different chip selects." newline bitfld.long 0x20 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 0.--4. 1. "W2W_DIFFCS_DLY_F0,Additional delay to insert between writes to different chip selects." line.long 0x24 "DDRSS_CTL_322" bitfld.long 0x24 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 24.--28. 1. "W2R_DIFFCS_DLY_F2,Additional delay to insert between writes and reads to different chip selects." newline bitfld.long 0x24 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 16.--20. 1. "R2W_DIFFCS_DLY_F2,Additional delay to insert between reads and writes to different chip selects." newline bitfld.long 0x24 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 8.--12. 1. "R2R_DIFFCS_DLY_F2,Additional delay to insert between reads to different chip selects." newline bitfld.long 0x24 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 0.--4. 1. "W2W_DIFFCS_DLY_F1,Additional delay to insert between writes to different chip selects." line.long 0x28 "DDRSS_CTL_323" bitfld.long 0x28 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 24.--28. 1. "R2W_SAMECS_DLY_F1,Additional delay to insert between reads and writes to the same chip select." newline bitfld.long 0x28 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 16.--20. 1. "R2W_SAMECS_DLY_F0,Additional delay to insert between reads and writes to the same chip select." newline bitfld.long 0x28 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 8.--12. 1. "R2R_SAMECS_DLY,Additional delay to insert between two reads to the same chip select." newline bitfld.long 0x28 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--4. 1. "W2W_DIFFCS_DLY_F2,Additional delay to insert between writes to different chip selects." line.long 0x2C "DDRSS_CTL_324" hexmask.long.byte 0x2C 28.--31. 1. "RESERVED" hexmask.long.byte 0x2C 24.--27. 1. "TDQSCK_MAX_F0,Additional delay needed for tDQSCK." newline bitfld.long 0x2C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 16.--20. 1. "W2W_SAMECS_DLY,Additional delay to insert between two writes to the same chip select." newline bitfld.long 0x2C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 8.--12. 1. "W2R_SAMECS_DLY,Additional delay to insert between writes and reads to the same chip select." newline bitfld.long 0x2C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 0.--4. 1. "R2W_SAMECS_DLY_F2,Additional delay to insert between reads and writes to the same chip select." line.long 0x30 "DDRSS_CTL_325" hexmask.long.byte 0x30 28.--31. 1. "RESERVED" hexmask.long.byte 0x30 24.--27. 1. "TDQSCK_MAX_F2,Additional delay needed for tDQSCK." newline hexmask.long.byte 0x30 19.--23. 1. "RESERVED" bitfld.long 0x30 16.--18. "TDQSCK_MIN_F1,Additional delay needed for tDQSCK." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x30 12.--15. 1. "RESERVED" hexmask.long.byte 0x30 8.--11. 1. "TDQSCK_MAX_F1,Additional delay needed for tDQSCK." newline hexmask.long.byte 0x30 3.--7. 1. "RESERVED" bitfld.long 0x30 0.--2. "TDQSCK_MIN_F0,Additional delay needed for tDQSCK." "0,1,2,3,4,5,6,7" line.long 0x34 "DDRSS_CTL_326" hexmask.long.byte 0x34 25.--31. 1. "RESERVED" bitfld.long 0x34 24. "SWLVL_START,User request to initiate software leveling of type in the SW_LEVELING_MODE parameter." "0,1" newline hexmask.long.byte 0x34 17.--23. 1. "RESERVED" bitfld.long 0x34 16. "SWLVL_LOAD,User request to load delays and execute software leveling." "0,1" newline hexmask.long.byte 0x34 11.--15. 1. "RESERVED" bitfld.long 0x34 8.--10. "SW_LEVELING_MODE,Defines the leveling operation for software leveling." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x34 3.--7. 1. "RESERVED" bitfld.long 0x34 0.--2. "TDQSCK_MIN_F2,Additional delay needed for tDQSCK." "0,1,2,3,4,5,6,7" line.long 0x38 "DDRSS_CTL_327" hexmask.long.byte 0x38 25.--31. 1. "RESERVED" rbitfld.long 0x38 24. "SWLVL_RESP_1,Leveling response for data slice 1." "0,1" newline hexmask.long.byte 0x38 17.--23. 1. "RESERVED" rbitfld.long 0x38 16. "SWLVL_RESP_0,Leveling response for data slice 0." "0,1" newline hexmask.long.byte 0x38 9.--15. 1. "RESERVED" rbitfld.long 0x38 8. "SWLVL_OP_DONE,Signals that software leveling is currently in progress." "0,1" newline hexmask.long.byte 0x38 1.--7. 1. "RESERVED" bitfld.long 0x38 0. "SWLVL_EXIT,User request to exit software leveling." "0,1" line.long 0x3C "DDRSS_CTL_328" hexmask.long.byte 0x3C 25.--31. 1. "RESERVED" bitfld.long 0x3C 24. "WRLVL_REQ,User request to initiate write leveling." "0,1" newline hexmask.long.byte 0x3C 17.--23. 1. "RESERVED" bitfld.long 0x3C 16. "PHYUPD_APPEND_EN,Specifies if a PHY update will be run prior to completing a training sequence." "0,1" newline hexmask.long.byte 0x3C 9.--15. 1. "RESERVED" rbitfld.long 0x3C 8. "SWLVL_RESP_3,Leveling response for data slice 3." "0,1" newline hexmask.long.byte 0x3C 1.--7. 1. "RESERVED" rbitfld.long 0x3C 0. "SWLVL_RESP_2,Leveling response for data slice 2." "0,1" line.long 0x40 "DDRSS_CTL_329" hexmask.long.byte 0x40 25.--31. 1. "RESERVED" bitfld.long 0x40 24. "WRLVL_EN,Enable the MC write leveling module." "0,1" newline bitfld.long 0x40 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x40 16.--21. 1. "WLMRD,Delay from issuing MRS to first write leveling strobe." newline bitfld.long 0x40 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x40 8.--13. 1. "WLDQSEN,Delay from issuing MRS to first DQS strobe for write leveling." newline hexmask.long.byte 0x40 1.--7. 1. "RESERVED" bitfld.long 0x40 0. "WRLVL_CS,Specifies the target chip select for the write leveling operation initiated through the WRLVL_REQ parameter." "0,1" line.long 0x44 "DDRSS_CTL_330" hexmask.long.byte 0x44 28.--31. 1. "RESERVED" hexmask.long.byte 0x44 24.--27. 1. "WRLVL_RESP_MASK,Mask for the dfi_wrlvl_resp signal during write leveling." newline hexmask.long.byte 0x44 17.--23. 1. "RESERVED" bitfld.long 0x44 16. "WRLVL_ON_SREF_EXIT,Enables automatic write leveling on a self-refresh exit." "0,1" newline hexmask.long.byte 0x44 9.--15. 1. "RESERVED" bitfld.long 0x44 8. "WRLVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during write leveling." "0,1" newline hexmask.long.byte 0x44 1.--7. 1. "RESERVED" bitfld.long 0x44 0. "DFI_PHY_WRLVL_MODE,Specifies the PHY support for DFI write leveling." "0,1" line.long 0x48 "DDRSS_CTL_331" hexmask.long.byte 0x48 27.--31. 1. "RESERVED" rbitfld.long 0x48 24.--26. "WRLVL_ERROR_STATUS,Holds the error associated with the write level error interrupt." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x48 18.--23. 1. "RESERVED" bitfld.long 0x48 16.--17. "WRLVL_CS_MAP,Defines the chip select map for write leveling operations." "0,1,2,3" newline hexmask.long.byte 0x48 9.--15. 1. "RESERVED" bitfld.long 0x48 8. "WRLVL_ROTATE,Enables rotational CS for interval write leveling." "0,1" newline hexmask.long.byte 0x48 1.--7. 1. "RESERVED" bitfld.long 0x48 0. "WRLVL_AREF_EN,Enables refreshes and other non-data commands to execute in the middle of write leveling." "0,1" line.long 0x4C "DDRSS_CTL_332" hexmask.long.word 0x4C 16.--31. 1. "WRLVL_HIGH_THRESHOLD_F0,Write leveling high threshold number of long counts until the high priority request is asserted." hexmask.long.word 0x4C 0.--15. 1. "WRLVL_NORM_THRESHOLD_F0,Write leveling normal threshold number of long counts until the normal priority request is asserted." line.long 0x50 "DDRSS_CTL_333" hexmask.long.word 0x50 16.--31. 1. "WRLVL_SW_PROMOTE_THRESHOLD_F0,Write leveling promotion number of long counts until the high priority request is asserted." hexmask.long.word 0x50 0.--15. 1. "WRLVL_TIMEOUT_F0,Write leveling timeout number of long counts until the timeout is asserted." line.long 0x54 "DDRSS_CTL_334" hexmask.long.word 0x54 16.--31. 1. "WRLVL_NORM_THRESHOLD_F1,Write leveling normal threshold number of long counts until the normal priority request is asserted." hexmask.long.word 0x54 0.--15. 1. "WRLVL_DFI_PROMOTE_THRESHOLD_F0,Write leveling promotion number of long counts until the high priority request is asserted." line.long 0x58 "DDRSS_CTL_335" hexmask.long.word 0x58 16.--31. 1. "WRLVL_TIMEOUT_F1,Write leveling timeout number of long counts until the timeout is asserted." hexmask.long.word 0x58 0.--15. 1. "WRLVL_HIGH_THRESHOLD_F1,Write leveling high threshold number of long counts until the high priority request is asserted." line.long 0x5C "DDRSS_CTL_336" hexmask.long.word 0x5C 16.--31. 1. "WRLVL_DFI_PROMOTE_THRESHOLD_F1,Write leveling promotion number of long counts until the high priority request is asserted." hexmask.long.word 0x5C 0.--15. 1. "WRLVL_SW_PROMOTE_THRESHOLD_F1,Write leveling promotion number of long counts until the high priority request is asserted." line.long 0x60 "DDRSS_CTL_337" hexmask.long.word 0x60 16.--31. 1. "WRLVL_HIGH_THRESHOLD_F2,Write leveling high threshold number of long counts until the high priority request is asserted." hexmask.long.word 0x60 0.--15. 1. "WRLVL_NORM_THRESHOLD_F2,Write leveling normal threshold number of long counts until the normal priority request is asserted." line.long 0x64 "DDRSS_CTL_338" hexmask.long.word 0x64 16.--31. 1. "WRLVL_SW_PROMOTE_THRESHOLD_F2,Write leveling promotion number of long counts until the high priority request is asserted." hexmask.long.word 0x64 0.--15. 1. "WRLVL_TIMEOUT_F2,Write leveling timeout number of long counts until the timeout is asserted." line.long 0x68 "DDRSS_CTL_339" hexmask.long.byte 0x68 25.--31. 1. "RESERVED" bitfld.long 0x68 24. "RDLVL_GATE_REQ,User request to initiate gate training." "0,1" newline hexmask.long.byte 0x68 17.--23. 1. "RESERVED" bitfld.long 0x68 16. "RDLVL_REQ,User request to initiate data eye training." "0,1" newline hexmask.long.word 0x68 0.--15. 1. "WRLVL_DFI_PROMOTE_THRESHOLD_F2,Write leveling promotion number of long counts until the high priority request is asserted." line.long 0x6C "DDRSS_CTL_340" hexmask.long.byte 0x6C 25.--31. 1. "RESERVED" bitfld.long 0x6C 24. "DFI_PHY_RDLVL_MODE,Specifies the PHY support for DFI data eye training." "0,1" newline hexmask.long.byte 0x6C 20.--23. 1. "RESERVED" hexmask.long.byte 0x6C 16.--19. 1. "RDLVL_GATE_SEQ_EN,Specifies the pattern format and MPR for gate training." newline hexmask.long.byte 0x6C 12.--15. 1. "RESERVED" hexmask.long.byte 0x6C 8.--11. 1. "RDLVL_SEQ_EN,Specifies the pattern format and MPR for data eye training." newline hexmask.long.byte 0x6C 1.--7. 1. "RESERVED" bitfld.long 0x6C 0. "RDLVL_CS,Specifies the target chip select for the data eye training operation initiated through the RDLVL_REQ parameter or the gate training operation initiated through the RDLVL_GATE_REQ parameter." "0,1" line.long 0x70 "DDRSS_CTL_341" hexmask.long.byte 0x70 25.--31. 1. "RESERVED" bitfld.long 0x70 24. "RDLVL_GATE_PERIODIC,Enables the use of the dfi_lvl_periodic signal during gate training." "0,1" newline hexmask.long.byte 0x70 17.--23. 1. "RESERVED" bitfld.long 0x70 16. "RDLVL_ON_SREF_EXIT,Enables automatic data eye training on a self-refresh exit." "0,1" newline hexmask.long.byte 0x70 9.--15. 1. "RESERVED" bitfld.long 0x70 8. "RDLVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during data eye training." "0,1" newline hexmask.long.byte 0x70 1.--7. 1. "RESERVED" bitfld.long 0x70 0. "DFI_PHY_RDLVL_GATE_MODE,Specifies the PHY support for DFI gate training." "0,1" line.long 0x74 "DDRSS_CTL_342" hexmask.long.byte 0x74 25.--31. 1. "RESERVED" bitfld.long 0x74 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x74 17.--23. 1. "RESERVED" bitfld.long 0x74 16. "RDLVL_GATE_AREF_EN,Enables refreshes and other non-data commands to execute in the middle of gate training." "0,1" newline hexmask.long.byte 0x74 9.--15. 1. "RESERVED" bitfld.long 0x74 8. "RDLVL_AREF_EN,Enables refreshes and other non-data commands to execute in the middle of data eye training." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RESERVED" bitfld.long 0x74 0. "RDLVL_GATE_ON_SREF_EXIT,Enables automatic gate training on a self-refresh exit." "0,1" line.long 0x78 "DDRSS_CTL_343" hexmask.long.byte 0x78 26.--31. 1. "RESERVED" bitfld.long 0x78 24.--25. "RDLVL_GATE_CS_MAP,Defines the chip select map for gate training operations." "0,1,2,3" newline hexmask.long.byte 0x78 18.--23. 1. "RESERVED" bitfld.long 0x78 16.--17. "RDLVL_CS_MAP,Defines the chip select map for data eye training operations." "0,1,2,3" newline hexmask.long.byte 0x78 9.--15. 1. "RESERVED" bitfld.long 0x78 8. "RDLVL_GATE_ROTATE,Enables rotational CS for interval gate training." "0,1" newline hexmask.long.byte 0x78 1.--7. 1. "RESERVED" bitfld.long 0x78 0. "RDLVL_ROTATE,Enables rotational CS for interval data eye training." "0,1" line.long 0x7C "DDRSS_CTL_344" hexmask.long.word 0x7C 16.--31. 1. "RDLVL_HIGH_THRESHOLD_F0,Read leveling high threshold number of long counts until the high priority request is asserted." hexmask.long.word 0x7C 0.--15. 1. "RDLVL_NORM_THRESHOLD_F0,Read leveling normal threshold number of long counts until the normal priority request is asserted." line.long 0x80 "DDRSS_CTL_345" hexmask.long.word 0x80 16.--31. 1. "RDLVL_SW_PROMOTE_THRESHOLD_F0,Read leveling promotion number of long counts until the high priority request is asserted." hexmask.long.word 0x80 0.--15. 1. "RDLVL_TIMEOUT_F0,Read leveling timeout number of long counts until the timeout is asserted." line.long 0x84 "DDRSS_CTL_346" hexmask.long.word 0x84 16.--31. 1. "RDLVL_GATE_NORM_THRESHOLD_F0,Gate training normal threshold number of long counts until the normal priority request is asserted." hexmask.long.word 0x84 0.--15. 1. "RDLVL_DFI_PROMOTE_THRESHOLD_F0,Read leveling promotion number of long counts until the high priority request is asserted." line.long 0x88 "DDRSS_CTL_347" hexmask.long.word 0x88 16.--31. 1. "RDLVL_GATE_TIMEOUT_F0,Gate training timeout number of long counts until the timeout is asserted." hexmask.long.word 0x88 0.--15. 1. "RDLVL_GATE_HIGH_THRESHOLD_F0,Gate training high threshold number of long counts until the high priority request is asserted." line.long 0x8C "DDRSS_CTL_348" hexmask.long.word 0x8C 16.--31. 1. "RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0,Gate training promotion number of long counts until the high priority request is asserted." hexmask.long.word 0x8C 0.--15. 1. "RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0,Gate training promotion number of long counts until the high priority request is asserted." line.long 0x90 "DDRSS_CTL_349" hexmask.long.word 0x90 16.--31. 1. "RDLVL_HIGH_THRESHOLD_F1,Read leveling high threshold number of long counts until the high priority request is asserted." hexmask.long.word 0x90 0.--15. 1. "RDLVL_NORM_THRESHOLD_F1,Read leveling normal threshold number of long counts until the normal priority request is asserted." line.long 0x94 "DDRSS_CTL_350" hexmask.long.word 0x94 16.--31. 1. "RDLVL_SW_PROMOTE_THRESHOLD_F1,Read leveling promotion number of long counts until the high priority request is asserted." hexmask.long.word 0x94 0.--15. 1. "RDLVL_TIMEOUT_F1,Read leveling timeout number of long counts until the timeout is asserted." line.long 0x98 "DDRSS_CTL_351" hexmask.long.word 0x98 16.--31. 1. "RDLVL_GATE_NORM_THRESHOLD_F1,Gate training normal threshold number of long counts until the normal priority request is asserted." hexmask.long.word 0x98 0.--15. 1. "RDLVL_DFI_PROMOTE_THRESHOLD_F1,Read leveling promotion number of long counts until the high priority request is asserted." line.long 0x9C "DDRSS_CTL_352" hexmask.long.word 0x9C 16.--31. 1. "RDLVL_GATE_TIMEOUT_F1,Gate training timeout number of long counts until the timeout is asserted." hexmask.long.word 0x9C 0.--15. 1. "RDLVL_GATE_HIGH_THRESHOLD_F1,Gate training high threshold number of long counts until the high priority request is asserted." line.long 0xA0 "DDRSS_CTL_353" hexmask.long.word 0xA0 16.--31. 1. "RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1,Gate training promotion number of long counts until the high priority request is asserted." hexmask.long.word 0xA0 0.--15. 1. "RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1,Gate training promotion number of long counts until the high priority request is asserted." line.long 0xA4 "DDRSS_CTL_354" hexmask.long.word 0xA4 16.--31. 1. "RDLVL_HIGH_THRESHOLD_F2,Read leveling high threshold number of long counts until the high priority request is asserted." hexmask.long.word 0xA4 0.--15. 1. "RDLVL_NORM_THRESHOLD_F2,Read leveling normal threshold number of long counts until the normal priority request is asserted." line.long 0xA8 "DDRSS_CTL_355" hexmask.long.word 0xA8 16.--31. 1. "RDLVL_SW_PROMOTE_THRESHOLD_F2,Read leveling promotion number of long counts until the high priority request is asserted." hexmask.long.word 0xA8 0.--15. 1. "RDLVL_TIMEOUT_F2,Read leveling timeout number of long counts until the timeout is asserted." line.long 0xAC "DDRSS_CTL_356" hexmask.long.word 0xAC 16.--31. 1. "RDLVL_GATE_NORM_THRESHOLD_F2,Gate training normal threshold number of long counts until the normal priority request is asserted." hexmask.long.word 0xAC 0.--15. 1. "RDLVL_DFI_PROMOTE_THRESHOLD_F2,Read leveling promotion number of long counts until the high priority request is asserted." line.long 0xB0 "DDRSS_CTL_357" hexmask.long.word 0xB0 16.--31. 1. "RDLVL_GATE_TIMEOUT_F2,Gate training timeout number of long counts until the timeout is asserted." hexmask.long.word 0xB0 0.--15. 1. "RDLVL_GATE_HIGH_THRESHOLD_F2,Gate training high threshold number of long counts until the high priority request is asserted." line.long 0xB4 "DDRSS_CTL_358" hexmask.long.word 0xB4 16.--31. 1. "RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2,Gate training promotion number of long counts until the high priority request is asserted." hexmask.long.word 0xB4 0.--15. 1. "RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2,Gate training promotion number of long counts until the high priority request is asserted." line.long 0xB8 "DDRSS_CTL_359" hexmask.long.tbyte 0xB8 9.--31. 1. "RESERVED" bitfld.long 0xB8 8. "CALVL_CS,Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter." "0,1" newline hexmask.long.byte 0xB8 1.--7. 1. "RESERVED" bitfld.long 0xB8 0. "CALVL_REQ,User request to initiate CA training." "0,1" line.long 0xBC "DDRSS_CTL_360" hexmask.long.word 0xBC 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xBC 0.--19. 1. "CALVL_PAT_0,CA Training pattern 0 driven on the CA bus during a calibration command." line.long 0xC0 "DDRSS_CTL_361" hexmask.long.word 0xC0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xC0 0.--19. 1. "CALVL_BG_PAT_0,CA Training pattern 0 driven on the CA bus before and after a calibration command." line.long 0xC4 "DDRSS_CTL_362" hexmask.long.word 0xC4 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xC4 0.--19. 1. "CALVL_PAT_1,CA Training pattern 1 driven on the CA bus during a calibration command." line.long 0xC8 "DDRSS_CTL_363" hexmask.long.word 0xC8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xC8 0.--19. 1. "CALVL_BG_PAT_1,CA Training pattern 1 driven on the CA bus before and after a calibration command." line.long 0xCC "DDRSS_CTL_364" hexmask.long.word 0xCC 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xCC 0.--19. 1. "CALVL_PAT_2,CA Training pattern 2 driven on the CA bus during a calibration command." line.long 0xD0 "DDRSS_CTL_365" hexmask.long.word 0xD0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xD0 0.--19. 1. "CALVL_BG_PAT_2,CA Training pattern 2 driven on the CA bus before and after a calibration command." line.long 0xD4 "DDRSS_CTL_366" hexmask.long.word 0xD4 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xD4 0.--19. 1. "CALVL_PAT_3,CA Training pattern 3 driven on the CA bus during a calibration command." line.long 0xD8 "DDRSS_CTL_367" hexmask.long.byte 0xD8 25.--31. 1. "RESERVED" bitfld.long 0xD8 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xD8 20.--23. 1. "RESERVED" hexmask.long.tbyte 0xD8 0.--19. 1. "CALVL_BG_PAT_3,CA Training pattern 3 driven on the CA bus before and after a calibration command." line.long 0xDC "DDRSS_CTL_368" hexmask.long.byte 0xDC 25.--31. 1. "RESERVED" bitfld.long 0xDC 24. "CALVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during CA training." "0,1" newline hexmask.long.byte 0xDC 17.--23. 1. "RESERVED" bitfld.long 0xDC 16. "DFI_PHY_CALVL_MODE,Specifies the PHY support for DFI CA training." "0,1" newline hexmask.long.byte 0xDC 10.--15. 1. "RESERVED" bitfld.long 0xDC 8.--9. "CALVL_SEQ_EN,Specifies which CA training patterns will be used." "0,1,2,3" newline hexmask.long.byte 0xDC 4.--7. 1. "RESERVED" hexmask.long.byte 0xDC 0.--3. 1. "RESERVED,Reserved" line.long 0xE0 "DDRSS_CTL_369" hexmask.long.byte 0xE0 26.--31. 1. "RESERVED" bitfld.long 0xE0 24.--25. "CALVL_CS_MAP,Defines the chip select map for CA training operations." "0,1,2,3" newline hexmask.long.byte 0xE0 17.--23. 1. "RESERVED" bitfld.long 0xE0 16. "CALVL_ROTATE,Enables rotational CS for interval CA training." "0,1" newline hexmask.long.byte 0xE0 9.--15. 1. "RESERVED" bitfld.long 0xE0 8. "CALVL_AREF_EN,Enables refreshes and other non-data commands to execute in the middle of CA training." "0,1" newline hexmask.long.byte 0xE0 1.--7. 1. "RESERVED" bitfld.long 0xE0 0. "CALVL_ON_SREF_EXIT,Enables automatic CA training on a self-refresh exit." "0,1" line.long 0xE4 "DDRSS_CTL_370" hexmask.long.word 0xE4 16.--31. 1. "CALVL_HIGH_THRESHOLD_F0,CA training high threshold number of long counts until the high priority request is asserted." hexmask.long.word 0xE4 0.--15. 1. "CALVL_NORM_THRESHOLD_F0,CA training normal threshold number of long counts until the normal priority request is asserted." line.long 0xE8 "DDRSS_CTL_371" hexmask.long.word 0xE8 16.--31. 1. "CALVL_SW_PROMOTE_THRESHOLD_F0,CA training promotion number of long counts until the high priority request is asserted." hexmask.long.word 0xE8 0.--15. 1. "CALVL_TIMEOUT_F0,CA training timeout number of long counts until the timeout is asserted." line.long 0xEC "DDRSS_CTL_372" hexmask.long.word 0xEC 16.--31. 1. "CALVL_NORM_THRESHOLD_F1,CA training normal threshold number of long counts until the normal priority request is asserted." hexmask.long.word 0xEC 0.--15. 1. "CALVL_DFI_PROMOTE_THRESHOLD_F0,CA training promotion number of long counts until the high priority request is asserted." line.long 0xF0 "DDRSS_CTL_373" hexmask.long.word 0xF0 16.--31. 1. "CALVL_TIMEOUT_F1,CA training timeout number of long counts until the timeout is asserted." hexmask.long.word 0xF0 0.--15. 1. "CALVL_HIGH_THRESHOLD_F1,CA training high threshold number of long counts until the high priority request is asserted." line.long 0xF4 "DDRSS_CTL_374" hexmask.long.word 0xF4 16.--31. 1. "CALVL_DFI_PROMOTE_THRESHOLD_F1,CA training promotion number of long counts until the high priority request is asserted." hexmask.long.word 0xF4 0.--15. 1. "CALVL_SW_PROMOTE_THRESHOLD_F1,CA training promotion number of long counts until the high priority request is asserted." line.long 0xF8 "DDRSS_CTL_375" hexmask.long.word 0xF8 16.--31. 1. "CALVL_HIGH_THRESHOLD_F2,CA training high threshold number of long counts until the high priority request is asserted." hexmask.long.word 0xF8 0.--15. 1. "CALVL_NORM_THRESHOLD_F2,CA training normal threshold number of long counts until the normal priority request is asserted." line.long 0xFC "DDRSS_CTL_376" hexmask.long.word 0xFC 16.--31. 1. "CALVL_SW_PROMOTE_THRESHOLD_F2,CA training promotion number of long counts until the high priority request is asserted." hexmask.long.word 0xFC 0.--15. 1. "CALVL_TIMEOUT_F2,CA training timeout number of long counts until the timeout is asserted." line.long 0x100 "DDRSS_CTL_377" hexmask.long.byte 0x100 25.--31. 1. "RESERVED" bitfld.long 0x100 24. "AXI0_FIXED_PORT_PRIORITY_ENABLE,Defines the priority control for AXI port 0 as per-port or per-command." "0,1" newline hexmask.long.byte 0x100 17.--23. 1. "RESERVED" bitfld.long 0x100 16. "AXI0_ALL_STROBES_USED_ENABLE,Enables use of the AWALLSTRB signal for AXI port 0." "0,1" newline hexmask.long.word 0x100 0.--15. 1. "CALVL_DFI_PROMOTE_THRESHOLD_F2,CA training promotion number of long counts until the high priority request is asserted." line.long 0x104 "DDRSS_CTL_378" hexmask.long.tbyte 0x104 11.--31. 1. "RESERVED" bitfld.long 0x104 8.--10. "AXI0_W_PRIORITY,Priority of write commands from AXI port 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x104 3.--7. 1. "RESERVED" bitfld.long 0x104 0.--2. "AXI0_R_PRIORITY,Priority of read commands from AXI port 0." "0,1,2,3,4,5,6,7" rgroup.long 0x5EC++0x1B line.long 0x0 "DDRSS_CTL_379" hexmask.long 0x0 0.--31. 1. "PARITY_ERROR_ADDRESS_0,Address of the AXI command that resulted in the parity error." line.long 0x4 "DDRSS_CTL_380" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 16.--28. 1. "PARITY_ERROR_BUS_CHANNEL,Reports the AXI field that resulted in the parity error." newline bitfld.long 0x4 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "PARITY_ERROR_MASTER_ID,Port ID and Master ID of the AXI command that resulted in the parity error." newline hexmask.long.byte 0x4 3.--7. 1. "RESERVED" bitfld.long 0x4 0.--2. "PARITY_ERROR_ADDRESS_1,Address of the AXI command that resulted in the parity error." "0,1,2,3,4,5,6,7" line.long 0x8 "DDRSS_CTL_381" hexmask.long 0x8 0.--31. 1. "PARITY_ERROR_WRITE_DATA_0,Write data of the AXI command that resulted in the parity error." line.long 0xC "DDRSS_CTL_382" hexmask.long 0xC 0.--31. 1. "PARITY_ERROR_WRITE_DATA_1,Write data of the AXI command that resulted in the parity error." line.long 0x10 "DDRSS_CTL_383" hexmask.long 0x10 0.--31. 1. "PARITY_ERROR_WRITE_DATA_2,Write data of the AXI command that resulted in the parity error." line.long 0x14 "DDRSS_CTL_384" hexmask.long 0x14 0.--31. 1. "PARITY_ERROR_WRITE_DATA_3,Write data of the AXI command that resulted in the parity error." line.long 0x18 "DDRSS_CTL_385" hexmask.long.byte 0x18 25.--31. 1. "RESERVED" bitfld.long 0x18 24. "MEM_RST_VALID,Register access to mem_rst_valid signal." "0,1" newline hexmask.long.byte 0x18 18.--23. 1. "RESERVED" bitfld.long 0x18 16.--17. "CKE_STATUS,Register access to cke_status signal." "0,1,2,3" newline hexmask.long.word 0x18 0.--15. 1. "PARITY_ERROR_WRITE_DATA_PARITY_VECTOR,Write data parity vector associated with the AXI command that resulted in the parity error." group.long 0x608++0xB3 line.long 0x0 "DDRSS_CTL_386" bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long.byte 0x0 24.--30. 1. "TDFI_PHY_WRLAT,Holds the calculated DFI tPHY_WRLAT timing parameter (in DFI PHY clocks) the maximum cycles between a write command and a dfi_wrdata_en assertion." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_RST_ADJ_DLY,Minimum cycles after setting master delay in DLL until the DLL reset signal dll_rst_n may be asserted." hexmask.long.word 0x0 0.--15. 1. "DLL_RST_DELAY,Minimum cycles required for DLL reset signal dll_rst_n to be held." line.long 0x4 "DDRSS_CTL_387" bitfld.long 0x4 31. "RESERVED" "0,1" hexmask.long.byte 0x4 24.--30. 1. "TDFI_PHY_RDLAT_F2,Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks) the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion." newline bitfld.long 0x4 23. "RESERVED" "0,1" hexmask.long.byte 0x4 16.--22. 1. "TDFI_PHY_RDLAT_F1,Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks) the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion." newline bitfld.long 0x4 15. "RESERVED" "0,1" hexmask.long.byte 0x4 8.--14. 1. "TDFI_PHY_RDLAT_F0,Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks) the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion." newline bitfld.long 0x4 7. "RESERVED" "0,1" hexmask.long.byte 0x4 0.--6. 1. "UPDATE_ERROR_STATUS,Identifies the source of any DFI MC-initiated or PHY-initiated update errors." line.long 0x8 "DDRSS_CTL_388" hexmask.long.byte 0x8 24.--31. 1. "RESERVED" hexmask.long.byte 0x8 16.--23. 1. "TDFI_CTRLUPD_MIN,Defines the DFI tCTRLUPD_MIN timing parameter (in DFI clocks) the minimum cycles that dfi_ctrlupd_req must be asserted." newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" bitfld.long 0x8 8.--9. "DRAM_CLK_DISABLE,Set value for the dfi_dram_clk_disable signal." "0,1,2,3" newline bitfld.long 0x8 7. "RESERVED" "0,1" hexmask.long.byte 0x8 0.--6. 1. "TDFI_RDDATA_EN,Holds the calculated DFI tRDDATA_EN timing parameter (in DFI PHY clocks) the maximum cycles between a read command and a dfi_rddata_en assertion." line.long 0xC "DDRSS_CTL_389" hexmask.long.word 0xC 21.--31. 1. "RESERVED" hexmask.long.tbyte 0xC 0.--20. 1. "TDFI_CTRLUPD_MAX_F0,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) the maximum cycles that dfi_ctrlupd_req can be asserted." line.long 0x10 "DDRSS_CTL_390" hexmask.long 0x10 0.--31. 1. "TDFI_PHYUPD_TYPE0_F0,Defines the DFI tPHYUPD_TYPE0 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0." line.long 0x14 "DDRSS_CTL_391" hexmask.long 0x14 0.--31. 1. "TDFI_PHYUPD_TYPE1_F0,Defines the DFI tPHYUPD_TYPE1 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1." line.long 0x18 "DDRSS_CTL_392" hexmask.long 0x18 0.--31. 1. "TDFI_PHYUPD_TYPE2_F0,Defines the DFI tPHYUPD_TYPE2 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2." line.long 0x1C "DDRSS_CTL_393" hexmask.long 0x1C 0.--31. 1. "TDFI_PHYUPD_TYPE3_F0,Defines the DFI tPHYUPD_TYPE3 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3." line.long 0x20 "DDRSS_CTL_394" hexmask.long.word 0x20 23.--31. 1. "RESERVED" hexmask.long.tbyte 0x20 0.--22. 1. "TDFI_PHYUPD_RESP_F0,Defines the DFI tPHYUPD_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion." line.long 0x24 "DDRSS_CTL_395" hexmask.long 0x24 0.--31. 1. "TDFI_CTRLUPD_INTERVAL_F0,Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) the maximum cycles between dfi_ctrlupd_req assertions." line.long 0x28 "DDRSS_CTL_396" hexmask.long.tbyte 0x28 15.--31. 1. "RESERVED" hexmask.long.byte 0x28 8.--14. 1. "WRLAT_ADJ_F0,Adjustment value for PHY write timing." newline bitfld.long 0x28 7. "RESERVED" "0,1" hexmask.long.byte 0x28 0.--6. 1. "RDLAT_ADJ_F0,Adjustment value for PHY read timing." line.long 0x2C "DDRSS_CTL_397" hexmask.long.word 0x2C 21.--31. 1. "RESERVED" hexmask.long.tbyte 0x2C 0.--20. 1. "TDFI_CTRLUPD_MAX_F1,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) the maximum cycles that dfi_ctrlupd_req can be asserted." line.long 0x30 "DDRSS_CTL_398" hexmask.long 0x30 0.--31. 1. "TDFI_PHYUPD_TYPE0_F1,Defines the DFI tPHYUPD_TYPE0 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0." line.long 0x34 "DDRSS_CTL_399" hexmask.long 0x34 0.--31. 1. "TDFI_PHYUPD_TYPE1_F1,Defines the DFI tPHYUPD_TYPE1 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1." line.long 0x38 "DDRSS_CTL_400" hexmask.long 0x38 0.--31. 1. "TDFI_PHYUPD_TYPE2_F1,Defines the DFI tPHYUPD_TYPE2 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2." line.long 0x3C "DDRSS_CTL_401" hexmask.long 0x3C 0.--31. 1. "TDFI_PHYUPD_TYPE3_F1,Defines the DFI tPHYUPD_TYPE3 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3." line.long 0x40 "DDRSS_CTL_402" hexmask.long.word 0x40 23.--31. 1. "RESERVED" hexmask.long.tbyte 0x40 0.--22. 1. "TDFI_PHYUPD_RESP_F1,Defines the DFI tPHYUPD_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion." line.long 0x44 "DDRSS_CTL_403" hexmask.long 0x44 0.--31. 1. "TDFI_CTRLUPD_INTERVAL_F1,Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) the maximum cycles between dfi_ctrlupd_req assertions." line.long 0x48 "DDRSS_CTL_404" hexmask.long.tbyte 0x48 15.--31. 1. "RESERVED" hexmask.long.byte 0x48 8.--14. 1. "WRLAT_ADJ_F1,Adjustment value for PHY write timing." newline bitfld.long 0x48 7. "RESERVED" "0,1" hexmask.long.byte 0x48 0.--6. 1. "RDLAT_ADJ_F1,Adjustment value for PHY read timing." line.long 0x4C "DDRSS_CTL_405" hexmask.long.word 0x4C 21.--31. 1. "RESERVED" hexmask.long.tbyte 0x4C 0.--20. 1. "TDFI_CTRLUPD_MAX_F2,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) the maximum cycles that dfi_ctrlupd_req can be asserted." line.long 0x50 "DDRSS_CTL_406" hexmask.long 0x50 0.--31. 1. "TDFI_PHYUPD_TYPE0_F2,Defines the DFI tPHYUPD_TYPE0 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0." line.long 0x54 "DDRSS_CTL_407" hexmask.long 0x54 0.--31. 1. "TDFI_PHYUPD_TYPE1_F2,Defines the DFI tPHYUPD_TYPE1 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1." line.long 0x58 "DDRSS_CTL_408" hexmask.long 0x58 0.--31. 1. "TDFI_PHYUPD_TYPE2_F2,Defines the DFI tPHYUPD_TYPE2 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2." line.long 0x5C "DDRSS_CTL_409" hexmask.long 0x5C 0.--31. 1. "TDFI_PHYUPD_TYPE3_F2,Defines the DFI tPHYUPD_TYPE3 timing parameter (in DFI clocks) the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3." line.long 0x60 "DDRSS_CTL_410" hexmask.long.word 0x60 23.--31. 1. "RESERVED" hexmask.long.tbyte 0x60 0.--22. 1. "TDFI_PHYUPD_RESP_F2,Defines the DFI tPHYUPD_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion." line.long 0x64 "DDRSS_CTL_411" hexmask.long 0x64 0.--31. 1. "TDFI_CTRLUPD_INTERVAL_F2,Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) the maximum cycles between dfi_ctrlupd_req assertions." line.long 0x68 "DDRSS_CTL_412" hexmask.long.byte 0x68 28.--31. 1. "RESERVED" hexmask.long.byte 0x68 24.--27. 1. "TDFI_CTRL_DELAY_F1,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) the delay between a DFI command change and a memory command." newline hexmask.long.byte 0x68 20.--23. 1. "RESERVED" hexmask.long.byte 0x68 16.--19. 1. "TDFI_CTRL_DELAY_F0,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) the delay between a DFI command change and a memory command." newline bitfld.long 0x68 15. "RESERVED" "0,1" hexmask.long.byte 0x68 8.--14. 1. "WRLAT_ADJ_F2,Adjustment value for PHY write timing." newline bitfld.long 0x68 7. "RESERVED" "0,1" hexmask.long.byte 0x68 0.--6. 1. "RDLAT_ADJ_F2,Adjustment value for PHY read timing." line.long 0x6C "DDRSS_CTL_413" hexmask.long.byte 0x6C 24.--31. 1. "TDFI_WRLVL_EN,Defines the DFI tWRLVL_EN timing parameter (in DFI clocks) the minimum cycles from a dfi_wrlvl_en assertion to the first dfi_wrlvl_strobe assertion." hexmask.long.byte 0x6C 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x6C 16.--19. 1. "TDFI_DRAM_CLK_ENABLE,Defines the DFI tDRAM_CLK_ENABLE timing parameter (in DFI clocks) the delay between a dfi_dram_clk_disable de-assertion and the memory clock enable." hexmask.long.byte 0x6C 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x6C 8.--11. 1. "TDFI_DRAM_CLK_DISABLE,Defines the DFI tDRAM_CLK_DISABLE timing parameter (in DFI clocks) the delay between a dfi_dram_clock_disable assertion and the memory clock disable." hexmask.long.byte 0x6C 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x6C 0.--3. 1. "TDFI_CTRL_DELAY_F2,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) the delay between a DFI command change and a memory command." line.long 0x70 "DDRSS_CTL_414" hexmask.long.tbyte 0x70 10.--31. 1. "RESERVED" hexmask.long.word 0x70 0.--9. 1. "TDFI_WRLVL_WW,Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) the minimum cycles between dfi_wrlvl_strobe assertions." line.long 0x74 "DDRSS_CTL_415" hexmask.long 0x74 0.--31. 1. "TDFI_WRLVL_RESP,Defines the DFI tWRLVL_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_wrlvl_req assertion and a dfi_wrlvl_en assertion." line.long 0x78 "DDRSS_CTL_416" hexmask.long 0x78 0.--31. 1. "TDFI_WRLVL_MAX,Defines the DFI tWRLVL_MAX timing parameter (in DFI clocks) the maximum cycles between a dfi_wrlvl_en assertion and a valid dfi_wrlvl_resp." line.long 0x7C "DDRSS_CTL_417" hexmask.long.word 0x7C 18.--31. 1. "RESERVED" hexmask.long.word 0x7C 8.--17. 1. "TDFI_RDLVL_RR,Defines the DFI tRDLVL_RR timing parameter (in DFI clocks) the minimum cycles between read commands." newline hexmask.long.byte 0x7C 0.--7. 1. "TDFI_RDLVL_EN,Defines the DFI tRDLVL_EN timing parameter (in DFI clocks) the minimum cycles from a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion to the first read or MRR." line.long 0x80 "DDRSS_CTL_418" hexmask.long 0x80 0.--31. 1. "TDFI_RDLVL_RESP,Defines the DFI tRDLVL_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_rdlvl_req or dfi_rdlvl_gate_req assertion and a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion." line.long 0x84 "DDRSS_CTL_419" hexmask.long.word 0x84 17.--31. 1. "RESERVED" bitfld.long 0x84 16. "RDLVL_GATE_EN,Enable the MC gate training module." "0,1" newline hexmask.long.byte 0x84 9.--15. 1. "RESERVED" bitfld.long 0x84 8. "RDLVL_EN,Enable the MC data eye training module." "0,1" newline hexmask.long.byte 0x84 0.--7. 1. "RDLVL_RESP_MASK,Mask for the dfi_rdlvl_resp signal during data eye training." line.long 0x88 "DDRSS_CTL_420" hexmask.long 0x88 0.--31. 1. "TDFI_RDLVL_MAX,Defines the DFI tRDLVL_MAX timing parameter (in DFI clocks) the maximum cycles between a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion and a valid dfi_rdlvl_resp." line.long 0x8C "DDRSS_CTL_421" hexmask.long.byte 0x8C 24.--31. 1. "RESERVED" hexmask.long.byte 0x8C 16.--23. 1. "TDFI_CALVL_EN,Defines the DFI tCALVL_EN timing parameter (in DFI clocks) the minimum cycles between a dfi_calvl_en assertion and a dfi_cke de-assertion." newline hexmask.long.byte 0x8C 11.--15. 1. "RESERVED" rbitfld.long 0x8C 8.--10. "RDLVL_GATE_ERROR_STATUS,Holds the error associated with the read gate training error or gate training error interrupt." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8C 3.--7. 1. "RESERVED" rbitfld.long 0x8C 0.--2. "RDLVL_ERROR_STATUS,Holds the error associated with the data eye training error or gate training error interrupt." "0,1,2,3,4,5,6,7" line.long 0x90 "DDRSS_CTL_422" hexmask.long.byte 0x90 26.--31. 1. "RESERVED" hexmask.long.word 0x90 16.--25. 1. "TDFI_CALVL_CAPTURE_F0,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) the minimum cycles between a calibration command and a dfi_calvl_capture pulse." newline hexmask.long.byte 0x90 10.--15. 1. "RESERVED" hexmask.long.word 0x90 0.--9. 1. "TDFI_CALVL_CC_F0,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) the minimum cycles between calibration commands." line.long 0x94 "DDRSS_CTL_423" hexmask.long.byte 0x94 26.--31. 1. "RESERVED" hexmask.long.word 0x94 16.--25. 1. "TDFI_CALVL_CAPTURE_F1,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) the minimum cycles between a calibration command and a dfi_calvl_capture pulse." newline hexmask.long.byte 0x94 10.--15. 1. "RESERVED" hexmask.long.word 0x94 0.--9. 1. "TDFI_CALVL_CC_F1,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) the minimum cycles between calibration commands." line.long 0x98 "DDRSS_CTL_424" hexmask.long.byte 0x98 26.--31. 1. "RESERVED" hexmask.long.word 0x98 16.--25. 1. "TDFI_CALVL_CAPTURE_F2,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) the minimum cycles between a calibration command and a dfi_calvl_capture pulse." newline hexmask.long.byte 0x98 10.--15. 1. "RESERVED" hexmask.long.word 0x98 0.--9. 1. "TDFI_CALVL_CC_F2,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) the minimum cycles between calibration commands." line.long 0x9C "DDRSS_CTL_425" hexmask.long 0x9C 0.--31. 1. "TDFI_CALVL_RESP,Defines the DFI tCALVL_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_calvl_req assertion and a dfi_calvl_en assertion." line.long 0xA0 "DDRSS_CTL_426" hexmask.long 0xA0 0.--31. 1. "TDFI_CALVL_MAX,Defines the DFI tCALVL_MAX timing parameter (in DFI clocks) the maximum cycles between a dfi_calvl_en assertion and a valid dfi_calvl_resp." line.long 0xA4 "DDRSS_CTL_427" hexmask.long.byte 0xA4 27.--31. 1. "RESERVED" bitfld.long 0xA4 24.--26. "TDFI_PHY_WRDATA_F0,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA4 20.--23. 1. "RESERVED" hexmask.long.byte 0xA4 16.--19. 1. "CALVL_ERROR_STATUS,Holds the error associated with the CA training error interrupt." newline hexmask.long.byte 0xA4 9.--15. 1. "RESERVED" bitfld.long 0xA4 8. "CALVL_EN,Enable the MC CA training module." "0,1" newline hexmask.long.byte 0xA4 1.--7. 1. "RESERVED" bitfld.long 0xA4 0. "CALVL_RESP_MASK,Mask for the dfi_calvl_resp signal during CA training." "0,1" line.long 0xA8 "DDRSS_CTL_428" bitfld.long 0xA8 31. "RESERVED" "0,1" hexmask.long.byte 0xA8 24.--30. 1. "TDFI_WRCSLAT_F0,Defines the DFI tPHY_WRCSLAT timing parameter (in DFI PHY clocks) the maximum cycles between a write command and a dfi_wrdata_cs_n assertion." newline bitfld.long 0xA8 23. "RESERVED" "0,1" hexmask.long.byte 0xA8 16.--22. 1. "TDFI_RDCSLAT_F0,Defines the DFI tPHY_RDCSLAT timing parameter (in DFI PHY clocks) the maximum cycles between a read command and a dfi_rddata_cs_n assertion." newline hexmask.long.byte 0xA8 11.--15. 1. "RESERVED" bitfld.long 0xA8 8.--10. "TDFI_PHY_WRDATA_F2,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA8 3.--7. 1. "RESERVED" bitfld.long 0xA8 0.--2. "TDFI_PHY_WRDATA_F1,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7" line.long 0xAC "DDRSS_CTL_429" bitfld.long 0xAC 31. "RESERVED" "0,1" hexmask.long.byte 0xAC 24.--30. 1. "TDFI_WRCSLAT_F2,Defines the DFI tPHY_WRCSLAT timing parameter (in DFI PHY clocks) the maximum cycles between a write command and a dfi_wrdata_cs_n assertion." newline bitfld.long 0xAC 23. "RESERVED" "0,1" hexmask.long.byte 0xAC 16.--22. 1. "TDFI_RDCSLAT_F2,Defines the DFI tPHY_RDCSLAT timing parameter (in DFI PHY clocks) the maximum cycles between a read command and a dfi_rddata_cs_n assertion." newline bitfld.long 0xAC 15. "RESERVED" "0,1" hexmask.long.byte 0xAC 8.--14. 1. "TDFI_WRCSLAT_F1,Defines the DFI tPHY_WRCSLAT timing parameter (in DFI PHY clocks) the maximum cycles between a write command and a dfi_wrdata_cs_n assertion." newline bitfld.long 0xAC 7. "RESERVED" "0,1" hexmask.long.byte 0xAC 0.--6. 1. "TDFI_RDCSLAT_F1,Defines the DFI tPHY_RDCSLAT timing parameter (in DFI PHY clocks) the maximum cycles between a read command and a dfi_rddata_cs_n assertion." line.long 0xB0 "DDRSS_CTL_430" hexmask.long.byte 0xB0 25.--31. 1. "RESERVED" bitfld.long 0xB0 24. "BL_ON_FLY_ENABLE,Enables the burst length on the fly feature." "0,1" newline hexmask.long.byte 0xB0 17.--23. 1. "RESERVED" bitfld.long 0xB0 16. "DISABLE_MEMORY_MASKED_WRITE,Restricts the controller from masked write commands." "0,1" newline hexmask.long.byte 0xB0 9.--15. 1. "RESERVED" bitfld.long 0xB0 8. "EN_1T_TIMING,Enable 1T timing in a system supporting both 1T and 2T timing." "0,1" newline hexmask.long.byte 0xB0 0.--7. 1. "TDFI_WRDATA_DELAY,Defines the tWRDATA_DELAY timing parameter (in DFI PHY clocks) the maximum cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus." group.long 0x6D4++0x1F line.long 0x0 "DDRSS_CTL_437" hexmask.long.byte 0x0 24.--31. 1. "GLOBAL_ERROR_INFO,Indicates the source of DDR controller safety error interrupts." hexmask.long.byte 0x0 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x0 8.--11. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED,Reserved" line.long 0x4 "DDRSS_CTL_438" hexmask.long.byte 0x4 24.--31. 1. "NWR_F1,DRAM NWR value in cycles for chip select 2." hexmask.long.byte 0x4 16.--23. 1. "NWR_F0,DRAM NWR value in cycles for chip select 2." newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED" rbitfld.long 0x4 8.--9. "AXI_PARITY_ERROR_STATUS,Specifies the source of the GLOBAL_ERROR_INFO bit (3) error." "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "GLOBAL_ERROR_MASK,Mask for the DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_FATAL_0 and DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_NONFATAL_0 signals from the GLOBAL_ERROR_INFO parameter." line.long 0x8 "DDRSS_CTL_439" hexmask.long.word 0x8 21.--31. 1. "RESERVED" hexmask.long.byte 0x8 16.--20. 1. "REGPORT_PARAM_PARITY_PROTECTION_STATUS,Specifies the source of the GLOBAL_ERROR_INFO bit (5) error." newline hexmask.long.byte 0x8 9.--15. 1. "RESERVED" bitfld.long 0x8 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "NWR_F2,DRAM NWR value in cycles for chip select 2." line.long 0xC "DDRSS_CTL_440" hexmask.long 0xC 0.--31. 1. "MC_PARITY_INJECTION_BYTE_ENABLE_0,Enables a parity error injection on the assocated byte." line.long 0x10 "DDRSS_CTL_441" hexmask.long 0x10 0.--31. 1. "MC_PARITY_INJECTION_BYTE_ENABLE_1,Enables a parity error injection on the assocated byte." line.long 0x14 "DDRSS_CTL_442" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "REGPORT_WRITE_PARITY_PROTECTION_EN,Enables regport write data parity checking from the regport to the param block." "0,1" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" bitfld.long 0x14 16. "REGPORT_WRITEMASK_PARITY_PROTECTION_EN,Enables regport write data mask parity checking from the regport to the param block." "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "REGPORT_ADDR_PARITY_PROTECTION_EN,Enables regport address/command parity checking from the regport to the param block." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "MC_PARITY_ERROR_TYPE,Defines if the parity error injected is a transient (one-time) or stuck-at (every time) error." "0,1" line.long 0x18 "DDRSS_CTL_443" hexmask.long.byte 0x18 25.--31. 1. "RESERVED" bitfld.long 0x18 24. "REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN,Enables regport write mask data parity error injection from the regport to the param block." "0,1" newline hexmask.long.byte 0x18 17.--23. 1. "RESERVED" bitfld.long 0x18 16. "REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN,Enables regport address/command parity error injection from the regport to the param block." "0,1" newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED" bitfld.long 0x18 8. "PARAMREG_PARITY_PROTECTION_EN,Enables parity checking on the param registers." "0,1" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED" bitfld.long 0x18 0. "REGPORT_READ_PARITY_PROTECTION_EN,Enables regport read data parity checking from the param block to the regport." "0,1" line.long 0x1C "DDRSS_CTL_444" hexmask.long.word 0x1C 17.--31. 1. "RESERVED" bitfld.long 0x1C 16. "PARAMREG_PARITY_PROTECTION_INJECTION_EN,Enables parity error injection on the param registers." "0,1" newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED" bitfld.long 0x1C 8. "REGPORT_READ_PARITY_PROTECTION_INJECTION_EN,Enables regport read data parity error injection from the param block to the regport." "0,1" newline hexmask.long.byte 0x1C 1.--7. 1. "RESERVED" bitfld.long 0x1C 0. "REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN,Enables regport write data parity error injection from the regport to the param block." "0,1" group.long 0x6FC++0xF line.long 0x0 "DDRSS_CTL_447" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "PORT_TO_CORE_PROTECTION_EN,Enables parity checking and logic replication protection from the port to the controller core." "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" line.long 0x4 "DDRSS_CTL_448" hexmask.long 0x4 0.--31. 1. "PORT_TO_CORE_PROTECTION_INJECTION_EN_0,Enables parity error injection from the port to the controller core." line.long 0x8 "DDRSS_CTL_449" hexmask.long 0x8 0.--31. 1. "PORT_TO_CORE_PROTECTION_INJECTION_EN_1,Enables parity error injection from the port to the controller core." line.long 0xC "DDRSS_CTL_450" hexmask.long 0xC 3.--31. 1. "RESERVED" bitfld.long 0xC 0.--2. "PORT_TO_CORE_PROTECTION_INJECTION_EN_2,Enables parity error injection from the port to the controller core." "0,1,2,3,4,5,6,7" group.long 0x71C++0xF line.long 0x0 "DDRSS_CTL_455" hexmask.long 0x0 0.--31. 1. "PORT_TO_CORE_LR_ERR_INJ_EN_0,Enables error injection from the port to the controller core." line.long 0x4 "DDRSS_CTL_456" hexmask.long 0x4 0.--31. 1. "PORT_TO_CORE_LR_ERR_INJ_EN_1,Enables error injection from the port to the controller core." line.long 0x8 "DDRSS_CTL_457" hexmask.long 0x8 0.--31. 1. "PORT_TO_CORE_LR_ERR_INJ_EN_2,Enables error injection from the port to the controller core." line.long 0xC "DDRSS_CTL_458" hexmask.long 0xC 4.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--3. 1. "PORT_TO_CORE_LR_ERR_INJ_EN_3,Enables error injection from the port to the controller core." tree.end tree "COMPUTE_CLUSTER0_CTL_CFG_PHY" base ad:0x2990000 group.long 0x4000++0x27 line.long 0x0 "DDRSS_PHY_0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--19. 1. "PHY_IO_PAD_DELAY_TIMING_BYPASS_0,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 0." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_0,Write data clock bypass mode slave delay setting for slice 0.} PADDING_BEFORE" line.long 0x4 "DDRSS_PHY_1" hexmask.long.word 0x4 19.--31. 1. "RESERVED" bitfld.long 0x4 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_0,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0,Write DQS bypass mode slave delay setting for slice 0." line.long 0x8 "DDRSS_PHY_2" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "PHY_CLK_BYPASS_OVERRIDE_0,Bypass mode override setting for slice 0." "0,1" newline hexmask.long.byte 0x8 18.--23. 1. "RESERVED" bitfld.long 0x8 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_0,Two_cycle_preamble for bypass mode for slice 0." "0,1,2,3" newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0,Read DQS bypass mode slave delay setting for slice 0." line.long 0xC "DDRSS_PHY_3" bitfld.long 0xC 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 24.--29. 1. "PHY_SW_WRDQ3_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 0." newline bitfld.long 0xC 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 16.--21. 1. "PHY_SW_WRDQ2_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 0." newline bitfld.long 0xC 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 8.--13. 1. "PHY_SW_WRDQ1_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 0." newline bitfld.long 0xC 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "PHY_SW_WRDQ0_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 0." line.long 0x10 "DDRSS_PHY_4" bitfld.long 0x10 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 24.--29. 1. "PHY_SW_WRDQ7_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 0." newline bitfld.long 0x10 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 16.--21. 1. "PHY_SW_WRDQ6_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 0." newline bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 8.--13. 1. "PHY_SW_WRDQ5_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 0." newline bitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 0.--5. 1. "PHY_SW_WRDQ4_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 0." line.long 0x14 "DDRSS_PHY_5" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_0,When set a register write will update parameters for all ranks at the same time in slice 0." "0,1" newline hexmask.long.byte 0x14 18.--23. 1. "RESERVED" bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_0,Per-rank CS map for slice 0." "0,1,2,3" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED" hexmask.long.byte 0x14 8.--11. 1. "PHY_SW_WRDQS_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 0." newline bitfld.long 0x14 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 0.--5. 1. "PHY_SW_WRDM_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 0." line.long 0x18 "DDRSS_PHY_6" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0." newline bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 16.--20. 1. "PHY_LP4_BOOT_RDDATA_EN_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 0." newline hexmask.long.byte 0x18 10.--15. 1. "RESERVED" bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0." "0,1,2,3" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED" bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_0,For per-rank training indicates which rank's paramters are read/written for slice 0." "0,1" line.long 0x1C "DDRSS_PHY_7" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 0." newline hexmask.long.byte 0x1C 18.--23. 1. "RESERVED" bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0,For LPDDR4 boot frequency write path clock gating disable for slice 0." "0,1,2,3" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED" hexmask.long.byte 0x1C 8.--11. 1. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED" hexmask.long.byte 0x1C 0.--3. 1. "PHY_LP4_BOOT_RPTR_UPDATE_0,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 0." line.long 0x20 "DDRSS_PHY_8" hexmask.long.byte 0x20 25.--31. 1. "RESERVED" bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_0,Loopback read only test timeout mechanism enable for slice 0." "0,1" newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_0,Loopback control bits for slice 0." newline hexmask.long.byte 0x20 2.--7. 1. "RESERVED" bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_0,Loopback control en for slice 0." "0,1,2,3" line.long 0x24 "DDRSS_PHY_9" hexmask.long 0x24 0.--31. 1. "PHY_AUTO_TIMING_MARGIN_CONTROL_0,Auto timing marging control bits for slice 0." rgroup.long 0x4028++0x3 line.long 0x0 "DDRSS_PHY_10" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_0,Observation register for the auto_timing_margin for slice 0." group.long 0x402C++0x13 line.long 0x0 "DDRSS_PHY_11" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RDLVL_MULTI_PATT_ENABLE_0,Read Leveling Multi-pattern enable for slice 0." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" hexmask.long.word 0x0 8.--16. 1. "PHY_PRBS_PATTERN_MASK_0,PRBS7 mask signal for slice 0." newline bitfld.long 0x0 7. "RESERVED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "PHY_PRBS_PATTERN_START_0,PRBS7 start pattern for slice 0." line.long 0x4 "DDRSS_PHY_12" hexmask.long.word 0x4 23.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--22. 1. "PHY_VREF_TRAIN_OBS_0,Observation register for best vref value for slice 0." newline bitfld.long 0x4 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "PHY_VREF_INITIAL_STEPSIZE_0,Data slice initial VREF training step size for slice 0." newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED" bitfld.long 0x4 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_0,Read Leveling read level windows disable reset for slice 0." "0,1" line.long 0x8 "DDRSS_PHY_13" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "SC_PHY_SNAP_OBS_REGS_0,Initiates a snapshot of the internal observation registers for slice 0." "0,1" newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED" hexmask.long.byte 0x8 16.--19. 1. "PHY_GATE_ERROR_DELAY_SELECT_0,Number of cycles to wait for the DQS gate to close before flagging an error for slice 0." newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0,Read DQS data clock bypass mode slave delay setting for slice 0." line.long 0xC "DDRSS_PHY_14" hexmask.long.byte 0xC 27.--31. 1. "RESERVED" bitfld.long 0xC 24.--26. "PHY_MEM_CLASS_0,Indicates the type of DRAM for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 17.--23. 1. "RESERVED" bitfld.long 0xC 16. "PHY_LPDDR_0,Adds a cycle of delay for the slice 0 to match the address slice." "0,1" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_0,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 0." line.long 0x10 "DDRSS_PHY_15" hexmask.long.word 0x10 18.--31. 1. "RESERVED" bitfld.long 0x10 16.--17. "ON_FLY_GATE_ADJUST_EN_0,Control the on-the-fly gate adjustment for slice 0." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_0,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 0." rgroup.long 0x4040++0x3 line.long 0x0 "DDRSS_PHY_16" hexmask.long 0x0 0.--31. 1. "PHY_GATE_TRACKING_OBS_0,Report the on-the-fly gate measurement result for slice 0." group.long 0x4044++0x6B line.long 0x0 "DDRSS_PHY_17" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" bitfld.long 0x0 8.--9. "PHY_LP4_PST_AMBLE_0,Controls the read postamble extension for LPDDR4 for slice 0." "0,1,2,3" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_DFI40_POLARITY_0,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 0." "0,1" line.long 0x4 "DDRSS_PHY_18" hexmask.long 0x4 0.--31. 1. "PHY_RDLVL_PATT8_0,Read leveling pattern 8 data for slice 0." line.long 0x8 "DDRSS_PHY_19" hexmask.long 0x8 0.--31. 1. "PHY_RDLVL_PATT9_0,Read leveling pattern 9 data for slice 0." line.long 0xC "DDRSS_PHY_20" hexmask.long 0xC 0.--31. 1. "PHY_RDLVL_PATT10_0,Read leveling pattern 10 data for slice 0." line.long 0x10 "DDRSS_PHY_21" hexmask.long 0x10 0.--31. 1. "PHY_RDLVL_PATT11_0,Read leveling pattern 11 data for slice 0." line.long 0x14 "DDRSS_PHY_22" hexmask.long 0x14 0.--31. 1. "PHY_RDLVL_PATT12_0,Read leveling pattern 12 data for slice 0." line.long 0x18 "DDRSS_PHY_23" hexmask.long 0x18 0.--31. 1. "PHY_RDLVL_PATT13_0,Read leveling pattern 13 data for slice 0." line.long 0x1C "DDRSS_PHY_24" hexmask.long 0x1C 0.--31. 1. "PHY_RDLVL_PATT14_0,Read leveling pattern 14 data for slice 0." line.long 0x20 "DDRSS_PHY_25" hexmask.long 0x20 0.--31. 1. "PHY_RDLVL_PATT15_0,Read leveling pattern 15 data for slice 0." line.long 0x24 "DDRSS_PHY_26" hexmask.long.byte 0x24 27.--31. 1. "RESERVED" bitfld.long 0x24 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_0,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 20.--23. 1. "RESERVED" hexmask.long.byte 0x24 16.--19. 1. "PHY_MASTER_DLY_LOCK_OBS_SELECT_0,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 0." newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED" bitfld.long 0x24 8. "PHY_SW_FIFO_PTR_RST_DISABLE_0,Disables automatic reset of the read entry FIFO pointers for slice 0." "0,1" newline hexmask.long.byte 0x24 3.--7. 1. "RESERVED" bitfld.long 0x24 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_0,Reserved for future use for slice 0." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_PHY_27" hexmask.long.byte 0x28 28.--31. 1. "RESERVED" hexmask.long.byte 0x28 24.--27. 1. "PHY_FIFO_PTR_OBS_SELECT_0,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 0." newline hexmask.long.byte 0x28 20.--23. 1. "RESERVED" hexmask.long.byte 0x28 16.--19. 1. "PHY_WR_SHIFT_OBS_SELECT_0,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 0." newline hexmask.long.byte 0x28 12.--15. 1. "RESERVED" hexmask.long.byte 0x28 8.--11. 1. "PHY_WR_ENC_OBS_SELECT_0,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 0." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED" hexmask.long.byte 0x28 0.--3. 1. "PHY_RDDQS_DQ_ENC_OBS_SELECT_0,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 0." line.long 0x2C "DDRSS_PHY_28" hexmask.long.byte 0x2C 24.--31. 1. "PHY_WRLVL_PER_START_0,Observation register for write leveling status for slice 0." hexmask.long.byte 0x2C 18.--23. 1. "RESERVED" newline bitfld.long 0x2C 16.--17. "PHY_WRLVL_ALGO_0,Write leveling algorithm selection for slice 0." "0,1,2,3" hexmask.long.byte 0x2C 9.--15. 1. "RESERVED" newline bitfld.long 0x2C 8. "SC_PHY_LVL_DEBUG_CONT_0,Allows the leveling state machine to advance (when in debug mode) for slice 0." "0,1" hexmask.long.byte 0x2C 1.--7. 1. "RESERVED" newline bitfld.long 0x2C 0. "PHY_LVL_DEBUG_MODE_0,Enables leveling debug mode for slice 0." "0,1" line.long 0x30 "DDRSS_PHY_29" hexmask.long.byte 0x30 24.--31. 1. "RESERVED" hexmask.long.byte 0x30 16.--23. 1. "PHY_DQ_MASK_0,For ECC slice should set this register to do DQ bit mask for slice 0." newline hexmask.long.byte 0x30 12.--15. 1. "RESERVED" hexmask.long.byte 0x30 8.--11. 1. "PHY_WRLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 0." newline bitfld.long 0x30 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x30 0.--5. 1. "PHY_WRLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during write leveling for slice 0." line.long 0x34 "DDRSS_PHY_30" hexmask.long.byte 0x34 28.--31. 1. "RESERVED" hexmask.long.byte 0x34 24.--27. 1. "PHY_GTLVL_UPDT_WAIT_CNT_0,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 0." newline bitfld.long 0x34 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x34 16.--21. 1. "PHY_GTLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during gate training for slice 0." newline hexmask.long.byte 0x34 10.--15. 1. "RESERVED" hexmask.long.word 0x34 0.--9. 1. "PHY_GTLVL_PER_START_0,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 0." line.long 0x38 "DDRSS_PHY_31" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 0." newline hexmask.long.byte 0x38 18.--23. 1. "RESERVED" bitfld.long 0x38 16.--17. "PHY_RDLVL_OP_MODE_0,Read leveling algorithm select for slice 0." "0,1,2,3" newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.byte 0x38 8.--11. 1. "PHY_RDLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 0." newline bitfld.long 0x38 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "PHY_RDLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during read leveling for slice 0." line.long 0x3C "DDRSS_PHY_32" bitfld.long 0x3C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x3C 24.--29. 1. "PHY_WDQLVL_BURST_CNT_0,Defines the write/read burst length in bytes during the write data leveling sequence for slice 0." newline hexmask.long.byte 0x3C 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_0,Defines the minimum gap requirment for the LE and TE window for slice 0." hexmask.long.byte 0x3C 8.--15. 1. "PHY_RDLVL_DATA_MASK_0,Per-bit mask for read leveling for slice 0." newline hexmask.long.byte 0x3C 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 0." line.long 0x40 "DDRSS_PHY_33" hexmask.long.byte 0x40 28.--31. 1. "RESERVED" hexmask.long.byte 0x40 24.--27. 1. "PHY_WDQLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 0." newline hexmask.long.byte 0x40 19.--23. 1. "RESERVED" hexmask.long.word 0x40 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0,Defines the write/read burst length in bytes during the write data leveling sequence for slice 0." newline hexmask.long.byte 0x40 3.--7. 1. "RESERVED" bitfld.long 0x40 0.--2. "PHY_WDQLVL_PATT_0,Defines the training patterns to be used during the write data leveling sequence for slice 0." "0,1,2,3,4,5,6,7" line.long 0x44 "DDRSS_PHY_34" hexmask.long.word 0x44 17.--31. 1. "RESERVED" bitfld.long 0x44 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_0,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 0." "0,1" newline hexmask.long.byte 0x44 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_0,Select value to map specific information during or post periodic write data leveling for slice 0." hexmask.long.byte 0x44 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x44 0.--3. 1. "PHY_WDQLVL_DQDM_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 0." line.long 0x48 "DDRSS_PHY_35" hexmask.long.tbyte 0x48 9.--31. 1. "RESERVED" hexmask.long.word 0x48 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_0,Per-bit mask for write data leveling for slice 0." line.long 0x4C "DDRSS_PHY_36" hexmask.long 0x4C 0.--31. 1. "PHY_USER_PATT0_0,User-defined pattern to be used during write data leveling for slice 0." line.long 0x50 "DDRSS_PHY_37" hexmask.long 0x50 0.--31. 1. "PHY_USER_PATT1_0,User-defined pattern to be used during write data leveling for slice 0." line.long 0x54 "DDRSS_PHY_38" hexmask.long 0x54 0.--31. 1. "PHY_USER_PATT2_0,User-defined pattern to be used during write data leveling for slice 0." line.long 0x58 "DDRSS_PHY_39" hexmask.long 0x58 0.--31. 1. "PHY_USER_PATT3_0,User-defined pattern to be used during write data leveling for slice 0." line.long 0x5C "DDRSS_PHY_40" hexmask.long.word 0x5C 17.--31. 1. "RESERVED" bitfld.long 0x5C 16. "PHY_NTP_MULT_TRAIN_0,Control for single pass only No-Topology training for slice 0." "0,1" newline hexmask.long.word 0x5C 0.--15. 1. "PHY_USER_PATT4_0,User-defined pattern to be used during write data leveling for slice 0." line.long 0x60 "DDRSS_PHY_41" hexmask.long.byte 0x60 26.--31. 1. "RESERVED" hexmask.long.word 0x60 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_0,Threshold Criteria of period threshold after No-Topology training is completed for slice 0." newline hexmask.long.byte 0x60 10.--15. 1. "RESERVED" hexmask.long.word 0x60 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_0,Threshold Criteria of early threshold after No-Topology training is completed for slice 0." line.long 0x64 "DDRSS_PHY_42" hexmask.long.byte 0x64 26.--31. 1. "RESERVED" hexmask.long.word 0x64 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_0,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 0." newline hexmask.long.byte 0x64 10.--15. 1. "RESERVED" hexmask.long.word 0x64 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_0,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 0." line.long 0x68 "DDRSS_PHY_43" hexmask.long.byte 0x68 24.--31. 1. "RESERVED" hexmask.long.byte 0x68 16.--23. 1. "PHY_FIFO_PTR_OBS_0,Observation register containing read entry FIFO pointers for slice 0." newline bitfld.long 0x68 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x68 8.--13. 1. "SC_PHY_MANUAL_CLEAR_0,Manual reset/clear of internal logic for slice 0." newline hexmask.long.byte 0x68 1.--7. 1. "RESERVED" bitfld.long 0x68 0. "PHY_CALVL_VREF_DRIVING_SLICE_0,Indicates if slice 0 is used to drive the VREF value to the device during CA training." "0,1" rgroup.long 0x40B0++0x47 line.long 0x0 "DDRSS_PHY_44" hexmask.long 0x0 0.--31. 1. "PHY_LPBK_RESULT_OBS_0,Observation register containing loopback status/results for slice 0." line.long 0x4 "DDRSS_PHY_45" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_0,Observation register containing master delay results for slice 0." newline hexmask.long.word 0x4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_0,Observation register containing total number of loopback error data for slice 0." line.long 0x8 "DDRSS_PHY_46" hexmask.long.byte 0x8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 0." hexmask.long.byte 0x8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_0,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 0." newline bitfld.long 0x8 15. "RESERVED" "0,1" hexmask.long.byte 0x8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0,Observation register containing read DQS base slave delay encoded value for slice 0." newline bitfld.long 0x8 7. "RESERVED" "0,1" hexmask.long.byte 0x8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_0,Observation register containing read DQ slave delay encoded values for slice 0." line.long 0xC "DDRSS_PHY_47" bitfld.long 0xC 31. "RESERVED" "0,1" hexmask.long.byte 0xC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0,Observation register containing write DQS base slave delay encoded value for slice 0." newline hexmask.long.byte 0xC 19.--23. 1. "RESERVED" hexmask.long.word 0xC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0,Observation register containing read DQS gate slave delay encoded value for slice 0." newline hexmask.long.byte 0xC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 0." line.long 0x10 "DDRSS_PHY_48" hexmask.long.word 0x10 19.--31. 1. "RESERVED" bitfld.long 0x10 16.--18. "PHY_WR_SHIFT_OBS_0,Observation register containing automatic half cycle and cycle shift values for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing write adder slave delay encoded value for slice 0." hexmask.long.byte 0x10 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0,Observation register containing write DQ base slave delay encoded value for slice 0." line.long 0x14 "DDRSS_PHY_49" hexmask.long.byte 0x14 26.--31. 1. "RESERVED" hexmask.long.word 0x14 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_0,Observation register containing write leveling first hard 1 DQS slave delay for slice 0." newline hexmask.long.byte 0x14 10.--15. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_0,Observation register containing write leveling last hard 0 DQS slave delay for slice 0." line.long 0x18 "DDRSS_PHY_50" hexmask.long.word 0x18 17.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--16. 1. "PHY_WRLVL_STATUS_OBS_0,Observation register containing write leveling status for slice 0." line.long 0x1C "DDRSS_PHY_51" hexmask.long.byte 0x1C 26.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0,Observation register containing gate sample2 slave delay encoded values for slice 0." newline hexmask.long.byte 0x1C 10.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0,Observation register containing gate sample1 slave delay encoded values for slice 0." line.long 0x20 "DDRSS_PHY_52" bitfld.long 0x20 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x20 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_0,Observation register containing gate training first hard 0 DQS slave delay for slice 0." newline hexmask.long.word 0x20 0.--15. 1. "PHY_WRLVL_ERROR_OBS_0,Observation register containing write leveling error status for slice 0." line.long 0x24 "DDRSS_PHY_53" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED" hexmask.long.word 0x24 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_0,Observation register containing gate training last hard 1 DQS slave delay for slice 0." line.long 0x28 "DDRSS_PHY_54" hexmask.long.word 0x28 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x28 0.--17. 1. "PHY_GTLVL_STATUS_OBS_0,Observation register containing gate training status for slice 0." line.long 0x2C "DDRSS_PHY_55" hexmask.long.byte 0x2C 26.--31. 1. "RESERVED" hexmask.long.word 0x2C 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0,Observation register containing read leveling data window trailing edge slave delay setting for slice 0." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" hexmask.long.word 0x2C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0,Observation register containing read leveling data window leading edge slave delay setting for slice 0." line.long 0x30 "DDRSS_PHY_56" hexmask.long 0x30 2.--31. 1. "RESERVED" bitfld.long 0x30 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0,Observation register containing read leveling number of windows found for slice 0." "0,1,2,3" line.long 0x34 "DDRSS_PHY_57" hexmask.long 0x34 0.--31. 1. "PHY_RDLVL_STATUS_OBS_0,Observation register containing read leveling status for slice 0." line.long 0x38 "DDRSS_PHY_58" hexmask.long 0x38 0.--31. 1. "PHY_RDLVL_PERIODIC_OBS_0,Observation register containing periodic read leveling status for slice 0." line.long 0x3C "DDRSS_PHY_59" hexmask.long.byte 0x3C 27.--31. 1. "RESERVED" hexmask.long.word 0x3C 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_0,Observation register containing write data leveling data window trailing edge slave delay setting for slice 0." newline hexmask.long.byte 0x3C 11.--15. 1. "RESERVED" hexmask.long.word 0x3C 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_0,Observation register containing write data leveling data window leading edge slave delay setting for slice 0." line.long 0x40 "DDRSS_PHY_60" hexmask.long 0x40 0.--31. 1. "PHY_WDQLVL_STATUS_OBS_0,Observation register containing write data leveling status for slice 0." line.long 0x44 "DDRSS_PHY_61" hexmask.long 0x44 0.--31. 1. "PHY_WDQLVL_PERIODIC_OBS_0,Observation register containing periodic write data leveling status for slice 0." group.long 0x40F8++0x7 line.long 0x0 "DDRSS_PHY_62" bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long 0x0 0.--30. 1. "PHY_DDL_MODE_0,DDL mode for slice 0." line.long 0x4 "DDRSS_PHY_63" hexmask.long 0x4 6.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "PHY_DDL_MASK_0,DDL mask for slice 0." rgroup.long 0x4100++0x7 line.long 0x0 "DDRSS_PHY_64" hexmask.long 0x0 0.--31. 1. "PHY_DDL_TEST_OBS_0,DDL test observation for slice 0." line.long 0x4 "DDRSS_PHY_65" hexmask.long 0x4 0.--31. 1. "PHY_DDL_TEST_MSTR_DLY_OBS_0,DDL test observation delays for slice 0 master DDL." group.long 0x4108++0x1F line.long 0x0 "DDRSS_PHY_66" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RX_CAL_OVERRIDE_0,Manual setting of RX Calibration enable for slice 0." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" bitfld.long 0x0 16. "SC_PHY_RX_CAL_START_0,Manual RX Calibration start for slice 0." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" bitfld.long 0x0 8. "PHY_LP4_WDQS_OE_EXTEND_0,LPDDR4 write preamble extension enable for slice 0." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_0,Specify threshold value for PHY init update tracking for slice 0." line.long 0x4 "DDRSS_PHY_67" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--24. 1. "PHY_RX_CAL_DQ0_0,RX Calibration codes for DQ0 for slice 0." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0,Data slice power reduction disable for slice 0." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_0,RX Calibration state machine wait count for slice 0." line.long 0x8 "DDRSS_PHY_68" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" hexmask.long.word 0x8 16.--24. 1. "PHY_RX_CAL_DQ2_0,RX Calibration codes for DQ2 for slice 0." newline hexmask.long.byte 0x8 9.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--8. 1. "PHY_RX_CAL_DQ1_0,RX Calibration codes for DQ1 for slice 0." line.long 0xC "DDRSS_PHY_69" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" hexmask.long.word 0xC 16.--24. 1. "PHY_RX_CAL_DQ4_0,RX Calibration codes for DQ4 for slice 0." newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "PHY_RX_CAL_DQ3_0,RX Calibration codes for DQ3 for slice 0." line.long 0x10 "DDRSS_PHY_70" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--24. 1. "PHY_RX_CAL_DQ6_0,RX Calibration codes for DQ6 for slice 0." newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "PHY_RX_CAL_DQ5_0,RX Calibration codes for DQ5 for slice 0." line.long 0x14 "DDRSS_PHY_71" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--8. 1. "PHY_RX_CAL_DQ7_0,RX Calibration codes for DQ7 for slice 0." line.long 0x18 "DDRSS_PHY_72" hexmask.long.word 0x18 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--17. 1. "PHY_RX_CAL_DM_0,RX Calibration codes for DM for slice 0." line.long 0x1C "DDRSS_PHY_73" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--24. 1. "PHY_RX_CAL_FDBK_0,RX Calibration codes for FDBK for slice 0." newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--8. 1. "PHY_RX_CAL_DQS_0,RX Calibration codes for DQS for slice 0." rgroup.long 0x4128++0x3 line.long 0x0 "DDRSS_PHY_74" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_0,RX Calibration lock results for slice 0." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_RX_CAL_OBS_0,RX Calibration results for slice 0." group.long 0x412C++0x103 line.long 0x0 "DDRSS_PHY_75" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RX_CAL_COMP_VAL_0,Expected C value from RX pad for slice 0." "0,1" newline bitfld.long 0x0 23. "RESERVED" "0,1" hexmask.long.byte 0x0 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_0,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 0." newline bitfld.long 0x0 15. "RESERVED" "0,1" hexmask.long.byte 0x0 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_0,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 0." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_RX_CAL_DISABLE_0,RX CAL disable signal for slice 0 set 1 to bypass the rx calibration" "0,1" line.long 0x4 "DDRSS_PHY_76" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--26. 1. "PHY_PAD_RX_BIAS_EN_0,Controls RX_BIAS_EN pin for each pad for slice 0." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_0,RX offset calibration mask of all RX pad for slice 0." line.long 0x8 "DDRSS_PHY_77" hexmask.long.byte 0x8 26.--31. 1. "RESERVED" bitfld.long 0x8 24.--25. "PHY_DATA_DC_WEIGHT_0,Determines weight of average calculating for slice 0." "0,1,2,3" newline hexmask.long.byte 0x8 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_0,Determines timeout number of iteration for slice 0." hexmask.long.byte 0x8 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_0,Determines number of cycles to wait for each sample for slice 0." newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PHY_STATIC_TOG_DISABLE_0,Control to disable toggle during static activity for slice 0." line.long 0xC "DDRSS_PHY_78" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "PHY_DATA_DC_ADJUST_DIRECT_0,Adjust direction for slice 0." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_0,Duty cycle adjust threshold around the mid-point for slice 0." hexmask.long.byte 0xC 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_0,Duty cycle adjust sample count for slice 0." newline bitfld.long 0xC 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "PHY_DATA_DC_ADJUST_START_0,Duty cycle adjust starting value for slice 0." line.long 0x10 "DDRSS_PHY_79" hexmask.long.byte 0x10 27.--31. 1. "RESERVED" bitfld.long 0x10 24.--26. "PHY_FDBK_PWR_CTRL_0,Shutoff gate feedback IO to reduce power for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 18.--23. 1. "RESERVED" bitfld.long 0x10 16.--17. "PHY_DATA_DC_SW_RANK_0,Rank selection for software based duty cycle correction for slice 0." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "PHY_DATA_DC_CAL_START_0,Manual trigger for DCC for slice 0." "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "PHY_DATA_DC_CAL_POLARITY_0,Calibration polarity for slice 0." "0,1" line.long 0x14 "DDRSS_PHY_80" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PHY_SLICE_PWR_RDC_DISABLE_0,Data slice power reduction disable for slice 0." "0,1" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" bitfld.long 0x14 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0,Data slice DCC and RX_CAL block power reduction disable for slice 0." "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "PHY_RDPATH_GATE_DISABLE_0,Data slice read path power reduction disable for slice 0." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_0,Data slice slv_dly_control block power reduction disable for slice 0." "0,1" line.long 0x18 "DDRSS_PHY_81" bitfld.long 0x18 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x18 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_0,Data slice level FSM Error Info for slice 0." newline hexmask.long.byte 0x18 11.--15. 1. "RESERVED" hexmask.long.word 0x18 0.--10. 1. "PHY_PARITY_ERROR_REGIF_0,Inject parity error to register interface signals for slice 0." line.long 0x1C "DDRSS_PHY_82" bitfld.long 0x1C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x1C 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0,Data slice level FSM Error Info for slice 0." newline bitfld.long 0x1C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x1C 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_0,Data slice level FSM Error Info Mask for slice 0." line.long 0x20 "DDRSS_PHY_83" hexmask.long.word 0x20 21.--31. 1. "RESERVED" hexmask.long.byte 0x20 16.--20. 1. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0,Data slice level training/calibration Error Info for slice 0." newline bitfld.long 0x20 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 8.--12. 1. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0,Data slice level training/calibration Error Info Mask for slice 0." newline bitfld.long 0x20 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 0.--4. 1. "PHY_DS_TRAIN_CALIB_ERROR_INFO_0,Data slice level training/calibration Error Info for slice 0." line.long 0x24 "DDRSS_PHY_84" hexmask.long.byte 0x24 27.--31. 1. "RESERVED" bitfld.long 0x24 24.--26. "PHY_DQS_TSEL_ENABLE_0,Operation type tsel enables for DQS signals for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 8.--23. 1. "PHY_DQ_TSEL_SELECT_0,Operation type tsel select values for DQ/DM signals for slice 0." hexmask.long.byte 0x24 3.--7. 1. "RESERVED" newline bitfld.long 0x24 0.--2. "PHY_DQ_TSEL_ENABLE_0,Operation type tsel enables for DQ/DM signals for slice 0." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_PHY_85" bitfld.long 0x28 31. "RESERVED" "0,1" hexmask.long.byte 0x28 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_0,Data slice initial VREF training start value for slice 0." newline hexmask.long.byte 0x28 18.--23. 1. "RESERVED" bitfld.long 0x28 16.--17. "PHY_TWO_CYC_PREAMBLE_0,2 cycle preamble support for slice 0." "0,1,2,3" newline hexmask.long.word 0x28 0.--15. 1. "PHY_DQS_TSEL_SELECT_0,Operation type tsel select values for DQS signals for slice 0." line.long 0x2C "DDRSS_PHY_86" hexmask.long.byte 0x2C 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_0,Step size of WR DQ slave delay during No-Topology training for slice 0." hexmask.long.byte 0x2C 17.--23. 1. "RESERVED" newline bitfld.long 0x2C 16. "PHY_NTP_TRAIN_EN_0,Enable for No-Topology training for slice 0." "0,1" hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" newline bitfld.long 0x2C 8.--9. "PHY_VREF_TRAINING_CTRL_0,Data slice vref training enable control for slice 0." "0,1,2,3" bitfld.long 0x2C 7. "RESERVED" "0,1" newline hexmask.long.byte 0x2C 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_0,Data slice initial VREF training stop value for slice 0." line.long 0x30 "DDRSS_PHY_87" hexmask.long.byte 0x30 27.--31. 1. "RESERVED" hexmask.long.word 0x30 16.--26. 1. "PHY_NTP_WDQ_STOP_0,End of WR DQ slave delay in No-Topology training for slice 0." newline hexmask.long.byte 0x30 11.--15. 1. "RESERVED" hexmask.long.word 0x30 0.--10. 1. "PHY_NTP_WDQ_START_0,Starting WR DQ slave delay in No-Topology training for slice 0." line.long 0x34 "DDRSS_PHY_88" hexmask.long.byte 0x34 25.--31. 1. "RESERVED" bitfld.long 0x34 24. "PHY_SW_WDQLVL_DVW_MIN_EN_0,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 0." "0,1" newline hexmask.long.byte 0x34 18.--23. 1. "RESERVED" hexmask.long.word 0x34 8.--17. 1. "PHY_WDQLVL_DVW_MIN_0,Minimum data valid window across DQs and ranks for slice 0." newline hexmask.long.byte 0x34 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_0,Enable Bit for WR DQ during No-Topology training for slice 0." line.long 0x38 "DDRSS_PHY_89" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "PHY_PAD_RX_DCD_0_0,Controls RX_DCD pin for each pad for slice 0." newline bitfld.long 0x38 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 16.--20. 1. "PHY_PAD_TX_DCD_0,Controls TX_DCD pin for each pad for slice 0." newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.byte 0x38 8.--11. 1. "PHY_FAST_LVL_EN_0,Enable for fast multi-pattern window search for slice 0." newline bitfld.long 0x38 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "PHY_WDQLVL_PER_START_OFFSET_0,Peridic training start point offset for slice 0." line.long 0x3C "DDRSS_PHY_90" bitfld.long 0x3C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 24.--28. 1. "PHY_PAD_RX_DCD_4_0,Controls RX_DCD pin for each pad for slice 0." newline bitfld.long 0x3C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--20. 1. "PHY_PAD_RX_DCD_3_0,Controls RX_DCD pin for each pad for slice 0." newline bitfld.long 0x3C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 8.--12. 1. "PHY_PAD_RX_DCD_2_0,Controls RX_DCD pin for each pad for slice 0." newline bitfld.long 0x3C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 0.--4. 1. "PHY_PAD_RX_DCD_1_0,Controls RX_DCD pin for each pad for slice 0." line.long 0x40 "DDRSS_PHY_91" bitfld.long 0x40 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 24.--28. 1. "PHY_PAD_DM_RX_DCD_0,Controls RX_DCD pin for dm pad for slice 0." newline bitfld.long 0x40 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 16.--20. 1. "PHY_PAD_RX_DCD_7_0,Controls RX_DCD pin for each pad for slice 0." newline bitfld.long 0x40 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 8.--12. 1. "PHY_PAD_RX_DCD_6_0,Controls RX_DCD pin for each pad for slice 0." newline bitfld.long 0x40 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 0.--4. 1. "PHY_PAD_RX_DCD_5_0,Controls RX_DCD pin for each pad for slice 0." line.long 0x44 "DDRSS_PHY_92" hexmask.long.word 0x44 22.--31. 1. "RESERVED" hexmask.long.byte 0x44 16.--21. 1. "PHY_PAD_DSLICE_IO_CFG_0,Controls PCLK/PARK pin for pad for slice 0." newline bitfld.long 0x44 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 8.--12. 1. "PHY_PAD_FDBK_RX_DCD_0,Controls RX_DCD pin for fdbk pad for slice 0." newline bitfld.long 0x44 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 0.--4. 1. "PHY_PAD_DQS_RX_DCD_0,Controls RX_DCD pin for dqs pad for slice 0." line.long 0x48 "DDRSS_PHY_93" hexmask.long.byte 0x48 26.--31. 1. "RESERVED" hexmask.long.word 0x48 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_0,Read DQ1 slave delay setting for slice 0." newline hexmask.long.byte 0x48 10.--15. 1. "RESERVED" hexmask.long.word 0x48 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_0,Read DQ0 slave delay setting for slice 0." line.long 0x4C "DDRSS_PHY_94" hexmask.long.byte 0x4C 26.--31. 1. "RESERVED" hexmask.long.word 0x4C 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_0,Read DQ3 slave delay setting for slice 0." newline hexmask.long.byte 0x4C 10.--15. 1. "RESERVED" hexmask.long.word 0x4C 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_0,Read DQ2 slave delay setting for slice 0." line.long 0x50 "DDRSS_PHY_95" hexmask.long.byte 0x50 26.--31. 1. "RESERVED" hexmask.long.word 0x50 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_0,Read DQ5 slave delay setting for slice 0." newline hexmask.long.byte 0x50 10.--15. 1. "RESERVED" hexmask.long.word 0x50 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_0,Read DQ4 slave delay setting for slice 0." line.long 0x54 "DDRSS_PHY_96" hexmask.long.byte 0x54 26.--31. 1. "RESERVED" hexmask.long.word 0x54 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_0,Read DQ7 slave delay setting for slice 0." newline hexmask.long.byte 0x54 10.--15. 1. "RESERVED" hexmask.long.word 0x54 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_0,Read DQ6 slave delay setting for slice 0." line.long 0x58 "DDRSS_PHY_97" hexmask.long.word 0x58 19.--31. 1. "RESERVED" bitfld.long 0x58 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_0,Determines DCC CAL clock for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 10.--15. 1. "RESERVED" hexmask.long.word 0x58 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_0,Read DM/DBI slave delay setting for slice 0." line.long 0x5C "DDRSS_PHY_98" hexmask.long.byte 0x5C 24.--31. 1. "PHY_DQS_OE_TIMING_0,Start/end timing values for DQS output enable signals for slice 0." hexmask.long.byte 0x5C 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_0,Start/end timing values for DQ/DM write based termination enable and select signals for slice 0." newline hexmask.long.byte 0x5C 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_0,Start/end timing values for DQ/DM read based termination enable and select signals for slice 0." hexmask.long.byte 0x5C 0.--7. 1. "PHY_DQ_OE_TIMING_0,Start/end timing values for DQ/DM output enable signals for slice 0." line.long 0x60 "DDRSS_PHY_99" hexmask.long.byte 0x60 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_0,Start/end timing values for DQS write based termination enable and select signals for slice 0." hexmask.long.byte 0x60 16.--23. 1. "PHY_DQS_OE_RD_TIMING_0,Start/end timing values for DQS read based OE extension for slice 0." newline hexmask.long.byte 0x60 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_0,Start/end timing values for DQS read based termination enable and select signals for slice 0." hexmask.long.byte 0x60 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x60 0.--3. 1. "PHY_IO_PAD_DELAY_TIMING_0,Feedback pad's OPAD and IPAD delay timing for slice 0." line.long 0x64 "DDRSS_PHY_100" hexmask.long.byte 0x64 28.--31. 1. "RESERVED" hexmask.long.word 0x64 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_0,Pad VREF control settings for DQ slice 0." newline hexmask.long.word 0x64 0.--15. 1. "PHY_VREF_SETTING_TIME_0,Number of cycles for vref settle after setting is changed for slice 0." line.long 0x68 "DDRSS_PHY_101" hexmask.long.byte 0x68 26.--31. 1. "RESERVED" bitfld.long 0x68 24.--25. "PHY_RDDATA_EN_IE_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0." "0,1,2,3" newline hexmask.long.byte 0x68 16.--23. 1. "PHY_DQS_IE_TIMING_0,Start/end timing values for DQS input enable signals for slice 0." hexmask.long.byte 0x68 8.--15. 1. "PHY_DQ_IE_TIMING_0,Start/end timing values for DQ/DM input enable signals for slice 0." newline hexmask.long.byte 0x68 1.--7. 1. "RESERVED" bitfld.long 0x68 0. "PHY_PER_CS_TRAINING_EN_0,Enables the per-rank training and read/write timing capabilities for slice 0." "0,1" line.long 0x6C "DDRSS_PHY_102" bitfld.long 0x6C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 24.--28. 1. "PHY_RDDATA_EN_OE_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 0." newline bitfld.long 0x6C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 16.--20. 1. "PHY_RDDATA_EN_TSEL_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0." newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED" bitfld.long 0x6C 8. "PHY_DBI_MODE_0,DBI mode for slice 0." "0,1" newline hexmask.long.byte 0x6C 2.--7. 1. "RESERVED" bitfld.long 0x6C 0.--1. "PHY_IE_MODE_0,Input enable mode bits for slice 0." "0,1,2,3" line.long 0x70 "DDRSS_PHY_103" bitfld.long 0x70 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x70 24.--29. 1. "PHY_MASTER_DELAY_STEP_0,Incremental step size for master delay line locking algorithm for slice 0." newline hexmask.long.byte 0x70 19.--23. 1. "RESERVED" hexmask.long.word 0x70 8.--18. 1. "PHY_MASTER_DELAY_START_0,Start value for master delay line locking algorithm for slice 0." newline hexmask.long.byte 0x70 4.--7. 1. "RESERVED" hexmask.long.byte 0x70 0.--3. 1. "PHY_SW_MASTER_MODE_0,Master delay line override settings for slice 0." line.long 0x74 "DDRSS_PHY_104" hexmask.long.byte 0x74 24.--31. 1. "PHY_WRLVL_DLY_STEP_0,DQS slave delay step size during write leveling for slice 0." hexmask.long.byte 0x74 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x74 16.--19. 1. "PHY_RPTR_UPDATE_0,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 0." hexmask.long.byte 0x74 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_0,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 0." newline hexmask.long.byte 0x74 0.--7. 1. "PHY_MASTER_DELAY_WAIT_0,Wait cycles for master delay line locking algorithm for slice 0." line.long 0x78 "DDRSS_PHY_105" bitfld.long 0x78 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x78 24.--28. 1. "PHY_GTLVL_RESP_WAIT_CNT_0,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 0." newline hexmask.long.byte 0x78 20.--23. 1. "RESERVED" hexmask.long.byte 0x78 16.--19. 1. "PHY_GTLVL_DLY_STEP_0,DQS slave delay step size during gate training for slice 0." newline bitfld.long 0x78 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x78 8.--13. 1. "PHY_WRLVL_RESP_WAIT_CNT_0,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 0." newline hexmask.long.byte 0x78 4.--7. 1. "RESERVED" hexmask.long.byte 0x78 0.--3. 1. "PHY_WRLVL_DLY_FINE_STEP_0,DQS slave delay fine step size during write leveling for slice 0." line.long 0x7C "DDRSS_PHY_106" hexmask.long.byte 0x7C 26.--31. 1. "RESERVED" hexmask.long.word 0x7C 16.--25. 1. "PHY_GTLVL_FINAL_STEP_0,Final backup step delay used in gate training algorithm for slice 0." newline hexmask.long.byte 0x7C 10.--15. 1. "RESERVED" hexmask.long.word 0x7C 0.--9. 1. "PHY_GTLVL_BACK_STEP_0,Interim backup step delay used in gate training algorithm for slice 0." line.long 0x80 "DDRSS_PHY_107" hexmask.long.byte 0x80 28.--31. 1. "RESERVED" hexmask.long.byte 0x80 24.--27. 1. "PHY_RDLVL_DLY_STEP_0,DQS slave delay step size during read leveling for slice 0." newline hexmask.long.byte 0x80 17.--23. 1. "RESERVED" bitfld.long 0x80 16. "PHY_TOGGLE_PRE_SUPPORT_0,Support the toggle read preamble for LPDDR4 for slice 0." "0,1" newline hexmask.long.byte 0x80 12.--15. 1. "RESERVED" hexmask.long.byte 0x80 8.--11. 1. "PHY_WDQLVL_QTR_DLY_STEP_0,Defines the step granularity for the logic to use once an edge is found for slice 0." newline hexmask.long.byte 0x80 0.--7. 1. "PHY_WDQLVL_DLY_STEP_0,DQ slave delay step size during write data leveling for slice 0." line.long 0x84 "DDRSS_PHY_108" hexmask.long.tbyte 0x84 10.--31. 1. "RESERVED" hexmask.long.word 0x84 0.--9. 1. "PHY_RDLVL_MAX_EDGE_0,The maximun rdlvl slave delay search window for read eye training for slice 0." line.long 0x88 "DDRSS_PHY_109" bitfld.long 0x88 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x88 24.--29. 1. "PHY_RDLVL_PER_START_OFFSET_0,Peridic training start point offset for slice 0." newline hexmask.long.byte 0x88 17.--23. 1. "RESERVED" bitfld.long 0x88 16. "PHY_SW_RDLVL_DVW_MIN_EN_0,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 0." "0,1" newline hexmask.long.byte 0x88 10.--15. 1. "RESERVED" hexmask.long.word 0x88 0.--9. 1. "PHY_RDLVL_DVW_MIN_0,Minimum data valid window across DQs and ranks for slice 0." line.long 0x8C "DDRSS_PHY_110" hexmask.long.word 0x8C 18.--31. 1. "RESERVED" bitfld.long 0x8C 16.--17. "PHY_DATA_DC_INIT_DISABLE_0,Disable duty cycle adjust at initialization for slice 0." "0,1,2,3" newline hexmask.long.byte 0x8C 11.--15. 1. "RESERVED" bitfld.long 0x8C 8.--10. "PHY_WRPATH_GATE_TIMING_0,Write path clock gating timing for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8C 2.--7. 1. "RESERVED" bitfld.long 0x8C 0.--1. "PHY_WRPATH_GATE_DISABLE_0,Write path clock gating disable for slice 0." "0,1,2,3" line.long 0x90 "DDRSS_PHY_111" hexmask.long.byte 0x90 27.--31. 1. "RESERVED" hexmask.long.word 0x90 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_0,Initial value of write DQ slave delay for slice 0." newline hexmask.long.byte 0x90 10.--15. 1. "RESERVED" hexmask.long.word 0x90 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_0,Initial value of write DQS slave delay for slice 0." line.long 0x94 "DDRSS_PHY_112" hexmask.long.byte 0x94 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0,Clock measurement cell threshold offset for differential signals for slice 0." hexmask.long.byte 0x94 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_0,Clock measurement cell threshold offset for single ended signals for slice 0." newline hexmask.long.byte 0x94 9.--15. 1. "RESERVED" bitfld.long 0x94 8. "PHY_DATA_DC_WDQLVL_ENABLE_0,Enable duty cycle adjust during write DQ training for slice 0." "0,1" newline hexmask.long.byte 0x94 1.--7. 1. "RESERVED" bitfld.long 0x94 0. "PHY_DATA_DC_WRLVL_ENABLE_0,Enable duty cycle adjust during write leveling for slice 0." "0,1" line.long 0x98 "DDRSS_PHY_113" hexmask.long.word 0x98 21.--31. 1. "RESERVED" hexmask.long.byte 0x98 16.--20. 1. "PHY_RDDATA_EN_DLY_0,Number of cycles that the dfi_rddata_en signal is early for slice 0." newline bitfld.long 0x98 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x98 8.--13. 1. "PHY_MEAS_DLY_STEP_ENABLE_0,Data slice training step definition using phy_meas_dly_step_value for slice 0." newline bitfld.long 0x98 7. "RESERVED" "0,1" hexmask.long.byte 0x98 0.--6. 1. "PHY_WDQ_OSC_DELTA_0,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 0." line.long 0x9C "DDRSS_PHY_114" hexmask.long 0x9C 0.--31. 1. "PHY_DQ_DM_SWIZZLE0_0,DQ/DM bit swizzling 0 for slice 0." line.long 0xA0 "DDRSS_PHY_115" hexmask.long 0xA0 4.--31. 1. "RESERVED" hexmask.long.byte 0xA0 0.--3. 1. "PHY_DQ_DM_SWIZZLE1_0,DQ/DM bit swizzling 1 for slice 0." line.long 0xA4 "DDRSS_PHY_116" hexmask.long.byte 0xA4 27.--31. 1. "RESERVED" hexmask.long.word 0xA4 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_0,Write clock slave delay setting for DQ1 for slice 0." newline hexmask.long.byte 0xA4 11.--15. 1. "RESERVED" hexmask.long.word 0xA4 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_0,Write clock slave delay setting for DQ0 for slice 0." line.long 0xA8 "DDRSS_PHY_117" hexmask.long.byte 0xA8 27.--31. 1. "RESERVED" hexmask.long.word 0xA8 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_0,Write clock slave delay setting for DQ3 for slice 0." newline hexmask.long.byte 0xA8 11.--15. 1. "RESERVED" hexmask.long.word 0xA8 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_0,Write clock slave delay setting for DQ2 for slice 0." line.long 0xAC "DDRSS_PHY_118" hexmask.long.byte 0xAC 27.--31. 1. "RESERVED" hexmask.long.word 0xAC 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_0,Write clock slave delay setting for DQ5 for slice 0." newline hexmask.long.byte 0xAC 11.--15. 1. "RESERVED" hexmask.long.word 0xAC 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_0,Write clock slave delay setting for DQ4 for slice 0." line.long 0xB0 "DDRSS_PHY_119" hexmask.long.byte 0xB0 27.--31. 1. "RESERVED" hexmask.long.word 0xB0 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_0,Write clock slave delay setting for DQ7 for slice 0." newline hexmask.long.byte 0xB0 11.--15. 1. "RESERVED" hexmask.long.word 0xB0 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_0,Write clock slave delay setting for DQ6 for slice 0." line.long 0xB4 "DDRSS_PHY_120" hexmask.long.byte 0xB4 26.--31. 1. "RESERVED" hexmask.long.word 0xB4 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_0,Write clock slave delay setting for DQS for slice 0." newline hexmask.long.byte 0xB4 11.--15. 1. "RESERVED" hexmask.long.word 0xB4 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_0,Write clock slave delay setting for DM for slice 0." line.long 0xB8 "DDRSS_PHY_121" hexmask.long.word 0xB8 18.--31. 1. "RESERVED" hexmask.long.word 0xB8 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ0 for slice 0." newline hexmask.long.byte 0xB8 2.--7. 1. "RESERVED" bitfld.long 0xB8 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_0,Write level threshold adjust value based on those thresholds for DQS for slice 0." "0,1,2,3" line.long 0xBC "DDRSS_PHY_122" hexmask.long.byte 0xBC 26.--31. 1. "RESERVED" hexmask.long.word 0xBC 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ1 for slice 0." newline hexmask.long.byte 0xBC 10.--15. 1. "RESERVED" hexmask.long.word 0xBC 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ0 for slice 0." line.long 0xC0 "DDRSS_PHY_123" hexmask.long.byte 0xC0 26.--31. 1. "RESERVED" hexmask.long.word 0xC0 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ2 for slice 0." newline hexmask.long.byte 0xC0 10.--15. 1. "RESERVED" hexmask.long.word 0xC0 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ1 for slice 0." line.long 0xC4 "DDRSS_PHY_124" hexmask.long.byte 0xC4 26.--31. 1. "RESERVED" hexmask.long.word 0xC4 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ3 for slice 0." newline hexmask.long.byte 0xC4 10.--15. 1. "RESERVED" hexmask.long.word 0xC4 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ2 for slice 0." line.long 0xC8 "DDRSS_PHY_125" hexmask.long.byte 0xC8 26.--31. 1. "RESERVED" hexmask.long.word 0xC8 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ4 for slice 0." newline hexmask.long.byte 0xC8 10.--15. 1. "RESERVED" hexmask.long.word 0xC8 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ3 for slice 0." line.long 0xCC "DDRSS_PHY_126" hexmask.long.byte 0xCC 26.--31. 1. "RESERVED" hexmask.long.word 0xCC 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ5 for slice 0." newline hexmask.long.byte 0xCC 10.--15. 1. "RESERVED" hexmask.long.word 0xCC 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ4 for slice 0." line.long 0xD0 "DDRSS_PHY_127" hexmask.long.byte 0xD0 26.--31. 1. "RESERVED" hexmask.long.word 0xD0 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ6 for slice 0." newline hexmask.long.byte 0xD0 10.--15. 1. "RESERVED" hexmask.long.word 0xD0 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ5 for slice 0." line.long 0xD4 "DDRSS_PHY_128" hexmask.long.byte 0xD4 26.--31. 1. "RESERVED" hexmask.long.word 0xD4 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ7 for slice 0." newline hexmask.long.byte 0xD4 10.--15. 1. "RESERVED" hexmask.long.word 0xD4 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ6 for slice 0." line.long 0xD8 "DDRSS_PHY_129" hexmask.long.byte 0xD8 26.--31. 1. "RESERVED" hexmask.long.word 0xD8 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DM for slice 0." newline hexmask.long.byte 0xD8 10.--15. 1. "RESERVED" hexmask.long.word 0xD8 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ7 for slice 0." line.long 0xDC "DDRSS_PHY_130" hexmask.long.byte 0xDC 26.--31. 1. "RESERVED" hexmask.long.word 0xDC 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_0,Read DQS slave delay setting for slice 0." newline hexmask.long.byte 0xDC 10.--15. 1. "RESERVED" hexmask.long.word 0xDC 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DM for slice 0." line.long 0xE0 "DDRSS_PHY_131" hexmask.long.byte 0xE0 26.--31. 1. "RESERVED" hexmask.long.word 0xE0 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_0,Write level delay threshold above which will be considered in previous cycle for slice 0." newline hexmask.long.byte 0xE0 11.--15. 1. "RESERVED" bitfld.long 0xE0 8.--10. "PHY_WRITE_PATH_LAT_ADD_0,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE0 4.--7. 1. "RESERVED" hexmask.long.byte 0xE0 0.--3. 1. "PHY_RDDQS_LATENCY_ADJUST_0,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0." line.long 0xE4 "DDRSS_PHY_132" hexmask.long.word 0xE4 17.--31. 1. "RESERVED" bitfld.long 0xE4 16. "PHY_WRLVL_EARLY_FORCE_ZERO_0,Force the final write level delay value (that meets the early threshold) to 0 for slice 0." "0,1" newline hexmask.long.byte 0xE4 10.--15. 1. "RESERVED" hexmask.long.word 0xE4 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0,Write level delay threshold below which will add a cycle of write path latency for slice 0." line.long 0xE8 "DDRSS_PHY_133" hexmask.long.word 0xE8 20.--31. 1. "RESERVED" hexmask.long.byte 0xE8 16.--19. 1. "PHY_GTLVL_LAT_ADJ_START_0,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 0." newline hexmask.long.byte 0xE8 10.--15. 1. "RESERVED" hexmask.long.word 0xE8 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_0,Initial read DQS gate slave delay setting during gate training for slice 0." line.long 0xEC "DDRSS_PHY_134" hexmask.long.byte 0xEC 25.--31. 1. "RESERVED" bitfld.long 0xEC 24. "PHY_NTP_PASS_0,Indicates if No-topology training found a passing result for slice 0." "0,1" newline hexmask.long.byte 0xEC 20.--23. 1. "RESERVED" hexmask.long.byte 0xEC 16.--19. 1. "PHY_NTP_WRLAT_START_0,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 0." newline hexmask.long.byte 0xEC 11.--15. 1. "RESERVED" hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_0,Initial DQ/DM slave delay setting during write data leveling for slice 0." line.long 0xF0 "DDRSS_PHY_135" hexmask.long.tbyte 0xF0 10.--31. 1. "RESERVED" hexmask.long.word 0xF0 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0,Read leveling starting value for the DQS/DQ slave delay settings for slice 0." line.long 0xF4 "DDRSS_PHY_136" hexmask.long.byte 0xF4 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." hexmask.long.byte 0xF4 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." newline hexmask.long.byte 0xF4 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." hexmask.long.byte 0xF4 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." line.long 0xF8 "DDRSS_PHY_137" hexmask.long.byte 0xF8 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." hexmask.long.byte 0xF8 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." newline hexmask.long.byte 0xF8 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." hexmask.long.byte 0xF8 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." line.long 0xFC "DDRSS_PHY_138" hexmask.long.word 0xFC 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_0,Setting for boost P/N of pad for slice 0." hexmask.long.byte 0xFC 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." newline hexmask.long.byte 0xFC 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0." line.long 0x100 "DDRSS_PHY_139" hexmask.long.word 0x100 18.--31. 1. "RESERVED" bitfld.long 0x100 16.--17. "PHY_DQS_FFE_0,TX_FFE setting for DQS pad for slice 0." "0,1,2,3" newline hexmask.long.byte 0x100 10.--15. 1. "RESERVED" bitfld.long 0x100 8.--9. "PHY_DQ_FFE_0,TX_FFE setting for DQ/DM pad for slice 0." "0,1,2,3" newline bitfld.long 0x100 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x100 0.--5. 1. "PHY_DSLICE_PAD_RX_CTLE_SETTING_0,Setting for RX ctle P/N of pad for slice 0." group.long 0x4400++0x27 line.long 0x0 "DDRSS_PHY_256" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--19. 1. "PHY_IO_PAD_DELAY_TIMING_BYPASS_1,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 1." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_1,Write data clock bypass mode slave delay setting for slice 1.} PADDING_BEFORE" line.long 0x4 "DDRSS_PHY_257" hexmask.long.word 0x4 19.--31. 1. "RESERVED" bitfld.long 0x4 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_1,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1,Write DQS bypass mode slave delay setting for slice 1." line.long 0x8 "DDRSS_PHY_258" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "PHY_CLK_BYPASS_OVERRIDE_1,Bypass mode override setting for slice 1." "0,1" newline hexmask.long.byte 0x8 18.--23. 1. "RESERVED" bitfld.long 0x8 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_1,Two_cycle_preamble for bypass mode for slice 1." "0,1,2,3" newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1,Read DQS bypass mode slave delay setting for slice 1." line.long 0xC "DDRSS_PHY_259" bitfld.long 0xC 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 24.--29. 1. "PHY_SW_WRDQ3_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 1." newline bitfld.long 0xC 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 16.--21. 1. "PHY_SW_WRDQ2_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 1." newline bitfld.long 0xC 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 8.--13. 1. "PHY_SW_WRDQ1_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 1." newline bitfld.long 0xC 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "PHY_SW_WRDQ0_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 1." line.long 0x10 "DDRSS_PHY_260" bitfld.long 0x10 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 24.--29. 1. "PHY_SW_WRDQ7_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 1." newline bitfld.long 0x10 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 16.--21. 1. "PHY_SW_WRDQ6_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 1." newline bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 8.--13. 1. "PHY_SW_WRDQ5_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 1." newline bitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 0.--5. 1. "PHY_SW_WRDQ4_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 1." line.long 0x14 "DDRSS_PHY_261" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_1,When set a register write will update parameters for all ranks at the same time in slice 1." "0,1" newline hexmask.long.byte 0x14 18.--23. 1. "RESERVED" bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_1,Per-rank CS map for slice 1." "0,1,2,3" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED" hexmask.long.byte 0x14 8.--11. 1. "PHY_SW_WRDQS_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 1." newline bitfld.long 0x14 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 0.--5. 1. "PHY_SW_WRDM_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 1." line.long 0x18 "DDRSS_PHY_262" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1." newline bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 16.--20. 1. "PHY_LP4_BOOT_RDDATA_EN_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 1." newline hexmask.long.byte 0x18 10.--15. 1. "RESERVED" bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1." "0,1,2,3" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED" bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_1,For per-rank training indicates which rank's paramters are read/written for slice 1." "0,1" line.long 0x1C "DDRSS_PHY_263" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 1." newline hexmask.long.byte 0x1C 18.--23. 1. "RESERVED" bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1,For LPDDR4 boot frequency write path clock gating disable for slice 1." "0,1,2,3" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED" hexmask.long.byte 0x1C 8.--11. 1. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED" hexmask.long.byte 0x1C 0.--3. 1. "PHY_LP4_BOOT_RPTR_UPDATE_1,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 1." line.long 0x20 "DDRSS_PHY_264" hexmask.long.byte 0x20 25.--31. 1. "RESERVED" bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_1,Loopback read only test timeout mechanism enable for slice 1." "0,1" newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_1,Loopback control bits for slice 1." newline hexmask.long.byte 0x20 2.--7. 1. "RESERVED" bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_1,Loopback control en for slice 1." "0,1,2,3" line.long 0x24 "DDRSS_PHY_265" hexmask.long 0x24 0.--31. 1. "PHY_AUTO_TIMING_MARGIN_CONTROL_1,Auto timing marging control bits for slice 1." rgroup.long 0x4428++0x3 line.long 0x0 "DDRSS_PHY_266" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_1,Observation register for the auto_timing_margin for slice 1." group.long 0x442C++0x13 line.long 0x0 "DDRSS_PHY_267" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RDLVL_MULTI_PATT_ENABLE_1,Read Leveling Multi-pattern enable for slice 1." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" hexmask.long.word 0x0 8.--16. 1. "PHY_PRBS_PATTERN_MASK_1,PRBS7 mask signal for slice 1." newline bitfld.long 0x0 7. "RESERVED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "PHY_PRBS_PATTERN_START_1,PRBS7 start pattern for slice 1." line.long 0x4 "DDRSS_PHY_268" hexmask.long.word 0x4 23.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--22. 1. "PHY_VREF_TRAIN_OBS_1,Observation register for best vref value for slice 1." newline bitfld.long 0x4 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "PHY_VREF_INITIAL_STEPSIZE_1,Data slice initial VREF training step size for slice 1." newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED" bitfld.long 0x4 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_1,Read Leveling read level windows disable reset for slice 1." "0,1" line.long 0x8 "DDRSS_PHY_269" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "SC_PHY_SNAP_OBS_REGS_1,Initiates a snapshot of the internal observation registers for slice 1." "0,1" newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED" hexmask.long.byte 0x8 16.--19. 1. "PHY_GATE_ERROR_DELAY_SELECT_1,Number of cycles to wait for the DQS gate to close before flagging an error for slice 1." newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1,Read DQS data clock bypass mode slave delay setting for slice 1." line.long 0xC "DDRSS_PHY_270" hexmask.long.byte 0xC 27.--31. 1. "RESERVED" bitfld.long 0xC 24.--26. "PHY_MEM_CLASS_1,Indicates the type of DRAM for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 17.--23. 1. "RESERVED" bitfld.long 0xC 16. "PHY_LPDDR_1,Adds a cycle of delay for the slice 1 to match the address slice." "0,1" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_1,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 1." line.long 0x10 "DDRSS_PHY_271" hexmask.long.word 0x10 18.--31. 1. "RESERVED" bitfld.long 0x10 16.--17. "ON_FLY_GATE_ADJUST_EN_1,Control the on-the-fly gate adjustment for slice 1." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_1,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 1." rgroup.long 0x4440++0x3 line.long 0x0 "DDRSS_PHY_272" hexmask.long 0x0 0.--31. 1. "PHY_GATE_TRACKING_OBS_1,Report the on-the-fly gate measurement result for slice 1." group.long 0x4444++0x6B line.long 0x0 "DDRSS_PHY_273" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" bitfld.long 0x0 8.--9. "PHY_LP4_PST_AMBLE_1,Controls the read postamble extension for LPDDR4 for slice 1." "0,1,2,3" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_DFI40_POLARITY_1,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 1." "0,1" line.long 0x4 "DDRSS_PHY_274" hexmask.long 0x4 0.--31. 1. "PHY_RDLVL_PATT8_1,Read leveling pattern 8 data for slice 1." line.long 0x8 "DDRSS_PHY_275" hexmask.long 0x8 0.--31. 1. "PHY_RDLVL_PATT9_1,Read leveling pattern 9 data for slice 1." line.long 0xC "DDRSS_PHY_276" hexmask.long 0xC 0.--31. 1. "PHY_RDLVL_PATT10_1,Read leveling pattern 10 data for slice 1." line.long 0x10 "DDRSS_PHY_277" hexmask.long 0x10 0.--31. 1. "PHY_RDLVL_PATT11_1,Read leveling pattern 11 data for slice 1." line.long 0x14 "DDRSS_PHY_278" hexmask.long 0x14 0.--31. 1. "PHY_RDLVL_PATT12_1,Read leveling pattern 12 data for slice 1." line.long 0x18 "DDRSS_PHY_279" hexmask.long 0x18 0.--31. 1. "PHY_RDLVL_PATT13_1,Read leveling pattern 13 data for slice 1." line.long 0x1C "DDRSS_PHY_280" hexmask.long 0x1C 0.--31. 1. "PHY_RDLVL_PATT14_1,Read leveling pattern 14 data for slice 1." line.long 0x20 "DDRSS_PHY_281" hexmask.long 0x20 0.--31. 1. "PHY_RDLVL_PATT15_1,Read leveling pattern 15 data for slice 1." line.long 0x24 "DDRSS_PHY_282" hexmask.long.byte 0x24 27.--31. 1. "RESERVED" bitfld.long 0x24 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_1,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 20.--23. 1. "RESERVED" hexmask.long.byte 0x24 16.--19. 1. "PHY_MASTER_DLY_LOCK_OBS_SELECT_1,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 1." newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED" bitfld.long 0x24 8. "PHY_SW_FIFO_PTR_RST_DISABLE_1,Disables automatic reset of the read entry FIFO pointers for slice 1." "0,1" newline hexmask.long.byte 0x24 3.--7. 1. "RESERVED" bitfld.long 0x24 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_1,Reserved for future use for slice 1." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_PHY_283" hexmask.long.byte 0x28 28.--31. 1. "RESERVED" hexmask.long.byte 0x28 24.--27. 1. "PHY_FIFO_PTR_OBS_SELECT_1,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 1." newline hexmask.long.byte 0x28 20.--23. 1. "RESERVED" hexmask.long.byte 0x28 16.--19. 1. "PHY_WR_SHIFT_OBS_SELECT_1,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 1." newline hexmask.long.byte 0x28 12.--15. 1. "RESERVED" hexmask.long.byte 0x28 8.--11. 1. "PHY_WR_ENC_OBS_SELECT_1,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 1." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED" hexmask.long.byte 0x28 0.--3. 1. "PHY_RDDQS_DQ_ENC_OBS_SELECT_1,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 1." line.long 0x2C "DDRSS_PHY_284" hexmask.long.byte 0x2C 24.--31. 1. "PHY_WRLVL_PER_START_1,Observation register for write leveling status for slice 1." hexmask.long.byte 0x2C 18.--23. 1. "RESERVED" newline bitfld.long 0x2C 16.--17. "PHY_WRLVL_ALGO_1,Write leveling algorithm selection for slice 1." "0,1,2,3" hexmask.long.byte 0x2C 9.--15. 1. "RESERVED" newline bitfld.long 0x2C 8. "SC_PHY_LVL_DEBUG_CONT_1,Allows the leveling state machine to advance (when in debug mode) for slice 1." "0,1" hexmask.long.byte 0x2C 1.--7. 1. "RESERVED" newline bitfld.long 0x2C 0. "PHY_LVL_DEBUG_MODE_1,Enables leveling debug mode for slice 1." "0,1" line.long 0x30 "DDRSS_PHY_285" hexmask.long.byte 0x30 24.--31. 1. "RESERVED" hexmask.long.byte 0x30 16.--23. 1. "PHY_DQ_MASK_1,For ECC slice should set this register to do DQ bit mask for slice 1." newline hexmask.long.byte 0x30 12.--15. 1. "RESERVED" hexmask.long.byte 0x30 8.--11. 1. "PHY_WRLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 1." newline bitfld.long 0x30 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x30 0.--5. 1. "PHY_WRLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during write leveling for slice 1." line.long 0x34 "DDRSS_PHY_286" hexmask.long.byte 0x34 28.--31. 1. "RESERVED" hexmask.long.byte 0x34 24.--27. 1. "PHY_GTLVL_UPDT_WAIT_CNT_1,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 1." newline bitfld.long 0x34 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x34 16.--21. 1. "PHY_GTLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during gate training for slice 1." newline hexmask.long.byte 0x34 10.--15. 1. "RESERVED" hexmask.long.word 0x34 0.--9. 1. "PHY_GTLVL_PER_START_1,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 1." line.long 0x38 "DDRSS_PHY_287" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 1." newline hexmask.long.byte 0x38 18.--23. 1. "RESERVED" bitfld.long 0x38 16.--17. "PHY_RDLVL_OP_MODE_1,Read leveling algorithm select for slice 1." "0,1,2,3" newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.byte 0x38 8.--11. 1. "PHY_RDLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 1." newline bitfld.long 0x38 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "PHY_RDLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during read leveling for slice 1." line.long 0x3C "DDRSS_PHY_288" bitfld.long 0x3C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x3C 24.--29. 1. "PHY_WDQLVL_BURST_CNT_1,Defines the write/read burst length in bytes during the write data leveling sequence for slice 1." newline hexmask.long.byte 0x3C 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_1,Defines the minimum gap requirment for the LE and TE window for slice 1." hexmask.long.byte 0x3C 8.--15. 1. "PHY_RDLVL_DATA_MASK_1,Per-bit mask for read leveling for slice 1." newline hexmask.long.byte 0x3C 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 1." line.long 0x40 "DDRSS_PHY_289" hexmask.long.byte 0x40 28.--31. 1. "RESERVED" hexmask.long.byte 0x40 24.--27. 1. "PHY_WDQLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 1." newline hexmask.long.byte 0x40 19.--23. 1. "RESERVED" hexmask.long.word 0x40 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1,Defines the write/read burst length in bytes during the write data leveling sequence for slice 1." newline hexmask.long.byte 0x40 3.--7. 1. "RESERVED" bitfld.long 0x40 0.--2. "PHY_WDQLVL_PATT_1,Defines the training patterns to be used during the write data leveling sequence for slice 1." "0,1,2,3,4,5,6,7" line.long 0x44 "DDRSS_PHY_290" hexmask.long.word 0x44 17.--31. 1. "RESERVED" bitfld.long 0x44 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_1,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 1." "0,1" newline hexmask.long.byte 0x44 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_1,Select value to map specific information during or post periodic write data leveling for slice 1." hexmask.long.byte 0x44 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x44 0.--3. 1. "PHY_WDQLVL_DQDM_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 1." line.long 0x48 "DDRSS_PHY_291" hexmask.long.tbyte 0x48 9.--31. 1. "RESERVED" hexmask.long.word 0x48 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_1,Per-bit mask for write data leveling for slice 1." line.long 0x4C "DDRSS_PHY_292" hexmask.long 0x4C 0.--31. 1. "PHY_USER_PATT0_1,User-defined pattern to be used during write data leveling for slice 1." line.long 0x50 "DDRSS_PHY_293" hexmask.long 0x50 0.--31. 1. "PHY_USER_PATT1_1,User-defined pattern to be used during write data leveling for slice 1." line.long 0x54 "DDRSS_PHY_294" hexmask.long 0x54 0.--31. 1. "PHY_USER_PATT2_1,User-defined pattern to be used during write data leveling for slice 1." line.long 0x58 "DDRSS_PHY_295" hexmask.long 0x58 0.--31. 1. "PHY_USER_PATT3_1,User-defined pattern to be used during write data leveling for slice 1." line.long 0x5C "DDRSS_PHY_296" hexmask.long.word 0x5C 17.--31. 1. "RESERVED" bitfld.long 0x5C 16. "PHY_NTP_MULT_TRAIN_1,Control for single pass only No-Topology training for slice 1." "0,1" newline hexmask.long.word 0x5C 0.--15. 1. "PHY_USER_PATT4_1,User-defined pattern to be used during write data leveling for slice 1." line.long 0x60 "DDRSS_PHY_297" hexmask.long.byte 0x60 26.--31. 1. "RESERVED" hexmask.long.word 0x60 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_1,Threshold Criteria of period threshold after No-Topology training is completed for slice 1." newline hexmask.long.byte 0x60 10.--15. 1. "RESERVED" hexmask.long.word 0x60 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_1,Threshold Criteria of early threshold after No-Topology training is completed for slice 1." line.long 0x64 "DDRSS_PHY_298" hexmask.long.byte 0x64 26.--31. 1. "RESERVED" hexmask.long.word 0x64 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_1,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 1." newline hexmask.long.byte 0x64 10.--15. 1. "RESERVED" hexmask.long.word 0x64 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_1,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 1." line.long 0x68 "DDRSS_PHY_299" hexmask.long.byte 0x68 24.--31. 1. "RESERVED" hexmask.long.byte 0x68 16.--23. 1. "PHY_FIFO_PTR_OBS_1,Observation register containing read entry FIFO pointers for slice 1." newline bitfld.long 0x68 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x68 8.--13. 1. "SC_PHY_MANUAL_CLEAR_1,Manual reset/clear of internal logic for slice 1." newline hexmask.long.byte 0x68 1.--7. 1. "RESERVED" bitfld.long 0x68 0. "PHY_CALVL_VREF_DRIVING_SLICE_1,Indicates if slice 1 is used to drive the VREF value to the device during CA training." "0,1" rgroup.long 0x44B0++0x47 line.long 0x0 "DDRSS_PHY_300" hexmask.long 0x0 0.--31. 1. "PHY_LPBK_RESULT_OBS_1,Observation register containing loopback status/results for slice 1." line.long 0x4 "DDRSS_PHY_301" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_1,Observation register containing master delay results for slice 1." newline hexmask.long.word 0x4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_1,Observation register containing total number of loopback error data for slice 1." line.long 0x8 "DDRSS_PHY_302" hexmask.long.byte 0x8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 1." hexmask.long.byte 0x8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_1,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 1." newline bitfld.long 0x8 15. "RESERVED" "0,1" hexmask.long.byte 0x8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1,Observation register containing read DQS base slave delay encoded value for slice 1." newline bitfld.long 0x8 7. "RESERVED" "0,1" hexmask.long.byte 0x8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_1,Observation register containing read DQ slave delay encoded values for slice 1." line.long 0xC "DDRSS_PHY_303" bitfld.long 0xC 31. "RESERVED" "0,1" hexmask.long.byte 0xC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1,Observation register containing write DQS base slave delay encoded value for slice 1." newline hexmask.long.byte 0xC 19.--23. 1. "RESERVED" hexmask.long.word 0xC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1,Observation register containing read DQS gate slave delay encoded value for slice 1." newline hexmask.long.byte 0xC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 1." line.long 0x10 "DDRSS_PHY_304" hexmask.long.word 0x10 19.--31. 1. "RESERVED" bitfld.long 0x10 16.--18. "PHY_WR_SHIFT_OBS_1,Observation register containing automatic half cycle and cycle shift values for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing write adder slave delay encoded value for slice 1." hexmask.long.byte 0x10 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1,Observation register containing write DQ base slave delay encoded value for slice 1." line.long 0x14 "DDRSS_PHY_305" hexmask.long.byte 0x14 26.--31. 1. "RESERVED" hexmask.long.word 0x14 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_1,Observation register containing write leveling first hard 1 DQS slave delay for slice 1." newline hexmask.long.byte 0x14 10.--15. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_1,Observation register containing write leveling last hard 0 DQS slave delay for slice 1." line.long 0x18 "DDRSS_PHY_306" hexmask.long.word 0x18 17.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--16. 1. "PHY_WRLVL_STATUS_OBS_1,Observation register containing write leveling status for slice 1." line.long 0x1C "DDRSS_PHY_307" hexmask.long.byte 0x1C 26.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1,Observation register containing gate sample2 slave delay encoded values for slice 1." newline hexmask.long.byte 0x1C 10.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1,Observation register containing gate sample1 slave delay encoded values for slice 1." line.long 0x20 "DDRSS_PHY_308" bitfld.long 0x20 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x20 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_1,Observation register containing gate training first hard 0 DQS slave delay for slice 1." newline hexmask.long.word 0x20 0.--15. 1. "PHY_WRLVL_ERROR_OBS_1,Observation register containing write leveling error status for slice 1." line.long 0x24 "DDRSS_PHY_309" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED" hexmask.long.word 0x24 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_1,Observation register containing gate training last hard 1 DQS slave delay for slice 1." line.long 0x28 "DDRSS_PHY_310" hexmask.long.word 0x28 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x28 0.--17. 1. "PHY_GTLVL_STATUS_OBS_1,Observation register containing gate training status for slice 1." line.long 0x2C "DDRSS_PHY_311" hexmask.long.byte 0x2C 26.--31. 1. "RESERVED" hexmask.long.word 0x2C 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1,Observation register containing read leveling data window trailing edge slave delay setting for slice 1." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" hexmask.long.word 0x2C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1,Observation register containing read leveling data window leading edge slave delay setting for slice 1." line.long 0x30 "DDRSS_PHY_312" hexmask.long 0x30 2.--31. 1. "RESERVED" bitfld.long 0x30 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1,Observation register containing read leveling number of windows found for slice 1." "0,1,2,3" line.long 0x34 "DDRSS_PHY_313" hexmask.long 0x34 0.--31. 1. "PHY_RDLVL_STATUS_OBS_1,Observation register containing read leveling status for slice 1." line.long 0x38 "DDRSS_PHY_314" hexmask.long 0x38 0.--31. 1. "PHY_RDLVL_PERIODIC_OBS_1,Observation register containing periodic read leveling status for slice 1." line.long 0x3C "DDRSS_PHY_315" hexmask.long.byte 0x3C 27.--31. 1. "RESERVED" hexmask.long.word 0x3C 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_1,Observation register containing write data leveling data window trailing edge slave delay setting for slice 1." newline hexmask.long.byte 0x3C 11.--15. 1. "RESERVED" hexmask.long.word 0x3C 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_1,Observation register containing write data leveling data window leading edge slave delay setting for slice 1." line.long 0x40 "DDRSS_PHY_316" hexmask.long 0x40 0.--31. 1. "PHY_WDQLVL_STATUS_OBS_1,Observation register containing write data leveling status for slice 1." line.long 0x44 "DDRSS_PHY_317" hexmask.long 0x44 0.--31. 1. "PHY_WDQLVL_PERIODIC_OBS_1,Observation register containing periodic write data leveling status for slice 1." group.long 0x44F8++0x7 line.long 0x0 "DDRSS_PHY_318" bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long 0x0 0.--30. 1. "PHY_DDL_MODE_1,DDL mode for slice 1." line.long 0x4 "DDRSS_PHY_319" hexmask.long 0x4 6.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "PHY_DDL_MASK_1,DDL mask for slice 1." rgroup.long 0x4500++0x7 line.long 0x0 "DDRSS_PHY_320" hexmask.long 0x0 0.--31. 1. "PHY_DDL_TEST_OBS_1,DDL test observation for slice 1." line.long 0x4 "DDRSS_PHY_321" hexmask.long 0x4 0.--31. 1. "PHY_DDL_TEST_MSTR_DLY_OBS_1,DDL test observation delays for slice 1 master DDL." group.long 0x4508++0x1F line.long 0x0 "DDRSS_PHY_322" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RX_CAL_OVERRIDE_1,Manual setting of RX Calibration enable for slice 1." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" bitfld.long 0x0 16. "SC_PHY_RX_CAL_START_1,Manual RX Calibration start for slice 1." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" bitfld.long 0x0 8. "PHY_LP4_WDQS_OE_EXTEND_1,LPDDR4 write preamble extension enable for slice 1." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_1,Specify threshold value for PHY init update tracking for slice 1." line.long 0x4 "DDRSS_PHY_323" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--24. 1. "PHY_RX_CAL_DQ0_1,RX Calibration codes for DQ0 for slice 1." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1,Data slice power reduction disable for slice 1." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_1,RX Calibration state machine wait count for slice 1." line.long 0x8 "DDRSS_PHY_324" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" hexmask.long.word 0x8 16.--24. 1. "PHY_RX_CAL_DQ2_1,RX Calibration codes for DQ2 for slice 1." newline hexmask.long.byte 0x8 9.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--8. 1. "PHY_RX_CAL_DQ1_1,RX Calibration codes for DQ1 for slice 1." line.long 0xC "DDRSS_PHY_325" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" hexmask.long.word 0xC 16.--24. 1. "PHY_RX_CAL_DQ4_1,RX Calibration codes for DQ4 for slice 1." newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "PHY_RX_CAL_DQ3_1,RX Calibration codes for DQ3 for slice 1." line.long 0x10 "DDRSS_PHY_326" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--24. 1. "PHY_RX_CAL_DQ6_1,RX Calibration codes for DQ6 for slice 1." newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "PHY_RX_CAL_DQ5_1,RX Calibration codes for DQ5 for slice 1." line.long 0x14 "DDRSS_PHY_327" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--8. 1. "PHY_RX_CAL_DQ7_1,RX Calibration codes for DQ7 for slice 1." line.long 0x18 "DDRSS_PHY_328" hexmask.long.word 0x18 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--17. 1. "PHY_RX_CAL_DM_1,RX Calibration codes for DM for slice 1." line.long 0x1C "DDRSS_PHY_329" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--24. 1. "PHY_RX_CAL_FDBK_1,RX Calibration codes for FDBK for slice 1." newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--8. 1. "PHY_RX_CAL_DQS_1,RX Calibration codes for DQS for slice 1." rgroup.long 0x4528++0x3 line.long 0x0 "DDRSS_PHY_330" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_1,RX Calibration lock results for slice 1." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_RX_CAL_OBS_1,RX Calibration results for slice 1." group.long 0x452C++0x103 line.long 0x0 "DDRSS_PHY_331" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RX_CAL_COMP_VAL_1,Expected C value from RX pad for slice 1." "0,1" newline bitfld.long 0x0 23. "RESERVED" "0,1" hexmask.long.byte 0x0 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_1,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 1." newline bitfld.long 0x0 15. "RESERVED" "0,1" hexmask.long.byte 0x0 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_1,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 1." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_RX_CAL_DISABLE_1,RX CAL disable signal for slice 1 set 1 to bypass the rx calibration" "0,1" line.long 0x4 "DDRSS_PHY_332" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--26. 1. "PHY_PAD_RX_BIAS_EN_1,Controls RX_BIAS_EN pin for each pad for slice 1." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_1,RX offset calibration mask of all RX pad for slice 1." line.long 0x8 "DDRSS_PHY_333" hexmask.long.byte 0x8 26.--31. 1. "RESERVED" bitfld.long 0x8 24.--25. "PHY_DATA_DC_WEIGHT_1,Determines weight of average calculating for slice 1." "0,1,2,3" newline hexmask.long.byte 0x8 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_1,Determines timeout number of iteration for slice 1." hexmask.long.byte 0x8 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_1,Determines number of cycles to wait for each sample for slice 1." newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PHY_STATIC_TOG_DISABLE_1,Control to disable toggle during static activity for slice 1." line.long 0xC "DDRSS_PHY_334" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "PHY_DATA_DC_ADJUST_DIRECT_1,Adjust direction for slice 1." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_1,Duty cycle adjust threshold around the mid-point for slice 1." hexmask.long.byte 0xC 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_1,Duty cycle adjust sample count for slice 1." newline bitfld.long 0xC 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "PHY_DATA_DC_ADJUST_START_1,Duty cycle adjust starting value for slice 1." line.long 0x10 "DDRSS_PHY_335" hexmask.long.byte 0x10 27.--31. 1. "RESERVED" bitfld.long 0x10 24.--26. "PHY_FDBK_PWR_CTRL_1,Shutoff gate feedback IO to reduce power for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 18.--23. 1. "RESERVED" bitfld.long 0x10 16.--17. "PHY_DATA_DC_SW_RANK_1,Rank selection for software based duty cycle correction for slice 1." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "PHY_DATA_DC_CAL_START_1,Manual trigger for DCC for slice 1." "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "PHY_DATA_DC_CAL_POLARITY_1,Calibration polarity for slice 1." "0,1" line.long 0x14 "DDRSS_PHY_336" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PHY_SLICE_PWR_RDC_DISABLE_1,Data slice power reduction disable for slice 1." "0,1" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" bitfld.long 0x14 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1,Data slice DCC and RX_CAL block power reduction disable for slice 1." "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "PHY_RDPATH_GATE_DISABLE_1,Data slice read path power reduction disable for slice 1." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_1,Data slice slv_dly_control block power reduction disable for slice 1." "0,1" line.long 0x18 "DDRSS_PHY_337" bitfld.long 0x18 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x18 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_1,Data slice level FSM Error Info for slice 1." newline hexmask.long.byte 0x18 11.--15. 1. "RESERVED" hexmask.long.word 0x18 0.--10. 1. "PHY_PARITY_ERROR_REGIF_1,Inject parity error to register interface signals for slice 1." line.long 0x1C "DDRSS_PHY_338" bitfld.long 0x1C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x1C 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1,Data slice level FSM Error Info for slice 1." newline bitfld.long 0x1C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x1C 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_1,Data slice level FSM Error Info Mask for slice 1." line.long 0x20 "DDRSS_PHY_339" hexmask.long.word 0x20 21.--31. 1. "RESERVED" hexmask.long.byte 0x20 16.--20. 1. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1,Data slice level training/calibration Error Info for slice 1." newline bitfld.long 0x20 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 8.--12. 1. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1,Data slice level training/calibration Error Info Mask for slice 1." newline bitfld.long 0x20 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 0.--4. 1. "PHY_DS_TRAIN_CALIB_ERROR_INFO_1,Data slice level training/calibration Error Info for slice 1." line.long 0x24 "DDRSS_PHY_340" hexmask.long.byte 0x24 27.--31. 1. "RESERVED" bitfld.long 0x24 24.--26. "PHY_DQS_TSEL_ENABLE_1,Operation type tsel enables for DQS signals for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 8.--23. 1. "PHY_DQ_TSEL_SELECT_1,Operation type tsel select values for DQ/DM signals for slice 1." hexmask.long.byte 0x24 3.--7. 1. "RESERVED" newline bitfld.long 0x24 0.--2. "PHY_DQ_TSEL_ENABLE_1,Operation type tsel enables for DQ/DM signals for slice 1." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_PHY_341" bitfld.long 0x28 31. "RESERVED" "0,1" hexmask.long.byte 0x28 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_1,Data slice initial VREF training start value for slice 1." newline hexmask.long.byte 0x28 18.--23. 1. "RESERVED" bitfld.long 0x28 16.--17. "PHY_TWO_CYC_PREAMBLE_1,2 cycle preamble support for slice 1." "0,1,2,3" newline hexmask.long.word 0x28 0.--15. 1. "PHY_DQS_TSEL_SELECT_1,Operation type tsel select values for DQS signals for slice 1." line.long 0x2C "DDRSS_PHY_342" hexmask.long.byte 0x2C 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_1,Step size of WR DQ slave delay during No-Topology training for slice 1." hexmask.long.byte 0x2C 17.--23. 1. "RESERVED" newline bitfld.long 0x2C 16. "PHY_NTP_TRAIN_EN_1,Enable for No-Topology training for slice 1." "0,1" hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" newline bitfld.long 0x2C 8.--9. "PHY_VREF_TRAINING_CTRL_1,Data slice vref training enable control for slice 1." "0,1,2,3" bitfld.long 0x2C 7. "RESERVED" "0,1" newline hexmask.long.byte 0x2C 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_1,Data slice initial VREF training stop value for slice 1." line.long 0x30 "DDRSS_PHY_343" hexmask.long.byte 0x30 27.--31. 1. "RESERVED" hexmask.long.word 0x30 16.--26. 1. "PHY_NTP_WDQ_STOP_1,End of WR DQ slave delay in No-Topology training for slice 1." newline hexmask.long.byte 0x30 11.--15. 1. "RESERVED" hexmask.long.word 0x30 0.--10. 1. "PHY_NTP_WDQ_START_1,Starting WR DQ slave delay in No-Topology training for slice 1." line.long 0x34 "DDRSS_PHY_344" hexmask.long.byte 0x34 25.--31. 1. "RESERVED" bitfld.long 0x34 24. "PHY_SW_WDQLVL_DVW_MIN_EN_1,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 1." "0,1" newline hexmask.long.byte 0x34 18.--23. 1. "RESERVED" hexmask.long.word 0x34 8.--17. 1. "PHY_WDQLVL_DVW_MIN_1,Minimum data valid window across DQs and ranks for slice 1." newline hexmask.long.byte 0x34 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_1,Enable Bit for WR DQ during No-Topology training for slice 1." line.long 0x38 "DDRSS_PHY_345" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "PHY_PAD_RX_DCD_0_1,Controls RX_DCD pin for each pad for slice 1." newline bitfld.long 0x38 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 16.--20. 1. "PHY_PAD_TX_DCD_1,Controls TX_DCD pin for each pad for slice 1." newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.byte 0x38 8.--11. 1. "PHY_FAST_LVL_EN_1,Enable for fast multi-pattern window search for slice 1." newline bitfld.long 0x38 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "PHY_WDQLVL_PER_START_OFFSET_1,Peridic training start point offset for slice 1." line.long 0x3C "DDRSS_PHY_346" bitfld.long 0x3C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 24.--28. 1. "PHY_PAD_RX_DCD_4_1,Controls RX_DCD pin for each pad for slice 1." newline bitfld.long 0x3C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--20. 1. "PHY_PAD_RX_DCD_3_1,Controls RX_DCD pin for each pad for slice 1." newline bitfld.long 0x3C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 8.--12. 1. "PHY_PAD_RX_DCD_2_1,Controls RX_DCD pin for each pad for slice 1." newline bitfld.long 0x3C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 0.--4. 1. "PHY_PAD_RX_DCD_1_1,Controls RX_DCD pin for each pad for slice 1." line.long 0x40 "DDRSS_PHY_347" bitfld.long 0x40 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 24.--28. 1. "PHY_PAD_DM_RX_DCD_1,Controls RX_DCD pin for dm pad for slice 1." newline bitfld.long 0x40 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 16.--20. 1. "PHY_PAD_RX_DCD_7_1,Controls RX_DCD pin for each pad for slice 1." newline bitfld.long 0x40 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 8.--12. 1. "PHY_PAD_RX_DCD_6_1,Controls RX_DCD pin for each pad for slice 1." newline bitfld.long 0x40 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 0.--4. 1. "PHY_PAD_RX_DCD_5_1,Controls RX_DCD pin for each pad for slice 1." line.long 0x44 "DDRSS_PHY_348" hexmask.long.word 0x44 22.--31. 1. "RESERVED" hexmask.long.byte 0x44 16.--21. 1. "PHY_PAD_DSLICE_IO_CFG_1,Controls PCLK/PARK pin for pad for slice 1." newline bitfld.long 0x44 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 8.--12. 1. "PHY_PAD_FDBK_RX_DCD_1,Controls RX_DCD pin for fdbk pad for slice 1." newline bitfld.long 0x44 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 0.--4. 1. "PHY_PAD_DQS_RX_DCD_1,Controls RX_DCD pin for dqs pad for slice 1." line.long 0x48 "DDRSS_PHY_349" hexmask.long.byte 0x48 26.--31. 1. "RESERVED" hexmask.long.word 0x48 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_1,Read DQ1 slave delay setting for slice 1." newline hexmask.long.byte 0x48 10.--15. 1. "RESERVED" hexmask.long.word 0x48 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_1,Read DQ0 slave delay setting for slice 1." line.long 0x4C "DDRSS_PHY_350" hexmask.long.byte 0x4C 26.--31. 1. "RESERVED" hexmask.long.word 0x4C 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_1,Read DQ3 slave delay setting for slice 1." newline hexmask.long.byte 0x4C 10.--15. 1. "RESERVED" hexmask.long.word 0x4C 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_1,Read DQ2 slave delay setting for slice 1." line.long 0x50 "DDRSS_PHY_351" hexmask.long.byte 0x50 26.--31. 1. "RESERVED" hexmask.long.word 0x50 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_1,Read DQ5 slave delay setting for slice 1." newline hexmask.long.byte 0x50 10.--15. 1. "RESERVED" hexmask.long.word 0x50 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_1,Read DQ4 slave delay setting for slice 1." line.long 0x54 "DDRSS_PHY_352" hexmask.long.byte 0x54 26.--31. 1. "RESERVED" hexmask.long.word 0x54 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_1,Read DQ7 slave delay setting for slice 1." newline hexmask.long.byte 0x54 10.--15. 1. "RESERVED" hexmask.long.word 0x54 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_1,Read DQ6 slave delay setting for slice 1." line.long 0x58 "DDRSS_PHY_353" hexmask.long.word 0x58 19.--31. 1. "RESERVED" bitfld.long 0x58 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_1,Determines DCC CAL clock for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 10.--15. 1. "RESERVED" hexmask.long.word 0x58 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_1,Read DM/DBI slave delay setting for slice 1." line.long 0x5C "DDRSS_PHY_354" hexmask.long.byte 0x5C 24.--31. 1. "PHY_DQS_OE_TIMING_1,Start/end timing values for DQS output enable signals for slice 1." hexmask.long.byte 0x5C 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_1,Start/end timing values for DQ/DM write based termination enable and select signals for slice 1." newline hexmask.long.byte 0x5C 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_1,Start/end timing values for DQ/DM read based termination enable and select signals for slice 1." hexmask.long.byte 0x5C 0.--7. 1. "PHY_DQ_OE_TIMING_1,Start/end timing values for DQ/DM output enable signals for slice 1." line.long 0x60 "DDRSS_PHY_355" hexmask.long.byte 0x60 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_1,Start/end timing values for DQS write based termination enable and select signals for slice 1." hexmask.long.byte 0x60 16.--23. 1. "PHY_DQS_OE_RD_TIMING_1,Start/end timing values for DQS read based OE extension for slice 1." newline hexmask.long.byte 0x60 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_1,Start/end timing values for DQS read based termination enable and select signals for slice 1." hexmask.long.byte 0x60 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x60 0.--3. 1. "PHY_IO_PAD_DELAY_TIMING_1,Feedback pad's OPAD and IPAD delay timing for slice 1." line.long 0x64 "DDRSS_PHY_356" hexmask.long.byte 0x64 28.--31. 1. "RESERVED" hexmask.long.word 0x64 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_1,Pad VREF control settings for DQ slice 1." newline hexmask.long.word 0x64 0.--15. 1. "PHY_VREF_SETTING_TIME_1,Number of cycles for vref settle after setting is changed for slice 1." line.long 0x68 "DDRSS_PHY_357" hexmask.long.byte 0x68 26.--31. 1. "RESERVED" bitfld.long 0x68 24.--25. "PHY_RDDATA_EN_IE_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1." "0,1,2,3" newline hexmask.long.byte 0x68 16.--23. 1. "PHY_DQS_IE_TIMING_1,Start/end timing values for DQS input enable signals for slice 1." hexmask.long.byte 0x68 8.--15. 1. "PHY_DQ_IE_TIMING_1,Start/end timing values for DQ/DM input enable signals for slice 1." newline hexmask.long.byte 0x68 1.--7. 1. "RESERVED" bitfld.long 0x68 0. "PHY_PER_CS_TRAINING_EN_1,Enables the per-rank training and read/write timing capabilities for slice 1." "0,1" line.long 0x6C "DDRSS_PHY_358" bitfld.long 0x6C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 24.--28. 1. "PHY_RDDATA_EN_OE_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 1." newline bitfld.long 0x6C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 16.--20. 1. "PHY_RDDATA_EN_TSEL_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1." newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED" bitfld.long 0x6C 8. "PHY_DBI_MODE_1,DBI mode for slice 1." "0,1" newline hexmask.long.byte 0x6C 2.--7. 1. "RESERVED" bitfld.long 0x6C 0.--1. "PHY_IE_MODE_1,Input enable mode bits for slice 1." "0,1,2,3" line.long 0x70 "DDRSS_PHY_359" bitfld.long 0x70 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x70 24.--29. 1. "PHY_MASTER_DELAY_STEP_1,Incremental step size for master delay line locking algorithm for slice 1." newline hexmask.long.byte 0x70 19.--23. 1. "RESERVED" hexmask.long.word 0x70 8.--18. 1. "PHY_MASTER_DELAY_START_1,Start value for master delay line locking algorithm for slice 1." newline hexmask.long.byte 0x70 4.--7. 1. "RESERVED" hexmask.long.byte 0x70 0.--3. 1. "PHY_SW_MASTER_MODE_1,Master delay line override settings for slice 1." line.long 0x74 "DDRSS_PHY_360" hexmask.long.byte 0x74 24.--31. 1. "PHY_WRLVL_DLY_STEP_1,DQS slave delay step size during write leveling for slice 1." hexmask.long.byte 0x74 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x74 16.--19. 1. "PHY_RPTR_UPDATE_1,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 1." hexmask.long.byte 0x74 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_1,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 1." newline hexmask.long.byte 0x74 0.--7. 1. "PHY_MASTER_DELAY_WAIT_1,Wait cycles for master delay line locking algorithm for slice 1." line.long 0x78 "DDRSS_PHY_361" bitfld.long 0x78 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x78 24.--28. 1. "PHY_GTLVL_RESP_WAIT_CNT_1,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 1." newline hexmask.long.byte 0x78 20.--23. 1. "RESERVED" hexmask.long.byte 0x78 16.--19. 1. "PHY_GTLVL_DLY_STEP_1,DQS slave delay step size during gate training for slice 1." newline bitfld.long 0x78 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x78 8.--13. 1. "PHY_WRLVL_RESP_WAIT_CNT_1,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 1." newline hexmask.long.byte 0x78 4.--7. 1. "RESERVED" hexmask.long.byte 0x78 0.--3. 1. "PHY_WRLVL_DLY_FINE_STEP_1,DQS slave delay fine step size during write leveling for slice 1." line.long 0x7C "DDRSS_PHY_362" hexmask.long.byte 0x7C 26.--31. 1. "RESERVED" hexmask.long.word 0x7C 16.--25. 1. "PHY_GTLVL_FINAL_STEP_1,Final backup step delay used in gate training algorithm for slice 1." newline hexmask.long.byte 0x7C 10.--15. 1. "RESERVED" hexmask.long.word 0x7C 0.--9. 1. "PHY_GTLVL_BACK_STEP_1,Interim backup step delay used in gate training algorithm for slice 1." line.long 0x80 "DDRSS_PHY_363" hexmask.long.byte 0x80 28.--31. 1. "RESERVED" hexmask.long.byte 0x80 24.--27. 1. "PHY_RDLVL_DLY_STEP_1,DQS slave delay step size during read leveling for slice 1." newline hexmask.long.byte 0x80 17.--23. 1. "RESERVED" bitfld.long 0x80 16. "PHY_TOGGLE_PRE_SUPPORT_1,Support the toggle read preamble for LPDDR4 for slice 1." "0,1" newline hexmask.long.byte 0x80 12.--15. 1. "RESERVED" hexmask.long.byte 0x80 8.--11. 1. "PHY_WDQLVL_QTR_DLY_STEP_1,Defines the step granularity for the logic to use once an edge is found for slice 1." newline hexmask.long.byte 0x80 0.--7. 1. "PHY_WDQLVL_DLY_STEP_1,DQ slave delay step size during write data leveling for slice 1." line.long 0x84 "DDRSS_PHY_364" hexmask.long.tbyte 0x84 10.--31. 1. "RESERVED" hexmask.long.word 0x84 0.--9. 1. "PHY_RDLVL_MAX_EDGE_1,The maximun rdlvl slave delay search window for read eye training for slice 1." line.long 0x88 "DDRSS_PHY_365" bitfld.long 0x88 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x88 24.--29. 1. "PHY_RDLVL_PER_START_OFFSET_1,Peridic training start point offset for slice 1." newline hexmask.long.byte 0x88 17.--23. 1. "RESERVED" bitfld.long 0x88 16. "PHY_SW_RDLVL_DVW_MIN_EN_1,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 1." "0,1" newline hexmask.long.byte 0x88 10.--15. 1. "RESERVED" hexmask.long.word 0x88 0.--9. 1. "PHY_RDLVL_DVW_MIN_1,Minimum data valid window across DQs and ranks for slice 1." line.long 0x8C "DDRSS_PHY_366" hexmask.long.word 0x8C 18.--31. 1. "RESERVED" bitfld.long 0x8C 16.--17. "PHY_DATA_DC_INIT_DISABLE_1,Disable duty cycle adjust at initialization for slice 1." "0,1,2,3" newline hexmask.long.byte 0x8C 11.--15. 1. "RESERVED" bitfld.long 0x8C 8.--10. "PHY_WRPATH_GATE_TIMING_1,Write path clock gating timing for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8C 2.--7. 1. "RESERVED" bitfld.long 0x8C 0.--1. "PHY_WRPATH_GATE_DISABLE_1,Write path clock gating disable for slice 1." "0,1,2,3" line.long 0x90 "DDRSS_PHY_367" hexmask.long.byte 0x90 27.--31. 1. "RESERVED" hexmask.long.word 0x90 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_1,Initial value of write DQ slave delay for slice 1." newline hexmask.long.byte 0x90 10.--15. 1. "RESERVED" hexmask.long.word 0x90 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_1,Initial value of write DQS slave delay for slice 1." line.long 0x94 "DDRSS_PHY_368" hexmask.long.byte 0x94 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1,Clock measurement cell threshold offset for differential signals for slice 1." hexmask.long.byte 0x94 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_1,Clock measurement cell threshold offset for single ended signals for slice 1." newline hexmask.long.byte 0x94 9.--15. 1. "RESERVED" bitfld.long 0x94 8. "PHY_DATA_DC_WDQLVL_ENABLE_1,Enable duty cycle adjust during write DQ training for slice 1." "0,1" newline hexmask.long.byte 0x94 1.--7. 1. "RESERVED" bitfld.long 0x94 0. "PHY_DATA_DC_WRLVL_ENABLE_1,Enable duty cycle adjust during write leveling for slice 1." "0,1" line.long 0x98 "DDRSS_PHY_369" hexmask.long.word 0x98 21.--31. 1. "RESERVED" hexmask.long.byte 0x98 16.--20. 1. "PHY_RDDATA_EN_DLY_1,Number of cycles that the dfi_rddata_en signal is early for slice 1." newline bitfld.long 0x98 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x98 8.--13. 1. "PHY_MEAS_DLY_STEP_ENABLE_1,Data slice training step definition using phy_meas_dly_step_value for slice 1." newline bitfld.long 0x98 7. "RESERVED" "0,1" hexmask.long.byte 0x98 0.--6. 1. "PHY_WDQ_OSC_DELTA_1,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 1." line.long 0x9C "DDRSS_PHY_370" hexmask.long 0x9C 0.--31. 1. "PHY_DQ_DM_SWIZZLE0_1,DQ/DM bit swizzling 0 for slice 1." line.long 0xA0 "DDRSS_PHY_371" hexmask.long 0xA0 4.--31. 1. "RESERVED" hexmask.long.byte 0xA0 0.--3. 1. "PHY_DQ_DM_SWIZZLE1_1,DQ/DM bit swizzling 1 for slice 1." line.long 0xA4 "DDRSS_PHY_372" hexmask.long.byte 0xA4 27.--31. 1. "RESERVED" hexmask.long.word 0xA4 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_1,Write clock slave delay setting for DQ1 for slice 1." newline hexmask.long.byte 0xA4 11.--15. 1. "RESERVED" hexmask.long.word 0xA4 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_1,Write clock slave delay setting for DQ0 for slice 1." line.long 0xA8 "DDRSS_PHY_373" hexmask.long.byte 0xA8 27.--31. 1. "RESERVED" hexmask.long.word 0xA8 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_1,Write clock slave delay setting for DQ3 for slice 1." newline hexmask.long.byte 0xA8 11.--15. 1. "RESERVED" hexmask.long.word 0xA8 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_1,Write clock slave delay setting for DQ2 for slice 1." line.long 0xAC "DDRSS_PHY_374" hexmask.long.byte 0xAC 27.--31. 1. "RESERVED" hexmask.long.word 0xAC 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_1,Write clock slave delay setting for DQ5 for slice 1." newline hexmask.long.byte 0xAC 11.--15. 1. "RESERVED" hexmask.long.word 0xAC 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_1,Write clock slave delay setting for DQ4 for slice 1." line.long 0xB0 "DDRSS_PHY_375" hexmask.long.byte 0xB0 27.--31. 1. "RESERVED" hexmask.long.word 0xB0 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_1,Write clock slave delay setting for DQ7 for slice 1." newline hexmask.long.byte 0xB0 11.--15. 1. "RESERVED" hexmask.long.word 0xB0 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_1,Write clock slave delay setting for DQ6 for slice 1." line.long 0xB4 "DDRSS_PHY_376" hexmask.long.byte 0xB4 26.--31. 1. "RESERVED" hexmask.long.word 0xB4 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_1,Write clock slave delay setting for DQS for slice 1." newline hexmask.long.byte 0xB4 11.--15. 1. "RESERVED" hexmask.long.word 0xB4 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_1,Write clock slave delay setting for DM for slice 1." line.long 0xB8 "DDRSS_PHY_377" hexmask.long.word 0xB8 18.--31. 1. "RESERVED" hexmask.long.word 0xB8 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ0 for slice 1." newline hexmask.long.byte 0xB8 2.--7. 1. "RESERVED" bitfld.long 0xB8 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_1,Write level threshold adjust value based on those thresholds for DQS for slice 1." "0,1,2,3" line.long 0xBC "DDRSS_PHY_378" hexmask.long.byte 0xBC 26.--31. 1. "RESERVED" hexmask.long.word 0xBC 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ1 for slice 1." newline hexmask.long.byte 0xBC 10.--15. 1. "RESERVED" hexmask.long.word 0xBC 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ0 for slice 1." line.long 0xC0 "DDRSS_PHY_379" hexmask.long.byte 0xC0 26.--31. 1. "RESERVED" hexmask.long.word 0xC0 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ2 for slice 1." newline hexmask.long.byte 0xC0 10.--15. 1. "RESERVED" hexmask.long.word 0xC0 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ1 for slice 1." line.long 0xC4 "DDRSS_PHY_380" hexmask.long.byte 0xC4 26.--31. 1. "RESERVED" hexmask.long.word 0xC4 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ3 for slice 1." newline hexmask.long.byte 0xC4 10.--15. 1. "RESERVED" hexmask.long.word 0xC4 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ2 for slice 1." line.long 0xC8 "DDRSS_PHY_381" hexmask.long.byte 0xC8 26.--31. 1. "RESERVED" hexmask.long.word 0xC8 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ4 for slice 1." newline hexmask.long.byte 0xC8 10.--15. 1. "RESERVED" hexmask.long.word 0xC8 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ3 for slice 1." line.long 0xCC "DDRSS_PHY_382" hexmask.long.byte 0xCC 26.--31. 1. "RESERVED" hexmask.long.word 0xCC 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ5 for slice 1." newline hexmask.long.byte 0xCC 10.--15. 1. "RESERVED" hexmask.long.word 0xCC 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ4 for slice 1." line.long 0xD0 "DDRSS_PHY_383" hexmask.long.byte 0xD0 26.--31. 1. "RESERVED" hexmask.long.word 0xD0 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ6 for slice 1." newline hexmask.long.byte 0xD0 10.--15. 1. "RESERVED" hexmask.long.word 0xD0 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ5 for slice 1." line.long 0xD4 "DDRSS_PHY_384" hexmask.long.byte 0xD4 26.--31. 1. "RESERVED" hexmask.long.word 0xD4 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ7 for slice 1." newline hexmask.long.byte 0xD4 10.--15. 1. "RESERVED" hexmask.long.word 0xD4 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ6 for slice 1." line.long 0xD8 "DDRSS_PHY_385" hexmask.long.byte 0xD8 26.--31. 1. "RESERVED" hexmask.long.word 0xD8 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DM for slice 1." newline hexmask.long.byte 0xD8 10.--15. 1. "RESERVED" hexmask.long.word 0xD8 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ7 for slice 1." line.long 0xDC "DDRSS_PHY_386" hexmask.long.byte 0xDC 26.--31. 1. "RESERVED" hexmask.long.word 0xDC 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_1,Read DQS slave delay setting for slice 1." newline hexmask.long.byte 0xDC 10.--15. 1. "RESERVED" hexmask.long.word 0xDC 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DM for slice 1." line.long 0xE0 "DDRSS_PHY_387" hexmask.long.byte 0xE0 26.--31. 1. "RESERVED" hexmask.long.word 0xE0 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_1,Write level delay threshold above which will be considered in previous cycle for slice 1." newline hexmask.long.byte 0xE0 11.--15. 1. "RESERVED" bitfld.long 0xE0 8.--10. "PHY_WRITE_PATH_LAT_ADD_1,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE0 4.--7. 1. "RESERVED" hexmask.long.byte 0xE0 0.--3. 1. "PHY_RDDQS_LATENCY_ADJUST_1,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1." line.long 0xE4 "DDRSS_PHY_388" hexmask.long.word 0xE4 17.--31. 1. "RESERVED" bitfld.long 0xE4 16. "PHY_WRLVL_EARLY_FORCE_ZERO_1,Force the final write level delay value (that meets the early threshold) to 0 for slice 1." "0,1" newline hexmask.long.byte 0xE4 10.--15. 1. "RESERVED" hexmask.long.word 0xE4 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1,Write level delay threshold below which will add a cycle of write path latency for slice 1." line.long 0xE8 "DDRSS_PHY_389" hexmask.long.word 0xE8 20.--31. 1. "RESERVED" hexmask.long.byte 0xE8 16.--19. 1. "PHY_GTLVL_LAT_ADJ_START_1,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 1." newline hexmask.long.byte 0xE8 10.--15. 1. "RESERVED" hexmask.long.word 0xE8 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_1,Initial read DQS gate slave delay setting during gate training for slice 1." line.long 0xEC "DDRSS_PHY_390" hexmask.long.byte 0xEC 25.--31. 1. "RESERVED" bitfld.long 0xEC 24. "PHY_NTP_PASS_1,Indicates if No-topology training found a passing result for slice 1." "0,1" newline hexmask.long.byte 0xEC 20.--23. 1. "RESERVED" hexmask.long.byte 0xEC 16.--19. 1. "PHY_NTP_WRLAT_START_1,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 1." newline hexmask.long.byte 0xEC 11.--15. 1. "RESERVED" hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_1,Initial DQ/DM slave delay setting during write data leveling for slice 1." line.long 0xF0 "DDRSS_PHY_391" hexmask.long.tbyte 0xF0 10.--31. 1. "RESERVED" hexmask.long.word 0xF0 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1,Read leveling starting value for the DQS/DQ slave delay settings for slice 1." line.long 0xF4 "DDRSS_PHY_392" hexmask.long.byte 0xF4 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." hexmask.long.byte 0xF4 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." newline hexmask.long.byte 0xF4 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." hexmask.long.byte 0xF4 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." line.long 0xF8 "DDRSS_PHY_393" hexmask.long.byte 0xF8 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." hexmask.long.byte 0xF8 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." newline hexmask.long.byte 0xF8 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." hexmask.long.byte 0xF8 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." line.long 0xFC "DDRSS_PHY_394" hexmask.long.word 0xFC 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_1,Setting for boost P/N of pad for slice 1." hexmask.long.byte 0xFC 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." newline hexmask.long.byte 0xFC 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1." line.long 0x100 "DDRSS_PHY_395" hexmask.long.word 0x100 18.--31. 1. "RESERVED" bitfld.long 0x100 16.--17. "PHY_DQS_FFE_1,TX_FFE setting for DQS pad for slice 1." "0,1,2,3" newline hexmask.long.byte 0x100 10.--15. 1. "RESERVED" bitfld.long 0x100 8.--9. "PHY_DQ_FFE_1,TX_FFE setting for DQ/DM pad for slice 1." "0,1,2,3" newline bitfld.long 0x100 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x100 0.--5. 1. "PHY_DSLICE_PAD_RX_CTLE_SETTING_1,Setting for RX ctle P/N of pad for slice 1." group.long 0x4800++0x27 line.long 0x0 "DDRSS_PHY_512" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--19. 1. "PHY_IO_PAD_DELAY_TIMING_BYPASS_2,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 2." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_2,Write data clock bypass mode slave delay setting for slice 2.} PADDING_BEFORE" line.long 0x4 "DDRSS_PHY_513" hexmask.long.word 0x4 19.--31. 1. "RESERVED" bitfld.long 0x4 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_2,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2,Write DQS bypass mode slave delay setting for slice 2." line.long 0x8 "DDRSS_PHY_514" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "PHY_CLK_BYPASS_OVERRIDE_2,Bypass mode override setting for slice 2." "0,1" newline hexmask.long.byte 0x8 18.--23. 1. "RESERVED" bitfld.long 0x8 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_2,Two_cycle_preamble for bypass mode for slice 2." "0,1,2,3" newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2,Read DQS bypass mode slave delay setting for slice 2." line.long 0xC "DDRSS_PHY_515" bitfld.long 0xC 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 24.--29. 1. "PHY_SW_WRDQ3_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 2." newline bitfld.long 0xC 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 16.--21. 1. "PHY_SW_WRDQ2_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 2." newline bitfld.long 0xC 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 8.--13. 1. "PHY_SW_WRDQ1_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 2." newline bitfld.long 0xC 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "PHY_SW_WRDQ0_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 2." line.long 0x10 "DDRSS_PHY_516" bitfld.long 0x10 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 24.--29. 1. "PHY_SW_WRDQ7_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 2." newline bitfld.long 0x10 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 16.--21. 1. "PHY_SW_WRDQ6_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 2." newline bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 8.--13. 1. "PHY_SW_WRDQ5_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 2." newline bitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 0.--5. 1. "PHY_SW_WRDQ4_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 2." line.long 0x14 "DDRSS_PHY_517" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_2,When set a register write will update parameters for all ranks at the same time in slice 2." "0,1" newline hexmask.long.byte 0x14 18.--23. 1. "RESERVED" bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_2,Per-rank CS map for slice 2." "0,1,2,3" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED" hexmask.long.byte 0x14 8.--11. 1. "PHY_SW_WRDQS_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 2." newline bitfld.long 0x14 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 0.--5. 1. "PHY_SW_WRDM_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 2." line.long 0x18 "DDRSS_PHY_518" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 2." newline bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 16.--20. 1. "PHY_LP4_BOOT_RDDATA_EN_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 2." newline hexmask.long.byte 0x18 10.--15. 1. "RESERVED" bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 2." "0,1,2,3" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED" bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_2,For per-rank training indicates which rank's paramters are read/written for slice 2." "0,1" line.long 0x1C "DDRSS_PHY_519" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 2." newline hexmask.long.byte 0x1C 18.--23. 1. "RESERVED" bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2,For LPDDR4 boot frequency write path clock gating disable for slice 2." "0,1,2,3" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED" hexmask.long.byte 0x1C 8.--11. 1. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 2." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED" hexmask.long.byte 0x1C 0.--3. 1. "PHY_LP4_BOOT_RPTR_UPDATE_2,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 2." line.long 0x20 "DDRSS_PHY_520" hexmask.long.byte 0x20 25.--31. 1. "RESERVED" bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_2,Loopback read only test timeout mechanism enable for slice 2." "0,1" newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_2,Loopback control bits for slice 2." newline hexmask.long.byte 0x20 2.--7. 1. "RESERVED" bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_2,Loopback control en for slice 2." "0,1,2,3" line.long 0x24 "DDRSS_PHY_521" hexmask.long 0x24 0.--31. 1. "PHY_AUTO_TIMING_MARGIN_CONTROL_2,Auto timing marging control bits for slice 2." rgroup.long 0x4828++0x3 line.long 0x0 "DDRSS_PHY_522" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_2,Observation register for the auto_timing_margin for slice 2." group.long 0x482C++0x13 line.long 0x0 "DDRSS_PHY_523" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RDLVL_MULTI_PATT_ENABLE_2,Read Leveling Multi-pattern enable for slice 2." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" hexmask.long.word 0x0 8.--16. 1. "PHY_PRBS_PATTERN_MASK_2,PRBS7 mask signal for slice 2." newline bitfld.long 0x0 7. "RESERVED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "PHY_PRBS_PATTERN_START_2,PRBS7 start pattern for slice 2." line.long 0x4 "DDRSS_PHY_524" hexmask.long.word 0x4 23.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--22. 1. "PHY_VREF_TRAIN_OBS_2,Observation register for best vref value for slice 2." newline bitfld.long 0x4 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "PHY_VREF_INITIAL_STEPSIZE_2,Data slice initial VREF training step size for slice 2." newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED" bitfld.long 0x4 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_2,Read Leveling read level windows disable reset for slice 2." "0,1" line.long 0x8 "DDRSS_PHY_525" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "SC_PHY_SNAP_OBS_REGS_2,Initiates a snapshot of the internal observation registers for slice 2." "0,1" newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED" hexmask.long.byte 0x8 16.--19. 1. "PHY_GATE_ERROR_DELAY_SELECT_2,Number of cycles to wait for the DQS gate to close before flagging an error for slice 2." newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2,Read DQS data clock bypass mode slave delay setting for slice 2." line.long 0xC "DDRSS_PHY_526" hexmask.long.byte 0xC 27.--31. 1. "RESERVED" bitfld.long 0xC 24.--26. "PHY_MEM_CLASS_2,Indicates the type of DRAM for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 17.--23. 1. "RESERVED" bitfld.long 0xC 16. "PHY_LPDDR_2,Adds a cycle of delay for the slice 2 to match the address slice." "0,1" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_2,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 2." line.long 0x10 "DDRSS_PHY_527" hexmask.long.word 0x10 18.--31. 1. "RESERVED" bitfld.long 0x10 16.--17. "ON_FLY_GATE_ADJUST_EN_2,Control the on-the-fly gate adjustment for slice 2." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_2,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 2." rgroup.long 0x4840++0x3 line.long 0x0 "DDRSS_PHY_528" hexmask.long 0x0 0.--31. 1. "PHY_GATE_TRACKING_OBS_2,Report the on-the-fly gate measurement result for slice 2." group.long 0x4844++0x6B line.long 0x0 "DDRSS_PHY_529" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" bitfld.long 0x0 8.--9. "PHY_LP4_PST_AMBLE_2,Controls the read postamble extension for LPDDR4 for slice 2." "0,1,2,3" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_DFI40_POLARITY_2,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 2." "0,1" line.long 0x4 "DDRSS_PHY_530" hexmask.long 0x4 0.--31. 1. "PHY_RDLVL_PATT8_2,Read leveling pattern 8 data for slice 2." line.long 0x8 "DDRSS_PHY_531" hexmask.long 0x8 0.--31. 1. "PHY_RDLVL_PATT9_2,Read leveling pattern 9 data for slice 2." line.long 0xC "DDRSS_PHY_532" hexmask.long 0xC 0.--31. 1. "PHY_RDLVL_PATT10_2,Read leveling pattern 10 data for slice 2." line.long 0x10 "DDRSS_PHY_533" hexmask.long 0x10 0.--31. 1. "PHY_RDLVL_PATT11_2,Read leveling pattern 11 data for slice 2." line.long 0x14 "DDRSS_PHY_534" hexmask.long 0x14 0.--31. 1. "PHY_RDLVL_PATT12_2,Read leveling pattern 12 data for slice 2." line.long 0x18 "DDRSS_PHY_535" hexmask.long 0x18 0.--31. 1. "PHY_RDLVL_PATT13_2,Read leveling pattern 13 data for slice 2." line.long 0x1C "DDRSS_PHY_536" hexmask.long 0x1C 0.--31. 1. "PHY_RDLVL_PATT14_2,Read leveling pattern 14 data for slice 2." line.long 0x20 "DDRSS_PHY_537" hexmask.long 0x20 0.--31. 1. "PHY_RDLVL_PATT15_2,Read leveling pattern 15 data for slice 2." line.long 0x24 "DDRSS_PHY_538" hexmask.long.byte 0x24 27.--31. 1. "RESERVED" bitfld.long 0x24 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_2,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 20.--23. 1. "RESERVED" hexmask.long.byte 0x24 16.--19. 1. "PHY_MASTER_DLY_LOCK_OBS_SELECT_2,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 2." newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED" bitfld.long 0x24 8. "PHY_SW_FIFO_PTR_RST_DISABLE_2,Disables automatic reset of the read entry FIFO pointers for slice 2." "0,1" newline hexmask.long.byte 0x24 3.--7. 1. "RESERVED" bitfld.long 0x24 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_2,Reserved for future use for slice 2." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_PHY_539" hexmask.long.byte 0x28 28.--31. 1. "RESERVED" hexmask.long.byte 0x28 24.--27. 1. "PHY_FIFO_PTR_OBS_SELECT_2,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 2." newline hexmask.long.byte 0x28 20.--23. 1. "RESERVED" hexmask.long.byte 0x28 16.--19. 1. "PHY_WR_SHIFT_OBS_SELECT_2,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 2." newline hexmask.long.byte 0x28 12.--15. 1. "RESERVED" hexmask.long.byte 0x28 8.--11. 1. "PHY_WR_ENC_OBS_SELECT_2,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 2." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED" hexmask.long.byte 0x28 0.--3. 1. "PHY_RDDQS_DQ_ENC_OBS_SELECT_2,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 2." line.long 0x2C "DDRSS_PHY_540" hexmask.long.byte 0x2C 24.--31. 1. "PHY_WRLVL_PER_START_2,Observation register for write leveling status for slice 2." hexmask.long.byte 0x2C 18.--23. 1. "RESERVED" newline bitfld.long 0x2C 16.--17. "PHY_WRLVL_ALGO_2,Write leveling algorithm selection for slice 2." "0,1,2,3" hexmask.long.byte 0x2C 9.--15. 1. "RESERVED" newline bitfld.long 0x2C 8. "SC_PHY_LVL_DEBUG_CONT_2,Allows the leveling state machine to advance (when in debug mode) for slice 2." "0,1" hexmask.long.byte 0x2C 1.--7. 1. "RESERVED" newline bitfld.long 0x2C 0. "PHY_LVL_DEBUG_MODE_2,Enables leveling debug mode for slice 2." "0,1" line.long 0x30 "DDRSS_PHY_541" hexmask.long.byte 0x30 24.--31. 1. "RESERVED" hexmask.long.byte 0x30 16.--23. 1. "PHY_DQ_MASK_2,For ECC slice should set this register to do DQ bit mask for slice 2." newline hexmask.long.byte 0x30 12.--15. 1. "RESERVED" hexmask.long.byte 0x30 8.--11. 1. "PHY_WRLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 2." newline bitfld.long 0x30 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x30 0.--5. 1. "PHY_WRLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during write leveling for slice 2." line.long 0x34 "DDRSS_PHY_542" hexmask.long.byte 0x34 28.--31. 1. "RESERVED" hexmask.long.byte 0x34 24.--27. 1. "PHY_GTLVL_UPDT_WAIT_CNT_2,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 2." newline bitfld.long 0x34 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x34 16.--21. 1. "PHY_GTLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during gate training for slice 2." newline hexmask.long.byte 0x34 10.--15. 1. "RESERVED" hexmask.long.word 0x34 0.--9. 1. "PHY_GTLVL_PER_START_2,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 2." line.long 0x38 "DDRSS_PHY_543" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 2." newline hexmask.long.byte 0x38 18.--23. 1. "RESERVED" bitfld.long 0x38 16.--17. "PHY_RDLVL_OP_MODE_2,Read leveling algorithm select for slice 2." "0,1,2,3" newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.byte 0x38 8.--11. 1. "PHY_RDLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 2." newline bitfld.long 0x38 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "PHY_RDLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during read leveling for slice 2." line.long 0x3C "DDRSS_PHY_544" bitfld.long 0x3C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x3C 24.--29. 1. "PHY_WDQLVL_BURST_CNT_2,Defines the write/read burst length in bytes during the write data leveling sequence for slice 2." newline hexmask.long.byte 0x3C 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_2,Defines the minimum gap requirment for the LE and TE window for slice 2." hexmask.long.byte 0x3C 8.--15. 1. "PHY_RDLVL_DATA_MASK_2,Per-bit mask for read leveling for slice 2." newline hexmask.long.byte 0x3C 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 2." line.long 0x40 "DDRSS_PHY_545" hexmask.long.byte 0x40 28.--31. 1. "RESERVED" hexmask.long.byte 0x40 24.--27. 1. "PHY_WDQLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 2." newline hexmask.long.byte 0x40 19.--23. 1. "RESERVED" hexmask.long.word 0x40 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2,Defines the write/read burst length in bytes during the write data leveling sequence for slice 2." newline hexmask.long.byte 0x40 3.--7. 1. "RESERVED" bitfld.long 0x40 0.--2. "PHY_WDQLVL_PATT_2,Defines the training patterns to be used during the write data leveling sequence for slice 2." "0,1,2,3,4,5,6,7" line.long 0x44 "DDRSS_PHY_546" hexmask.long.word 0x44 17.--31. 1. "RESERVED" bitfld.long 0x44 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_2,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 2." "0,1" newline hexmask.long.byte 0x44 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_2,Select value to map specific information during or post periodic write data leveling for slice 2." hexmask.long.byte 0x44 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x44 0.--3. 1. "PHY_WDQLVL_DQDM_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 2." line.long 0x48 "DDRSS_PHY_547" hexmask.long.tbyte 0x48 9.--31. 1. "RESERVED" hexmask.long.word 0x48 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_2,Per-bit mask for write data leveling for slice 2." line.long 0x4C "DDRSS_PHY_548" hexmask.long 0x4C 0.--31. 1. "PHY_USER_PATT0_2,User-defined pattern to be used during write data leveling for slice 2." line.long 0x50 "DDRSS_PHY_549" hexmask.long 0x50 0.--31. 1. "PHY_USER_PATT1_2,User-defined pattern to be used during write data leveling for slice 2." line.long 0x54 "DDRSS_PHY_550" hexmask.long 0x54 0.--31. 1. "PHY_USER_PATT2_2,User-defined pattern to be used during write data leveling for slice 2." line.long 0x58 "DDRSS_PHY_551" hexmask.long 0x58 0.--31. 1. "PHY_USER_PATT3_2,User-defined pattern to be used during write data leveling for slice 2." line.long 0x5C "DDRSS_PHY_552" hexmask.long.word 0x5C 17.--31. 1. "RESERVED" bitfld.long 0x5C 16. "PHY_NTP_MULT_TRAIN_2,Control for single pass only No-Topology training for slice 2." "0,1" newline hexmask.long.word 0x5C 0.--15. 1. "PHY_USER_PATT4_2,User-defined pattern to be used during write data leveling for slice 2." line.long 0x60 "DDRSS_PHY_553" hexmask.long.byte 0x60 26.--31. 1. "RESERVED" hexmask.long.word 0x60 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_2,Threshold Criteria of period threshold after No-Topology training is completed for slice 2." newline hexmask.long.byte 0x60 10.--15. 1. "RESERVED" hexmask.long.word 0x60 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_2,Threshold Criteria of early threshold after No-Topology training is completed for slice 2." line.long 0x64 "DDRSS_PHY_554" hexmask.long.byte 0x64 26.--31. 1. "RESERVED" hexmask.long.word 0x64 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_2,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 2." newline hexmask.long.byte 0x64 10.--15. 1. "RESERVED" hexmask.long.word 0x64 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_2,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 2." line.long 0x68 "DDRSS_PHY_555" hexmask.long.byte 0x68 24.--31. 1. "RESERVED" hexmask.long.byte 0x68 16.--23. 1. "PHY_FIFO_PTR_OBS_2,Observation register containing read entry FIFO pointers for slice 2." newline bitfld.long 0x68 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x68 8.--13. 1. "SC_PHY_MANUAL_CLEAR_2,Manual reset/clear of internal logic for slice 2." newline hexmask.long.byte 0x68 1.--7. 1. "RESERVED" bitfld.long 0x68 0. "PHY_CALVL_VREF_DRIVING_SLICE_2,Indicates if slice 2 is used to drive the VREF value to the device during CA training." "0,1" rgroup.long 0x48B0++0x47 line.long 0x0 "DDRSS_PHY_556" hexmask.long 0x0 0.--31. 1. "PHY_LPBK_RESULT_OBS_2,Observation register containing loopback status/results for slice 2." line.long 0x4 "DDRSS_PHY_557" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_2,Observation register containing master delay results for slice 2." newline hexmask.long.word 0x4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_2,Observation register containing total number of loopback error data for slice 2." line.long 0x8 "DDRSS_PHY_558" hexmask.long.byte 0x8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 2." hexmask.long.byte 0x8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_2,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 2." newline bitfld.long 0x8 15. "RESERVED" "0,1" hexmask.long.byte 0x8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2,Observation register containing read DQS base slave delay encoded value for slice 2." newline bitfld.long 0x8 7. "RESERVED" "0,1" hexmask.long.byte 0x8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_2,Observation register containing read DQ slave delay encoded values for slice 2." line.long 0xC "DDRSS_PHY_559" bitfld.long 0xC 31. "RESERVED" "0,1" hexmask.long.byte 0xC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2,Observation register containing write DQS base slave delay encoded value for slice 2." newline hexmask.long.byte 0xC 19.--23. 1. "RESERVED" hexmask.long.word 0xC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2,Observation register containing read DQS gate slave delay encoded value for slice 2." newline hexmask.long.byte 0xC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 2." line.long 0x10 "DDRSS_PHY_560" hexmask.long.word 0x10 19.--31. 1. "RESERVED" bitfld.long 0x10 16.--18. "PHY_WR_SHIFT_OBS_2,Observation register containing automatic half cycle and cycle shift values for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing write adder slave delay encoded value for slice 2." hexmask.long.byte 0x10 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2,Observation register containing write DQ base slave delay encoded value for slice 2." line.long 0x14 "DDRSS_PHY_561" hexmask.long.byte 0x14 26.--31. 1. "RESERVED" hexmask.long.word 0x14 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_2,Observation register containing write leveling first hard 1 DQS slave delay for slice 2." newline hexmask.long.byte 0x14 10.--15. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_2,Observation register containing write leveling last hard 0 DQS slave delay for slice 2." line.long 0x18 "DDRSS_PHY_562" hexmask.long.word 0x18 17.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--16. 1. "PHY_WRLVL_STATUS_OBS_2,Observation register containing write leveling status for slice 2." line.long 0x1C "DDRSS_PHY_563" hexmask.long.byte 0x1C 26.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2,Observation register containing gate sample2 slave delay encoded values for slice 2." newline hexmask.long.byte 0x1C 10.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2,Observation register containing gate sample1 slave delay encoded values for slice 2." line.long 0x20 "DDRSS_PHY_564" bitfld.long 0x20 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x20 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_2,Observation register containing gate training first hard 0 DQS slave delay for slice 2." newline hexmask.long.word 0x20 0.--15. 1. "PHY_WRLVL_ERROR_OBS_2,Observation register containing write leveling error status for slice 2." line.long 0x24 "DDRSS_PHY_565" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED" hexmask.long.word 0x24 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_2,Observation register containing gate training last hard 1 DQS slave delay for slice 2." line.long 0x28 "DDRSS_PHY_566" hexmask.long.word 0x28 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x28 0.--17. 1. "PHY_GTLVL_STATUS_OBS_2,Observation register containing gate training status for slice 2." line.long 0x2C "DDRSS_PHY_567" hexmask.long.byte 0x2C 26.--31. 1. "RESERVED" hexmask.long.word 0x2C 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2,Observation register containing read leveling data window trailing edge slave delay setting for slice 2." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" hexmask.long.word 0x2C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2,Observation register containing read leveling data window leading edge slave delay setting for slice 2." line.long 0x30 "DDRSS_PHY_568" hexmask.long 0x30 2.--31. 1. "RESERVED" bitfld.long 0x30 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2,Observation register containing read leveling number of windows found for slice 2." "0,1,2,3" line.long 0x34 "DDRSS_PHY_569" hexmask.long 0x34 0.--31. 1. "PHY_RDLVL_STATUS_OBS_2,Observation register containing read leveling status for slice 2." line.long 0x38 "DDRSS_PHY_570" hexmask.long 0x38 0.--31. 1. "PHY_RDLVL_PERIODIC_OBS_2,Observation register containing periodic read leveling status for slice 2." line.long 0x3C "DDRSS_PHY_571" hexmask.long.byte 0x3C 27.--31. 1. "RESERVED" hexmask.long.word 0x3C 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_2,Observation register containing write data leveling data window trailing edge slave delay setting for slice 2." newline hexmask.long.byte 0x3C 11.--15. 1. "RESERVED" hexmask.long.word 0x3C 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_2,Observation register containing write data leveling data window leading edge slave delay setting for slice 2." line.long 0x40 "DDRSS_PHY_572" hexmask.long 0x40 0.--31. 1. "PHY_WDQLVL_STATUS_OBS_2,Observation register containing write data leveling status for slice 2." line.long 0x44 "DDRSS_PHY_573" hexmask.long 0x44 0.--31. 1. "PHY_WDQLVL_PERIODIC_OBS_2,Observation register containing periodic write data leveling status for slice 2." group.long 0x48F8++0x7 line.long 0x0 "DDRSS_PHY_574" bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long 0x0 0.--30. 1. "PHY_DDL_MODE_2,DDL mode for slice 2." line.long 0x4 "DDRSS_PHY_575" hexmask.long 0x4 6.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "PHY_DDL_MASK_2,DDL mask for slice 2." rgroup.long 0x4900++0x7 line.long 0x0 "DDRSS_PHY_576" hexmask.long 0x0 0.--31. 1. "PHY_DDL_TEST_OBS_2,DDL test observation for slice 2." line.long 0x4 "DDRSS_PHY_577" hexmask.long 0x4 0.--31. 1. "PHY_DDL_TEST_MSTR_DLY_OBS_2,DDL test observation delays for slice 2 master DDL." group.long 0x4908++0x1F line.long 0x0 "DDRSS_PHY_578" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RX_CAL_OVERRIDE_2,Manual setting of RX Calibration enable for slice 2." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" bitfld.long 0x0 16. "SC_PHY_RX_CAL_START_2,Manual RX Calibration start for slice 2." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" bitfld.long 0x0 8. "PHY_LP4_WDQS_OE_EXTEND_2,LPDDR4 write preamble extension enable for slice 2." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_2,Specify threshold value for PHY init update tracking for slice 2." line.long 0x4 "DDRSS_PHY_579" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--24. 1. "PHY_RX_CAL_DQ0_2,RX Calibration codes for DQ0 for slice 2." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2,Data slice power reduction disable for slice 2." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_2,RX Calibration state machine wait count for slice 2." line.long 0x8 "DDRSS_PHY_580" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" hexmask.long.word 0x8 16.--24. 1. "PHY_RX_CAL_DQ2_2,RX Calibration codes for DQ2 for slice 2." newline hexmask.long.byte 0x8 9.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--8. 1. "PHY_RX_CAL_DQ1_2,RX Calibration codes for DQ1 for slice 2." line.long 0xC "DDRSS_PHY_581" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" hexmask.long.word 0xC 16.--24. 1. "PHY_RX_CAL_DQ4_2,RX Calibration codes for DQ4 for slice 2." newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "PHY_RX_CAL_DQ3_2,RX Calibration codes for DQ3 for slice 2." line.long 0x10 "DDRSS_PHY_582" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--24. 1. "PHY_RX_CAL_DQ6_2,RX Calibration codes for DQ6 for slice 2." newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "PHY_RX_CAL_DQ5_2,RX Calibration codes for DQ5 for slice 2." line.long 0x14 "DDRSS_PHY_583" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--8. 1. "PHY_RX_CAL_DQ7_2,RX Calibration codes for DQ7 for slice 2." line.long 0x18 "DDRSS_PHY_584" hexmask.long.word 0x18 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--17. 1. "PHY_RX_CAL_DM_2,RX Calibration codes for DM for slice 2." line.long 0x1C "DDRSS_PHY_585" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--24. 1. "PHY_RX_CAL_FDBK_2,RX Calibration codes for FDBK for slice 2." newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--8. 1. "PHY_RX_CAL_DQS_2,RX Calibration codes for DQS for slice 2." rgroup.long 0x4928++0x3 line.long 0x0 "DDRSS_PHY_586" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_2,RX Calibration lock results for slice 2." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_RX_CAL_OBS_2,RX Calibration results for slice 2." group.long 0x492C++0x103 line.long 0x0 "DDRSS_PHY_587" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RX_CAL_COMP_VAL_2,Expected C value from RX pad for slice 2." "0,1" newline bitfld.long 0x0 23. "RESERVED" "0,1" hexmask.long.byte 0x0 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_2,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 2." newline bitfld.long 0x0 15. "RESERVED" "0,1" hexmask.long.byte 0x0 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_2,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 2." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_RX_CAL_DISABLE_2,RX CAL disable signal for slice 2 set 1 to bypass the rx calibration" "0,1" line.long 0x4 "DDRSS_PHY_588" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--26. 1. "PHY_PAD_RX_BIAS_EN_2,Controls RX_BIAS_EN pin for each pad for slice 2." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_2,RX offset calibration mask of all RX pad for slice 2." line.long 0x8 "DDRSS_PHY_589" hexmask.long.byte 0x8 26.--31. 1. "RESERVED" bitfld.long 0x8 24.--25. "PHY_DATA_DC_WEIGHT_2,Determines weight of average calculating for slice 2." "0,1,2,3" newline hexmask.long.byte 0x8 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_2,Determines timeout number of iteration for slice 2." hexmask.long.byte 0x8 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_2,Determines number of cycles to wait for each sample for slice 2." newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PHY_STATIC_TOG_DISABLE_2,Control to disable toggle during static activity for slice 2." line.long 0xC "DDRSS_PHY_590" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "PHY_DATA_DC_ADJUST_DIRECT_2,Adjust direction for slice 2." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_2,Duty cycle adjust threshold around the mid-point for slice 2." hexmask.long.byte 0xC 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_2,Duty cycle adjust sample count for slice 2." newline bitfld.long 0xC 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "PHY_DATA_DC_ADJUST_START_2,Duty cycle adjust starting value for slice 2." line.long 0x10 "DDRSS_PHY_591" hexmask.long.byte 0x10 27.--31. 1. "RESERVED" bitfld.long 0x10 24.--26. "PHY_FDBK_PWR_CTRL_2,Shutoff gate feedback IO to reduce power for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 18.--23. 1. "RESERVED" bitfld.long 0x10 16.--17. "PHY_DATA_DC_SW_RANK_2,Rank selection for software based duty cycle correction for slice 2." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "PHY_DATA_DC_CAL_START_2,Manual trigger for DCC for slice 2." "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "PHY_DATA_DC_CAL_POLARITY_2,Calibration polarity for slice 2." "0,1" line.long 0x14 "DDRSS_PHY_592" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PHY_SLICE_PWR_RDC_DISABLE_2,Data slice power reduction disable for slice 2." "0,1" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" bitfld.long 0x14 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2,Data slice DCC and RX_CAL block power reduction disable for slice 2." "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "PHY_RDPATH_GATE_DISABLE_2,Data slice read path power reduction disable for slice 2." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_2,Data slice slv_dly_control block power reduction disable for slice 2." "0,1" line.long 0x18 "DDRSS_PHY_593" bitfld.long 0x18 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x18 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_2,Data slice level FSM Error Info for slice 2." newline hexmask.long.byte 0x18 11.--15. 1. "RESERVED" hexmask.long.word 0x18 0.--10. 1. "PHY_PARITY_ERROR_REGIF_2,Inject parity error to register interface signals for slice 2." line.long 0x1C "DDRSS_PHY_594" bitfld.long 0x1C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x1C 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2,Data slice level FSM Error Info for slice 2." newline bitfld.long 0x1C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x1C 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_2,Data slice level FSM Error Info Mask for slice 2." line.long 0x20 "DDRSS_PHY_595" hexmask.long.word 0x20 21.--31. 1. "RESERVED" hexmask.long.byte 0x20 16.--20. 1. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2,Data slice level training/calibration Error Info for slice 2." newline bitfld.long 0x20 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 8.--12. 1. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2,Data slice level training/calibration Error Info Mask for slice 2." newline bitfld.long 0x20 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 0.--4. 1. "PHY_DS_TRAIN_CALIB_ERROR_INFO_2,Data slice level training/calibration Error Info for slice 2." line.long 0x24 "DDRSS_PHY_596" hexmask.long.byte 0x24 27.--31. 1. "RESERVED" bitfld.long 0x24 24.--26. "PHY_DQS_TSEL_ENABLE_2,Operation type tsel enables for DQS signals for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 8.--23. 1. "PHY_DQ_TSEL_SELECT_2,Operation type tsel select values for DQ/DM signals for slice 2." hexmask.long.byte 0x24 3.--7. 1. "RESERVED" newline bitfld.long 0x24 0.--2. "PHY_DQ_TSEL_ENABLE_2,Operation type tsel enables for DQ/DM signals for slice 2." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_PHY_597" bitfld.long 0x28 31. "RESERVED" "0,1" hexmask.long.byte 0x28 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_2,Data slice initial VREF training start value for slice 2." newline hexmask.long.byte 0x28 18.--23. 1. "RESERVED" bitfld.long 0x28 16.--17. "PHY_TWO_CYC_PREAMBLE_2,2 cycle preamble support for slice 2." "0,1,2,3" newline hexmask.long.word 0x28 0.--15. 1. "PHY_DQS_TSEL_SELECT_2,Operation type tsel select values for DQS signals for slice 2." line.long 0x2C "DDRSS_PHY_598" hexmask.long.byte 0x2C 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_2,Step size of WR DQ slave delay during No-Topology training for slice 2." hexmask.long.byte 0x2C 17.--23. 1. "RESERVED" newline bitfld.long 0x2C 16. "PHY_NTP_TRAIN_EN_2,Enable for No-Topology training for slice 2." "0,1" hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" newline bitfld.long 0x2C 8.--9. "PHY_VREF_TRAINING_CTRL_2,Data slice vref training enable control for slice 2." "0,1,2,3" bitfld.long 0x2C 7. "RESERVED" "0,1" newline hexmask.long.byte 0x2C 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_2,Data slice initial VREF training stop value for slice 2." line.long 0x30 "DDRSS_PHY_599" hexmask.long.byte 0x30 27.--31. 1. "RESERVED" hexmask.long.word 0x30 16.--26. 1. "PHY_NTP_WDQ_STOP_2,End of WR DQ slave delay in No-Topology training for slice 2." newline hexmask.long.byte 0x30 11.--15. 1. "RESERVED" hexmask.long.word 0x30 0.--10. 1. "PHY_NTP_WDQ_START_2,Starting WR DQ slave delay in No-Topology training for slice 2." line.long 0x34 "DDRSS_PHY_600" hexmask.long.byte 0x34 25.--31. 1. "RESERVED" bitfld.long 0x34 24. "PHY_SW_WDQLVL_DVW_MIN_EN_2,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 2." "0,1" newline hexmask.long.byte 0x34 18.--23. 1. "RESERVED" hexmask.long.word 0x34 8.--17. 1. "PHY_WDQLVL_DVW_MIN_2,Minimum data valid window across DQs and ranks for slice 2." newline hexmask.long.byte 0x34 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_2,Enable Bit for WR DQ during No-Topology training for slice 2." line.long 0x38 "DDRSS_PHY_601" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "PHY_PAD_RX_DCD_0_2,Controls RX_DCD pin for each pad for slice 2." newline bitfld.long 0x38 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 16.--20. 1. "PHY_PAD_TX_DCD_2,Controls TX_DCD pin for each pad for slice 2." newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.byte 0x38 8.--11. 1. "PHY_FAST_LVL_EN_2,Enable for fast multi-pattern window search for slice 2." newline bitfld.long 0x38 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "PHY_WDQLVL_PER_START_OFFSET_2,Peridic training start point offset for slice 2." line.long 0x3C "DDRSS_PHY_602" bitfld.long 0x3C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 24.--28. 1. "PHY_PAD_RX_DCD_4_2,Controls RX_DCD pin for each pad for slice 2." newline bitfld.long 0x3C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--20. 1. "PHY_PAD_RX_DCD_3_2,Controls RX_DCD pin for each pad for slice 2." newline bitfld.long 0x3C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 8.--12. 1. "PHY_PAD_RX_DCD_2_2,Controls RX_DCD pin for each pad for slice 2." newline bitfld.long 0x3C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 0.--4. 1. "PHY_PAD_RX_DCD_1_2,Controls RX_DCD pin for each pad for slice 2." line.long 0x40 "DDRSS_PHY_603" bitfld.long 0x40 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 24.--28. 1. "PHY_PAD_DM_RX_DCD_2,Controls RX_DCD pin for dm pad for slice 2." newline bitfld.long 0x40 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 16.--20. 1. "PHY_PAD_RX_DCD_7_2,Controls RX_DCD pin for each pad for slice 2." newline bitfld.long 0x40 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 8.--12. 1. "PHY_PAD_RX_DCD_6_2,Controls RX_DCD pin for each pad for slice 2." newline bitfld.long 0x40 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 0.--4. 1. "PHY_PAD_RX_DCD_5_2,Controls RX_DCD pin for each pad for slice 2." line.long 0x44 "DDRSS_PHY_604" hexmask.long.word 0x44 22.--31. 1. "RESERVED" hexmask.long.byte 0x44 16.--21. 1. "PHY_PAD_DSLICE_IO_CFG_2,Controls PCLK/PARK pin for pad for slice 2." newline bitfld.long 0x44 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 8.--12. 1. "PHY_PAD_FDBK_RX_DCD_2,Controls RX_DCD pin for fdbk pad for slice 2." newline bitfld.long 0x44 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 0.--4. 1. "PHY_PAD_DQS_RX_DCD_2,Controls RX_DCD pin for dqs pad for slice 2." line.long 0x48 "DDRSS_PHY_605" hexmask.long.byte 0x48 26.--31. 1. "RESERVED" hexmask.long.word 0x48 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_2,Read DQ1 slave delay setting for slice 2." newline hexmask.long.byte 0x48 10.--15. 1. "RESERVED" hexmask.long.word 0x48 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_2,Read DQ0 slave delay setting for slice 2." line.long 0x4C "DDRSS_PHY_606" hexmask.long.byte 0x4C 26.--31. 1. "RESERVED" hexmask.long.word 0x4C 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_2,Read DQ3 slave delay setting for slice 2." newline hexmask.long.byte 0x4C 10.--15. 1. "RESERVED" hexmask.long.word 0x4C 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_2,Read DQ2 slave delay setting for slice 2." line.long 0x50 "DDRSS_PHY_607" hexmask.long.byte 0x50 26.--31. 1. "RESERVED" hexmask.long.word 0x50 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_2,Read DQ5 slave delay setting for slice 2." newline hexmask.long.byte 0x50 10.--15. 1. "RESERVED" hexmask.long.word 0x50 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_2,Read DQ4 slave delay setting for slice 2." line.long 0x54 "DDRSS_PHY_608" hexmask.long.byte 0x54 26.--31. 1. "RESERVED" hexmask.long.word 0x54 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_2,Read DQ7 slave delay setting for slice 2." newline hexmask.long.byte 0x54 10.--15. 1. "RESERVED" hexmask.long.word 0x54 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_2,Read DQ6 slave delay setting for slice 2." line.long 0x58 "DDRSS_PHY_609" hexmask.long.word 0x58 19.--31. 1. "RESERVED" bitfld.long 0x58 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_2,Determines DCC CAL clock for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 10.--15. 1. "RESERVED" hexmask.long.word 0x58 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_2,Read DM/DBI slave delay setting for slice 2." line.long 0x5C "DDRSS_PHY_610" hexmask.long.byte 0x5C 24.--31. 1. "PHY_DQS_OE_TIMING_2,Start/end timing values for DQS output enable signals for slice 2." hexmask.long.byte 0x5C 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_2,Start/end timing values for DQ/DM write based termination enable and select signals for slice 2." newline hexmask.long.byte 0x5C 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_2,Start/end timing values for DQ/DM read based termination enable and select signals for slice 2." hexmask.long.byte 0x5C 0.--7. 1. "PHY_DQ_OE_TIMING_2,Start/end timing values for DQ/DM output enable signals for slice 2." line.long 0x60 "DDRSS_PHY_611" hexmask.long.byte 0x60 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_2,Start/end timing values for DQS write based termination enable and select signals for slice 2." hexmask.long.byte 0x60 16.--23. 1. "PHY_DQS_OE_RD_TIMING_2,Start/end timing values for DQS read based OE extension for slice 2." newline hexmask.long.byte 0x60 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_2,Start/end timing values for DQS read based termination enable and select signals for slice 2." hexmask.long.byte 0x60 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x60 0.--3. 1. "PHY_IO_PAD_DELAY_TIMING_2,Feedback pad's OPAD and IPAD delay timing for slice 2." line.long 0x64 "DDRSS_PHY_612" hexmask.long.byte 0x64 28.--31. 1. "RESERVED" hexmask.long.word 0x64 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_2,Pad VREF control settings for DQ slice 2." newline hexmask.long.word 0x64 0.--15. 1. "PHY_VREF_SETTING_TIME_2,Number of cycles for vref settle after setting is changed for slice 2." line.long 0x68 "DDRSS_PHY_613" hexmask.long.byte 0x68 26.--31. 1. "RESERVED" bitfld.long 0x68 24.--25. "PHY_RDDATA_EN_IE_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 2." "0,1,2,3" newline hexmask.long.byte 0x68 16.--23. 1. "PHY_DQS_IE_TIMING_2,Start/end timing values for DQS input enable signals for slice 2." hexmask.long.byte 0x68 8.--15. 1. "PHY_DQ_IE_TIMING_2,Start/end timing values for DQ/DM input enable signals for slice 2." newline hexmask.long.byte 0x68 1.--7. 1. "RESERVED" bitfld.long 0x68 0. "PHY_PER_CS_TRAINING_EN_2,Enables the per-rank training and read/write timing capabilities for slice 2." "0,1" line.long 0x6C "DDRSS_PHY_614" bitfld.long 0x6C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 24.--28. 1. "PHY_RDDATA_EN_OE_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 2." newline bitfld.long 0x6C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 16.--20. 1. "PHY_RDDATA_EN_TSEL_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 2." newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED" bitfld.long 0x6C 8. "PHY_DBI_MODE_2,DBI mode for slice 2." "0,1" newline hexmask.long.byte 0x6C 2.--7. 1. "RESERVED" bitfld.long 0x6C 0.--1. "PHY_IE_MODE_2,Input enable mode bits for slice 2." "0,1,2,3" line.long 0x70 "DDRSS_PHY_615" bitfld.long 0x70 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x70 24.--29. 1. "PHY_MASTER_DELAY_STEP_2,Incremental step size for master delay line locking algorithm for slice 2." newline hexmask.long.byte 0x70 19.--23. 1. "RESERVED" hexmask.long.word 0x70 8.--18. 1. "PHY_MASTER_DELAY_START_2,Start value for master delay line locking algorithm for slice 2." newline hexmask.long.byte 0x70 4.--7. 1. "RESERVED" hexmask.long.byte 0x70 0.--3. 1. "PHY_SW_MASTER_MODE_2,Master delay line override settings for slice 2." line.long 0x74 "DDRSS_PHY_616" hexmask.long.byte 0x74 24.--31. 1. "PHY_WRLVL_DLY_STEP_2,DQS slave delay step size during write leveling for slice 2." hexmask.long.byte 0x74 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x74 16.--19. 1. "PHY_RPTR_UPDATE_2,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 2." hexmask.long.byte 0x74 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_2,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 2." newline hexmask.long.byte 0x74 0.--7. 1. "PHY_MASTER_DELAY_WAIT_2,Wait cycles for master delay line locking algorithm for slice 2." line.long 0x78 "DDRSS_PHY_617" bitfld.long 0x78 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x78 24.--28. 1. "PHY_GTLVL_RESP_WAIT_CNT_2,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 2." newline hexmask.long.byte 0x78 20.--23. 1. "RESERVED" hexmask.long.byte 0x78 16.--19. 1. "PHY_GTLVL_DLY_STEP_2,DQS slave delay step size during gate training for slice 2." newline bitfld.long 0x78 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x78 8.--13. 1. "PHY_WRLVL_RESP_WAIT_CNT_2,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 2." newline hexmask.long.byte 0x78 4.--7. 1. "RESERVED" hexmask.long.byte 0x78 0.--3. 1. "PHY_WRLVL_DLY_FINE_STEP_2,DQS slave delay fine step size during write leveling for slice 2." line.long 0x7C "DDRSS_PHY_618" hexmask.long.byte 0x7C 26.--31. 1. "RESERVED" hexmask.long.word 0x7C 16.--25. 1. "PHY_GTLVL_FINAL_STEP_2,Final backup step delay used in gate training algorithm for slice 2." newline hexmask.long.byte 0x7C 10.--15. 1. "RESERVED" hexmask.long.word 0x7C 0.--9. 1. "PHY_GTLVL_BACK_STEP_2,Interim backup step delay used in gate training algorithm for slice 2." line.long 0x80 "DDRSS_PHY_619" hexmask.long.byte 0x80 28.--31. 1. "RESERVED" hexmask.long.byte 0x80 24.--27. 1. "PHY_RDLVL_DLY_STEP_2,DQS slave delay step size during read leveling for slice 2." newline hexmask.long.byte 0x80 17.--23. 1. "RESERVED" bitfld.long 0x80 16. "PHY_TOGGLE_PRE_SUPPORT_2,Support the toggle read preamble for LPDDR4 for slice 2." "0,1" newline hexmask.long.byte 0x80 12.--15. 1. "RESERVED" hexmask.long.byte 0x80 8.--11. 1. "PHY_WDQLVL_QTR_DLY_STEP_2,Defines the step granularity for the logic to use once an edge is found for slice 2." newline hexmask.long.byte 0x80 0.--7. 1. "PHY_WDQLVL_DLY_STEP_2,DQ slave delay step size during write data leveling for slice 2." line.long 0x84 "DDRSS_PHY_620" hexmask.long.tbyte 0x84 10.--31. 1. "RESERVED" hexmask.long.word 0x84 0.--9. 1. "PHY_RDLVL_MAX_EDGE_2,The maximun rdlvl slave delay search window for read eye training for slice 2." line.long 0x88 "DDRSS_PHY_621" bitfld.long 0x88 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x88 24.--29. 1. "PHY_RDLVL_PER_START_OFFSET_2,Peridic training start point offset for slice 2." newline hexmask.long.byte 0x88 17.--23. 1. "RESERVED" bitfld.long 0x88 16. "PHY_SW_RDLVL_DVW_MIN_EN_2,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 2." "0,1" newline hexmask.long.byte 0x88 10.--15. 1. "RESERVED" hexmask.long.word 0x88 0.--9. 1. "PHY_RDLVL_DVW_MIN_2,Minimum data valid window across DQs and ranks for slice 2." line.long 0x8C "DDRSS_PHY_622" hexmask.long.word 0x8C 18.--31. 1. "RESERVED" bitfld.long 0x8C 16.--17. "PHY_DATA_DC_INIT_DISABLE_2,Disable duty cycle adjust at initialization for slice 2." "0,1,2,3" newline hexmask.long.byte 0x8C 11.--15. 1. "RESERVED" bitfld.long 0x8C 8.--10. "PHY_WRPATH_GATE_TIMING_2,Write path clock gating timing for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8C 2.--7. 1. "RESERVED" bitfld.long 0x8C 0.--1. "PHY_WRPATH_GATE_DISABLE_2,Write path clock gating disable for slice 2." "0,1,2,3" line.long 0x90 "DDRSS_PHY_623" hexmask.long.byte 0x90 27.--31. 1. "RESERVED" hexmask.long.word 0x90 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_2,Initial value of write DQ slave delay for slice 2." newline hexmask.long.byte 0x90 10.--15. 1. "RESERVED" hexmask.long.word 0x90 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_2,Initial value of write DQS slave delay for slice 2." line.long 0x94 "DDRSS_PHY_624" hexmask.long.byte 0x94 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2,Clock measurement cell threshold offset for differential signals for slice 2." hexmask.long.byte 0x94 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_2,Clock measurement cell threshold offset for single ended signals for slice 2." newline hexmask.long.byte 0x94 9.--15. 1. "RESERVED" bitfld.long 0x94 8. "PHY_DATA_DC_WDQLVL_ENABLE_2,Enable duty cycle adjust during write DQ training for slice 2." "0,1" newline hexmask.long.byte 0x94 1.--7. 1. "RESERVED" bitfld.long 0x94 0. "PHY_DATA_DC_WRLVL_ENABLE_2,Enable duty cycle adjust during write leveling for slice 2." "0,1" line.long 0x98 "DDRSS_PHY_625" hexmask.long.word 0x98 21.--31. 1. "RESERVED" hexmask.long.byte 0x98 16.--20. 1. "PHY_RDDATA_EN_DLY_2,Number of cycles that the dfi_rddata_en signal is early for slice 2." newline bitfld.long 0x98 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x98 8.--13. 1. "PHY_MEAS_DLY_STEP_ENABLE_2,Data slice training step definition using phy_meas_dly_step_value for slice 2." newline bitfld.long 0x98 7. "RESERVED" "0,1" hexmask.long.byte 0x98 0.--6. 1. "PHY_WDQ_OSC_DELTA_2,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 2." line.long 0x9C "DDRSS_PHY_626" hexmask.long 0x9C 0.--31. 1. "PHY_DQ_DM_SWIZZLE0_2,DQ/DM bit swizzling 0 for slice 2." line.long 0xA0 "DDRSS_PHY_627" hexmask.long 0xA0 4.--31. 1. "RESERVED" hexmask.long.byte 0xA0 0.--3. 1. "PHY_DQ_DM_SWIZZLE1_2,DQ/DM bit swizzling 1 for slice 2." line.long 0xA4 "DDRSS_PHY_628" hexmask.long.byte 0xA4 27.--31. 1. "RESERVED" hexmask.long.word 0xA4 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_2,Write clock slave delay setting for DQ1 for slice 2." newline hexmask.long.byte 0xA4 11.--15. 1. "RESERVED" hexmask.long.word 0xA4 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_2,Write clock slave delay setting for DQ0 for slice 2." line.long 0xA8 "DDRSS_PHY_629" hexmask.long.byte 0xA8 27.--31. 1. "RESERVED" hexmask.long.word 0xA8 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_2,Write clock slave delay setting for DQ3 for slice 2." newline hexmask.long.byte 0xA8 11.--15. 1. "RESERVED" hexmask.long.word 0xA8 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_2,Write clock slave delay setting for DQ2 for slice 2." line.long 0xAC "DDRSS_PHY_630" hexmask.long.byte 0xAC 27.--31. 1. "RESERVED" hexmask.long.word 0xAC 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_2,Write clock slave delay setting for DQ5 for slice 2." newline hexmask.long.byte 0xAC 11.--15. 1. "RESERVED" hexmask.long.word 0xAC 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_2,Write clock slave delay setting for DQ4 for slice 2." line.long 0xB0 "DDRSS_PHY_631" hexmask.long.byte 0xB0 27.--31. 1. "RESERVED" hexmask.long.word 0xB0 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_2,Write clock slave delay setting for DQ7 for slice 2." newline hexmask.long.byte 0xB0 11.--15. 1. "RESERVED" hexmask.long.word 0xB0 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_2,Write clock slave delay setting for DQ6 for slice 2." line.long 0xB4 "DDRSS_PHY_632" hexmask.long.byte 0xB4 26.--31. 1. "RESERVED" hexmask.long.word 0xB4 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_2,Write clock slave delay setting for DQS for slice 2." newline hexmask.long.byte 0xB4 11.--15. 1. "RESERVED" hexmask.long.word 0xB4 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_2,Write clock slave delay setting for DM for slice 2." line.long 0xB8 "DDRSS_PHY_633" hexmask.long.word 0xB8 18.--31. 1. "RESERVED" hexmask.long.word 0xB8 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ0 for slice 2." newline hexmask.long.byte 0xB8 2.--7. 1. "RESERVED" bitfld.long 0xB8 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_2,Write level threshold adjust value based on those thresholds for DQS for slice 2." "0,1,2,3" line.long 0xBC "DDRSS_PHY_634" hexmask.long.byte 0xBC 26.--31. 1. "RESERVED" hexmask.long.word 0xBC 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ1 for slice 2." newline hexmask.long.byte 0xBC 10.--15. 1. "RESERVED" hexmask.long.word 0xBC 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ0 for slice 2." line.long 0xC0 "DDRSS_PHY_635" hexmask.long.byte 0xC0 26.--31. 1. "RESERVED" hexmask.long.word 0xC0 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ2 for slice 2." newline hexmask.long.byte 0xC0 10.--15. 1. "RESERVED" hexmask.long.word 0xC0 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ1 for slice 2." line.long 0xC4 "DDRSS_PHY_636" hexmask.long.byte 0xC4 26.--31. 1. "RESERVED" hexmask.long.word 0xC4 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ3 for slice 2." newline hexmask.long.byte 0xC4 10.--15. 1. "RESERVED" hexmask.long.word 0xC4 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ2 for slice 2." line.long 0xC8 "DDRSS_PHY_637" hexmask.long.byte 0xC8 26.--31. 1. "RESERVED" hexmask.long.word 0xC8 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ4 for slice 2." newline hexmask.long.byte 0xC8 10.--15. 1. "RESERVED" hexmask.long.word 0xC8 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ3 for slice 2." line.long 0xCC "DDRSS_PHY_638" hexmask.long.byte 0xCC 26.--31. 1. "RESERVED" hexmask.long.word 0xCC 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ5 for slice 2." newline hexmask.long.byte 0xCC 10.--15. 1. "RESERVED" hexmask.long.word 0xCC 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ4 for slice 2." line.long 0xD0 "DDRSS_PHY_639" hexmask.long.byte 0xD0 26.--31. 1. "RESERVED" hexmask.long.word 0xD0 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ6 for slice 2." newline hexmask.long.byte 0xD0 10.--15. 1. "RESERVED" hexmask.long.word 0xD0 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ5 for slice 2." line.long 0xD4 "DDRSS_PHY_640" hexmask.long.byte 0xD4 26.--31. 1. "RESERVED" hexmask.long.word 0xD4 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ7 for slice 2." newline hexmask.long.byte 0xD4 10.--15. 1. "RESERVED" hexmask.long.word 0xD4 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ6 for slice 2." line.long 0xD8 "DDRSS_PHY_641" hexmask.long.byte 0xD8 26.--31. 1. "RESERVED" hexmask.long.word 0xD8 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DM for slice 2." newline hexmask.long.byte 0xD8 10.--15. 1. "RESERVED" hexmask.long.word 0xD8 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ7 for slice 2." line.long 0xDC "DDRSS_PHY_642" hexmask.long.byte 0xDC 26.--31. 1. "RESERVED" hexmask.long.word 0xDC 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_2,Read DQS slave delay setting for slice 2." newline hexmask.long.byte 0xDC 10.--15. 1. "RESERVED" hexmask.long.word 0xDC 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DM for slice 2." line.long 0xE0 "DDRSS_PHY_643" hexmask.long.byte 0xE0 26.--31. 1. "RESERVED" hexmask.long.word 0xE0 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_2,Write level delay threshold above which will be considered in previous cycle for slice 2." newline hexmask.long.byte 0xE0 11.--15. 1. "RESERVED" bitfld.long 0xE0 8.--10. "PHY_WRITE_PATH_LAT_ADD_2,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 2." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE0 4.--7. 1. "RESERVED" hexmask.long.byte 0xE0 0.--3. 1. "PHY_RDDQS_LATENCY_ADJUST_2,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 2." line.long 0xE4 "DDRSS_PHY_644" hexmask.long.word 0xE4 17.--31. 1. "RESERVED" bitfld.long 0xE4 16. "PHY_WRLVL_EARLY_FORCE_ZERO_2,Force the final write level delay value (that meets the early threshold) to 0 for slice 2." "0,1" newline hexmask.long.byte 0xE4 10.--15. 1. "RESERVED" hexmask.long.word 0xE4 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2,Write level delay threshold below which will add a cycle of write path latency for slice 2." line.long 0xE8 "DDRSS_PHY_645" hexmask.long.word 0xE8 20.--31. 1. "RESERVED" hexmask.long.byte 0xE8 16.--19. 1. "PHY_GTLVL_LAT_ADJ_START_2,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 2." newline hexmask.long.byte 0xE8 10.--15. 1. "RESERVED" hexmask.long.word 0xE8 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_2,Initial read DQS gate slave delay setting during gate training for slice 2." line.long 0xEC "DDRSS_PHY_646" hexmask.long.byte 0xEC 25.--31. 1. "RESERVED" bitfld.long 0xEC 24. "PHY_NTP_PASS_2,Indicates if No-topology training found a passing result for slice 2." "0,1" newline hexmask.long.byte 0xEC 20.--23. 1. "RESERVED" hexmask.long.byte 0xEC 16.--19. 1. "PHY_NTP_WRLAT_START_2,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 2." newline hexmask.long.byte 0xEC 11.--15. 1. "RESERVED" hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_2,Initial DQ/DM slave delay setting during write data leveling for slice 2." line.long 0xF0 "DDRSS_PHY_647" hexmask.long.tbyte 0xF0 10.--31. 1. "RESERVED" hexmask.long.word 0xF0 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2,Read leveling starting value for the DQS/DQ slave delay settings for slice 2." line.long 0xF4 "DDRSS_PHY_648" hexmask.long.byte 0xF4 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." hexmask.long.byte 0xF4 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." newline hexmask.long.byte 0xF4 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." hexmask.long.byte 0xF4 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." line.long 0xF8 "DDRSS_PHY_649" hexmask.long.byte 0xF8 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." hexmask.long.byte 0xF8 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." newline hexmask.long.byte 0xF8 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." hexmask.long.byte 0xF8 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." line.long 0xFC "DDRSS_PHY_650" hexmask.long.word 0xFC 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_2,Setting for boost P/N of pad for slice 2." hexmask.long.byte 0xFC 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." newline hexmask.long.byte 0xFC 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2." line.long 0x100 "DDRSS_PHY_651" hexmask.long.word 0x100 18.--31. 1. "RESERVED" bitfld.long 0x100 16.--17. "PHY_DQS_FFE_2,TX_FFE setting for DQS pad for slice 2." "0,1,2,3" newline hexmask.long.byte 0x100 10.--15. 1. "RESERVED" bitfld.long 0x100 8.--9. "PHY_DQ_FFE_2,TX_FFE setting for DQ/DM pad for slice 2." "0,1,2,3" newline bitfld.long 0x100 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x100 0.--5. 1. "PHY_DSLICE_PAD_RX_CTLE_SETTING_2,Setting for RX ctle P/N of pad for slice 2." group.long 0x4C00++0x27 line.long 0x0 "DDRSS_PHY_768" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--19. 1. "PHY_IO_PAD_DELAY_TIMING_BYPASS_3,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 3." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_3,Write data clock bypass mode slave delay setting for slice 3.} PADDING_BEFORE" line.long 0x4 "DDRSS_PHY_769" hexmask.long.word 0x4 19.--31. 1. "RESERVED" bitfld.long 0x4 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_3,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3,Write DQS bypass mode slave delay setting for slice 3." line.long 0x8 "DDRSS_PHY_770" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "PHY_CLK_BYPASS_OVERRIDE_3,Bypass mode override setting for slice 3." "0,1" newline hexmask.long.byte 0x8 18.--23. 1. "RESERVED" bitfld.long 0x8 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_3,Two_cycle_preamble for bypass mode for slice 3." "0,1,2,3" newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3,Read DQS bypass mode slave delay setting for slice 3." line.long 0xC "DDRSS_PHY_771" bitfld.long 0xC 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 24.--29. 1. "PHY_SW_WRDQ3_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 3." newline bitfld.long 0xC 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 16.--21. 1. "PHY_SW_WRDQ2_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 3." newline bitfld.long 0xC 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 8.--13. 1. "PHY_SW_WRDQ1_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 3." newline bitfld.long 0xC 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "PHY_SW_WRDQ0_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 3." line.long 0x10 "DDRSS_PHY_772" bitfld.long 0x10 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 24.--29. 1. "PHY_SW_WRDQ7_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 3." newline bitfld.long 0x10 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 16.--21. 1. "PHY_SW_WRDQ6_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 3." newline bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 8.--13. 1. "PHY_SW_WRDQ5_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 3." newline bitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 0.--5. 1. "PHY_SW_WRDQ4_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 3." line.long 0x14 "DDRSS_PHY_773" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_3,When set a register write will update parameters for all ranks at the same time in slice 3." "0,1" newline hexmask.long.byte 0x14 18.--23. 1. "RESERVED" bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_3,Per-rank CS map for slice 3." "0,1,2,3" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED" hexmask.long.byte 0x14 8.--11. 1. "PHY_SW_WRDQS_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 3." newline bitfld.long 0x14 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 0.--5. 1. "PHY_SW_WRDM_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 3." line.long 0x18 "DDRSS_PHY_774" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 3." newline bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 16.--20. 1. "PHY_LP4_BOOT_RDDATA_EN_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 3." newline hexmask.long.byte 0x18 10.--15. 1. "RESERVED" bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 3." "0,1,2,3" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED" bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_3,For per-rank training indicates which rank's paramters are read/written for slice 3." "0,1" line.long 0x1C "DDRSS_PHY_775" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 3." newline hexmask.long.byte 0x1C 18.--23. 1. "RESERVED" bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3,For LPDDR4 boot frequency write path clock gating disable for slice 3." "0,1,2,3" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED" hexmask.long.byte 0x1C 8.--11. 1. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 3." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED" hexmask.long.byte 0x1C 0.--3. 1. "PHY_LP4_BOOT_RPTR_UPDATE_3,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 3." line.long 0x20 "DDRSS_PHY_776" hexmask.long.byte 0x20 25.--31. 1. "RESERVED" bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_3,Loopback read only test timeout mechanism enable for slice 3." "0,1" newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_3,Loopback control bits for slice 3." newline hexmask.long.byte 0x20 2.--7. 1. "RESERVED" bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_3,Loopback control en for slice 3." "0,1,2,3" line.long 0x24 "DDRSS_PHY_777" hexmask.long 0x24 0.--31. 1. "PHY_AUTO_TIMING_MARGIN_CONTROL_3,Auto timing marging control bits for slice 3." rgroup.long 0x4C28++0x3 line.long 0x0 "DDRSS_PHY_778" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_3,Observation register for the auto_timing_margin for slice 3." group.long 0x4C2C++0x13 line.long 0x0 "DDRSS_PHY_779" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RDLVL_MULTI_PATT_ENABLE_3,Read Leveling Multi-pattern enable for slice 3." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" hexmask.long.word 0x0 8.--16. 1. "PHY_PRBS_PATTERN_MASK_3,PRBS7 mask signal for slice 3." newline bitfld.long 0x0 7. "RESERVED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "PHY_PRBS_PATTERN_START_3,PRBS7 start pattern for slice 3." line.long 0x4 "DDRSS_PHY_780" hexmask.long.word 0x4 23.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--22. 1. "PHY_VREF_TRAIN_OBS_3,Observation register for best vref value for slice 3." newline bitfld.long 0x4 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "PHY_VREF_INITIAL_STEPSIZE_3,Data slice initial VREF training step size for slice 3." newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED" bitfld.long 0x4 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_3,Read Leveling read level windows disable reset for slice 3." "0,1" line.long 0x8 "DDRSS_PHY_781" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "SC_PHY_SNAP_OBS_REGS_3,Initiates a snapshot of the internal observation registers for slice 3." "0,1" newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED" hexmask.long.byte 0x8 16.--19. 1. "PHY_GATE_ERROR_DELAY_SELECT_3,Number of cycles to wait for the DQS gate to close before flagging an error for slice 3." newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3,Read DQS data clock bypass mode slave delay setting for slice 3." line.long 0xC "DDRSS_PHY_782" hexmask.long.byte 0xC 27.--31. 1. "RESERVED" bitfld.long 0xC 24.--26. "PHY_MEM_CLASS_3,Indicates the type of DRAM for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 17.--23. 1. "RESERVED" bitfld.long 0xC 16. "PHY_LPDDR_3,Adds a cycle of delay for the slice 3 to match the address slice." "0,1" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_3,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 3." line.long 0x10 "DDRSS_PHY_783" hexmask.long.word 0x10 18.--31. 1. "RESERVED" bitfld.long 0x10 16.--17. "ON_FLY_GATE_ADJUST_EN_3,Control the on-the-fly gate adjustment for slice 3." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_3,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 3." rgroup.long 0x4C40++0x3 line.long 0x0 "DDRSS_PHY_784" hexmask.long 0x0 0.--31. 1. "PHY_GATE_TRACKING_OBS_3,Report the on-the-fly gate measurement result for slice 3." group.long 0x4C44++0x6B line.long 0x0 "DDRSS_PHY_785" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" bitfld.long 0x0 8.--9. "PHY_LP4_PST_AMBLE_3,Controls the read postamble extension for LPDDR4 for slice 3." "0,1,2,3" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_DFI40_POLARITY_3,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 3." "0,1" line.long 0x4 "DDRSS_PHY_786" hexmask.long 0x4 0.--31. 1. "PHY_RDLVL_PATT8_3,Read leveling pattern 8 data for slice 3." line.long 0x8 "DDRSS_PHY_787" hexmask.long 0x8 0.--31. 1. "PHY_RDLVL_PATT9_3,Read leveling pattern 9 data for slice 3." line.long 0xC "DDRSS_PHY_788" hexmask.long 0xC 0.--31. 1. "PHY_RDLVL_PATT10_3,Read leveling pattern 10 data for slice 3." line.long 0x10 "DDRSS_PHY_789" hexmask.long 0x10 0.--31. 1. "PHY_RDLVL_PATT11_3,Read leveling pattern 11 data for slice 3." line.long 0x14 "DDRSS_PHY_790" hexmask.long 0x14 0.--31. 1. "PHY_RDLVL_PATT12_3,Read leveling pattern 12 data for slice 3." line.long 0x18 "DDRSS_PHY_791" hexmask.long 0x18 0.--31. 1. "PHY_RDLVL_PATT13_3,Read leveling pattern 13 data for slice 3." line.long 0x1C "DDRSS_PHY_792" hexmask.long 0x1C 0.--31. 1. "PHY_RDLVL_PATT14_3,Read leveling pattern 14 data for slice 3." line.long 0x20 "DDRSS_PHY_793" hexmask.long 0x20 0.--31. 1. "PHY_RDLVL_PATT15_3,Read leveling pattern 15 data for slice 3." line.long 0x24 "DDRSS_PHY_794" hexmask.long.byte 0x24 27.--31. 1. "RESERVED" bitfld.long 0x24 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_3,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 20.--23. 1. "RESERVED" hexmask.long.byte 0x24 16.--19. 1. "PHY_MASTER_DLY_LOCK_OBS_SELECT_3,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 3." newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED" bitfld.long 0x24 8. "PHY_SW_FIFO_PTR_RST_DISABLE_3,Disables automatic reset of the read entry FIFO pointers for slice 3." "0,1" newline hexmask.long.byte 0x24 3.--7. 1. "RESERVED" bitfld.long 0x24 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_3,Reserved for future use for slice 3." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_PHY_795" hexmask.long.byte 0x28 28.--31. 1. "RESERVED" hexmask.long.byte 0x28 24.--27. 1. "PHY_FIFO_PTR_OBS_SELECT_3,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 3." newline hexmask.long.byte 0x28 20.--23. 1. "RESERVED" hexmask.long.byte 0x28 16.--19. 1. "PHY_WR_SHIFT_OBS_SELECT_3,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 3." newline hexmask.long.byte 0x28 12.--15. 1. "RESERVED" hexmask.long.byte 0x28 8.--11. 1. "PHY_WR_ENC_OBS_SELECT_3,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 3." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED" hexmask.long.byte 0x28 0.--3. 1. "PHY_RDDQS_DQ_ENC_OBS_SELECT_3,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 3." line.long 0x2C "DDRSS_PHY_796" hexmask.long.byte 0x2C 24.--31. 1. "PHY_WRLVL_PER_START_3,Observation register for write leveling status for slice 3." hexmask.long.byte 0x2C 18.--23. 1. "RESERVED" newline bitfld.long 0x2C 16.--17. "PHY_WRLVL_ALGO_3,Write leveling algorithm selection for slice 3." "0,1,2,3" hexmask.long.byte 0x2C 9.--15. 1. "RESERVED" newline bitfld.long 0x2C 8. "SC_PHY_LVL_DEBUG_CONT_3,Allows the leveling state machine to advance (when in debug mode) for slice 3." "0,1" hexmask.long.byte 0x2C 1.--7. 1. "RESERVED" newline bitfld.long 0x2C 0. "PHY_LVL_DEBUG_MODE_3,Enables leveling debug mode for slice 3." "0,1" line.long 0x30 "DDRSS_PHY_797" hexmask.long.byte 0x30 24.--31. 1. "RESERVED" hexmask.long.byte 0x30 16.--23. 1. "PHY_DQ_MASK_3,For ECC slice should set this register to do DQ bit mask for slice 3." newline hexmask.long.byte 0x30 12.--15. 1. "RESERVED" hexmask.long.byte 0x30 8.--11. 1. "PHY_WRLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 3." newline bitfld.long 0x30 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x30 0.--5. 1. "PHY_WRLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during write leveling for slice 3." line.long 0x34 "DDRSS_PHY_798" hexmask.long.byte 0x34 28.--31. 1. "RESERVED" hexmask.long.byte 0x34 24.--27. 1. "PHY_GTLVL_UPDT_WAIT_CNT_3,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 3." newline bitfld.long 0x34 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x34 16.--21. 1. "PHY_GTLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during gate training for slice 3." newline hexmask.long.byte 0x34 10.--15. 1. "RESERVED" hexmask.long.word 0x34 0.--9. 1. "PHY_GTLVL_PER_START_3,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 3." line.long 0x38 "DDRSS_PHY_799" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 3." newline hexmask.long.byte 0x38 18.--23. 1. "RESERVED" bitfld.long 0x38 16.--17. "PHY_RDLVL_OP_MODE_3,Read leveling algorithm select for slice 3." "0,1,2,3" newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.byte 0x38 8.--11. 1. "PHY_RDLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 3." newline bitfld.long 0x38 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "PHY_RDLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during read leveling for slice 3." line.long 0x3C "DDRSS_PHY_800" bitfld.long 0x3C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x3C 24.--29. 1. "PHY_WDQLVL_BURST_CNT_3,Defines the write/read burst length in bytes during the write data leveling sequence for slice 3." newline hexmask.long.byte 0x3C 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_3,Defines the minimum gap requirment for the LE and TE window for slice 3." hexmask.long.byte 0x3C 8.--15. 1. "PHY_RDLVL_DATA_MASK_3,Per-bit mask for read leveling for slice 3." newline hexmask.long.byte 0x3C 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 3." line.long 0x40 "DDRSS_PHY_801" hexmask.long.byte 0x40 28.--31. 1. "RESERVED" hexmask.long.byte 0x40 24.--27. 1. "PHY_WDQLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 3." newline hexmask.long.byte 0x40 19.--23. 1. "RESERVED" hexmask.long.word 0x40 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3,Defines the write/read burst length in bytes during the write data leveling sequence for slice 3." newline hexmask.long.byte 0x40 3.--7. 1. "RESERVED" bitfld.long 0x40 0.--2. "PHY_WDQLVL_PATT_3,Defines the training patterns to be used during the write data leveling sequence for slice 3." "0,1,2,3,4,5,6,7" line.long 0x44 "DDRSS_PHY_802" hexmask.long.word 0x44 17.--31. 1. "RESERVED" bitfld.long 0x44 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_3,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 3." "0,1" newline hexmask.long.byte 0x44 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_3,Select value to map specific information during or post periodic write data leveling for slice 3." hexmask.long.byte 0x44 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x44 0.--3. 1. "PHY_WDQLVL_DQDM_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 3." line.long 0x48 "DDRSS_PHY_803" hexmask.long.tbyte 0x48 9.--31. 1. "RESERVED" hexmask.long.word 0x48 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_3,Per-bit mask for write data leveling for slice 3." line.long 0x4C "DDRSS_PHY_804" hexmask.long 0x4C 0.--31. 1. "PHY_USER_PATT0_3,User-defined pattern to be used during write data leveling for slice 3." line.long 0x50 "DDRSS_PHY_805" hexmask.long 0x50 0.--31. 1. "PHY_USER_PATT1_3,User-defined pattern to be used during write data leveling for slice 3." line.long 0x54 "DDRSS_PHY_806" hexmask.long 0x54 0.--31. 1. "PHY_USER_PATT2_3,User-defined pattern to be used during write data leveling for slice 3." line.long 0x58 "DDRSS_PHY_807" hexmask.long 0x58 0.--31. 1. "PHY_USER_PATT3_3,User-defined pattern to be used during write data leveling for slice 3." line.long 0x5C "DDRSS_PHY_808" hexmask.long.word 0x5C 17.--31. 1. "RESERVED" bitfld.long 0x5C 16. "PHY_NTP_MULT_TRAIN_3,Control for single pass only No-Topology training for slice 3." "0,1" newline hexmask.long.word 0x5C 0.--15. 1. "PHY_USER_PATT4_3,User-defined pattern to be used during write data leveling for slice 3." line.long 0x60 "DDRSS_PHY_809" hexmask.long.byte 0x60 26.--31. 1. "RESERVED" hexmask.long.word 0x60 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_3,Threshold Criteria of period threshold after No-Topology training is completed for slice 3." newline hexmask.long.byte 0x60 10.--15. 1. "RESERVED" hexmask.long.word 0x60 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_3,Threshold Criteria of early threshold after No-Topology training is completed for slice 3." line.long 0x64 "DDRSS_PHY_810" hexmask.long.byte 0x64 26.--31. 1. "RESERVED" hexmask.long.word 0x64 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_3,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 3." newline hexmask.long.byte 0x64 10.--15. 1. "RESERVED" hexmask.long.word 0x64 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_3,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 3." line.long 0x68 "DDRSS_PHY_811" hexmask.long.byte 0x68 24.--31. 1. "RESERVED" hexmask.long.byte 0x68 16.--23. 1. "PHY_FIFO_PTR_OBS_3,Observation register containing read entry FIFO pointers for slice 3." newline bitfld.long 0x68 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x68 8.--13. 1. "SC_PHY_MANUAL_CLEAR_3,Manual reset/clear of internal logic for slice 3." newline hexmask.long.byte 0x68 1.--7. 1. "RESERVED" bitfld.long 0x68 0. "PHY_CALVL_VREF_DRIVING_SLICE_3,Indicates if slice 3 is used to drive the VREF value to the device during CA training." "0,1" rgroup.long 0x4CB0++0x47 line.long 0x0 "DDRSS_PHY_812" hexmask.long 0x0 0.--31. 1. "PHY_LPBK_RESULT_OBS_3,Observation register containing loopback status/results for slice 3." line.long 0x4 "DDRSS_PHY_813" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_3,Observation register containing master delay results for slice 3." newline hexmask.long.word 0x4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_3,Observation register containing total number of loopback error data for slice 3." line.long 0x8 "DDRSS_PHY_814" hexmask.long.byte 0x8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 3." hexmask.long.byte 0x8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_3,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 3." newline bitfld.long 0x8 15. "RESERVED" "0,1" hexmask.long.byte 0x8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3,Observation register containing read DQS base slave delay encoded value for slice 3." newline bitfld.long 0x8 7. "RESERVED" "0,1" hexmask.long.byte 0x8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_3,Observation register containing read DQ slave delay encoded values for slice 3." line.long 0xC "DDRSS_PHY_815" bitfld.long 0xC 31. "RESERVED" "0,1" hexmask.long.byte 0xC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3,Observation register containing write DQS base slave delay encoded value for slice 3." newline hexmask.long.byte 0xC 19.--23. 1. "RESERVED" hexmask.long.word 0xC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3,Observation register containing read DQS gate slave delay encoded value for slice 3." newline hexmask.long.byte 0xC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 3." line.long 0x10 "DDRSS_PHY_816" hexmask.long.word 0x10 19.--31. 1. "RESERVED" bitfld.long 0x10 16.--18. "PHY_WR_SHIFT_OBS_3,Observation register containing automatic half cycle and cycle shift values for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing write adder slave delay encoded value for slice 3." hexmask.long.byte 0x10 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3,Observation register containing write DQ base slave delay encoded value for slice 3." line.long 0x14 "DDRSS_PHY_817" hexmask.long.byte 0x14 26.--31. 1. "RESERVED" hexmask.long.word 0x14 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_3,Observation register containing write leveling first hard 1 DQS slave delay for slice 3." newline hexmask.long.byte 0x14 10.--15. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_3,Observation register containing write leveling last hard 0 DQS slave delay for slice 3." line.long 0x18 "DDRSS_PHY_818" hexmask.long.word 0x18 17.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--16. 1. "PHY_WRLVL_STATUS_OBS_3,Observation register containing write leveling status for slice 3." line.long 0x1C "DDRSS_PHY_819" hexmask.long.byte 0x1C 26.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3,Observation register containing gate sample2 slave delay encoded values for slice 3." newline hexmask.long.byte 0x1C 10.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3,Observation register containing gate sample1 slave delay encoded values for slice 3." line.long 0x20 "DDRSS_PHY_820" bitfld.long 0x20 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x20 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_3,Observation register containing gate training first hard 0 DQS slave delay for slice 3." newline hexmask.long.word 0x20 0.--15. 1. "PHY_WRLVL_ERROR_OBS_3,Observation register containing write leveling error status for slice 3." line.long 0x24 "DDRSS_PHY_821" hexmask.long.tbyte 0x24 14.--31. 1. "RESERVED" hexmask.long.word 0x24 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_3,Observation register containing gate training last hard 1 DQS slave delay for slice 3." line.long 0x28 "DDRSS_PHY_822" hexmask.long.word 0x28 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x28 0.--17. 1. "PHY_GTLVL_STATUS_OBS_3,Observation register containing gate training status for slice 3." line.long 0x2C "DDRSS_PHY_823" hexmask.long.byte 0x2C 26.--31. 1. "RESERVED" hexmask.long.word 0x2C 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3,Observation register containing read leveling data window trailing edge slave delay setting for slice 3." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" hexmask.long.word 0x2C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3,Observation register containing read leveling data window leading edge slave delay setting for slice 3." line.long 0x30 "DDRSS_PHY_824" hexmask.long 0x30 2.--31. 1. "RESERVED" bitfld.long 0x30 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3,Observation register containing read leveling number of windows found for slice 3." "0,1,2,3" line.long 0x34 "DDRSS_PHY_825" hexmask.long 0x34 0.--31. 1. "PHY_RDLVL_STATUS_OBS_3,Observation register containing read leveling status for slice 3." line.long 0x38 "DDRSS_PHY_826" hexmask.long 0x38 0.--31. 1. "PHY_RDLVL_PERIODIC_OBS_3,Observation register containing periodic read leveling status for slice 3." line.long 0x3C "DDRSS_PHY_827" hexmask.long.byte 0x3C 27.--31. 1. "RESERVED" hexmask.long.word 0x3C 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_3,Observation register containing write data leveling data window trailing edge slave delay setting for slice 3." newline hexmask.long.byte 0x3C 11.--15. 1. "RESERVED" hexmask.long.word 0x3C 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_3,Observation register containing write data leveling data window leading edge slave delay setting for slice 3." line.long 0x40 "DDRSS_PHY_828" hexmask.long 0x40 0.--31. 1. "PHY_WDQLVL_STATUS_OBS_3,Observation register containing write data leveling status for slice 3." line.long 0x44 "DDRSS_PHY_829" hexmask.long 0x44 0.--31. 1. "PHY_WDQLVL_PERIODIC_OBS_3,Observation register containing periodic write data leveling status for slice 3." group.long 0x4CF8++0x7 line.long 0x0 "DDRSS_PHY_830" bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long 0x0 0.--30. 1. "PHY_DDL_MODE_3,DDL mode for slice 3." line.long 0x4 "DDRSS_PHY_831" hexmask.long 0x4 6.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "PHY_DDL_MASK_3,DDL mask for slice 3." rgroup.long 0x4D00++0x7 line.long 0x0 "DDRSS_PHY_832" hexmask.long 0x0 0.--31. 1. "PHY_DDL_TEST_OBS_3,DDL test observation for slice 3." line.long 0x4 "DDRSS_PHY_833" hexmask.long 0x4 0.--31. 1. "PHY_DDL_TEST_MSTR_DLY_OBS_3,DDL test observation delays for slice 3 master DDL." group.long 0x4D08++0x1F line.long 0x0 "DDRSS_PHY_834" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RX_CAL_OVERRIDE_3,Manual setting of RX Calibration enable for slice 3." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" bitfld.long 0x0 16. "SC_PHY_RX_CAL_START_3,Manual RX Calibration start for slice 3." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" bitfld.long 0x0 8. "PHY_LP4_WDQS_OE_EXTEND_3,LPDDR4 write preamble extension enable for slice 3." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_3,Specify threshold value for PHY init update tracking for slice 3." line.long 0x4 "DDRSS_PHY_835" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--24. 1. "PHY_RX_CAL_DQ0_3,RX Calibration codes for DQ0 for slice 3." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3,Data slice power reduction disable for slice 3." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_3,RX Calibration state machine wait count for slice 3." line.long 0x8 "DDRSS_PHY_836" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" hexmask.long.word 0x8 16.--24. 1. "PHY_RX_CAL_DQ2_3,RX Calibration codes for DQ2 for slice 3." newline hexmask.long.byte 0x8 9.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--8. 1. "PHY_RX_CAL_DQ1_3,RX Calibration codes for DQ1 for slice 3." line.long 0xC "DDRSS_PHY_837" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" hexmask.long.word 0xC 16.--24. 1. "PHY_RX_CAL_DQ4_3,RX Calibration codes for DQ4 for slice 3." newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "PHY_RX_CAL_DQ3_3,RX Calibration codes for DQ3 for slice 3." line.long 0x10 "DDRSS_PHY_838" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--24. 1. "PHY_RX_CAL_DQ6_3,RX Calibration codes for DQ6 for slice 3." newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "PHY_RX_CAL_DQ5_3,RX Calibration codes for DQ5 for slice 3." line.long 0x14 "DDRSS_PHY_839" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--8. 1. "PHY_RX_CAL_DQ7_3,RX Calibration codes for DQ7 for slice 3." line.long 0x18 "DDRSS_PHY_840" hexmask.long.word 0x18 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--17. 1. "PHY_RX_CAL_DM_3,RX Calibration codes for DM for slice 3." line.long 0x1C "DDRSS_PHY_841" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--24. 1. "PHY_RX_CAL_FDBK_3,RX Calibration codes for FDBK for slice 3." newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--8. 1. "PHY_RX_CAL_DQS_3,RX Calibration codes for DQS for slice 3." rgroup.long 0x4D28++0x3 line.long 0x0 "DDRSS_PHY_842" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_3,RX Calibration lock results for slice 3." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_RX_CAL_OBS_3,RX Calibration results for slice 3." group.long 0x4D2C++0x103 line.long 0x0 "DDRSS_PHY_843" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_RX_CAL_COMP_VAL_3,Expected C value from RX pad for slice 3." "0,1" newline bitfld.long 0x0 23. "RESERVED" "0,1" hexmask.long.byte 0x0 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_3,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 3." newline bitfld.long 0x0 15. "RESERVED" "0,1" hexmask.long.byte 0x0 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_3,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 3." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_RX_CAL_DISABLE_3,RX CAL disable signal for slice 3 set 1 to bypass the rx calibration" "0,1" line.long 0x4 "DDRSS_PHY_844" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--26. 1. "PHY_PAD_RX_BIAS_EN_3,Controls RX_BIAS_EN pin for each pad for slice 3." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED" hexmask.long.word 0x4 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_3,RX offset calibration mask of all RX pad for slice 3." line.long 0x8 "DDRSS_PHY_845" hexmask.long.byte 0x8 26.--31. 1. "RESERVED" bitfld.long 0x8 24.--25. "PHY_DATA_DC_WEIGHT_3,Determines weight of average calculating for slice 3." "0,1,2,3" newline hexmask.long.byte 0x8 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_3,Determines timeout number of iteration for slice 3." hexmask.long.byte 0x8 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_3,Determines number of cycles to wait for each sample for slice 3." newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PHY_STATIC_TOG_DISABLE_3,Control to disable toggle during static activity for slice 3." line.long 0xC "DDRSS_PHY_846" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "PHY_DATA_DC_ADJUST_DIRECT_3,Adjust direction for slice 3." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_3,Duty cycle adjust threshold around the mid-point for slice 3." hexmask.long.byte 0xC 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_3,Duty cycle adjust sample count for slice 3." newline bitfld.long 0xC 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "PHY_DATA_DC_ADJUST_START_3,Duty cycle adjust starting value for slice 3." line.long 0x10 "DDRSS_PHY_847" hexmask.long.byte 0x10 27.--31. 1. "RESERVED" bitfld.long 0x10 24.--26. "PHY_FDBK_PWR_CTRL_3,Shutoff gate feedback IO to reduce power for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 18.--23. 1. "RESERVED" bitfld.long 0x10 16.--17. "PHY_DATA_DC_SW_RANK_3,Rank selection for software based duty cycle correction for slice 3." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "PHY_DATA_DC_CAL_START_3,Manual trigger for DCC for slice 3." "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "PHY_DATA_DC_CAL_POLARITY_3,Calibration polarity for slice 3." "0,1" line.long 0x14 "DDRSS_PHY_848" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PHY_SLICE_PWR_RDC_DISABLE_3,Data slice power reduction disable for slice 3." "0,1" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" bitfld.long 0x14 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3,Data slice DCC and RX_CAL block power reduction disable for slice 3." "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "PHY_RDPATH_GATE_DISABLE_3,Data slice read path power reduction disable for slice 3." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_3,Data slice slv_dly_control block power reduction disable for slice 3." "0,1" line.long 0x18 "DDRSS_PHY_849" bitfld.long 0x18 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x18 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_3,Data slice level FSM Error Info for slice 3." newline hexmask.long.byte 0x18 11.--15. 1. "RESERVED" hexmask.long.word 0x18 0.--10. 1. "PHY_PARITY_ERROR_REGIF_3,Inject parity error to register interface signals for slice 3." line.long 0x1C "DDRSS_PHY_850" bitfld.long 0x1C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x1C 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3,Data slice level FSM Error Info for slice 3." newline bitfld.long 0x1C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x1C 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_3,Data slice level FSM Error Info Mask for slice 3." line.long 0x20 "DDRSS_PHY_851" hexmask.long.word 0x20 21.--31. 1. "RESERVED" hexmask.long.byte 0x20 16.--20. 1. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3,Data slice level training/calibration Error Info for slice 3." newline bitfld.long 0x20 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 8.--12. 1. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3,Data slice level training/calibration Error Info Mask for slice 3." newline bitfld.long 0x20 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 0.--4. 1. "PHY_DS_TRAIN_CALIB_ERROR_INFO_3,Data slice level training/calibration Error Info for slice 3." line.long 0x24 "DDRSS_PHY_852" hexmask.long.byte 0x24 27.--31. 1. "RESERVED" bitfld.long 0x24 24.--26. "PHY_DQS_TSEL_ENABLE_3,Operation type tsel enables for DQS signals for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 8.--23. 1. "PHY_DQ_TSEL_SELECT_3,Operation type tsel select values for DQ/DM signals for slice 3." hexmask.long.byte 0x24 3.--7. 1. "RESERVED" newline bitfld.long 0x24 0.--2. "PHY_DQ_TSEL_ENABLE_3,Operation type tsel enables for DQ/DM signals for slice 3." "0,1,2,3,4,5,6,7" line.long 0x28 "DDRSS_PHY_853" bitfld.long 0x28 31. "RESERVED" "0,1" hexmask.long.byte 0x28 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_3,Data slice initial VREF training start value for slice 3." newline hexmask.long.byte 0x28 18.--23. 1. "RESERVED" bitfld.long 0x28 16.--17. "PHY_TWO_CYC_PREAMBLE_3,2 cycle preamble support for slice 3." "0,1,2,3" newline hexmask.long.word 0x28 0.--15. 1. "PHY_DQS_TSEL_SELECT_3,Operation type tsel select values for DQS signals for slice 3." line.long 0x2C "DDRSS_PHY_854" hexmask.long.byte 0x2C 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_3,Step size of WR DQ slave delay during No-Topology training for slice 3." hexmask.long.byte 0x2C 17.--23. 1. "RESERVED" newline bitfld.long 0x2C 16. "PHY_NTP_TRAIN_EN_3,Enable for No-Topology training for slice 3." "0,1" hexmask.long.byte 0x2C 10.--15. 1. "RESERVED" newline bitfld.long 0x2C 8.--9. "PHY_VREF_TRAINING_CTRL_3,Data slice vref training enable control for slice 3." "0,1,2,3" bitfld.long 0x2C 7. "RESERVED" "0,1" newline hexmask.long.byte 0x2C 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_3,Data slice initial VREF training stop value for slice 3." line.long 0x30 "DDRSS_PHY_855" hexmask.long.byte 0x30 27.--31. 1. "RESERVED" hexmask.long.word 0x30 16.--26. 1. "PHY_NTP_WDQ_STOP_3,End of WR DQ slave delay in No-Topology training for slice 3." newline hexmask.long.byte 0x30 11.--15. 1. "RESERVED" hexmask.long.word 0x30 0.--10. 1. "PHY_NTP_WDQ_START_3,Starting WR DQ slave delay in No-Topology training for slice 3." line.long 0x34 "DDRSS_PHY_856" hexmask.long.byte 0x34 25.--31. 1. "RESERVED" bitfld.long 0x34 24. "PHY_SW_WDQLVL_DVW_MIN_EN_3,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 3." "0,1" newline hexmask.long.byte 0x34 18.--23. 1. "RESERVED" hexmask.long.word 0x34 8.--17. 1. "PHY_WDQLVL_DVW_MIN_3,Minimum data valid window across DQs and ranks for slice 3." newline hexmask.long.byte 0x34 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_3,Enable Bit for WR DQ during No-Topology training for slice 3." line.long 0x38 "DDRSS_PHY_857" bitfld.long 0x38 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 24.--28. 1. "PHY_PAD_RX_DCD_0_3,Controls RX_DCD pin for each pad for slice 3." newline bitfld.long 0x38 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 16.--20. 1. "PHY_PAD_TX_DCD_3,Controls TX_DCD pin for each pad for slice 3." newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.byte 0x38 8.--11. 1. "PHY_FAST_LVL_EN_3,Enable for fast multi-pattern window search for slice 3." newline bitfld.long 0x38 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "PHY_WDQLVL_PER_START_OFFSET_3,Peridic training start point offset for slice 3." line.long 0x3C "DDRSS_PHY_858" bitfld.long 0x3C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 24.--28. 1. "PHY_PAD_RX_DCD_4_3,Controls RX_DCD pin for each pad for slice 3." newline bitfld.long 0x3C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 16.--20. 1. "PHY_PAD_RX_DCD_3_3,Controls RX_DCD pin for each pad for slice 3." newline bitfld.long 0x3C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 8.--12. 1. "PHY_PAD_RX_DCD_2_3,Controls RX_DCD pin for each pad for slice 3." newline bitfld.long 0x3C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 0.--4. 1. "PHY_PAD_RX_DCD_1_3,Controls RX_DCD pin for each pad for slice 3." line.long 0x40 "DDRSS_PHY_859" bitfld.long 0x40 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 24.--28. 1. "PHY_PAD_DM_RX_DCD_3,Controls RX_DCD pin for dm pad for slice 3." newline bitfld.long 0x40 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 16.--20. 1. "PHY_PAD_RX_DCD_7_3,Controls RX_DCD pin for each pad for slice 3." newline bitfld.long 0x40 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 8.--12. 1. "PHY_PAD_RX_DCD_6_3,Controls RX_DCD pin for each pad for slice 3." newline bitfld.long 0x40 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 0.--4. 1. "PHY_PAD_RX_DCD_5_3,Controls RX_DCD pin for each pad for slice 3." line.long 0x44 "DDRSS_PHY_860" hexmask.long.word 0x44 22.--31. 1. "RESERVED" hexmask.long.byte 0x44 16.--21. 1. "PHY_PAD_DSLICE_IO_CFG_3,Controls PCLK/PARK pin for pad for slice 3." newline bitfld.long 0x44 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 8.--12. 1. "PHY_PAD_FDBK_RX_DCD_3,Controls RX_DCD pin for fdbk pad for slice 3." newline bitfld.long 0x44 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 0.--4. 1. "PHY_PAD_DQS_RX_DCD_3,Controls RX_DCD pin for dqs pad for slice 3." line.long 0x48 "DDRSS_PHY_861" hexmask.long.byte 0x48 26.--31. 1. "RESERVED" hexmask.long.word 0x48 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_3,Read DQ1 slave delay setting for slice 3." newline hexmask.long.byte 0x48 10.--15. 1. "RESERVED" hexmask.long.word 0x48 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_3,Read DQ0 slave delay setting for slice 3." line.long 0x4C "DDRSS_PHY_862" hexmask.long.byte 0x4C 26.--31. 1. "RESERVED" hexmask.long.word 0x4C 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_3,Read DQ3 slave delay setting for slice 3." newline hexmask.long.byte 0x4C 10.--15. 1. "RESERVED" hexmask.long.word 0x4C 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_3,Read DQ2 slave delay setting for slice 3." line.long 0x50 "DDRSS_PHY_863" hexmask.long.byte 0x50 26.--31. 1. "RESERVED" hexmask.long.word 0x50 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_3,Read DQ5 slave delay setting for slice 3." newline hexmask.long.byte 0x50 10.--15. 1. "RESERVED" hexmask.long.word 0x50 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_3,Read DQ4 slave delay setting for slice 3." line.long 0x54 "DDRSS_PHY_864" hexmask.long.byte 0x54 26.--31. 1. "RESERVED" hexmask.long.word 0x54 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_3,Read DQ7 slave delay setting for slice 3." newline hexmask.long.byte 0x54 10.--15. 1. "RESERVED" hexmask.long.word 0x54 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_3,Read DQ6 slave delay setting for slice 3." line.long 0x58 "DDRSS_PHY_865" hexmask.long.word 0x58 19.--31. 1. "RESERVED" bitfld.long 0x58 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_3,Determines DCC CAL clock for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 10.--15. 1. "RESERVED" hexmask.long.word 0x58 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_3,Read DM/DBI slave delay setting for slice 3." line.long 0x5C "DDRSS_PHY_866" hexmask.long.byte 0x5C 24.--31. 1. "PHY_DQS_OE_TIMING_3,Start/end timing values for DQS output enable signals for slice 3." hexmask.long.byte 0x5C 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_3,Start/end timing values for DQ/DM write based termination enable and select signals for slice 3." newline hexmask.long.byte 0x5C 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_3,Start/end timing values for DQ/DM read based termination enable and select signals for slice 3." hexmask.long.byte 0x5C 0.--7. 1. "PHY_DQ_OE_TIMING_3,Start/end timing values for DQ/DM output enable signals for slice 3." line.long 0x60 "DDRSS_PHY_867" hexmask.long.byte 0x60 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_3,Start/end timing values for DQS write based termination enable and select signals for slice 3." hexmask.long.byte 0x60 16.--23. 1. "PHY_DQS_OE_RD_TIMING_3,Start/end timing values for DQS read based OE extension for slice 3." newline hexmask.long.byte 0x60 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_3,Start/end timing values for DQS read based termination enable and select signals for slice 3." hexmask.long.byte 0x60 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x60 0.--3. 1. "PHY_IO_PAD_DELAY_TIMING_3,Feedback pad's OPAD and IPAD delay timing for slice 3." line.long 0x64 "DDRSS_PHY_868" hexmask.long.byte 0x64 28.--31. 1. "RESERVED" hexmask.long.word 0x64 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_3,Pad VREF control settings for DQ slice 3." newline hexmask.long.word 0x64 0.--15. 1. "PHY_VREF_SETTING_TIME_3,Number of cycles for vref settle after setting is changed for slice 3." line.long 0x68 "DDRSS_PHY_869" hexmask.long.byte 0x68 26.--31. 1. "RESERVED" bitfld.long 0x68 24.--25. "PHY_RDDATA_EN_IE_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 3." "0,1,2,3" newline hexmask.long.byte 0x68 16.--23. 1. "PHY_DQS_IE_TIMING_3,Start/end timing values for DQS input enable signals for slice 3." hexmask.long.byte 0x68 8.--15. 1. "PHY_DQ_IE_TIMING_3,Start/end timing values for DQ/DM input enable signals for slice 3." newline hexmask.long.byte 0x68 1.--7. 1. "RESERVED" bitfld.long 0x68 0. "PHY_PER_CS_TRAINING_EN_3,Enables the per-rank training and read/write timing capabilities for slice 3." "0,1" line.long 0x6C "DDRSS_PHY_870" bitfld.long 0x6C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 24.--28. 1. "PHY_RDDATA_EN_OE_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 3." newline bitfld.long 0x6C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 16.--20. 1. "PHY_RDDATA_EN_TSEL_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 3." newline hexmask.long.byte 0x6C 9.--15. 1. "RESERVED" bitfld.long 0x6C 8. "PHY_DBI_MODE_3,DBI mode for slice 3." "0,1" newline hexmask.long.byte 0x6C 2.--7. 1. "RESERVED" bitfld.long 0x6C 0.--1. "PHY_IE_MODE_3,Input enable mode bits for slice 3." "0,1,2,3" line.long 0x70 "DDRSS_PHY_871" bitfld.long 0x70 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x70 24.--29. 1. "PHY_MASTER_DELAY_STEP_3,Incremental step size for master delay line locking algorithm for slice 3." newline hexmask.long.byte 0x70 19.--23. 1. "RESERVED" hexmask.long.word 0x70 8.--18. 1. "PHY_MASTER_DELAY_START_3,Start value for master delay line locking algorithm for slice 3." newline hexmask.long.byte 0x70 4.--7. 1. "RESERVED" hexmask.long.byte 0x70 0.--3. 1. "PHY_SW_MASTER_MODE_3,Master delay line override settings for slice 3." line.long 0x74 "DDRSS_PHY_872" hexmask.long.byte 0x74 24.--31. 1. "PHY_WRLVL_DLY_STEP_3,DQS slave delay step size during write leveling for slice 3." hexmask.long.byte 0x74 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x74 16.--19. 1. "PHY_RPTR_UPDATE_3,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 3." hexmask.long.byte 0x74 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_3,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 3." newline hexmask.long.byte 0x74 0.--7. 1. "PHY_MASTER_DELAY_WAIT_3,Wait cycles for master delay line locking algorithm for slice 3." line.long 0x78 "DDRSS_PHY_873" bitfld.long 0x78 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x78 24.--28. 1. "PHY_GTLVL_RESP_WAIT_CNT_3,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 3." newline hexmask.long.byte 0x78 20.--23. 1. "RESERVED" hexmask.long.byte 0x78 16.--19. 1. "PHY_GTLVL_DLY_STEP_3,DQS slave delay step size during gate training for slice 3." newline bitfld.long 0x78 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x78 8.--13. 1. "PHY_WRLVL_RESP_WAIT_CNT_3,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 3." newline hexmask.long.byte 0x78 4.--7. 1. "RESERVED" hexmask.long.byte 0x78 0.--3. 1. "PHY_WRLVL_DLY_FINE_STEP_3,DQS slave delay fine step size during write leveling for slice 3." line.long 0x7C "DDRSS_PHY_874" hexmask.long.byte 0x7C 26.--31. 1. "RESERVED" hexmask.long.word 0x7C 16.--25. 1. "PHY_GTLVL_FINAL_STEP_3,Final backup step delay used in gate training algorithm for slice 3." newline hexmask.long.byte 0x7C 10.--15. 1. "RESERVED" hexmask.long.word 0x7C 0.--9. 1. "PHY_GTLVL_BACK_STEP_3,Interim backup step delay used in gate training algorithm for slice 3." line.long 0x80 "DDRSS_PHY_875" hexmask.long.byte 0x80 28.--31. 1. "RESERVED" hexmask.long.byte 0x80 24.--27. 1. "PHY_RDLVL_DLY_STEP_3,DQS slave delay step size during read leveling for slice 3." newline hexmask.long.byte 0x80 17.--23. 1. "RESERVED" bitfld.long 0x80 16. "PHY_TOGGLE_PRE_SUPPORT_3,Support the toggle read preamble for LPDDR4 for slice 3." "0,1" newline hexmask.long.byte 0x80 12.--15. 1. "RESERVED" hexmask.long.byte 0x80 8.--11. 1. "PHY_WDQLVL_QTR_DLY_STEP_3,Defines the step granularity for the logic to use once an edge is found for slice 3." newline hexmask.long.byte 0x80 0.--7. 1. "PHY_WDQLVL_DLY_STEP_3,DQ slave delay step size during write data leveling for slice 3." line.long 0x84 "DDRSS_PHY_876" hexmask.long.tbyte 0x84 10.--31. 1. "RESERVED" hexmask.long.word 0x84 0.--9. 1. "PHY_RDLVL_MAX_EDGE_3,The maximun rdlvl slave delay search window for read eye training for slice 3." line.long 0x88 "DDRSS_PHY_877" bitfld.long 0x88 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x88 24.--29. 1. "PHY_RDLVL_PER_START_OFFSET_3,Peridic training start point offset for slice 3." newline hexmask.long.byte 0x88 17.--23. 1. "RESERVED" bitfld.long 0x88 16. "PHY_SW_RDLVL_DVW_MIN_EN_3,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 3." "0,1" newline hexmask.long.byte 0x88 10.--15. 1. "RESERVED" hexmask.long.word 0x88 0.--9. 1. "PHY_RDLVL_DVW_MIN_3,Minimum data valid window across DQs and ranks for slice 3." line.long 0x8C "DDRSS_PHY_878" hexmask.long.word 0x8C 18.--31. 1. "RESERVED" bitfld.long 0x8C 16.--17. "PHY_DATA_DC_INIT_DISABLE_3,Disable duty cycle adjust at initialization for slice 3." "0,1,2,3" newline hexmask.long.byte 0x8C 11.--15. 1. "RESERVED" bitfld.long 0x8C 8.--10. "PHY_WRPATH_GATE_TIMING_3,Write path clock gating timing for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8C 2.--7. 1. "RESERVED" bitfld.long 0x8C 0.--1. "PHY_WRPATH_GATE_DISABLE_3,Write path clock gating disable for slice 3." "0,1,2,3" line.long 0x90 "DDRSS_PHY_879" hexmask.long.byte 0x90 27.--31. 1. "RESERVED" hexmask.long.word 0x90 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_3,Initial value of write DQ slave delay for slice 3." newline hexmask.long.byte 0x90 10.--15. 1. "RESERVED" hexmask.long.word 0x90 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_3,Initial value of write DQS slave delay for slice 3." line.long 0x94 "DDRSS_PHY_880" hexmask.long.byte 0x94 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3,Clock measurement cell threshold offset for differential signals for slice 3." hexmask.long.byte 0x94 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_3,Clock measurement cell threshold offset for single ended signals for slice 3." newline hexmask.long.byte 0x94 9.--15. 1. "RESERVED" bitfld.long 0x94 8. "PHY_DATA_DC_WDQLVL_ENABLE_3,Enable duty cycle adjust during write DQ training for slice 3." "0,1" newline hexmask.long.byte 0x94 1.--7. 1. "RESERVED" bitfld.long 0x94 0. "PHY_DATA_DC_WRLVL_ENABLE_3,Enable duty cycle adjust during write leveling for slice 3." "0,1" line.long 0x98 "DDRSS_PHY_881" hexmask.long.word 0x98 21.--31. 1. "RESERVED" hexmask.long.byte 0x98 16.--20. 1. "PHY_RDDATA_EN_DLY_3,Number of cycles that the dfi_rddata_en signal is early for slice 3." newline bitfld.long 0x98 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x98 8.--13. 1. "PHY_MEAS_DLY_STEP_ENABLE_3,Data slice training step definition using phy_meas_dly_step_value for slice 3." newline bitfld.long 0x98 7. "RESERVED" "0,1" hexmask.long.byte 0x98 0.--6. 1. "PHY_WDQ_OSC_DELTA_3,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 3." line.long 0x9C "DDRSS_PHY_882" hexmask.long 0x9C 0.--31. 1. "PHY_DQ_DM_SWIZZLE0_3,DQ/DM bit swizzling 0 for slice 3." line.long 0xA0 "DDRSS_PHY_883" hexmask.long 0xA0 4.--31. 1. "RESERVED" hexmask.long.byte 0xA0 0.--3. 1. "PHY_DQ_DM_SWIZZLE1_3,DQ/DM bit swizzling 1 for slice 3." line.long 0xA4 "DDRSS_PHY_884" hexmask.long.byte 0xA4 27.--31. 1. "RESERVED" hexmask.long.word 0xA4 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_3,Write clock slave delay setting for DQ1 for slice 3." newline hexmask.long.byte 0xA4 11.--15. 1. "RESERVED" hexmask.long.word 0xA4 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_3,Write clock slave delay setting for DQ0 for slice 3." line.long 0xA8 "DDRSS_PHY_885" hexmask.long.byte 0xA8 27.--31. 1. "RESERVED" hexmask.long.word 0xA8 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_3,Write clock slave delay setting for DQ3 for slice 3." newline hexmask.long.byte 0xA8 11.--15. 1. "RESERVED" hexmask.long.word 0xA8 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_3,Write clock slave delay setting for DQ2 for slice 3." line.long 0xAC "DDRSS_PHY_886" hexmask.long.byte 0xAC 27.--31. 1. "RESERVED" hexmask.long.word 0xAC 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_3,Write clock slave delay setting for DQ5 for slice 3." newline hexmask.long.byte 0xAC 11.--15. 1. "RESERVED" hexmask.long.word 0xAC 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_3,Write clock slave delay setting for DQ4 for slice 3." line.long 0xB0 "DDRSS_PHY_887" hexmask.long.byte 0xB0 27.--31. 1. "RESERVED" hexmask.long.word 0xB0 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_3,Write clock slave delay setting for DQ7 for slice 3." newline hexmask.long.byte 0xB0 11.--15. 1. "RESERVED" hexmask.long.word 0xB0 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_3,Write clock slave delay setting for DQ6 for slice 3." line.long 0xB4 "DDRSS_PHY_888" hexmask.long.byte 0xB4 26.--31. 1. "RESERVED" hexmask.long.word 0xB4 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_3,Write clock slave delay setting for DQS for slice 3." newline hexmask.long.byte 0xB4 11.--15. 1. "RESERVED" hexmask.long.word 0xB4 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_3,Write clock slave delay setting for DM for slice 3." line.long 0xB8 "DDRSS_PHY_889" hexmask.long.word 0xB8 18.--31. 1. "RESERVED" hexmask.long.word 0xB8 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ0 for slice 3." newline hexmask.long.byte 0xB8 2.--7. 1. "RESERVED" bitfld.long 0xB8 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_3,Write level threshold adjust value based on those thresholds for DQS for slice 3." "0,1,2,3" line.long 0xBC "DDRSS_PHY_890" hexmask.long.byte 0xBC 26.--31. 1. "RESERVED" hexmask.long.word 0xBC 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ1 for slice 3." newline hexmask.long.byte 0xBC 10.--15. 1. "RESERVED" hexmask.long.word 0xBC 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ0 for slice 3." line.long 0xC0 "DDRSS_PHY_891" hexmask.long.byte 0xC0 26.--31. 1. "RESERVED" hexmask.long.word 0xC0 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ2 for slice 3." newline hexmask.long.byte 0xC0 10.--15. 1. "RESERVED" hexmask.long.word 0xC0 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ1 for slice 3." line.long 0xC4 "DDRSS_PHY_892" hexmask.long.byte 0xC4 26.--31. 1. "RESERVED" hexmask.long.word 0xC4 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ3 for slice 3." newline hexmask.long.byte 0xC4 10.--15. 1. "RESERVED" hexmask.long.word 0xC4 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ2 for slice 3." line.long 0xC8 "DDRSS_PHY_893" hexmask.long.byte 0xC8 26.--31. 1. "RESERVED" hexmask.long.word 0xC8 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ4 for slice 3." newline hexmask.long.byte 0xC8 10.--15. 1. "RESERVED" hexmask.long.word 0xC8 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ3 for slice 3." line.long 0xCC "DDRSS_PHY_894" hexmask.long.byte 0xCC 26.--31. 1. "RESERVED" hexmask.long.word 0xCC 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ5 for slice 3." newline hexmask.long.byte 0xCC 10.--15. 1. "RESERVED" hexmask.long.word 0xCC 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ4 for slice 3." line.long 0xD0 "DDRSS_PHY_895" hexmask.long.byte 0xD0 26.--31. 1. "RESERVED" hexmask.long.word 0xD0 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ6 for slice 3." newline hexmask.long.byte 0xD0 10.--15. 1. "RESERVED" hexmask.long.word 0xD0 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ5 for slice 3." line.long 0xD4 "DDRSS_PHY_896" hexmask.long.byte 0xD4 26.--31. 1. "RESERVED" hexmask.long.word 0xD4 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ7 for slice 3." newline hexmask.long.byte 0xD4 10.--15. 1. "RESERVED" hexmask.long.word 0xD4 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ6 for slice 3." line.long 0xD8 "DDRSS_PHY_897" hexmask.long.byte 0xD8 26.--31. 1. "RESERVED" hexmask.long.word 0xD8 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DM for slice 3." newline hexmask.long.byte 0xD8 10.--15. 1. "RESERVED" hexmask.long.word 0xD8 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ7 for slice 3." line.long 0xDC "DDRSS_PHY_898" hexmask.long.byte 0xDC 26.--31. 1. "RESERVED" hexmask.long.word 0xDC 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_3,Read DQS slave delay setting for slice 3." newline hexmask.long.byte 0xDC 10.--15. 1. "RESERVED" hexmask.long.word 0xDC 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DM for slice 3." line.long 0xE0 "DDRSS_PHY_899" hexmask.long.byte 0xE0 26.--31. 1. "RESERVED" hexmask.long.word 0xE0 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_3,Write level delay threshold above which will be considered in previous cycle for slice 3." newline hexmask.long.byte 0xE0 11.--15. 1. "RESERVED" bitfld.long 0xE0 8.--10. "PHY_WRITE_PATH_LAT_ADD_3,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 3." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE0 4.--7. 1. "RESERVED" hexmask.long.byte 0xE0 0.--3. 1. "PHY_RDDQS_LATENCY_ADJUST_3,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 3." line.long 0xE4 "DDRSS_PHY_900" hexmask.long.word 0xE4 17.--31. 1. "RESERVED" bitfld.long 0xE4 16. "PHY_WRLVL_EARLY_FORCE_ZERO_3,Force the final write level delay value (that meets the early threshold) to 0 for slice 3." "0,1" newline hexmask.long.byte 0xE4 10.--15. 1. "RESERVED" hexmask.long.word 0xE4 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3,Write level delay threshold below which will add a cycle of write path latency for slice 3." line.long 0xE8 "DDRSS_PHY_901" hexmask.long.word 0xE8 20.--31. 1. "RESERVED" hexmask.long.byte 0xE8 16.--19. 1. "PHY_GTLVL_LAT_ADJ_START_3,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 3." newline hexmask.long.byte 0xE8 10.--15. 1. "RESERVED" hexmask.long.word 0xE8 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_3,Initial read DQS gate slave delay setting during gate training for slice 3." line.long 0xEC "DDRSS_PHY_902" hexmask.long.byte 0xEC 25.--31. 1. "RESERVED" bitfld.long 0xEC 24. "PHY_NTP_PASS_3,Indicates if No-topology training found a passing result for slice 3." "0,1" newline hexmask.long.byte 0xEC 20.--23. 1. "RESERVED" hexmask.long.byte 0xEC 16.--19. 1. "PHY_NTP_WRLAT_START_3,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 3." newline hexmask.long.byte 0xEC 11.--15. 1. "RESERVED" hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_3,Initial DQ/DM slave delay setting during write data leveling for slice 3." line.long 0xF0 "DDRSS_PHY_903" hexmask.long.tbyte 0xF0 10.--31. 1. "RESERVED" hexmask.long.word 0xF0 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3,Read leveling starting value for the DQS/DQ slave delay settings for slice 3." line.long 0xF4 "DDRSS_PHY_904" hexmask.long.byte 0xF4 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." hexmask.long.byte 0xF4 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." newline hexmask.long.byte 0xF4 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." hexmask.long.byte 0xF4 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." line.long 0xF8 "DDRSS_PHY_905" hexmask.long.byte 0xF8 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." hexmask.long.byte 0xF8 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." newline hexmask.long.byte 0xF8 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." hexmask.long.byte 0xF8 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." line.long 0xFC "DDRSS_PHY_906" hexmask.long.word 0xFC 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_3,Setting for boost P/N of pad for slice 3." hexmask.long.byte 0xFC 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." newline hexmask.long.byte 0xFC 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3." line.long 0x100 "DDRSS_PHY_907" hexmask.long.word 0x100 18.--31. 1. "RESERVED" bitfld.long 0x100 16.--17. "PHY_DQS_FFE_3,TX_FFE setting for DQS pad for slice 3." "0,1,2,3" newline hexmask.long.byte 0x100 10.--15. 1. "RESERVED" bitfld.long 0x100 8.--9. "PHY_DQ_FFE_3,TX_FFE setting for DQ/DM pad for slice 3." "0,1,2,3" newline bitfld.long 0x100 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x100 0.--5. 1. "PHY_DSLICE_PAD_RX_CTLE_SETTING_3,Setting for RX ctle P/N of pad for slice 3." group.long 0x5000++0x3 line.long 0x0 "DDRSS_PHY_1024" hexmask.long.byte 0x0 27.--31. 1. "RESERVED" bitfld.long 0x0 24.--26. "SC_PHY_ADR_MANUAL_CLEAR_0,Manual reset/clear of internal logic for address slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" bitfld.long 0x0 16. "PHY_ADR_CLK_BYPASS_OVERRIDE_0,Bypass mode override setting for address slice 0." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0,Command/Address clock bypass mode slave delay setting for address slice 0." rgroup.long 0x5004++0x3 line.long 0x0 "DDRSS_PHY_1025" hexmask.long 0x0 0.--31. 1. "PHY_ADR_LPBK_RESULT_OBS_0,Observation register containing loopback status/results for address slice 0." group.long 0x5008++0x3 line.long 0x0 "DDRSS_PHY_1026" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long.byte 0x0 24.--27. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0,Select value to map the internal master delay observation registers to the accessible master delay observation register for address slice 0." newline hexmask.long.byte 0x0 16.--23. 1. "PHY_ADR_MEAS_DLY_STEP_VALUE_0,Contains the fraction of a cycle in 1 delay element numerator with demominator of 512 for address slice 0." hexmask.long.word 0x0 0.--15. 1. "PHY_ADR_LPBK_ERROR_COUNT_OBS_0,Observation register containing total number of loopback error data for address slice 0." rgroup.long 0x500C++0x3 line.long 0x0 "DDRSS_PHY_1027" hexmask.long.byte 0x0 24.--31. 1. "PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing addr slave delay for address slice 0." bitfld.long 0x0 23. "RESERVED" "0,1" newline hexmask.long.byte 0x0 16.--22. 1. "PHY_ADR_BASE_SLV_DLY_ENC_OBS_0,Observation register containing base slave delay for address slice 0." hexmask.long.byte 0x0 11.--15. 1. "RESERVED" newline hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_0,Observation register containing master delay results for address slice 0." group.long 0x5010++0x13 line.long 0x0 "DDRSS_PHY_1028" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_ADR_TSEL_ENABLE_0,Enables tsel_en for address slice 0." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" bitfld.long 0x0 16. "SC_PHY_ADR_SNAP_OBS_REGS_0,Initiates a snapshot of the internal observation registers for address slice 0." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" bitfld.long 0x0 8.--10. "PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0,Select value to map the addr bits delay observation registers to the accessible delay observation register for address slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" bitfld.long 0x0 0.--2. "PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0,Reserved for address slice 0." "0,1,2,3,4,5,6,7" line.long 0x4 "DDRSS_PHY_1029" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" bitfld.long 0x4 24. "PHY_ADR_PWR_RDC_DISABLE_0,Power reduction disable for address slice 0." "0,1" newline bitfld.long 0x4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "PHY_ADR_PRBS_PATTERN_MASK_0,PRBS7 mask signal for address slice 0." newline bitfld.long 0x4 15. "RESERVED" "0,1" hexmask.long.byte 0x4 8.--14. 1. "PHY_ADR_PRBS_PATTERN_START_0,PRBS7 start pattern for address slice 0." newline bitfld.long 0x4 7. "RESERVED" "0,1" hexmask.long.byte 0x4 0.--6. 1. "PHY_ADR_LPBK_CONTROL_0,Loopback control bits for address slice 0." line.long 0x8 "DDRSS_PHY_1030" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "PHY_ADR_IE_MODE_0,Input enable control for address slice 0." "0,1" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED" rbitfld.long 0x8 16.--18. "PHY_ADR_WRADDR_SHIFT_OBS_0,Observation register containing automatic half cycle and cycle shift values for address slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" bitfld.long 0x8 8.--9. "PHY_ADR_TYPE_0,DRAM type for address slice 0." "0,1,2,3" newline hexmask.long.byte 0x8 1.--7. 1. "RESERVED" bitfld.long 0x8 0. "PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0,Power reduction slv_dly_control block gate disable for address slice 0." "0,1" line.long 0xC "DDRSS_PHY_1031" hexmask.long.byte 0xC 27.--31. 1. "RESERVED" hexmask.long 0xC 0.--26. 1. "PHY_ADR_DDL_MODE_0,DDL mode for address slice 0." line.long 0x10 "DDRSS_PHY_1032" hexmask.long 0x10 6.--31. 1. "RESERVED" hexmask.long.byte 0x10 0.--5. 1. "PHY_ADR_DDL_MASK_0,DDL mask for address slice 0." rgroup.long 0x5024++0x7 line.long 0x0 "DDRSS_PHY_1033" hexmask.long 0x0 0.--31. 1. "PHY_ADR_DDL_TEST_OBS_0,Observation register containing DDL test bits for address slice 0." line.long 0x4 "DDRSS_PHY_1034" hexmask.long 0x4 0.--31. 1. "PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0,Observation register containing master DDL bits for address slice 0." group.long 0x502C++0x17 line.long 0x0 "DDRSS_PHY_1035" hexmask.long.byte 0x0 27.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--26. 1. "PHY_ADR_CALVL_COARSE_DLY_0,Coarse CA training DDL increment value for address slice 0." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_ADR_CALVL_START_0,CA training DDL start value for address slice 0." line.long 0x4 "DDRSS_PHY_1036" hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--10. 1. "PHY_ADR_CALVL_QTR_0,CA training DDL quarter cycle delay value for address slice 0." line.long 0x8 "DDRSS_PHY_1037" hexmask.long.byte 0x8 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE0_0,CA training RD DQ bit swizzle map 0 for address slice 0." line.long 0xC "DDRSS_PHY_1038" hexmask.long.byte 0xC 26.--31. 1. "RESERVED" bitfld.long 0xC 24.--25. "PHY_ADR_CALVL_RANK_CTRL_0,CA training rank aggregation control bits for address slice 0." "0,1,2,3" newline hexmask.long.tbyte 0xC 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE1_0,CA training RD DQ bit swizzle map 1 for address slice 0." line.long 0x10 "DDRSS_PHY_1039" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--24. 1. "PHY_ADR_CALVL_PERIODIC_START_OFFSET_0,Relative offset to start periodic CALVL from previous result" newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED" hexmask.long.byte 0x10 8.--11. 1. "PHY_ADR_CALVL_RESP_WAIT_CNT_0,Number of samples to wait before sampling response during CA training for address slice 0." newline hexmask.long.byte 0x10 2.--7. 1. "RESERVED" bitfld.long 0x10 0.--1. "PHY_ADR_CALVL_NUM_PATTERNS_0,Number of patterns to use during CA training for address slice 0." "0,1,2,3" line.long 0x14 "DDRSS_PHY_1040" hexmask.long.byte 0x14 27.--31. 1. "RESERVED" bitfld.long 0x14 24.--26. "PHY_ADR_CALVL_OBS_SELECT_0,CA bit lane to observe result from OBS0 during CA training for address slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" bitfld.long 0x14 16. "SC_PHY_ADR_CALVL_ERROR_CLR_0,Clears the CA training state machine error status for address slice 0." "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "SC_PHY_ADR_CALVL_DEBUG_CONT_0,Allows the CA training state machine to advance (when in debug mode) for address slice 0." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "PHY_ADR_CALVL_DEBUG_MODE_0,Enables CA training debug mode for address slice 0." "0,1" rgroup.long 0x5044++0xF line.long 0x0 "DDRSS_PHY_1041" hexmask.long 0x0 0.--31. 1. "PHY_ADR_CALVL_CH0_OBS0_0,Observation register for CA training for channel 0 slice 0." line.long 0x4 "DDRSS_PHY_1042" hexmask.long 0x4 0.--31. 1. "PHY_ADR_CALVL_CH1_OBS0_0,Observation register for CA training for channel 1 slice 0." line.long 0x8 "DDRSS_PHY_1043" hexmask.long 0x8 0.--31. 1. "PHY_ADR_CALVL_OBS1_0,Observation register contains general CA training bits for slice 0." line.long 0xC "DDRSS_PHY_1044" hexmask.long 0xC 0.--31. 1. "PHY_ADR_CALVL_OBS2_0,Observation register contains periodic CA training bits for slice 0." group.long 0x5054++0x47 line.long 0x0 "DDRSS_PHY_1045" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "PHY_ADR_CALVL_FG_0_0,CA training foreground pattern 0 for address slice 0." line.long 0x4 "DDRSS_PHY_1046" hexmask.long.word 0x4 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--19. 1. "PHY_ADR_CALVL_BG_0_0,CA training background pattern 0 for address slice 0." line.long 0x8 "DDRSS_PHY_1047" hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "PHY_ADR_CALVL_FG_1_0,CA training foreground pattern 1 for address slice 0." line.long 0xC "DDRSS_PHY_1048" hexmask.long.word 0xC 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xC 0.--19. 1. "PHY_ADR_CALVL_BG_1_0,CA training background pattern 1 for address slice 0." line.long 0x10 "DDRSS_PHY_1049" hexmask.long.word 0x10 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x10 0.--19. 1. "PHY_ADR_CALVL_FG_2_0,CA training foreground pattern 2 for address slice 0." line.long 0x14 "DDRSS_PHY_1050" hexmask.long.word 0x14 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x14 0.--19. 1. "PHY_ADR_CALVL_BG_2_0,CA training background pattern 2 for address slice 0." line.long 0x18 "DDRSS_PHY_1051" hexmask.long.word 0x18 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--19. 1. "PHY_ADR_CALVL_FG_3_0,CA training foreground pattern 3 for address slice 0." line.long 0x1C "DDRSS_PHY_1052" hexmask.long.word 0x1C 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x1C 0.--19. 1. "PHY_ADR_CALVL_BG_3_0,CA training background pattern 3 for address slice 0." line.long 0x20 "DDRSS_PHY_1053" hexmask.long.byte 0x20 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x20 0.--23. 1. "PHY_ADR_ADDR_SEL_0,Selects which DFI address pins connect to which CA pins for LPDDR3/4 for address slice 0." line.long 0x24 "DDRSS_PHY_1054" bitfld.long 0x24 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x24 24.--29. 1. "PHY_ADR_SEG_MASK_0,Segment mask bit for address slice 0." newline bitfld.long 0x24 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x24 16.--21. 1. "PHY_ADR_BIT_MASK_0,Mask bit for address slice 0." newline hexmask.long.byte 0x24 10.--15. 1. "RESERVED" hexmask.long.word 0x24 0.--9. 1. "PHY_ADR_LP4_BOOT_SLV_DELAY_0,Address slave delay setting during the LPDDR4 boot frequency operation for address slice 0." line.long 0x28 "DDRSS_PHY_1055" bitfld.long 0x28 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x28 24.--29. 1. "PHY_ADR_SW_TXIO_CTRL_0,Controls address pad output enable for address slice 0." newline hexmask.long.byte 0x28 20.--23. 1. "RESERVED" hexmask.long.byte 0x28 16.--19. 1. "PHY_ADR_STATIC_TOG_DISABLE_0,Toggle control during static activity for address slice 0." newline bitfld.long 0x28 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x28 8.--13. 1. "PHY_ADR_CSLVL_TRAIN_MASK_0,Mask bit for CS training participation for address slice 0." newline bitfld.long 0x28 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x28 0.--5. 1. "PHY_ADR_CALVL_TRAIN_MASK_0,Mask bit for CA training participation for address slice 0." line.long 0x2C "DDRSS_PHY_1056" hexmask.long.byte 0x2C 24.--31. 1. "PHY_ADR_DC_ADR2_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 2 for address slice 0." hexmask.long.byte 0x2C 16.--23. 1. "PHY_ADR_DC_ADR1_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 1 for address slice 0." newline hexmask.long.byte 0x2C 8.--15. 1. "PHY_ADR_DC_ADR0_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 0 for address slice 0." hexmask.long.byte 0x2C 2.--7. 1. "RESERVED" newline bitfld.long 0x2C 0.--1. "PHY_ADR_DC_INIT_DISABLE_0,Duty Cycle Corrector disable at initialization for address slice 0." "0,1,2,3" line.long 0x30 "DDRSS_PHY_1057" hexmask.long.byte 0x30 25.--31. 1. "RESERVED" bitfld.long 0x30 24. "PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0,DCC and RX_CAL clk gate disable for address slice 0." "0,1" newline hexmask.long.byte 0x30 16.--23. 1. "PHY_ADR_DC_ADR5_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 5 for address slice 0." hexmask.long.byte 0x30 8.--15. 1. "PHY_ADR_DC_ADR4_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 4 for address slice 0." newline hexmask.long.byte 0x30 0.--7. 1. "PHY_ADR_DC_ADR3_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 3 for address slice 0." line.long 0x34 "DDRSS_PHY_1058" bitfld.long 0x34 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x34 24.--29. 1. "PHY_ADR_DC_ADJUST_START_0,DCC calibration starting value for address slice 0." newline hexmask.long.byte 0x34 18.--23. 1. "RESERVED" bitfld.long 0x34 16.--17. "PHY_ADR_DC_WEIGHT_0,DCC weighting factor base value for address slice 0." "0,1,2,3" newline hexmask.long.byte 0x34 8.--15. 1. "PHY_ADR_DC_CAL_TIMEOUT_0,DCC number of iterations to wait before timeout for address slice 0." hexmask.long.byte 0x34 0.--7. 1. "PHY_ADR_DC_CAL_SAMPLE_WAIT_0,DCC cycles to wait after calibration change before sampling results for address slice 0." line.long 0x38 "DDRSS_PHY_1059" hexmask.long.byte 0x38 25.--31. 1. "RESERVED" bitfld.long 0x38 24. "PHY_ADR_DC_CAL_POLARITY_0,DCC calibration polarity for address slice 0." "0,1" newline hexmask.long.byte 0x38 17.--23. 1. "RESERVED" bitfld.long 0x38 16. "PHY_ADR_DC_ADJUST_DIRECT_0,DCC adjust direction for address slice 0." "0,1" newline hexmask.long.byte 0x38 8.--15. 1. "PHY_ADR_DC_ADJUST_THRSHLD_0,DCC adjust threshold around the mid-point for address slice 0." hexmask.long.byte 0x38 0.--7. 1. "PHY_ADR_DC_ADJUST_SAMPLE_CNT_0,DCC number of samples to take for address slice 0." line.long 0x3C "DDRSS_PHY_1060" hexmask.long.byte 0x3C 27.--31. 1. "RESERVED" hexmask.long.word 0x3C 16.--26. 1. "PHY_PARITY_ERROR_REGIF_ADR_0,Inject parity error to register interface signals for address slice 0." newline bitfld.long 0x3C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x3C 8.--13. 1. "PHY_ADR_SW_TXPWR_CTRL_0,Disable address output enables in deep sleep mode for address slice 0." newline hexmask.long.byte 0x3C 1.--7. 1. "RESERVED" bitfld.long 0x3C 0. "PHY_ADR_DC_CAL_START_0,DCC Manual trigger for address slice 0." "0,1" line.long 0x40 "DDRSS_PHY_1061" hexmask.long.byte 0x40 25.--31. 1. "RESERVED" hexmask.long.word 0x40 16.--24. 1. "PHY_AS_FSM_ERROR_INFO_MASK_0,FSM Error Info Mask for address slice 0." newline hexmask.long.byte 0x40 9.--15. 1. "RESERVED" hexmask.long.word 0x40 0.--8. 1. "PHY_AS_FSM_ERROR_INFO_0,FSM Error Info for address slice 0." line.long 0x44 "DDRSS_PHY_1062" hexmask.long.byte 0x44 25.--31. 1. "RESERVED" bitfld.long 0x44 24. "PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0,Training/Calibration Error Info Mask for address slice 0." "0,1" newline hexmask.long.byte 0x44 17.--23. 1. "RESERVED" rbitfld.long 0x44 16. "PHY_AS_TRAIN_CALIB_ERROR_INFO_0,Training/Calibration Error Info for address slice 0." "0,1" newline hexmask.long.byte 0x44 9.--15. 1. "RESERVED" hexmask.long.word 0x44 0.--8. 1. "SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0,FSM Error Info clear for address slice 0." wgroup.long 0x509C++0x3 line.long 0x0 "DDRSS_PHY_1063" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0,Training/Calibration Error Info clear for address slice 0." "0,1" group.long 0x50A0++0x2F line.long 0x0 "DDRSS_PHY_1064" hexmask.long.byte 0x0 27.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--26. 1. "PHY_PAD_ADR_IO_CFG_0,Controls I/O pads for address pad for address slice 0." newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" bitfld.long 0x0 8.--10. "PHY_ADR_DC_CAL_CLK_SEL_0,DCC CAL clock for address slice 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "PHY_ADR_TSEL_SELECT_0,Tsel select values for address slice 0." line.long 0x4 "DDRSS_PHY_1065" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "PHY_ADR1_SW_WRADDR_SHIFT_0,Manual override of CA bit 1 of automatic half_cycle_shift/cycle_shift for address slice 0." newline hexmask.long.byte 0x4 19.--23. 1. "RESERVED" hexmask.long.word 0x4 8.--18. 1. "PHY_ADR0_CLK_WR_SLAVE_DELAY_0,CA bit 0 slave delay setting for address slice 0." newline bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "PHY_ADR0_SW_WRADDR_SHIFT_0,Manual override of CA bit 0 of automatic half_cycle_shift/cycle_shift for address slice 0." line.long 0x8 "DDRSS_PHY_1066" hexmask.long.word 0x8 21.--31. 1. "RESERVED" hexmask.long.byte 0x8 16.--20. 1. "PHY_ADR2_SW_WRADDR_SHIFT_0,Manual override of CA bit 2 of automatic half_cycle_shift/cycle_shift for address slice 0." newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--10. 1. "PHY_ADR1_CLK_WR_SLAVE_DELAY_0,CA bit 1 slave delay setting for address slice 0." line.long 0xC "DDRSS_PHY_1067" hexmask.long.word 0xC 21.--31. 1. "RESERVED" hexmask.long.byte 0xC 16.--20. 1. "PHY_ADR3_SW_WRADDR_SHIFT_0,Manual override of CA bit 3 of automatic half_cycle_shift/cycle_shift for address slice 0." newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED" hexmask.long.word 0xC 0.--10. 1. "PHY_ADR2_CLK_WR_SLAVE_DELAY_0,CA bit 2 slave delay setting for address slice 0." line.long 0x10 "DDRSS_PHY_1068" hexmask.long.word 0x10 21.--31. 1. "RESERVED" hexmask.long.byte 0x10 16.--20. 1. "PHY_ADR4_SW_WRADDR_SHIFT_0,Manual override of CA bit 4 of automatic half_cycle_shift/cycle_shift for address slice 0." newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--10. 1. "PHY_ADR3_CLK_WR_SLAVE_DELAY_0,CA bit 3 slave delay setting for address slice 0." line.long 0x14 "DDRSS_PHY_1069" hexmask.long.word 0x14 21.--31. 1. "RESERVED" hexmask.long.byte 0x14 16.--20. 1. "PHY_ADR5_SW_WRADDR_SHIFT_0,Manual override of CA bit 5 of automatic half_cycle_shift/cycle_shift for address slice 0." newline hexmask.long.byte 0x14 11.--15. 1. "RESERVED" hexmask.long.word 0x14 0.--10. 1. "PHY_ADR4_CLK_WR_SLAVE_DELAY_0,CA bit 4 slave delay setting for address slice 0." line.long 0x18 "DDRSS_PHY_1070" hexmask.long.word 0x18 20.--31. 1. "RESERVED" hexmask.long.byte 0x18 16.--19. 1. "PHY_ADR_SW_MASTER_MODE_0,Master delay line override settings for address slice 0." newline hexmask.long.byte 0x18 11.--15. 1. "RESERVED" hexmask.long.word 0x18 0.--10. 1. "PHY_ADR5_CLK_WR_SLAVE_DELAY_0,CA bit 5 slave delay setting for address slice 0." line.long 0x1C "DDRSS_PHY_1071" hexmask.long.byte 0x1C 24.--31. 1. "PHY_ADR_MASTER_DELAY_WAIT_0,Wait cycles for master delay line locking algorithm for address slice 0." bitfld.long 0x1C 22.--23. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x1C 16.--21. 1. "PHY_ADR_MASTER_DELAY_STEP_0,Incremental step size for master delay line locking algorithm for address slice 0." hexmask.long.byte 0x1C 11.--15. 1. "RESERVED" newline hexmask.long.word 0x1C 0.--10. 1. "PHY_ADR_MASTER_DELAY_START_0,Start value for master delay line locking algorithm for address slice 0." line.long 0x20 "DDRSS_PHY_1072" hexmask.long.byte 0x20 25.--31. 1. "RESERVED" bitfld.long 0x20 24. "PHY_ADR_SW_CALVL_DVW_MIN_EN_0,Enables the software override data valid window size during CA training for address slice 0." "0,1" newline hexmask.long.byte 0x20 18.--23. 1. "RESERVED" hexmask.long.word 0x20 8.--17. 1. "PHY_ADR_SW_CALVL_DVW_MIN_0,Sets the software override data valid window size during CA training for address slice 0." newline hexmask.long.byte 0x20 0.--7. 1. "PHY_ADR_MASTER_DELAY_HALF_MEASURE_0,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle for the master in address slice 0" line.long 0x24 "DDRSS_PHY_1073" hexmask.long 0x24 4.--31. 1. "RESERVED" hexmask.long.byte 0x24 0.--3. 1. "PHY_ADR_CALVL_DLY_STEP_0,Sets the delay step size plus 1 during CA training for address slice 0." line.long 0x28 "DDRSS_PHY_1074" hexmask.long.byte 0x28 26.--31. 1. "RESERVED" hexmask.long.word 0x28 16.--25. 1. "PHY_ADR_DC_INIT_SLV_DELAY_0,DCC initialization value of write ADDR slave delay for address slice 0." newline hexmask.long.byte 0x28 9.--15. 1. "RESERVED" bitfld.long 0x28 8. "PHY_ADR_MEAS_DLY_STEP_ENABLE_0,Enables delay parameter setting using phy_adr_meas_dly_step_value for address slice 0." "0,1" newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED" hexmask.long.byte 0x28 0.--3. 1. "PHY_ADR_CALVL_CAPTURE_CNT_0,Number of samples to take at each ADDR slave delay setting during CA training for address slice 0." line.long 0x2C "DDRSS_PHY_1075" hexmask.long.word 0x2C 16.--31. 1. "RESERVED" hexmask.long.byte 0x2C 8.--15. 1. "PHY_ADR_DC_DM_CLK_THRSHLD_0,DCC clock measurement cell threshold offset for address slice 0." newline hexmask.long.byte 0x2C 1.--7. 1. "RESERVED" bitfld.long 0x2C 0. "PHY_ADR_DC_CALVL_ENABLE_0,DCC enable duty cycle adjust during CA leveling for address slice 0." "0,1" group.long 0x5400++0x1B line.long 0x0 "DDRSS_PHY_1280" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "PHY_FREQ_SEL,Specifies which copy of the frequency-dependent timing parameters will be used by the PHY." "0,1,2,3" line.long 0x4 "DDRSS_PHY_1281" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "PHY_SW_GRP0_SHIFT_0,Address slice slave delay setting for address slice 4." newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED" bitfld.long 0x4 16.--17. "PHY_FREQ_SEL_INDEX,Selects which frequency set to update when PHY_FREQ_SEL_MULTICAST_EN is not set." "0,1,2,3" newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "PHY_FREQ_SEL_MULTICAST_EN,When set a register write will update parameters for all frequency sets simultaneously." "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED" bitfld.long 0x4 0. "PHY_FREQ_SEL_FROM_REGIF,Indicates which source is used to select the frequency copy." "0,1" line.long 0x8 "DDRSS_PHY_1282" bitfld.long 0x8 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "PHY_SW_GRP0_SHIFT_1,Address slice slave delay setting for address slice 4." newline bitfld.long 0x8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 16.--20. 1. "PHY_SW_GRP3_SHIFT_0,Address slice slave delay setting for address slice 4." newline bitfld.long 0x8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "PHY_SW_GRP2_SHIFT_0,Address slice slave delay setting for address slice 4." newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PHY_SW_GRP1_SHIFT_0,Address slice slave delay setting for address slice 4." line.long 0xC "DDRSS_PHY_1283" hexmask.long.word 0xC 21.--31. 1. "RESERVED" hexmask.long.byte 0xC 16.--20. 1. "PHY_SW_GRP3_SHIFT_1,Address slice slave delay setting for address slice 4." newline bitfld.long 0xC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--12. 1. "PHY_SW_GRP2_SHIFT_1,Address slice slave delay setting for address slice 4." newline bitfld.long 0xC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--4. 1. "PHY_SW_GRP1_SHIFT_1,Address slice slave delay setting for address slice 4." line.long 0x10 "DDRSS_PHY_1284" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" bitfld.long 0x10 24. "PHY_GRP_BYPASS_OVERRIDE,Address/control group slice bypass mode override setting." "0,1" newline bitfld.long 0x10 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 16.--20. 1. "PHY_SW_GRP_BYPASS_SHIFT,Address/control group slice bypass mode shift settings." newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED" hexmask.long.word 0x10 0.--10. 1. "PHY_GRP_BYPASS_SLAVE_DELAY,Address/control group slice bypass mode slave delay setting." line.long 0x14 "DDRSS_PHY_1285" hexmask.long.byte 0x14 27.--31. 1. "RESERVED" hexmask.long.word 0x14 16.--26. 1. "PHY_CSLVL_START,Defines the CS training DDL start value." newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "PHY_MANUAL_UPDATE_PHYUPD_ENABLE,Manual update selection of all slave delay line settings." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "SC_PHY_MANUAL_UPDATE,Manual update of all slave delay line settings." "0,1" line.long 0x18 "DDRSS_PHY_1286" hexmask.long.byte 0x18 25.--31. 1. "RESERVED" bitfld.long 0x18 24. "SC_PHY_CSLVL_DEBUG_CONT,Allows the CS training state machine to advance (when in debug mode)." "0,1" newline hexmask.long.byte 0x18 17.--23. 1. "RESERVED" bitfld.long 0x18 16. "PHY_CSLVL_DEBUG_MODE,Enables CS training debug mode." "0,1" newline hexmask.long.byte 0x18 11.--15. 1. "RESERVED" hexmask.long.word 0x18 0.--10. 1. "PHY_CSLVL_COARSE_DLY,Defines the CS training DDL coarse cycle delay value." wgroup.long 0x541C++0x3 line.long 0x0 "DDRSS_PHY_1287" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SC_PHY_CSLVL_ERROR_CLR,Clears the CS training state machine error status." "0,1" rgroup.long 0x5420++0xB line.long 0x0 "DDRSS_PHY_1288" hexmask.long 0x0 0.--31. 1. "PHY_CSLVL_OBS0,Observation register for CS training delay values." line.long 0x4 "DDRSS_PHY_1289" hexmask.long 0x4 0.--31. 1. "PHY_CSLVL_OBS1,Observation register for CS training algorithm status." line.long 0x8 "DDRSS_PHY_1290" hexmask.long 0x8 0.--31. 1. "PHY_CSLVL_OBS2,Observation register for periodic CS training delay values." group.long 0x542C++0x2B line.long 0x0 "DDRSS_PHY_1291" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_LP4_BOOT_DISABLE,Controls the handling of the DFI frequency." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" hexmask.long.word 0x0 8.--16. 1. "PHY_CSLVL_PERIODIC_START_OFFSET,Defines the relative offset from previous LE and TE to start periodic CSLVL with." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_CSLVL_ENABLE,CS training enable." "0,1" line.long 0x4 "DDRSS_PHY_1292" hexmask.long.word 0x4 19.--31. 1. "RESERVED" hexmask.long.word 0x4 8.--18. 1. "PHY_CSLVL_QTR,Defines the CS training DDL 1/4 cycle delay value." newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "PHY_CSLVL_CS_MAP,CS training map." line.long 0x8 "DDRSS_PHY_1293" hexmask.long.byte 0x8 24.--31. 1. "PHY_CALVL_CS_MAP,Defines the slice numbers associated with each CS during CA training." hexmask.long.byte 0x8 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x8 16.--19. 1. "PHY_CSLVL_COARSE_CAPTURE_CNT,Defines the number of samples to take at each GRP slave delay setting during CS training coarse CA training." hexmask.long.byte 0x8 11.--15. 1. "RESERVED" newline hexmask.long.word 0x8 0.--10. 1. "PHY_CSLVL_COARSE_CHK,Defines the CS training coarse CA training DDL 1/16th cycle delay value." line.long 0xC "DDRSS_PHY_1294" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "PHY_ADRCTL_LPDDR,Adds a cycle of delay for the address/control slices to match the address slice." "0,1" newline hexmask.long.byte 0xC 18.--23. 1. "RESERVED" bitfld.long 0xC 16.--17. "PHY_DFI_PHYUPD_TYPE,Defines the value of the dfi_phyupd_type output signal to MC." "0,1,2,3" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" bitfld.long 0xC 8. "PHY_ADRCTL_SNAP_OBS_REGS,Initiates a snapshot of the internal observation registers for the address/control block." "0,1" newline hexmask.long.byte 0xC 3.--7. 1. "RESERVED" bitfld.long 0xC 0.--2. "PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE,Reserved for the address/control master." "0,1,2,3,4,5,6,7" line.long 0x10 "DDRSS_PHY_1295" hexmask.long.byte 0x10 24.--31. 1. "PHY_CLK_DC_CAL_TIMEOUT,Duty cycle correction maximum iteration count." hexmask.long.byte 0x10 16.--23. 1. "PHY_CLK_DC_CAL_SAMPLE_WAIT,Number of cal clock cycles to wait for a sample to be taken." newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "PHY_LPDDR3_CS,Alters reset state polarity for LPDDR chip selects." "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "PHY_LP4_ACTIVE,Indicates an LPDDR4 device is connected to the PHY." "0,1" line.long 0x14 "DDRSS_PHY_1296" hexmask.long.byte 0x14 24.--31. 1. "PHY_CLK_DC_ADJUST_SAMPLE_CNT,Duty cycle correction algorithm sample count per adjustment setting." bitfld.long 0x14 22.--23. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x14 16.--21. 1. "PHY_CLK_DC_ADJUST_START,Duty cycle correction algorithm adjustment starting value." hexmask.long.byte 0x14 9.--15. 1. "RESERVED" newline bitfld.long 0x14 8. "PHY_CLK_DC_FREQ_CHG_ADJ,Duty cycle correction during frequency change control." "0,1" hexmask.long.byte 0x14 2.--7. 1. "RESERVED" newline bitfld.long 0x14 0.--1. "PHY_CLK_DC_WEIGHT,Duty cycle correction weighting factor base value." "0,1,2,3" line.long 0x18 "DDRSS_PHY_1297" hexmask.long.byte 0x18 25.--31. 1. "RESERVED" bitfld.long 0x18 24. "PHY_CLK_DC_CAL_START,Duty cycle correction calibration manual start." "0,1" newline hexmask.long.byte 0x18 17.--23. 1. "RESERVED" bitfld.long 0x18 16. "PHY_CLK_DC_CAL_POLARITY,Duty cycle correction algorithm measurement polarity." "0,1" newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED" bitfld.long 0x18 8. "PHY_CLK_DC_ADJUST_DIRECT,Duty cycle correction algorithm adjustment direction." "0,1" newline hexmask.long.byte 0x18 0.--7. 1. "PHY_CLK_DC_ADJUST_THRSHLD,Duty cycle correction algorithm threshold delta comparison." line.long 0x1C "DDRSS_PHY_1298" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED" hexmask.long.byte 0x1C 24.--27. 1. "PHY_SW_TXIO_CTRL_1,This register is used to control if command pad (CS/RAS...) should be shutoff for TX mode." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED" hexmask.long.byte 0x1C 16.--19. 1. "PHY_SW_TXIO_CTRL_0,This register is used to control if command pad (CS/RAS...) should be shutoff for TX mode." newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED" bitfld.long 0x1C 8. "PHY_CONTINUOUS_CLK_CAL_UPDATE,Continuous update of all latest PVTP PVTN and PVTR values to the CLK IO pads." "0,1" newline hexmask.long.byte 0x1C 1.--7. 1. "RESERVED" bitfld.long 0x1C 0. "SC_PHY_UPDATE_CLK_CAL_VALUES,Manual update of all latest PVTP PVTN and PVTR values to the CLK IO pads." "0,1" line.long 0x20 "DDRSS_PHY_1299" hexmask.long.byte 0x20 25.--31. 1. "RESERVED" bitfld.long 0x20 24. "PHY_MEMCLK_SW_TXPWR_CTRL,This register is used to control if clk pads should be shutoff for TX mode in deep sleep mode." "0,1" newline hexmask.long.byte 0x20 20.--23. 1. "RESERVED" hexmask.long.byte 0x20 16.--19. 1. "PHY_ADRCTL_SW_TXPWR_CTRL_1,This register is used to control if address/command pad (address/CS/RAS...) should be shutoff for TX mode in deep sleep mode." newline hexmask.long.byte 0x20 12.--15. 1. "RESERVED" hexmask.long.byte 0x20 8.--11. 1. "PHY_ADRCTL_SW_TXPWR_CTRL_0,This register is used to control if address/command pad (address/CS/RAS...) should be shutoff for TX mode in deep sleep mode." newline hexmask.long.byte 0x20 1.--7. 1. "RESERVED" bitfld.long 0x20 0. "PHY_MEMCLK_SW_TXIO_CTRL,This register is used to control if clk pads should be shutoff for TX mode." "0,1" line.long 0x24 "DDRSS_PHY_1300" hexmask.long.word 0x24 16.--31. 1. "PHY_STATIC_TOG_CONTROL,Clock divider to create toggle signal." hexmask.long.byte 0x24 9.--15. 1. "RESERVED" newline bitfld.long 0x24 8. "PHY_BYTE_DISABLE_STATIC_TOG_DISABLE,Control to disable the toggle signal for data slice during static activity when dfi_data_byte_disable is asserted." "0,1" hexmask.long.byte 0x24 1.--7. 1. "RESERVED" newline bitfld.long 0x24 0. "PHY_TOP_STATIC_TOG_DISABLE,Disables the generation of the toggle for static clock based paths in the PHY to prevent assymetric aging." "0,1" line.long 0x28 "DDRSS_PHY_1301" hexmask.long.word 0x28 17.--31. 1. "RESERVED" bitfld.long 0x28 16. "PHY_LP4_BOOT_PLL_BYPASS,PHY clock PLL bypass select." "0,1" newline hexmask.long.byte 0x28 9.--15. 1. "RESERVED" bitfld.long 0x28 8. "PHY_MEMCLK_STATIC_TOG_DISABLE,Control to disable toggle during static activity." "0,1" newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED" hexmask.long.byte 0x28 0.--3. 1. "PHY_ADRCTL_STATIC_TOG_DISABLE,Control to disable toggle during static activity." rgroup.long 0x5458++0x3 line.long 0x0 "DDRSS_PHY_1302" hexmask.long 0x0 0.--31. 1. "PHY_CLK_SWITCH_OBS,Observation register for Clock switch state machine READ-ONLY" group.long 0x545C++0x23 line.long 0x0 "DDRSS_PHY_1303" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "PHY_PLL_WAIT,PHY clock PLL wait time after locking." line.long 0x4 "DDRSS_PHY_1304" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PHY_SW_PLL_BYPASS,PHY clock PLL bypass select." "0,1" line.long 0x8 "DDRSS_PHY_1305" hexmask.long.byte 0x8 28.--31. 1. "RESERVED" hexmask.long.byte 0x8 24.--27. 1. "PHY_CS_ACS_ALLOCATION_BIT1_0,The map for which chip select is associated with each bit in the adrctl slice 0." newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED" hexmask.long.byte 0x8 16.--19. 1. "PHY_CS_ACS_ALLOCATION_BIT0_0,The map for which chip select is associated with each bit in the adrctl slice 0." newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "PHY_SET_DFI_INPUT_1,Used to indicate the default value of the adrctl slice bits." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED" hexmask.long.byte 0x8 0.--3. 1. "PHY_SET_DFI_INPUT_0,Used to indicate the default value of the adrctl slice bits." line.long 0xC "DDRSS_PHY_1306" hexmask.long.byte 0xC 28.--31. 1. "RESERVED" hexmask.long.byte 0xC 24.--27. 1. "PHY_CS_ACS_ALLOCATION_BIT1_1,The map for which chip select is associated with each bit in the adrctl slice 1." newline hexmask.long.byte 0xC 20.--23. 1. "RESERVED" hexmask.long.byte 0xC 16.--19. 1. "PHY_CS_ACS_ALLOCATION_BIT0_1,The map for which chip select is associated with each bit in the adrctl slice 1." newline hexmask.long.byte 0xC 12.--15. 1. "RESERVED" hexmask.long.byte 0xC 8.--11. 1. "PHY_CS_ACS_ALLOCATION_BIT3_0,The map for which chip select is associated with each bit in the adrctl slice 0." newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED" hexmask.long.byte 0xC 0.--3. 1. "PHY_CS_ACS_ALLOCATION_BIT2_0,The map for which chip select is associated with each bit in the adrctl slice 0." line.long 0x10 "DDRSS_PHY_1307" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" bitfld.long 0x10 24. "PHY_CLK_DC_INIT_DISABLE,Disable duty cycle adjust at initialization." "0,1" newline hexmask.long.byte 0x10 16.--23. 1. "PHY_CLK_DC_ADJUST_0,Adjust value of Duty Cycle Adjuster for clock slice 0." hexmask.long.byte 0x10 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x10 8.--11. 1. "PHY_CS_ACS_ALLOCATION_BIT3_1,The map for which chip select is associated with each bit in the adrctl slice 1." hexmask.long.byte 0x10 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x10 0.--3. 1. "PHY_CS_ACS_ALLOCATION_BIT2_1,The map for which chip select is associated with each bit in the adrctl slice 1." line.long 0x14 "DDRSS_PHY_1308" hexmask.long.word 0x14 21.--31. 1. "RESERVED" hexmask.long.word 0x14 8.--20. 1. "PHY_LP4_BOOT_PLL_CTRL,PHY deskew PLL controls for LPDDR4 boot frequency." newline hexmask.long.byte 0x14 0.--7. 1. "PHY_CLK_DC_DM_THRSHLD,Data measurement cell threshold offset." line.long 0x18 "DDRSS_PHY_1309" hexmask.long.word 0x18 17.--31. 1. "RESERVED" bitfld.long 0x18 16. "PHY_USE_PLL_DSKEWCALLOCK,Use DSKEWCALLOCK or not." "0,1" newline hexmask.long.word 0x18 0.--15. 1. "PHY_PLL_CTRL_OVERRIDE,Individual PHY clock PLL control overrides." line.long 0x1C "DDRSS_PHY_1310" hexmask.long.byte 0x1C 26.--31. 1. "RESERVED" bitfld.long 0x1C 24.--25. "SC_PHY_PLL_SPO_CAL_SNAP_OBS,Register command to take a snapshot of PLL output." "0,1,2,3" newline hexmask.long.byte 0x1C 19.--23. 1. "RESERVED" hexmask.long.tbyte 0x1C 0.--18. 1. "PHY_PLL_SPO_CAL_CTRL,PLL SPO Cal controls." line.long 0x20 "DDRSS_PHY_1311" hexmask.long.word 0x20 18.--31. 1. "RESERVED" bitfld.long 0x20 16.--17. "SC_PHY_PLL_CAL_CLK_MEAS,Register command to initiate cal_clklout clock frequency measurement." "0,1,2,3" newline hexmask.long.byte 0x20 10.--15. 1. "RESERVED" hexmask.long.word 0x20 0.--9. 1. "PHY_PLL_CAL_CLK_MEAS_CYCLES,Measurement cycles of cal_clkout clock." rgroup.long 0x5480++0x13 line.long 0x0 "DDRSS_PHY_1312" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "PHY_PLL_OBS_0,PHY TOP level clock PLL_0 observe values." line.long 0x4 "DDRSS_PHY_1313" hexmask.long.word 0x4 17.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--16. 1. "PHY_PLL_SPO_CAL_OBS_0,PHY TOP level PLL_0 SPO Cal observe values." line.long 0x8 "DDRSS_PHY_1314" hexmask.long.word 0x8 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--17. 1. "PHY_PLL_CAL_CLK_MEAS_OBS_0,PHY TOP level PLL_0 cal_clkout measurement observe values." line.long 0xC "DDRSS_PHY_1315" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "PHY_PLL_OBS_1,PHY TOP level clock PLL_1 observe values." line.long 0x10 "DDRSS_PHY_1316" hexmask.long.word 0x10 17.--31. 1. "RESERVED" hexmask.long.tbyte 0x10 0.--16. 1. "PHY_PLL_SPO_CAL_OBS_1,PHY TOP level PLL_1 SPO Cal observe values." group.long 0x5494++0x3F line.long 0x0 "DDRSS_PHY_1317" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PHY_LP4_BOOT_LOW_FREQ_SEL,Control the PLL domain enter/exit from the negative clock edge for LPDDR4 boot frequency." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--17. 1. "PHY_PLL_CAL_CLK_MEAS_OBS_1,PHY TOP level PLL_1 cal_clkout measurement observe values." line.long 0x4 "DDRSS_PHY_1318" hexmask.long.word 0x4 17.--31. 1. "RESERVED" bitfld.long 0x4 16. "PHY_LS_IDLE_EN,Indicates the Reduced Idle Power State is enabled in low power mode." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "PHY_LP_WAKEUP,Specifies the number of cycles the PHY takes to wakeup in low power mode." hexmask.long.byte 0x4 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--3. 1. "PHY_TCKSRE_WAIT,Specifies the number of cycles the PHY should wait before turning off the PLL for a deep sleep or DFS event." line.long 0x8 "DDRSS_PHY_1319" hexmask.long.word 0x8 17.--31. 1. "RESERVED" bitfld.long 0x8 16. "PHY_TDFI_PHY_WRDELAY,DFI timing parameter TDFI_PHY_WRDELAY." "0,1" newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "PHY_LP_CTRLUPD_CNTR_CFG,Specifies the number of cycles the PHY takes from light sleep req deassert to ack deassert in low power mode." line.long 0xC "DDRSS_PHY_1320" hexmask.long.word 0xC 18.--31. 1. "RESERVED" hexmask.long.tbyte 0xC 0.--17. 1. "PHY_PAD_FDBK_TERM,Controls term settings for gate feedback pads." line.long 0x10 "DDRSS_PHY_1321" hexmask.long.word 0x10 17.--31. 1. "RESERVED" hexmask.long.tbyte 0x10 0.--16. 1. "PHY_PAD_DATA_TERM,Controls term settings for data pads." line.long 0x14 "DDRSS_PHY_1322" hexmask.long.word 0x14 17.--31. 1. "RESERVED" hexmask.long.tbyte 0x14 0.--16. 1. "PHY_PAD_DQS_TERM,Controls term settings for dqs pads." line.long 0x18 "DDRSS_PHY_1323" hexmask.long.word 0x18 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x18 0.--17. 1. "PHY_PAD_ADDR_TERM,Controls term settings for the address/control pads." line.long 0x1C "DDRSS_PHY_1324" hexmask.long.word 0x1C 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x1C 0.--17. 1. "PHY_PAD_CLK_TERM,Controls term settings for clock pads." line.long 0x20 "DDRSS_PHY_1325" hexmask.long.word 0x20 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x20 0.--17. 1. "PHY_PAD_CKE_TERM,Controls term settings for cke pads." line.long 0x24 "DDRSS_PHY_1326" hexmask.long.word 0x24 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x24 0.--17. 1. "PHY_PAD_RST_TERM,Controls term settings for reset_n pads." line.long 0x28 "DDRSS_PHY_1327" hexmask.long.word 0x28 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x28 0.--17. 1. "PHY_PAD_CS_TERM,Controls term settings for cs pads." line.long 0x2C "DDRSS_PHY_1328" hexmask.long.word 0x2C 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x2C 0.--17. 1. "PHY_PAD_ODT_TERM,Controls term settings for odt pads." line.long 0x30 "DDRSS_PHY_1329" bitfld.long 0x30 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.word 0x30 16.--28. 1. "PHY_ADRCTL_LP3_RX_CAL,PHY CKE/RESET_N RX calibration controls." newline hexmask.long.byte 0x30 10.--15. 1. "RESERVED" hexmask.long.word 0x30 0.--9. 1. "PHY_ADRCTL_RX_CAL,PHY address/control RX calibration controls." line.long 0x34 "DDRSS_PHY_1330" hexmask.long.byte 0x34 25.--31. 1. "RESERVED" bitfld.long 0x34 24. "PHY_CAL_START_0,Manual start for the pad calibration state machine for block 0." "0,1" newline hexmask.long.byte 0x34 17.--23. 1. "RESERVED" bitfld.long 0x34 16. "PHY_CAL_CLEAR_0,Clear the pad calibration state machine and results for block 0." "0,1" newline bitfld.long 0x34 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.word 0x34 0.--12. 1. "PHY_CAL_MODE_0,Pad calibration mode bits for block 0." line.long 0x38 "DDRSS_PHY_1331" hexmask.long 0x38 0.--31. 1. "PHY_CAL_INTERVAL_COUNT_0,Pad calibration interval counter compare value for block 0." line.long 0x3C "DDRSS_PHY_1332" hexmask.long.tbyte 0x3C 11.--31. 1. "RESERVED" bitfld.long 0x3C 8.--10. "PHY_LP4_BOOT_CAL_CLK_SELECT_0,Pad calibration pad clock frequency select setting for LPDDR4 boot frequency for block 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x3C 0.--7. 1. "PHY_CAL_SAMPLE_WAIT_0,Pad calibration state machine wait count in pad clock cycles for block 0." rgroup.long 0x54D4++0x13 line.long 0x0 "DDRSS_PHY_1333" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--23. 1. "PHY_CAL_RESULT_OBS_0,Pad calibration results observation values for block 0." line.long 0x4 "DDRSS_PHY_1334" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--23. 1. "PHY_CAL_RESULT2_OBS_0,Pad calibration results (CKE/RESET_N) observation values for block 0." line.long 0x8 "DDRSS_PHY_1335" hexmask.long.byte 0x8 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--23. 1. "PHY_CAL_RESULT4_OBS_0,Pad calibration pass1 shadow results observation values for block 0." line.long 0xC "DDRSS_PHY_1336" hexmask.long.byte 0xC 24.--31. 1. "RESERVED" hexmask.long.tbyte 0xC 0.--23. 1. "PHY_CAL_RESULT5_OBS_0,Pad calibration pass2 shadow results observation values for block 0." line.long 0x10 "DDRSS_PHY_1337" hexmask.long.byte 0x10 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x10 0.--23. 1. "PHY_CAL_RESULT6_OBS_0,Pad calibration internal results observation delta values for block 0." group.long 0x54E8++0x7 line.long 0x0 "DDRSS_PHY_1338" bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long.byte 0x0 24.--30. 1. "PHY_CAL_CPTR_CNT_0,defines sample capture number in pad calibration process" newline hexmask.long.tbyte 0x0 0.--23. 1. "PHY_CAL_RESULT7_OBS_0,Pad calibration internal results observation delta values for block 0." line.long 0x4 "DDRSS_PHY_1339" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" bitfld.long 0x4 24. "PHY_CAL_DBG_CFG_0,defines debug configuration in pad calibration process" "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "PHY_CAL_RCV_FINE_ADJ_0,defines adjustment for RCV code in pad calibration process" hexmask.long.byte 0x4 8.--15. 1. "PHY_CAL_PD_FINE_ADJ_0,defines adjustment for PD code in pad calibration process" newline hexmask.long.byte 0x4 0.--7. 1. "PHY_CAL_PU_FINE_ADJ_0,defines adjustment for PU code in pad calibration process" wgroup.long 0x54F0++0x3 line.long 0x0 "DDRSS_PHY_1340" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SC_PHY_PAD_DBG_CONT_0,Allows the pad calibration state machine to advance (when in debug mode) for slice 0." "0,1" rgroup.long 0x54F4++0x3 line.long 0x0 "DDRSS_PHY_1341" hexmask.long 0x0 0.--31. 1. "PHY_CAL_RESULT3_OBS_0,Pad calibration results first/last0/1 observation values for block 0." group.long 0x54F8++0x27 line.long 0x0 "DDRSS_PHY_1342" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 8.--27. 1. "PHY_CAL_SLOPE_ADJ_0,defines slope configure in pad calibration process" newline bitfld.long 0x0 7. "RESERVED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "PHY_ADRCTL_PVT_MAP_0,defines slope configure in pad calibration process" line.long 0x4 "DDRSS_PHY_1343" hexmask.long.word 0x4 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--19. 1. "PHY_CAL_SLOPE_ADJ_PASS2_0,defines slope configure for pass2 in pad calibration process" line.long 0x8 "DDRSS_PHY_1344" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" hexmask.long 0x8 0.--24. 1. "PHY_CAL_TWO_PASS_CFG_0,defines cal_en configure in pad calibration process" line.long 0xC "DDRSS_PHY_1345" bitfld.long 0xC 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 24.--29. 1. "PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0,Pad calibration pass1 pu results won't update if out of max delta range ." newline bitfld.long 0xC 23. "RESERVED" "0,1" hexmask.long.tbyte 0xC 0.--22. 1. "PHY_CAL_SW_CAL_CFG_0,defines firmware based pad calibration process" line.long 0x10 "DDRSS_PHY_1346" bitfld.long 0x10 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 24.--29. 1. "PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0,Pad calibration pass2 pd results won't update if out of max delta range ." newline bitfld.long 0x10 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 16.--21. 1. "PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0,Pad calibration pass2 pu results won't update if out of max delta range ." newline bitfld.long 0x10 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--12. 1. "PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0,Pad calibration pass1 rx results won't update if out of max delta range ." newline bitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 0.--5. 1. "PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0,Pad calibration pass1 pd results won't update if out of max delta range ." line.long 0x14 "DDRSS_PHY_1347" bitfld.long 0x14 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 24.--28. 1. "PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0,Pad calibration pass1 rx results won't update if out of min delta range ." newline bitfld.long 0x14 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 16.--21. 1. "PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0,Pad calibration pass1 pd results won't update if out of min delta range ." newline bitfld.long 0x14 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14 8.--13. 1. "PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0,Pad calibration pass1 pu results won't update if out of min delta range ." newline bitfld.long 0x14 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 0.--4. 1. "PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0,Pad calibration pass2 rx results won't update if out of max delta range ." line.long 0x18 "DDRSS_PHY_1348" hexmask.long.word 0x18 21.--31. 1. "RESERVED" hexmask.long.byte 0x18 16.--20. 1. "PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0,Pad calibration pass2 rx results won't update if out of min delta range ." newline bitfld.long 0x18 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x18 8.--13. 1. "PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0,Pad calibration pass2 pd results won't update if out of min delta range ." newline bitfld.long 0x18 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x18 0.--5. 1. "PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0,Pad calibration pass2 pu results won't update if out of min delta range ." line.long 0x1C "DDRSS_PHY_1349" hexmask.long.byte 0x1C 27.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--26. 1. "PHY_PARITY_ERROR_REGIF_AC,Inject parity error to register interface signals for ac slice." newline hexmask.long.word 0x1C 0.--15. 1. "PHY_PAD_ATB_CTRL,Pad ATB control settings." line.long 0x20 "DDRSS_PHY_1350" hexmask.long.byte 0x20 26.--31. 1. "RESERVED" bitfld.long 0x20 24.--25. "PHY_AC_LPBK_ENABLE,Loopback enable for the address/control slices." "0,1,2,3" newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" bitfld.long 0x20 16. "PHY_AC_LPBK_OBS_SELECT,Select value to map an individual loopback address/control slice observation register to the global observation register." "0,1" newline hexmask.long.byte 0x20 9.--15. 1. "RESERVED" bitfld.long 0x20 8. "PHY_AC_LPBK_ERR_CLEAR,Address/control loopback error clear." "0,1" newline hexmask.long.byte 0x20 1.--7. 1. "RESERVED" bitfld.long 0x20 0. "PHY_ADRCTL_MANUAL_UPDATE,Address/control manual update of slave delay lines." "0,1" line.long 0x24 "DDRSS_PHY_1351" hexmask.long.byte 0x24 28.--31. 1. "RESERVED" hexmask.long.byte 0x24 24.--27. 1. "PHY_AC_PRBS_PATTERN_MASK,PRBS7 mask signal for address/control slice." newline bitfld.long 0x24 23. "RESERVED" "0,1" hexmask.long.byte 0x24 16.--22. 1. "PHY_AC_PRBS_PATTERN_START,PRBS7 start pattern for address/control slice." newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED" hexmask.long.word 0x24 0.--8. 1. "PHY_AC_LPBK_CONTROL,Address/control slice loopback control setting." rgroup.long 0x5520++0x3 line.long 0x0 "DDRSS_PHY_1352" hexmask.long 0x0 0.--31. 1. "PHY_AC_LPBK_RESULT_OBS,Observation register for the loopback address/control slices." group.long 0x5524++0x27 line.long 0x0 "DDRSS_PHY_1353" hexmask.long.word 0x0 22.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--21. 1. "PHY_AC_CLK_LPBK_CONTROL,Mem clk block loopback control setting." newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" bitfld.long 0x0 8. "PHY_AC_CLK_LPBK_ENABLE,Loopback enable for mem clk blocks." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_AC_CLK_LPBK_OBS_SELECT,Select value to map an individual loopback mem clk block observation register to the global observation register." "0,1" line.long 0x4 "DDRSS_PHY_1354" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" bitfld.long 0x4 24. "PHY_TOP_PWR_RDC_DISABLE,top param power reduction disable." "0,1" newline hexmask.long.byte 0x4 17.--23. 1. "RESERVED" bitfld.long 0x4 16. "PHY_AC_PWR_RDC_DISABLE,ac slice power reduction disable." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "PHY_AC_CLK_LPBK_RESULT_OBS,Observation register for loopback mem clk blocks." line.long 0x8 "DDRSS_PHY_1355" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "PHY_AC_SLV_DLY_CTRL_GATE_DISABLE,ac slice slv_dly_control block power reduction disable." "0,1" line.long 0xC "DDRSS_PHY_1356" hexmask.long 0xC 0.--31. 1. "PHY_DATA_BYTE_ORDER_SEL,Used to define the data slice's byte swap for CA bits 7:0." line.long 0x10 "DDRSS_PHY_1357" hexmask.long.byte 0x10 26.--31. 1. "RESERVED" bitfld.long 0x10 24.--25. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_0,Select adrctl_mstr_dly_enc for the address/control slice 0 ." "0,1,2,3" newline bitfld.long 0x10 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 16.--20. 1. "PHY_CALVL_DEVICE_MAP,Define which device's DQ feedback data bits should be used during CA training" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "PHY_LPDDR4_CONNECT,PHY is connected to LPDDR4 devices" "0,1" newline hexmask.long.byte 0x10 0.--7. 1. "PHY_DATA_BYTE_ORDER_SEL_HIGH,Used to define the data slice's byte swap for CA bits" line.long 0x14 "DDRSS_PHY_1358" hexmask.long 0x14 2.--31. 1. "RESERVED" bitfld.long 0x14 0.--1. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_1,Select adrctl_mstr_dly_enc for the address/control slice 1 ." "0,1,2,3" line.long 0x18 "DDRSS_PHY_1359" hexmask.long 0x18 0.--31. 1. "PHY_DDL_AC_ENABLE,PHY Address/Control DDL BIST mode enable." line.long 0x1C "DDRSS_PHY_1360" hexmask.long.byte 0x1C 26.--31. 1. "RESERVED" hexmask.long 0x1C 0.--25. 1. "PHY_DDL_AC_MODE,PHY Address/Control DDL BIST mode." line.long 0x20 "DDRSS_PHY_1361" hexmask.long.byte 0x20 27.--31. 1. "RESERVED" bitfld.long 0x20 24.--26. "PHY_ERR_MASK_EN,PHY ERROR information report mask enable." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 16.--23. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_AC,Specify threshold value for PHY init update tracking for AC slice." hexmask.long.byte 0x20 11.--15. 1. "RESERVED" newline bitfld.long 0x20 8.--10. "PHY_INIT_UPDATE_CONFIG,PHY init update function configuration." "0,1,2,3,4,5,6,7" bitfld.long 0x20 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x20 0.--5. 1. "PHY_DDL_AC_MASK,PHY Address/Control DDL BIST mask." line.long 0x24 "DDRSS_PHY_1362" hexmask.long 0x24 3.--31. 1. "RESERVED" bitfld.long 0x24 0.--2. "PHY_ERR_STATUS,PHY ERROR information." "0,1,2,3,4,5,6,7" rgroup.long 0x554C++0xF line.long 0x0 "DDRSS_PHY_1363" hexmask.long 0x0 0.--31. 1. "PHY_DS0_DQS_ERR_COUNTER,PHY DATA SLICE 0 DQS ERROR counter." line.long 0x4 "DDRSS_PHY_1364" hexmask.long 0x4 0.--31. 1. "PHY_DS1_DQS_ERR_COUNTER,PHY DATA SLICE 1 DQS ERROR counter." line.long 0x8 "DDRSS_PHY_1365" hexmask.long 0x8 0.--31. 1. "PHY_DS2_DQS_ERR_COUNTER,PHY DATA SLICE 2 DQS ERROR counter." line.long 0xC "DDRSS_PHY_1366" hexmask.long 0xC 0.--31. 1. "PHY_DS3_DQS_ERR_COUNTER,PHY DATA SLICE 3 DQS ERROR counter." group.long 0x555C++0x7 line.long 0x0 "DDRSS_PHY_1367" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long.byte 0x0 24.--27. 1. "PHY_DS_INIT_COMPLETE_OBS,Observation register for dfi_init_complete for data slice." newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED" hexmask.long.word 0x0 8.--17. 1. "PHY_AC_INIT_COMPLETE_OBS,Observation register for dfi_init_complete for adr and ac slice." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED" bitfld.long 0x0 0.--1. "PHY_DLL_RST_EN,PHY DDL reset software interface enable." "0,1,2,3" line.long 0x4 "DDRSS_PHY_1368" hexmask.long.byte 0x4 27.--31. 1. "RESERVED" bitfld.long 0x4 24.--26. "PHY_GRP_SHIFT_OBS_SELECT,Select value to map an individual address/control group slice automatic cycle/half_cycle shift settings to the observation register." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 20.--23. 1. "RESERVED" hexmask.long.byte 0x4 16.--19. 1. "PHY_GRP_SLV_DLY_ENC_OBS_SELECT,Select value to map an individual address/control group slice slave delay to the encoded value observation register." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE,Memory clock bit slice DCC block power reduction disable." "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED" bitfld.long 0x4 0. "PHY_UPDATE_MASK,Control to disable the generation of dfi_phyupd_req and use of dfi_ctrlupd_req." "0,1" rgroup.long 0x5564++0x3 line.long 0x0 "DDRSS_PHY_1369" hexmask.long.word 0x0 19.--31. 1. "RESERVED" bitfld.long 0x0 16.--18. "PHY_GRP_SHIFT_OBS,Observation register for the address/control group automatic half cycle and cycle shift values." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "PHY_GRP_SLV_DLY_ENC_OBS,Observation register for all address/control group slice slave delay encoded values." group.long 0x5568++0xD3 line.long 0x0 "DDRSS_PHY_1370" hexmask.long.byte 0x0 27.--31. 1. "RESERVED" bitfld.long 0x0 24.--26. "PHY_PLL_LOCK_DEASSERT_MASK,PLL Lock de-assert Mask." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED" hexmask.long.word 0x0 8.--18. 1. "PHY_PARITY_ERROR_REGIF_PS,Injects parity error to register interface signals in param_split." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PHY_PARITY_ERROR_INJECTION_ENABLE,Enable parity error injection." "0,1" line.long 0x4 "DDRSS_PHY_1371" hexmask.long.word 0x4 23.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--22. 1. "SC_PHY_PARITY_ERROR_INFO_WOCLR,Parity Error Info." newline bitfld.long 0x4 15. "RESERVED" "0,1" hexmask.long.byte 0x4 8.--14. 1. "PHY_PARITY_ERROR_INFO_MASK,Parity Error Info Mask." newline bitfld.long 0x4 7. "RESERVED" "0,1" hexmask.long.byte 0x4 0.--6. 1. "PHY_PARITY_ERROR_INFO,Parity Error Info." line.long 0x8 "DDRSS_PHY_1372" bitfld.long 0x8 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x8 16.--29. 1. "PHY_TIMEOUT_ERROR_INFO_MASK,Timeout Error Info Mask." newline bitfld.long 0x8 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x8 0.--13. 1. "PHY_TIMEOUT_ERROR_INFO,Timeout Error Info." line.long 0xC "DDRSS_PHY_1373" bitfld.long 0xC 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 24.--29. 1. "PHY_PLL_FREQUENCY_ERROR_MASK,PLL Frequency Error Info Mask." newline hexmask.long.byte 0xC 20.--23. 1. "RESERVED" hexmask.long.byte 0xC 16.--19. 1. "PHY_PLL_FREQUENCY_ERROR,PLL Frequency Error Info." newline bitfld.long 0xC 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0xC 0.--13. 1. "SC_PHY_TIMEOUT_ERROR_INFO_WOCLR,Timeout Error Info." line.long 0x10 "DDRSS_PHY_1374" hexmask.long.word 0x10 20.--31. 1. "RESERVED" hexmask.long.word 0x10 8.--19. 1. "PHY_PLL_DSKEWCALOUT_MIN,PLL DSKEWCALOUT threshold min value." newline bitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10 0.--5. 1. "SC_PHY_PLL_FREQUENCY_ERROR_WOCLR,PLL_Frequency Error Info." line.long 0x14 "DDRSS_PHY_1375" hexmask.long.byte 0x14 26.--31. 1. "RESERVED" bitfld.long 0x14 24.--25. "PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK,PLL DSKEWCALOUT threshold Error Info Mask." "0,1,2,3" newline hexmask.long.byte 0x14 18.--23. 1. "RESERVED" rbitfld.long 0x14 16.--17. "PHY_PLL_DSKEWCALOUT_ERROR_INFO,PLL DSKEWCALOUT threshold Error Info." "0,1,2,3" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED" hexmask.long.word 0x14 0.--11. 1. "PHY_PLL_DSKEWCALOUT_MAX,PLL DSKEWCALOUT threshold max value." line.long 0x18 "DDRSS_PHY_1376" hexmask.long.word 0x18 17.--31. 1. "RESERVED" hexmask.long.word 0x18 8.--16. 1. "PHY_TOP_FSM_ERROR_INFO,Top level FSM Error Info." newline hexmask.long.byte 0x18 2.--7. 1. "RESERVED" bitfld.long 0x18 0.--1. "SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR,PLL DSKEWCALOUT threshold Error Info." "0,1,2,3" line.long 0x1C "DDRSS_PHY_1377" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" hexmask.long.word 0x1C 16.--24. 1. "SC_PHY_TOP_FSM_ERROR_INFO_WOCLR,Top level FSM Error Info." newline hexmask.long.byte 0x1C 9.--15. 1. "RESERVED" hexmask.long.word 0x1C 0.--8. 1. "PHY_TOP_FSM_ERROR_INFO_MASK,Top level FSM Error Info Mask." line.long 0x20 "DDRSS_PHY_1378" hexmask.long.byte 0x20 26.--31. 1. "RESERVED" hexmask.long.word 0x20 16.--25. 1. "PHY_FSM_TRANSIENT_ERROR_INFO_MASK,Accumulated Top level FSM Error Info Mask." newline hexmask.long.byte 0x20 10.--15. 1. "RESERVED" hexmask.long.word 0x20 0.--9. 1. "PHY_FSM_TRANSIENT_ERROR_INFO,Accumulated Top level FSM Error Info." line.long 0x24 "DDRSS_PHY_1379" hexmask.long.byte 0x24 26.--31. 1. "RESERVED" bitfld.long 0x24 24.--25. "PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK,Training/Calibration Error Info Mask for TOP." "0,1,2,3" newline hexmask.long.byte 0x24 18.--23. 1. "RESERVED" rbitfld.long 0x24 16.--17. "PHY_TOP_TRAIN_CALIB_ERROR_INFO,Training/Calibration Error Info for TOP." "0,1,2,3" newline hexmask.long.byte 0x24 10.--15. 1. "RESERVED" hexmask.long.word 0x24 0.--9. 1. "SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR,Accumulated Top level FSM Error Info." line.long 0x28 "DDRSS_PHY_1380" bitfld.long 0x28 31. "RESERVED" "0,1" hexmask.long.byte 0x28 24.--30. 1. "SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR,Training/Calibration Error Info." newline bitfld.long 0x28 23. "RESERVED" "0,1" hexmask.long.byte 0x28 16.--22. 1. "PHY_TRAIN_CALIB_ERROR_INFO_MASK,Training/Calibration Error Info Mask." newline bitfld.long 0x28 15. "RESERVED" "0,1" hexmask.long.byte 0x28 8.--14. 1. "PHY_TRAIN_CALIB_ERROR_INFO,Training/Calibration Error Info." newline hexmask.long.byte 0x28 2.--7. 1. "RESERVED" bitfld.long 0x28 0.--1. "SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR,Training/Calibration Error Info for TOP." "0,1,2,3" line.long 0x2C "DDRSS_PHY_1381" hexmask.long.tbyte 0x2C 14.--31. 1. "RESERVED" hexmask.long.byte 0x2C 8.--13. 1. "PHY_GLOBAL_ERROR_INFO_MASK,Global Error Info Mask." newline bitfld.long 0x2C 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x2C 0.--5. 1. "PHY_GLOBAL_ERROR_INFO,Global Error Info." line.long 0x30 "DDRSS_PHY_1382" hexmask.long.word 0x30 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x30 0.--19. 1. "PHY_TRAINING_TIMEOUT_VALUE,Training timeout value." line.long 0x34 "DDRSS_PHY_1383" hexmask.long.word 0x34 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x34 0.--19. 1. "PHY_INIT_TIMEOUT_VALUE,Init or DFS timeout value." line.long 0x38 "DDRSS_PHY_1384" hexmask.long.word 0x38 16.--31. 1. "RESERVED" hexmask.long.word 0x38 0.--15. 1. "PHY_LP_TIMEOUT_VALUE,DFI LP timeout value." line.long 0x3C "DDRSS_PHY_1385" hexmask.long 0x3C 0.--31. 1. "PHY_PHYUPD_TIMEOUT_VALUE,DFI PHYUPD timeout value." line.long 0x40 "DDRSS_PHY_1386" bitfld.long 0x40 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 24.--28. 1. "PHY_PLL_LOCK_0_MIN_VALUE,PLL min timeout value." newline hexmask.long.byte 0x40 20.--23. 1. "RESERVED" hexmask.long.tbyte 0x40 0.--19. 1. "PHY_PHYMSTR_TIMEOUT_VALUE,DFI PHYMSTR timeout value." line.long 0x44 "DDRSS_PHY_1387" hexmask.long.byte 0x44 28.--31. 1. "RESERVED" hexmask.long.byte 0x44 24.--27. 1. "PHY_PLL_FREQUENCY_DELTA,Acceptable PLL frequency delta." newline hexmask.long.byte 0x44 16.--23. 1. "PHY_RDDATA_VALID_TIMEOUT_VALUE,RDDATA VALID timeout value." hexmask.long.word 0x44 0.--15. 1. "PHY_PLL_LOCK_TIMEOUT_VALUE,PLL max timeout value." line.long 0x48 "DDRSS_PHY_1388" bitfld.long 0x48 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x48 16.--29. 1. "PHY_ADRCTL_FSM_ERROR_INFO_0,ADRCTL slice level FSM Error Info." newline hexmask.long.word 0x48 0.--15. 1. "PHY_PLL_FREQUENCY_COMPARE_INTERVAL,PLL Frequency compare interval." line.long 0x4C "DDRSS_PHY_1389" bitfld.long 0x4C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x4C 16.--29. 1. "SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0,ADRCTL Slice level FSM Error Info." newline bitfld.long 0x4C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x4C 0.--13. 1. "PHY_ADRCTL_FSM_ERROR_INFO_MASK_0,ADRCTL Slice level FSM Error Info Mask." line.long 0x50 "DDRSS_PHY_1390" bitfld.long 0x50 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x50 16.--29. 1. "PHY_ADRCTL_FSM_ERROR_INFO_MASK_1,ADRCTL Slice level FSM Error Info Mask." newline bitfld.long 0x50 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x50 0.--13. 1. "PHY_ADRCTL_FSM_ERROR_INFO_1,ADRCTL slice level FSM Error Info." line.long 0x54 "DDRSS_PHY_1391" bitfld.long 0x54 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x54 16.--29. 1. "PHY_MEMCLK_FSM_ERROR_INFO_0,MEMCLK slice level FSM Error Info." newline bitfld.long 0x54 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x54 0.--13. 1. "SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1,ADRCTL Slice level FSM Error Info." line.long 0x58 "DDRSS_PHY_1392" bitfld.long 0x58 30.--31. "RESERVED" "0,1,2,3" hexmask.long.word 0x58 16.--29. 1. "SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0,MEMCLK Slice level FSM Error Info." newline bitfld.long 0x58 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x58 0.--13. 1. "PHY_MEMCLK_FSM_ERROR_INFO_MASK_0,MEMCLK Slice level FSM Error Info Mask." line.long 0x5C "DDRSS_PHY_1393" hexmask.long.word 0x5C 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x5C 0.--17. 1. "PHY_PAD_CAL_IO_CFG_0,Pad calibration Controls PCLK/PARK pin and vref switch." line.long 0x60 "DDRSS_PHY_1394" hexmask.long.tbyte 0x60 14.--31. 1. "RESERVED" hexmask.long.word 0x60 0.--13. 1. "PHY_PAD_ACS_IO_CFG,Controls PCLK/PARK pin for acs pad." line.long 0x64 "DDRSS_PHY_1395" hexmask.long 0x64 1.--31. 1. "RESERVED" bitfld.long 0x64 0. "PHY_PLL_BYPASS,PHY clock PLL bypass select." "0,1" line.long 0x68 "DDRSS_PHY_1396" hexmask.long.word 0x68 17.--31. 1. "RESERVED" bitfld.long 0x68 16. "PHY_LOW_FREQ_SEL,Enables the PHY to enter/exit the PLL domain from the negative clock edge." "0,1" newline bitfld.long 0x68 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.word 0x68 0.--12. 1. "PHY_PLL_CTRL,PHY clock PLL controls." line.long 0x6C "DDRSS_PHY_1397" hexmask.long.byte 0x6C 28.--31. 1. "RESERVED" hexmask.long.byte 0x6C 24.--27. 1. "PHY_CSLVL_DLY_STEP,Sets the delay step size plus 1 during CS training." newline hexmask.long.byte 0x6C 20.--23. 1. "RESERVED" hexmask.long.byte 0x6C 16.--19. 1. "PHY_CSLVL_CAPTURE_CNT,Defines the number of samples to take at each GRP slave delay setting during CS training." newline hexmask.long.byte 0x6C 12.--15. 1. "RESERVED" hexmask.long.word 0x6C 0.--11. 1. "PHY_PAD_VREF_CTRL_AC,Pad VREF control settings for the address/control." line.long 0x70 "DDRSS_PHY_1398" hexmask.long.byte 0x70 25.--31. 1. "RESERVED" bitfld.long 0x70 24. "PHY_LVL_MEAS_DLY_STEP_ENABLE,Enables the phy_adr_meas_dly_step_value to be used instead of the phy_cslvl_dly_step parameter." "0,1" newline hexmask.long.byte 0x70 17.--23. 1. "RESERVED" bitfld.long 0x70 16. "PHY_SW_CSLVL_DVW_MIN_EN,Enables the software override data valid window size during CS training." "0,1" newline hexmask.long.byte 0x70 9.--15. 1. "RESERVED" hexmask.long.word 0x70 0.--8. 1. "PHY_SW_CSLVL_DVW_MIN,Sets the software override data valid window size during CS training." line.long 0x74 "DDRSS_PHY_1399" hexmask.long.byte 0x74 27.--31. 1. "RESERVED" hexmask.long.word 0x74 16.--26. 1. "PHY_GRP1_SLAVE_DELAY_0,Address slice slave delay setting for address slice 1." newline hexmask.long.byte 0x74 11.--15. 1. "RESERVED" hexmask.long.word 0x74 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_0,Address slice slave delay setting for address slice 0." line.long 0x78 "DDRSS_PHY_1400" hexmask.long.byte 0x78 27.--31. 1. "RESERVED" hexmask.long.word 0x78 16.--26. 1. "PHY_GRP3_SLAVE_DELAY_0,Address slice slave delay setting for address slice 3." newline hexmask.long.byte 0x78 11.--15. 1. "RESERVED" hexmask.long.word 0x78 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_0,Address slice slave delay setting for address slice 2." line.long 0x7C "DDRSS_PHY_1401" hexmask.long.tbyte 0x7C 11.--31. 1. "RESERVED" hexmask.long.word 0x7C 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_1,Address slice slave delay setting for address slice 0." line.long 0x80 "DDRSS_PHY_1402" hexmask.long.tbyte 0x80 11.--31. 1. "RESERVED" hexmask.long.word 0x80 0.--10. 1. "PHY_GRP1_SLAVE_DELAY_1,Address slice slave delay setting for address slice 1." line.long 0x84 "DDRSS_PHY_1403" hexmask.long.tbyte 0x84 11.--31. 1. "RESERVED" hexmask.long.word 0x84 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_1,Address slice slave delay setting for address slice 2." line.long 0x88 "DDRSS_PHY_1404" hexmask.long.tbyte 0x88 11.--31. 1. "RESERVED" hexmask.long.word 0x88 0.--10. 1. "PHY_GRP3_SLAVE_DELAY_1,Address slice slave delay setting for address slice 3." line.long 0x8C "DDRSS_PHY_1405" hexmask.long 0x8C 3.--31. 1. "RESERVED" bitfld.long 0x8C 0.--2. "PHY_CLK_DC_CAL_CLK_SEL,Determines DCC CAL clock." "0,1,2,3,4,5,6,7" line.long 0x90 "DDRSS_PHY_1406" bitfld.long 0x90 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0x90 0.--29. 1. "PHY_PAD_FDBK_DRIVE,Controls drive settings for gate feedback pads." line.long 0x94 "DDRSS_PHY_1407" hexmask.long.word 0x94 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x94 0.--17. 1. "PHY_PAD_FDBK_DRIVE2,Controls drive settings (enslice/boost) for gate feedback pads." line.long 0x98 "DDRSS_PHY_1408" bitfld.long 0x98 31. "RESERVED" "0,1" hexmask.long 0x98 0.--30. 1. "PHY_PAD_DATA_DRIVE,Controls drive settings for data pads." line.long 0x9C "DDRSS_PHY_1409" hexmask.long 0x9C 0.--31. 1. "PHY_PAD_DQS_DRIVE,Controls drive settings for dqs pads." line.long 0xA0 "DDRSS_PHY_1410" bitfld.long 0xA0 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0xA0 0.--29. 1. "PHY_PAD_ADDR_DRIVE,Controls drive settings for the address/control pads." line.long 0xA4 "DDRSS_PHY_1411" hexmask.long.byte 0xA4 27.--31. 1. "RESERVED" hexmask.long 0xA4 0.--26. 1. "PHY_PAD_ADDR_DRIVE2,Controls drive settings for the address/control pads." line.long 0xA8 "DDRSS_PHY_1412" hexmask.long 0xA8 0.--31. 1. "PHY_PAD_CLK_DRIVE,Controls drive settings for clock pads." line.long 0xAC "DDRSS_PHY_1413" hexmask.long.word 0xAC 18.--31. 1. "RESERVED" hexmask.long.tbyte 0xAC 0.--17. 1. "PHY_PAD_CLK_DRIVE2,Controls drive settings for clock pads." line.long 0xB0 "DDRSS_PHY_1414" bitfld.long 0xB0 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0xB0 0.--29. 1. "PHY_PAD_CKE_DRIVE,Controls drive settings for cke pads." line.long 0xB4 "DDRSS_PHY_1415" hexmask.long.byte 0xB4 27.--31. 1. "RESERVED" hexmask.long 0xB4 0.--26. 1. "PHY_PAD_CKE_DRIVE2,Controls drive settings for cke pads." line.long 0xB8 "DDRSS_PHY_1416" bitfld.long 0xB8 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0xB8 0.--29. 1. "PHY_PAD_RST_DRIVE,Controls drive settings for reset_n pads." line.long 0xBC "DDRSS_PHY_1417" hexmask.long.byte 0xBC 27.--31. 1. "RESERVED" hexmask.long 0xBC 0.--26. 1. "PHY_PAD_RST_DRIVE2,Controls drive settings for reset_n pads." line.long 0xC0 "DDRSS_PHY_1418" bitfld.long 0xC0 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0xC0 0.--29. 1. "PHY_PAD_CS_DRIVE,Controls drive settings for cs pads." line.long 0xC4 "DDRSS_PHY_1419" hexmask.long.byte 0xC4 27.--31. 1. "RESERVED" hexmask.long 0xC4 0.--26. 1. "PHY_PAD_CS_DRIVE2,Controls drive settings for cs pads." line.long 0xC8 "DDRSS_PHY_1420" bitfld.long 0xC8 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0xC8 0.--29. 1. "PHY_PAD_ODT_DRIVE,Controls drive settings for odt pads." line.long 0xCC "DDRSS_PHY_1421" hexmask.long.byte 0xCC 27.--31. 1. "RESERVED" hexmask.long 0xCC 0.--26. 1. "PHY_PAD_ODT_DRIVE2,Controls drive settings for odt pads." line.long 0xD0 "DDRSS_PHY_1422" bitfld.long 0xD0 31. "RESERVED" "0,1" hexmask.long.byte 0xD0 24.--30. 1. "PHY_CAL_SETTLING_PRD_0,Number of clock cycles to extend dfi_phyupd_req after the ack is received for settling of final values" newline hexmask.long.word 0xD0 8.--23. 1. "PHY_CAL_VREF_SWITCH_TIMER_0,The settling time for a switch in VREF during IO pad calibration." hexmask.long.byte 0xD0 3.--7. 1. "RESERVED" newline bitfld.long 0xD0 0.--2. "PHY_CAL_CLK_SELECT_0,Pad calibration pad clock frequency select setting for block 0." "0,1,2,3,4,5,6,7" tree.end tree "COMPUTE_CLUSTER0_CTL_CFG_PI" base ad:0x2990000 group.long 0x2000++0x3 line.long 0x0 "DDRSS_PI_0" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" hexmask.long.byte 0x0 8.--11. 1. "PI_DRAM_CLASS,Defines the memory class for the PI.Bh - LPDDR4All other values reserved" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PI_START,Initiate command processing in the PI." "0,1" rgroup.long 0x2004++0xF line.long 0x0 "DDRSS_PI_1" hexmask.long 0x0 0.--31. 1. "PI_VERSION_0,Holds the PI version number." line.long 0x4 "DDRSS_PI_2" hexmask.long 0x4 0.--31. 1. "PI_VERSION_1,Holds the PI version number." line.long 0x8 "DDRSS_PI_3" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "PI_ID,Holds the PI ID number." line.long 0xC "DDRSS_PI_4" hexmask.long 0xC 0.--31. 1. "PI_UNUSED_REG_0,Unused register" group.long 0x2014++0xB line.long 0x0 "DDRSS_PI_5" hexmask.long.word 0x0 17.--31. 1. "RESERVED" bitfld.long 0x0 16. "PI_NOTCARE_PHYUPD,Allow the PI to issue a master request to the controller if a phyupd_req from the PHY has been detected." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" bitfld.long 0x0 8. "PI_INIT_LVL_EN,Enables the initial leveling sequence after PI initialization procedure." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PI_NORMAL_LVL_SEQ,Enable the PI to finish all the pending leveling before releasing the DFI bus." "0,1" line.long 0x4 "DDRSS_PI_6" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" bitfld.long 0x4 24. "PI_TRAIN_ALL_FREQ_REQ,Triggers training for all supported frequencies in PI_FREQ_MAP." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "PI_TCMD_GAP,Specifies the minimum gap in DFI clocks between two commands." line.long 0x8 "DDRSS_PI_7" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "PI_DFI_PHYMSTR_STATE_SEL_R,DFI PHY Master State Select: Indication from the PHY to the MC whether the requested memory state is IDLE or Self refresh." "0,1" newline hexmask.long.byte 0x8 17.--23. 1. "RESERVED" bitfld.long 0x8 16. "PI_DFI_PHYMSTR_CS_STATE_R,This signal indicates the state of the DRAM when the PHY becomes the master." "0,1" newline hexmask.long.byte 0x8 10.--15. 1. "RESERVED" bitfld.long 0x8 8.--9. "PI_DFI_PHYMSTR_TYPE,DFI Master Request Type used for dfi 4.1 verision: This signal indicates the required state of DRAM when PHY becomes the master." "0,1,2,3" newline hexmask.long.byte 0x8 1.--7. 1. "RESERVED" bitfld.long 0x8 0. "PI_DFI_VERSION,Define the DFI master version set 1 for DFI4.1 set 0 for DFI4.0" "0,1" rgroup.long 0x2020++0xF line.long 0x0 "DDRSS_PI_8" hexmask.long 0x0 0.--31. 1. "PI_TDFI_PHYMSTR_MAX,Indicates the maximum number of DFI clock cycles registered while the dfi_phymstr_req signal is asserted and the dfi_phymstr_ack signal is asserted." line.long 0x4 "DDRSS_PI_9" hexmask.long.word 0x4 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--19. 1. "PI_TDFI_PHYMSTR_RESP,Indicates the maximum number of DFI clock cycles registered between a dfi_phymstr_req signal assertion and a dfi_phymstr_ack signal assertion." line.long 0x8 "DDRSS_PI_10" hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "PI_TDFI_PHYUPD_RESP,Indicates the maximum number of DFI clock cycles registered between a dfi_phyupd_req signal assertion and a dfi_phyupd_ack signal assertion." line.long 0xC "DDRSS_PI_11" hexmask.long 0xC 0.--31. 1. "PI_TDFI_PHYUPD_MAX,Indicates the maximum number of DFI clock cycles registered while the dfi_phyupd_req signal is asserted and the dfi_phy_ack signal is asserted." group.long 0x2030++0x17 line.long 0x0 "DDRSS_PI_12" hexmask.long 0x0 0.--31. 1. "PI_FREQ_MAP,Frequency map for supported working frequencies." line.long 0x4 "DDRSS_PI_13" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" bitfld.long 0x4 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 17.--23. 1. "RESERVED" bitfld.long 0x4 16. "PI_SW_RST_N,User request to reset the whole PI except the parameter modules." "0,1" newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "PI_INIT_DFS_CALVL_ONLY,Enables frequency training for CA leveling only." "0,1" newline bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "PI_INIT_WORK_FREQ,Indicates the initial work frequency after initialization and initial leveling sequence." line.long 0x8 "DDRSS_PI_14" hexmask.long.byte 0x8 28.--31. 1. "RESERVED" hexmask.long.byte 0x8 24.--27. 1. "PI_TMRR,DRAM tMRR value in memory clock cycles." newline hexmask.long.byte 0x8 17.--23. 1. "RESERVED" bitfld.long 0x8 16. "PI_SRX_LVL_TARGET_CS_EN,Defines self refresh exit trigger target rank/ranks training or all ranks training." "0,1" newline bitfld.long 0x8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "PI_RANK_NUM_PER_CKE,Defines the number of chip selects share one cke" newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED" hexmask.long.byte 0x8 0.--3. 1. "PI_CS_MAP,Defines which chip selects are active." line.long 0xC "DDRSS_PI_15" hexmask.long.word 0xC 17.--31. 1. "RESERVED" bitfld.long 0xC 16. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" bitfld.long 0xC 8. "PI_MCAREF_FORWARD_ONLY,Controls the generation of AREF from the PI module or forward the MC received value." "0,1" newline hexmask.long.byte 0xC 2.--7. 1. "RESERVED" bitfld.long 0xC 0.--1. "PI_PREAMBLE_SUPPORT,Defines the read and write preamble length." "0,1,2,3" line.long 0x10 "DDRSS_PI_16" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" rbitfld.long 0x10 24. "PI_ON_DFIBUS,Monitors the state of the PI controlling the DFI bus." "0,1" newline hexmask.long.byte 0x10 20.--23. 1. "RESERVED" hexmask.long.tbyte 0x10 0.--19. 1. "PI_TREF_INTERVAL,Defines the cycles between refreshes to different chip selects." line.long 0x14 "DDRSS_PI_17" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" rbitfld.long 0x14 24. "PI_SW_WRLVL_RESP_0,Write leveling response for data slice 0." "0,1" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" rbitfld.long 0x14 16. "PI_SWLVL_OP_DONE,Reports the status of the software leveling operation." "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "PI_SWLVL_LOAD,User request to load delays and execute software leveling." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" rbitfld.long 0x14 0. "PI_DATA_RETENTION,Monitors the readiness for the PHY to be put into data retention mode after pi_sref_entry req parameter has been written." "0,1" rgroup.long 0x2048++0x7 line.long 0x0 "DDRSS_PI_18" hexmask.long.byte 0x0 26.--31. 1. "RESERVED" bitfld.long 0x0 24.--25. "PI_SW_RDLVL_RESP_0,Read leveling response for data slice 0." "0,1,2,3" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" bitfld.long 0x0 16. "PI_SW_WRLVL_RESP_3,Write leveling response for data slice 3." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" bitfld.long 0x0 8. "PI_SW_WRLVL_RESP_2,Write leveling response for data slice 2." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" bitfld.long 0x0 0. "PI_SW_WRLVL_RESP_1,Write leveling response for data slice 1." "0,1" line.long 0x4 "DDRSS_PI_19" hexmask.long.byte 0x4 26.--31. 1. "RESERVED" bitfld.long 0x4 24.--25. "PI_SW_CALVL_RESP_0,CA leveling response for address slice 0." "0,1,2,3" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED" bitfld.long 0x4 16.--17. "PI_SW_RDLVL_RESP_3,Read leveling response for data slice 3." "0,1,2,3" newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED" bitfld.long 0x4 8.--9. "PI_SW_RDLVL_RESP_2,Read leveling response for data slice 2." "0,1,2,3" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" bitfld.long 0x4 0.--1. "PI_SW_RDLVL_RESP_1,Read leveling response for data slice 1." "0,1,2,3" group.long 0x2050++0xEB line.long 0x0 "DDRSS_PI_20" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PI_SWLVL_WR_SLICE_0,SW leveling write command in WDQ training." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" bitfld.long 0x0 16. "PI_SWLVL_EXIT,User request to exit software leveling." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" bitfld.long 0x0 8. "PI_SWLVL_START,User request to initiate software leveling of type in the SW_LEVELING_MODE parameter." "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" bitfld.long 0x0 0.--2. "PI_SW_LEVELING_MODE,Defines the leveling operation for software leveling." "0,1,2,3,4,5,6,7" line.long 0x4 "DDRSS_PI_21" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" bitfld.long 0x4 24. "PI_SWLVL_WR_SLICE_1,SW leveling write command in WDQ training." "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED" rbitfld.long 0x4 16.--17. "PI_SW_WDQLVL_RESP_0,Leveling response for data slice 0." "0,1,2,3" newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "PI_SWLVL_VREF_UPDATE_SLICE_0,SW leveling vref update command in WDQ training." "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED" bitfld.long 0x4 0. "PI_SWLVL_RD_SLICE_0,SW leveling read command in WDQ training." "0,1" line.long 0x8 "DDRSS_PI_22" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "PI_SWLVL_WR_SLICE_2,SW leveling write command in WDQ training." "0,1" newline hexmask.long.byte 0x8 18.--23. 1. "RESERVED" rbitfld.long 0x8 16.--17. "PI_SW_WDQLVL_RESP_1,Leveling response for data slice 1." "0,1,2,3" newline hexmask.long.byte 0x8 9.--15. 1. "RESERVED" bitfld.long 0x8 8. "PI_SWLVL_VREF_UPDATE_SLICE_1,SW leveling vref update command in WDQ training." "0,1" newline hexmask.long.byte 0x8 1.--7. 1. "RESERVED" bitfld.long 0x8 0. "PI_SWLVL_RD_SLICE_1,SW leveling read command in WDQ training." "0,1" line.long 0xC "DDRSS_PI_23" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "PI_SWLVL_WR_SLICE_3,SW leveling write command in WDQ training." "0,1" newline hexmask.long.byte 0xC 18.--23. 1. "RESERVED" rbitfld.long 0xC 16.--17. "PI_SW_WDQLVL_RESP_2,Leveling response for data slice 2." "0,1,2,3" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" bitfld.long 0xC 8. "PI_SWLVL_VREF_UPDATE_SLICE_2,SW leveling vref update command in WDQ training." "0,1" newline hexmask.long.byte 0xC 1.--7. 1. "RESERVED" bitfld.long 0xC 0. "PI_SWLVL_RD_SLICE_2,SW leveling read command in WDQ training." "0,1" line.long 0x10 "DDRSS_PI_24" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" bitfld.long 0x10 24. "PI_SWLVL_SM2_START,SW leveling start command for stage 2." "0,1" newline hexmask.long.byte 0x10 18.--23. 1. "RESERVED" rbitfld.long 0x10 16.--17. "PI_SW_WDQLVL_RESP_3,Leveling response for data slice 3." "0,1,2,3" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "PI_SWLVL_VREF_UPDATE_SLICE_3,SW leveling vref update command in WDQ training." "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "PI_SWLVL_RD_SLICE_3,SW leveling read command in WDQ training." "0,1" line.long 0x14 "DDRSS_PI_25" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "PI_DFS_PERIOD_EN,Enable the DFS triggered periodic leveling." "0,1" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" bitfld.long 0x14 16. "PI_SEQUENTIAL_LVL_REQ,User request to initiate all possible leveling sequences." "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "PI_SWLVL_SM2_RD,SW leveling read command for stage 2." "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "PI_SWLVL_SM2_WR,SW leveling write command for stage 2." "0,1" line.long 0x18 "DDRSS_PI_26" hexmask.long.byte 0x18 25.--31. 1. "RESERVED" bitfld.long 0x18 24. "PI_WRLVL_REQ,User request to initiate write leveling." "0,1" newline hexmask.long.byte 0x18 17.--23. 1. "RESERVED" bitfld.long 0x18 16. "PI_16BIT_DRAM_CONNECT,Enable 16/32 bit DRAM configuration." "0,1" newline hexmask.long.byte 0x18 9.--15. 1. "RESERVED" bitfld.long 0x18 8. "PI_DFI40_POLARITY,Defines the polarity of the dfi_wrdata_cs_n/dfi_rddata_cs_n signals." "0,1" newline hexmask.long.byte 0x18 1.--7. 1. "RESERVED" bitfld.long 0x18 0. "PI_SRE_PERIOD_EN,Enable the self refresh exit triggered periodic leveling." "0,1" line.long 0x1C "DDRSS_PI_27" hexmask.long.word 0x1C 22.--31. 1. "RESERVED" hexmask.long.byte 0x1C 16.--21. 1. "PI_WLMRD,Delay from issuing MRS to first write leveling strobe." newline bitfld.long 0x1C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x1C 8.--13. 1. "PI_WLDQSEN,Delay from issuing MRS to first DQS strobe for write leveling." newline hexmask.long.byte 0x1C 2.--7. 1. "RESERVED" bitfld.long 0x1C 0.--1. "PI_WRLVL_CS,Specifies the target chip select for the write leveling operation initiated through the WRLVL_REQ parameter." "0,1,2,3" line.long 0x20 "DDRSS_PI_28" hexmask.long.byte 0x20 25.--31. 1. "RESERVED" bitfld.long 0x20 24. "PI_WRLVL_ON_SREF_EXIT,Enables automatic write leveling on a self-refresh exit." "0,1" newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" bitfld.long 0x20 16. "PI_WRLVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during write leveling." "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PI_WRLVL_INTERVAL,Number of long count sequences counted between automatic write leveling commands." line.long 0x24 "DDRSS_PI_29" hexmask.long.byte 0x24 28.--31. 1. "RESERVED" hexmask.long.byte 0x24 24.--27. 1. "PI_WRLVL_CS_MAP,Defines the chip select map for write leveling operations." newline hexmask.long.byte 0x24 17.--23. 1. "RESERVED" bitfld.long 0x24 16. "PI_WRLVL_ROTATE,Enables rotational CS for counter triggered automatic write leveling." "0,1" newline hexmask.long.byte 0x24 12.--15. 1. "RESERVED" hexmask.long.byte 0x24 8.--11. 1. "PI_WRLVL_RESP_MASK,Mask for the dfi_wrlvl_resp signal during write leveling." newline hexmask.long.byte 0x24 1.--7. 1. "RESERVED" bitfld.long 0x24 0. "PI_WRLVL_DISABLE_DFS,Disable automatic write leveling on freq change." "0,1" line.long 0x28 "DDRSS_PI_30" hexmask.long.word 0x28 16.--31. 1. "RESERVED" hexmask.long.byte 0x28 8.--15. 1. "PI_TDFI_WRLVL_EN,Defines the DFI tWRLVL_EN timing parameter (in DFI clocks) the minimum cycles from a dfi_wrlvl_en assertion to the first dfi_wrlvl_strobe assertion." newline hexmask.long.byte 0x28 1.--7. 1. "RESERVED" rbitfld.long 0x28 0. "PI_WRLVL_ERROR_STATUS,Holds the error associated with the write level error interrupt." "0,1" line.long 0x2C "DDRSS_PI_31" hexmask.long 0x2C 0.--31. 1. "PI_TDFI_WRLVL_RESP,Defines the DFI tWRLVL_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_wrlvl_req assertion and a dfi_wrlvl_en assertion." line.long 0x30 "DDRSS_PI_32" hexmask.long 0x30 0.--31. 1. "PI_TDFI_WRLVL_MAX,Defines the DFI tWRLVL_MAX timing parameter (in DFI clocks) the maximum cycles between a dfi_wrlvl_en assertion and a valid dfi_wrlvl_resp." line.long 0x34 "DDRSS_PI_33" hexmask.long.byte 0x34 28.--31. 1. "RESERVED" hexmask.long.byte 0x34 24.--27. 1. "PI_ODT_VALUE,When using LPDDR4 this value will be driven out on the dfi_odt signal." newline hexmask.long.byte 0x34 20.--23. 1. "RESERVED" hexmask.long.byte 0x34 16.--19. 1. "PI_TODTH_RD,Defines the minimum DRAM cycles of ODT high time for a read command in memory clocks." newline hexmask.long.byte 0x34 12.--15. 1. "RESERVED" hexmask.long.byte 0x34 8.--11. 1. "PI_TODTH_WR,Defines the minimum DRAM cycles of ODT high time for a write command in memory clocks." newline bitfld.long 0x34 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34 0.--4. 1. "PI_WRLVL_STROBE_NUM,Defines the number of write leveling strobes generated." line.long 0x38 "DDRSS_PI_34" hexmask.long.word 0x38 18.--31. 1. "RESERVED" bitfld.long 0x38 16.--17. "PI_RDLVL_CS,Specifies the target chip select for the data eye training operation initiated through the RDLVL_REQ parameter or the gate training operation initiated through the RDLVL_GATE_REQ parameter." "0,1,2,3" newline hexmask.long.byte 0x38 9.--15. 1. "RESERVED" bitfld.long 0x38 8. "PI_RDLVL_GATE_REQ,User request to initiate gate training." "0,1" newline hexmask.long.byte 0x38 1.--7. 1. "RESERVED" bitfld.long 0x38 0. "PI_RDLVL_REQ,User request to initiate data eye training." "0,1" line.long 0x3C "DDRSS_PI_35" hexmask.long 0x3C 0.--31. 1. "PI_RDLVL_PAT_0,Non-default pattern 0 used for read data eye training of DDR4 or LPDDR4 and read dbi training of DDR4." line.long 0x40 "DDRSS_PI_36" hexmask.long 0x40 0.--31. 1. "PI_RDLVL_PAT_1,Non-default pattern 1 used for read data eye training of DDR4 or LPDDR4 and read dbi training of DDR4." line.long 0x44 "DDRSS_PI_37" hexmask.long 0x44 0.--31. 1. "PI_RDLVL_PAT_2,Non-default pattern 2 used for read data eye training of DDR4 or LPDDR4 and read dbi training of DDR4." line.long 0x48 "DDRSS_PI_38" hexmask.long 0x48 0.--31. 1. "PI_RDLVL_PAT_3,Non-default pattern 3 used for read data eye training of DDR4 or LPDDR4 and read dbi training of DDR4." line.long 0x4C "DDRSS_PI_39" hexmask.long 0x4C 0.--31. 1. "PI_RDLVL_PAT_4,Non-default pattern 4 used for read data eye training of DDR4 or LPDDR4 and read dbi training of DDR4." line.long 0x50 "DDRSS_PI_40" hexmask.long 0x50 0.--31. 1. "PI_RDLVL_PAT_5,Non-default pattern 5 used for read data eye training of DDR4 or LPDDR4 and read dbi training of DDR4." line.long 0x54 "DDRSS_PI_41" hexmask.long 0x54 0.--31. 1. "PI_RDLVL_PAT_6,Non-default pattern 6 used for read data eye training of DDR4 or LPDDR4 and read dbi training of DDR4." line.long 0x58 "DDRSS_PI_42" hexmask.long 0x58 0.--31. 1. "PI_RDLVL_PAT_7,Non-default pattern 7 used for read data eye training of DDR4 or LPDDR4 and read dbi training of DDR4." line.long 0x5C "DDRSS_PI_43" hexmask.long.byte 0x5C 25.--31. 1. "RESERVED" bitfld.long 0x5C 24. "PI_RDLVL_DISABLE_DFS,Disables automatic data eye training on freq change." "0,1" newline hexmask.long.byte 0x5C 17.--23. 1. "RESERVED" bitfld.long 0x5C 16. "PI_RDLVL_ON_SREF_EXIT,Enables automatic data eye training on a self-refresh exit." "0,1" newline hexmask.long.byte 0x5C 9.--15. 1. "RESERVED" bitfld.long 0x5C 8. "PI_RDLVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during data eye training." "0,1" newline hexmask.long.byte 0x5C 4.--7. 1. "RESERVED" hexmask.long.byte 0x5C 0.--3. 1. "PI_RDLVL_SEQ_EN,Specifies the pattern format and MPR for data eye training." line.long 0x60 "DDRSS_PI_44" hexmask.long.byte 0x60 25.--31. 1. "RESERVED" bitfld.long 0x60 24. "PI_RDLVL_ROTATE,Enables rotational CS for interval data eye training." "0,1" newline hexmask.long.byte 0x60 17.--23. 1. "RESERVED" bitfld.long 0x60 16. "PI_RDLVL_GATE_DISABLE_DFS,Disables automatic gate training on freq change." "0,1" newline hexmask.long.byte 0x60 9.--15. 1. "RESERVED" bitfld.long 0x60 8. "PI_RDLVL_GATE_ON_SREF_EXIT,Enables automatic gate training on a self-refresh exit." "0,1" newline hexmask.long.byte 0x60 1.--7. 1. "RESERVED" bitfld.long 0x60 0. "PI_RDLVL_GATE_PERIODIC,Enables the use of the dfi_lvl_periodic signal during gate training." "0,1" line.long 0x64 "DDRSS_PI_45" hexmask.long.word 0x64 20.--31. 1. "RESERVED" hexmask.long.byte 0x64 16.--19. 1. "PI_RDLVL_GATE_CS_MAP,Defines the chip select map for gate training operations." newline hexmask.long.byte 0x64 12.--15. 1. "RESERVED" hexmask.long.byte 0x64 8.--11. 1. "PI_RDLVL_CS_MAP,Defines the chip select map for data eye training operations." newline hexmask.long.byte 0x64 1.--7. 1. "RESERVED" bitfld.long 0x64 0. "PI_RDLVL_GATE_ROTATE,Enables rotational CS for interval gate training." "0,1" line.long 0x68 "DDRSS_PI_46" hexmask.long.tbyte 0x68 10.--31. 1. "RESERVED" hexmask.long.word 0x68 0.--9. 1. "PI_TDFI_RDLVL_RR,Defines the DFI tRDLVL_RR timing parameter (in DFI clocks) the minimum cycles between read commands." line.long 0x6C "DDRSS_PI_47" hexmask.long 0x6C 0.--31. 1. "PI_TDFI_RDLVL_RESP,Defines the DFI tRDLVL_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_rdlvl_req or dfi_rdlvl_gate_req assertion and a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion." line.long 0x70 "DDRSS_PI_48" hexmask.long.word 0x70 16.--31. 1. "RESERVED" hexmask.long.byte 0x70 8.--15. 1. "PI_TDFI_RDLVL_EN,Defines the DFI tRDLVL_EN timing parameter (in DFI clocks) the minimum cycles from a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion to the first read or MRR." newline hexmask.long.byte 0x70 4.--7. 1. "RESERVED" hexmask.long.byte 0x70 0.--3. 1. "PI_RDLVL_RESP_MASK,Mask for the dfi_rdlvl_resp signal during data eye training." line.long 0x74 "DDRSS_PI_49" hexmask.long 0x74 0.--31. 1. "PI_TDFI_RDLVL_MAX,Defines the DFI tRDLVL_MAX timing parameter (in DFI clocks) the maximum cycles between a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion and a valid dfi_rdlvl_resp." line.long 0x78 "DDRSS_PI_50" hexmask.long.byte 0x78 24.--31. 1. "RESERVED" hexmask.long.word 0x78 8.--23. 1. "PI_RDLVL_INTERVAL,Number of long count sequences counted between automatic data eye training commands." newline hexmask.long.byte 0x78 1.--7. 1. "RESERVED" rbitfld.long 0x78 0. "PI_RDLVL_ERROR_STATUS,Holds the error associated with the data eye training error or gate training error interrupt." "0,1" line.long 0x7C "DDRSS_PI_51" hexmask.long.byte 0x7C 28.--31. 1. "RESERVED" hexmask.long.byte 0x7C 24.--27. 1. "PI_RDLVL_PATTERN_NUM,Defines the number of pattern supported in read leveling." newline hexmask.long.byte 0x7C 20.--23. 1. "RESERVED" hexmask.long.byte 0x7C 16.--19. 1. "PI_RDLVL_PATTERN_START,Defines the start pattern in read leveling." newline hexmask.long.word 0x7C 0.--15. 1. "PI_RDLVL_GATE_INTERVAL,Number of long count sequences counted between automatic gate training commands." line.long 0x80 "DDRSS_PI_52" hexmask.long.byte 0x80 25.--31. 1. "RESERVED" bitfld.long 0x80 24. "PI_REG_DIMM_ENABLE,Enable registered DIMM operation." "0,1" newline hexmask.long.byte 0x80 17.--23. 1. "RESERVED" bitfld.long 0x80 16. "PI_RD_PREAMBLE_TRAINING_EN,Enable read preamble training during gate training." "0,1" newline bitfld.long 0x80 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x80 8.--12. 1. "PI_RDLVL_GATE_STROBE_NUM,Defines the number of back to back MPC command in one read process in read gate training." newline bitfld.long 0x80 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x80 0.--4. 1. "PI_RDLVL_STROBE_NUM,Defines the number of back to back MPC command in one read process in read eye training." line.long 0x84 "DDRSS_PI_53" hexmask.long.byte 0x84 26.--31. 1. "RESERVED" bitfld.long 0x84 24.--25. "PI_CALVL_CS,Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter." "0,1,2,3" newline hexmask.long.byte 0x84 17.--23. 1. "RESERVED" bitfld.long 0x84 16. "PI_CALVL_REQ,User request to initiate CA training." "0,1" newline bitfld.long 0x84 15. "RESERVED" "0,1" hexmask.long.byte 0x84 8.--14. 1. "PI_TDFI_PHY_WRLAT,Holds the calculated DFI tPHY_WRLAT timing parameter (in DFI PHY clocks) the maximum cycles between a write command and a dfi_wrdata_en assertion." newline bitfld.long 0x84 7. "RESERVED" "0,1" hexmask.long.byte 0x84 0.--6. 1. "PI_TDFI_RDDATA_EN,Holds the calculated DFI tRDDATA_EN timing parameter (in DFI PHY clocks) the maximum cycles between a read command and a dfi_rddata_en assertion." line.long 0x88 "DDRSS_PI_54" hexmask.long.byte 0x88 25.--31. 1. "RESERVED" bitfld.long 0x88 24. "PI_CALVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during CA training." "0,1" newline hexmask.long.byte 0x88 18.--23. 1. "RESERVED" bitfld.long 0x88 16.--17. "PI_CALVL_SEQ_EN,Specifies which CA training patterns will be used." "0,1,2,3" newline hexmask.long.byte 0x88 12.--15. 1. "RESERVED" hexmask.long.byte 0x88 8.--11. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x88 1.--7. 1. "RESERVED" bitfld.long 0x88 0. "RESERVED,Reserved" "0,1" line.long 0x8C "DDRSS_PI_55" hexmask.long.byte 0x8C 28.--31. 1. "RESERVED" hexmask.long.byte 0x8C 24.--27. 1. "PI_CALVL_CS_MAP,Defines the chip select map for CA training operations." newline hexmask.long.byte 0x8C 17.--23. 1. "RESERVED" bitfld.long 0x8C 16. "PI_CALVL_ROTATE,Enables rotational CS for interval CA training." "0,1" newline hexmask.long.byte 0x8C 9.--15. 1. "RESERVED" bitfld.long 0x8C 8. "PI_CALVL_DISABLE_DFS,Disables automatic CA training on freq change." "0,1" newline hexmask.long.byte 0x8C 1.--7. 1. "RESERVED" bitfld.long 0x8C 0. "PI_CALVL_ON_SREF_EXIT,Enables automatic CA training on a self-refresh exit." "0,1" line.long 0x90 "DDRSS_PI_56" hexmask.long.tbyte 0x90 8.--31. 1. "RESERVED" hexmask.long.byte 0x90 0.--7. 1. "PI_TDFI_CALVL_EN,Defines the DFI tCALVL_EN timing parameter (in DFI clocks) the minimum cycles between a dfi_calvl_en assertion and a dfi_cke de-assertion." line.long 0x94 "DDRSS_PI_57" hexmask.long 0x94 0.--31. 1. "PI_TDFI_CALVL_RESP,Defines the DFI tCALVL_RESP timing parameter (in DFI clocks) the maximum cycles between a dfi_calvl_req assertion and a dfi_calvl_en assertion." line.long 0x98 "DDRSS_PI_58" hexmask.long 0x98 0.--31. 1. "PI_TDFI_CALVL_MAX,Defines the DFI tCALVL_MAX timing parameter (in DFI clocks) the maximum cycles between a dfi_calvl_en assertion and a valid dfi_calvl_resp." line.long 0x9C "DDRSS_PI_59" hexmask.long.word 0x9C 16.--31. 1. "PI_CALVL_INTERVAL,Number of long count sequences counted between automatic CA training commands." hexmask.long.byte 0x9C 10.--15. 1. "RESERVED" newline rbitfld.long 0x9C 8.--9. "PI_CALVL_ERROR_STATUS,Holds the error associated with the CA training error interrupt." "0,1,2,3" hexmask.long.byte 0x9C 1.--7. 1. "RESERVED" newline bitfld.long 0x9C 0. "PI_CALVL_RESP_MASK,Mask for the dfi_calvl_resp signal during CA training." "0,1" line.long 0xA0 "DDRSS_PI_60" bitfld.long 0xA0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA0 24.--28. 1. "PI_TCAEXT,DRAM tCAEXT value in memory cycles." newline bitfld.long 0xA0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA0 16.--20. 1. "PI_TCACKEH,DRAM tCACKEH value in memory cycles." newline bitfld.long 0xA0 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0xA0 8.--13. 1. "PI_TCAMRD,DRAM tCAMRD value in memory cycles." newline bitfld.long 0xA0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA0 0.--4. 1. "PI_TCACKEL,DRAM tCACKEL value in memory cycles." line.long 0xA4 "DDRSS_PI_61" hexmask.long.byte 0xA4 24.--31. 1. "PI_TDFI_INIT_START_MIN,Minimum number of DFI clocks before dfi_init_start can be driven after a previous command/training event." hexmask.long.byte 0xA4 20.--23. 1. "RESERVED" newline hexmask.long.byte 0xA4 16.--19. 1. "PI_CALVL_VREF_NORMAL_STEPSIZE,The adjust step for the post-initial Vref(ca) training." hexmask.long.byte 0xA4 12.--15. 1. "RESERVED" newline hexmask.long.byte 0xA4 8.--11. 1. "PI_CALVL_VREF_INITIAL_STEPSIZE,The adjust step for the initial Vref(ca) training." hexmask.long.byte 0xA4 1.--7. 1. "RESERVED" newline bitfld.long 0xA4 0. "PI_CA_TRAIN_VREF_EN,Control for VREF training during CA training post power-on initialization." "0,1" line.long 0xA8 "DDRSS_PI_62" bitfld.long 0xA8 31. "RESERVED" "0,1" hexmask.long.byte 0xA8 24.--30. 1. "PI_SW_CA_TRAIN_VREF,The Vref value which is set for SW step by step CA training." newline bitfld.long 0xA8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA8 16.--20. 1. "PI_CALVL_STROBE_NUM,The consecutive dfi_calvl_strobe number when updating the CA vref data." newline hexmask.long.byte 0xA8 12.--15. 1. "RESERVED" hexmask.long.byte 0xA8 8.--11. 1. "PI_TCKCKEH,DRAM tCKELCK Clock and command valid before CKE HIGH." newline hexmask.long.byte 0xA8 0.--7. 1. "PI_TDFI_INIT_COMPLETE_MIN,Minimum number of DFI clocks from dfi_init_complete to a command/training event." line.long 0xAC "DDRSS_PI_63" hexmask.long.byte 0xAC 25.--31. 1. "RESERVED" bitfld.long 0xAC 24. "PI_REFRESH_BETWEEN_SEGMENT_DISABLE,Disable the refresh between CA first and second segment training." "0,1" newline hexmask.long.byte 0xAC 17.--23. 1. "RESERVED" bitfld.long 0xAC 16. "PI_DRAM_CLK_DISABLE_DEASSERT_SEL,Indicate dfi_dram_clk_disable deassert following dfi_init_start deassert or dfi_init_complete assert." "0,1" newline hexmask.long.byte 0xAC 8.--15. 1. "PI_INIT_STARTORCOMPLETE_2_CLKDISABLE,Defines the delay from deasserting of dfi_init_start or asserting of dfi_init_complete to deasserting of dfi_dram_clk_disable in DFI clock." hexmask.long.byte 0xAC 0.--7. 1. "PI_CLKDISABLE_2_INIT_START,Defines the delay from the asserting of dfi_dram_clk_disable to the asserting of dfi_init_start in DFI clock." line.long 0xB0 "DDRSS_PI_64" hexmask.long.byte 0xB0 24.--31. 1. "RESERVED" hexmask.long.word 0xB0 8.--23. 1. "PI_FSM_ERROR_INFO_MASK,PI FSM Error Info MASK" newline hexmask.long.byte 0xB0 1.--7. 1. "RESERVED" bitfld.long 0xB0 0. "PI_MC_DFS_PI_SET_VREF_ENABLE,Enable the PI to set VREF value after DFS issued by MC." "0,1" line.long 0xB4 "DDRSS_PI_65" hexmask.long.word 0xB4 16.--31. 1. "PI_FSM_ERROR_INFO,Gather each fsm error bit." hexmask.long.word 0xB4 0.--15. 1. "PI_SC_FSM_ERROR_INFO_WOCLR,PI FSM Error Info." line.long 0xB8 "DDRSS_PI_66" hexmask.long.byte 0xB8 25.--31. 1. "RESERVED" bitfld.long 0xB8 24. "PI_WDQLVL_ROTATE,Enables write DQ training rotate for interval training." "0,1" newline hexmask.long.byte 0xB8 20.--23. 1. "RESERVED" hexmask.long.byte 0xB8 16.--19. 1. "PI_WDQLVL_RESP_MASK,Write DQ training response mask." newline hexmask.long.byte 0xB8 11.--15. 1. "RESERVED" bitfld.long 0xB8 8.--10. "PI_WDQLVL_BST_NUM,Defines the number of write/read bursts issued at each step in write DQ training." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB8 1.--7. 1. "RESERVED" bitfld.long 0xB8 0. "PI_WDQLVL_VREF_EN,Control for VREF training as part of non-initialization write DQ training." "0,1" line.long 0xBC "DDRSS_PI_67" hexmask.long.byte 0xBC 25.--31. 1. "RESERVED" bitfld.long 0xBC 24. "PI_WDQLVL_PERIODIC,Enables periodic write DQ training." "0,1" newline bitfld.long 0xBC 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xBC 16.--20. 1. "PI_WDQLVL_VREF_NORMAL_STEPSIZE,Write DQ training vref step size for post_initial training." newline bitfld.long 0xBC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xBC 8.--12. 1. "PI_WDQLVL_VREF_INITIAL_STEPSIZE,Write DQ training vref step size for initial training." newline hexmask.long.byte 0xBC 4.--7. 1. "RESERVED" hexmask.long.byte 0xBC 0.--3. 1. "PI_WDQLVL_CS_MAP,Map of CS's included in write DQ training sequence." line.long 0xC0 "DDRSS_PI_68" hexmask.long.byte 0xC0 24.--31. 1. "RESERVED" hexmask.long.byte 0xC0 16.--23. 1. "PI_TDFI_WDQLVL_EN,DFI timing param tWDQLVL_EN." newline hexmask.long.byte 0xC0 10.--15. 1. "RESERVED" bitfld.long 0xC0 8.--9. "PI_WDQLVL_CS,Write DQ training target chip select." "0,1,2,3" newline hexmask.long.byte 0xC0 1.--7. 1. "RESERVED" bitfld.long 0xC0 0. "PI_WDQLVL_REQ,SW write to initiate Write DQ training request." "0,1" line.long 0xC4 "DDRSS_PI_69" hexmask.long 0xC4 0.--31. 1. "PI_TDFI_WDQLVL_RESP,DFI timing param tWDQLVL_RESP." line.long 0xC8 "DDRSS_PI_70" hexmask.long 0xC8 0.--31. 1. "PI_TDFI_WDQLVL_MAX,DFI timing param tWDQLVL_MAX." line.long 0xCC "DDRSS_PI_71" hexmask.long.byte 0xCC 25.--31. 1. "RESERVED" bitfld.long 0xCC 24. "PI_WDQLVL_DISABLE_DFS,Disable automatic write DQ training on freq change." "0,1" newline hexmask.long.byte 0xCC 17.--23. 1. "RESERVED" bitfld.long 0xCC 16. "PI_WDQLVL_ON_SREF_EXIT,Issue a write DQ training command on self-refresh exit." "0,1" newline hexmask.long.word 0xCC 0.--15. 1. "PI_WDQLVL_INTERVAL,Sets the maximum number of long count sequences allowed between automatic write DQ training operations." line.long 0xD0 "DDRSS_PI_72" hexmask.long.byte 0xD0 25.--31. 1. "RESERVED" bitfld.long 0xD0 24. "PI_PARALLEL_WDQLVL_EN,Enable per rank parallel Write DQ training for LPDDR4 " "0,1" newline hexmask.long.byte 0xD0 17.--23. 1. "RESERVED" bitfld.long 0xD0 16. "PI_DQS_OSC_PERIOD_EN,Enable for DQS oscillator triggered periodic write DQ training " "0,1" newline hexmask.long.byte 0xD0 9.--15. 1. "RESERVED" bitfld.long 0xD0 8. "PI_WDQLVL_OSC_EN,Enable for DQS oscillator triggered write DQ training " "0,1" newline hexmask.long.byte 0xD0 2.--7. 1. "RESERVED" rbitfld.long 0xD0 0.--1. "PI_WDQLVL_ERROR_STATUS,Holds the error associated with the write dq level error interrupt." "0,1,2,3" line.long 0xD4 "DDRSS_PI_73" hexmask.long.byte 0xD4 28.--31. 1. "RESERVED" hexmask.long.byte 0xD4 24.--27. 1. "RESERVED,Reserved" newline bitfld.long 0xD4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD4 16.--20. 1. "PI_TCCD,DRAM CAS-to-CAS value in cycles." newline hexmask.long.byte 0xD4 11.--15. 1. "RESERVED" bitfld.long 0xD4 8.--10. "PI_ROW_DIFF,Difference between number of address pins available and number being used." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD4 2.--7. 1. "RESERVED" bitfld.long 0xD4 0.--1. "PI_BANK_DIFF,Difference between number of bank pins available and number being used." "0,1,2,3" line.long 0xD8 "DDRSS_PI_74" hexmask.long.byte 0xD8 28.--31. 1. "RESERVED" hexmask.long.byte 0xD8 24.--27. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xD8 20.--23. 1. "RESERVED" hexmask.long.byte 0xD8 16.--19. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xD8 12.--15. 1. "RESERVED" hexmask.long.byte 0xD8 8.--11. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xD8 4.--7. 1. "RESERVED" hexmask.long.byte 0xD8 0.--3. 1. "RESERVED,Reserved" line.long 0xDC "DDRSS_PI_75" hexmask.long.byte 0xDC 28.--31. 1. "RESERVED" hexmask.long.byte 0xDC 24.--27. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xDC 20.--23. 1. "RESERVED" hexmask.long.byte 0xDC 16.--19. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xDC 12.--15. 1. "RESERVED" hexmask.long.byte 0xDC 8.--11. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xDC 4.--7. 1. "RESERVED" hexmask.long.byte 0xDC 0.--3. 1. "RESERVED,Reserved" line.long 0xE0 "DDRSS_PI_76" hexmask.long.byte 0xE0 28.--31. 1. "RESERVED" hexmask.long.byte 0xE0 24.--27. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xE0 20.--23. 1. "RESERVED" hexmask.long.byte 0xE0 16.--19. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xE0 12.--15. 1. "RESERVED" hexmask.long.byte 0xE0 8.--11. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xE0 4.--7. 1. "RESERVED" hexmask.long.byte 0xE0 0.--3. 1. "RESERVED,Reserved" line.long 0xE4 "DDRSS_PI_77" hexmask.long.byte 0xE4 28.--31. 1. "RESERVED" hexmask.long.byte 0xE4 24.--27. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xE4 20.--23. 1. "RESERVED" hexmask.long.byte 0xE4 16.--19. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xE4 12.--15. 1. "RESERVED" hexmask.long.byte 0xE4 8.--11. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xE4 4.--7. 1. "RESERVED" hexmask.long.byte 0xE4 0.--3. 1. "RESERVED,Reserved" line.long 0xE8 "DDRSS_PI_78" hexmask.long.word 0xE8 20.--31. 1. "RESERVED" hexmask.long.byte 0xE8 16.--19. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xE8 12.--15. 1. "RESERVED" hexmask.long.byte 0xE8 8.--11. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xE8 4.--7. 1. "RESERVED" hexmask.long.byte 0xE8 0.--3. 1. "RESERVED,Reserved" rgroup.long 0x213C++0x3 line.long 0x0 "DDRSS_PI_79" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PI_INT_STATUS,Status of interrupt features in the PI." wgroup.long 0x2140++0x3 line.long 0x0 "DDRSS_PI_80" hexmask.long.byte 0x0 27.--31. 1. "RESERVED" hexmask.long 0x0 0.--26. 1. "PI_INT_ACK,Clear the corresponding interrupt bit of the PI_INT_STATUS parameter." group.long 0x2144++0x3 line.long 0x0 "DDRSS_PI_81" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PI_INT_MASK,Mask for PI_int signals from the PI_INT_STATUS parameter." rgroup.long 0x2148++0x23 line.long 0x0 "DDRSS_PI_82" hexmask.long 0x0 0.--31. 1. "PI_BIST_EXP_DATA_0,Expected data on BIST error." line.long 0x4 "DDRSS_PI_83" hexmask.long 0x4 0.--31. 1. "PI_BIST_EXP_DATA_1,Expected data on BIST error." line.long 0x8 "DDRSS_PI_84" hexmask.long 0x8 0.--31. 1. "PI_BIST_EXP_DATA_2,Expected data on BIST error." line.long 0xC "DDRSS_PI_85" hexmask.long 0xC 0.--31. 1. "PI_BIST_EXP_DATA_3,Expected data on BIST error." line.long 0x10 "DDRSS_PI_86" hexmask.long 0x10 0.--31. 1. "PI_BIST_FAIL_DATA_0,Actual data on BIST error." line.long 0x14 "DDRSS_PI_87" hexmask.long 0x14 0.--31. 1. "PI_BIST_FAIL_DATA_1,Actual data on BIST error." line.long 0x18 "DDRSS_PI_88" hexmask.long 0x18 0.--31. 1. "PI_BIST_FAIL_DATA_2,Actual data on BIST error." line.long 0x1C "DDRSS_PI_89" hexmask.long 0x1C 0.--31. 1. "PI_BIST_FAIL_DATA_3,Actual data on BIST error." line.long 0x20 "DDRSS_PI_90" hexmask.long 0x20 0.--31. 1. "PI_BIST_FAIL_ADDR_0,The burst aligned address of BIST error." group.long 0x216C++0xEF line.long 0x0 "DDRSS_PI_91" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "PI_CMD_SWAP_EN,Command pin swap function enable" "0,1" newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "PI_LONG_COUNT_MASK,Reduces the length of the long counter from 1024 cycles." newline bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "PI_BSTLEN,Encoded burst length sent to DRAMs during initialization." newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" rbitfld.long 0x0 0.--2. "PI_BIST_FAIL_ADDR_1,The burst aligned address of BIST error." "0,1,2,3,4,5,6,7" line.long 0x4 "DDRSS_PI_92" hexmask.long.byte 0x4 26.--31. 1. "RESERVED" bitfld.long 0x4 24.--25. "PI_DATA_BYTE_SWAP_SLICE2,DATA pin 2 mux selector" "0,1,2,3" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED" bitfld.long 0x4 16.--17. "PI_DATA_BYTE_SWAP_SLICE1,DATA pin 1 mux selector" "0,1,2,3" newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED" bitfld.long 0x4 8.--9. "PI_DATA_BYTE_SWAP_SLICE0,DATA pin 0 mux selector" "0,1,2,3" newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED" bitfld.long 0x4 0. "PI_DATA_BYTE_SWAP_EN,DATA pin swap function enable" "0,1" line.long 0x8 "DDRSS_PI_93" hexmask.long.byte 0x8 26.--31. 1. "RESERVED" rbitfld.long 0x8 24.--25. "PI_UPDATE_ERROR_STATUS,Identifies the source of any DFI PI-initiated update errors." "0,1,2,3" newline hexmask.long.byte 0x8 16.--23. 1. "PI_TDFI_CTRLUPD_MIN,Reports the DFI tCTRLUPD_MIN timing parameter (in DFI clocks) the minimum cycles that dfi_ctrlupd_req must be asserted." hexmask.long.byte 0x8 9.--15. 1. "RESERVED" newline bitfld.long 0x8 8. "PI_CTRLUPD_REQ_PER_AREF_EN,Enable an automatic PI initiated update (dfi_ctrlupd_req) after every refresh." "0,1" hexmask.long.byte 0x8 2.--7. 1. "RESERVED" newline bitfld.long 0x8 0.--1. "PI_DATA_BYTE_SWAP_SLICE3,DATA pin 3 mux selector" "0,1,2,3" line.long 0xC "DDRSS_PI_94" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "PI_BIST_DATA_CHECK,Enable data checking with BIST operation." "0,1" newline bitfld.long 0xC 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0xC 16.--21. 1. "PI_ADDR_SPACE,Sets the number of address bits to check during BIST operation." newline hexmask.long.byte 0xC 10.--15. 1. "RESERVED" rbitfld.long 0xC 8.--9. "PI_BIST_RESULT,BIST operation status (pass/fail)." "0,1,2,3" newline hexmask.long.byte 0xC 1.--7. 1. "RESERVED" bitfld.long 0xC 0. "PI_BIST_GO,Initiate a BIST operation." "0,1" line.long 0x10 "DDRSS_PI_95" hexmask.long 0x10 1.--31. 1. "RESERVED" bitfld.long 0x10 0. "PI_BIST_ADDR_CHECK,Enable address checking with BIST operation." "0,1" line.long 0x14 "DDRSS_PI_96" hexmask.long 0x14 0.--31. 1. "PI_BIST_START_ADDRESS_0,Start BIST checking at this address." line.long 0x18 "DDRSS_PI_97" hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.byte 0x18 8.--15. 1. "PI_MBIST_INIT_PATTERN,PI mbist data check random lfsr pattern mode init pattern seed." newline hexmask.long.byte 0x18 3.--7. 1. "RESERVED" bitfld.long 0x18 0.--2. "PI_BIST_START_ADDRESS_1,Start BIST checking at this address." "0,1,2,3,4,5,6,7" line.long 0x1C "DDRSS_PI_98" hexmask.long 0x1C 0.--31. 1. "PI_BIST_DATA_MASK_0,Mask applied to data for BIST error checking." line.long 0x20 "DDRSS_PI_99" hexmask.long 0x20 0.--31. 1. "PI_BIST_DATA_MASK_1,Mask applied to data for BIST error checking." line.long 0x24 "DDRSS_PI_100" hexmask.long.byte 0x24 28.--31. 1. "RESERVED" hexmask.long.word 0x24 16.--27. 1. "PI_BIST_ERR_STOP,Defines the maximum number of error occurrences allowed prior to quitting when the BIST_TEST_MODE parameter is set to 1 2 or 3." newline hexmask.long.byte 0x24 12.--15. 1. "RESERVED" hexmask.long.word 0x24 0.--11. 1. "PI_BIST_ERR_COUNT,Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is set to 1 2 or 3." line.long 0x28 "DDRSS_PI_101" hexmask.long 0x28 0.--31. 1. "PI_BIST_ADDR_MASK_0_0,Defines an address to be masked during the BIST operation.." line.long 0x2C "DDRSS_PI_102" hexmask.long 0x2C 4.--31. 1. "RESERVED" hexmask.long.byte 0x2C 0.--3. 1. "PI_BIST_ADDR_MASK_0_1,Defines an address to be masked during the BIST operation.." line.long 0x30 "DDRSS_PI_103" hexmask.long 0x30 0.--31. 1. "PI_BIST_ADDR_MASK_1_0,Defines an address to be masked during the BIST operation.." line.long 0x34 "DDRSS_PI_104" hexmask.long 0x34 4.--31. 1. "RESERVED" hexmask.long.byte 0x34 0.--3. 1. "PI_BIST_ADDR_MASK_1_1,Defines an address to be masked during the BIST operation.." line.long 0x38 "DDRSS_PI_105" hexmask.long 0x38 0.--31. 1. "PI_BIST_ADDR_MASK_2_0,Defines an address to be masked during the BIST operation.." line.long 0x3C "DDRSS_PI_106" hexmask.long 0x3C 4.--31. 1. "RESERVED" hexmask.long.byte 0x3C 0.--3. 1. "PI_BIST_ADDR_MASK_2_1,Defines an address to be masked during the BIST operation.." line.long 0x40 "DDRSS_PI_107" hexmask.long 0x40 0.--31. 1. "PI_BIST_ADDR_MASK_3_0,Defines an address to be masked during the BIST operation.." line.long 0x44 "DDRSS_PI_108" hexmask.long 0x44 4.--31. 1. "RESERVED" hexmask.long.byte 0x44 0.--3. 1. "PI_BIST_ADDR_MASK_3_1,Defines an address to be masked during the BIST operation.." line.long 0x48 "DDRSS_PI_109" hexmask.long 0x48 0.--31. 1. "PI_BIST_ADDR_MASK_4_0,Defines an address to be masked during the BIST operation.." line.long 0x4C "DDRSS_PI_110" hexmask.long 0x4C 4.--31. 1. "RESERVED" hexmask.long.byte 0x4C 0.--3. 1. "PI_BIST_ADDR_MASK_4_1,Defines an address to be masked during the BIST operation.." line.long 0x50 "DDRSS_PI_111" hexmask.long 0x50 0.--31. 1. "PI_BIST_ADDR_MASK_5_0,Defines an address to be masked during the BIST operation.." line.long 0x54 "DDRSS_PI_112" hexmask.long 0x54 4.--31. 1. "RESERVED" hexmask.long.byte 0x54 0.--3. 1. "PI_BIST_ADDR_MASK_5_1,Defines an address to be masked during the BIST operation.." line.long 0x58 "DDRSS_PI_113" hexmask.long 0x58 0.--31. 1. "PI_BIST_ADDR_MASK_6_0,Defines an address to be masked during the BIST operation.." line.long 0x5C "DDRSS_PI_114" hexmask.long 0x5C 4.--31. 1. "RESERVED" hexmask.long.byte 0x5C 0.--3. 1. "PI_BIST_ADDR_MASK_6_1,Defines an address to be masked during the BIST operation.." line.long 0x60 "DDRSS_PI_115" hexmask.long 0x60 0.--31. 1. "PI_BIST_ADDR_MASK_7_0,Defines an address to be masked during the BIST operation.." line.long 0x64 "DDRSS_PI_116" hexmask.long 0x64 4.--31. 1. "RESERVED" hexmask.long.byte 0x64 0.--3. 1. "PI_BIST_ADDR_MASK_7_1,Defines an address to be masked during the BIST operation.." line.long 0x68 "DDRSS_PI_117" hexmask.long 0x68 0.--31. 1. "PI_BIST_ADDR_MASK_8_0,Defines an address to be masked during the BIST operation.." line.long 0x6C "DDRSS_PI_118" hexmask.long 0x6C 4.--31. 1. "RESERVED" hexmask.long.byte 0x6C 0.--3. 1. "PI_BIST_ADDR_MASK_8_1,Defines an address to be masked during the BIST operation.." line.long 0x70 "DDRSS_PI_119" hexmask.long 0x70 0.--31. 1. "PI_BIST_ADDR_MASK_9_0,Defines an address to be masked during the BIST operation.." line.long 0x74 "DDRSS_PI_120" hexmask.long.byte 0x74 26.--31. 1. "RESERVED" bitfld.long 0x74 24.--25. "PI_BIST_PAT_MODE,Sets the pattern mode of BIST." "0,1,2,3" newline hexmask.long.byte 0x74 18.--23. 1. "RESERVED" bitfld.long 0x74 16.--17. "PI_BIST_ADDR_MODE,Sets the address traversing order of BIST." "0,1,2,3" newline hexmask.long.byte 0x74 11.--15. 1. "RESERVED" bitfld.long 0x74 8.--10. "PI_BIST_MODE,Sets the BIST data checking mode." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x74 4.--7. 1. "RESERVED" hexmask.long.byte 0x74 0.--3. 1. "PI_BIST_ADDR_MASK_9_1,Defines an address to be masked during the BIST operation.." line.long 0x78 "DDRSS_PI_121" hexmask.long 0x78 0.--31. 1. "PI_BIST_USER_PAT_0,Sets the user-specified pattern of BIST." line.long 0x7C "DDRSS_PI_122" hexmask.long 0x7C 0.--31. 1. "PI_BIST_USER_PAT_1,Sets the user-specified pattern of BIST." line.long 0x80 "DDRSS_PI_123" hexmask.long 0x80 0.--31. 1. "PI_BIST_USER_PAT_2,Sets the user-specified pattern of BIST." line.long 0x84 "DDRSS_PI_124" hexmask.long 0x84 0.--31. 1. "PI_BIST_USER_PAT_3,Sets the user-specified pattern of BIST." line.long 0x88 "DDRSS_PI_125" hexmask.long 0x88 4.--31. 1. "RESERVED" hexmask.long.byte 0x88 0.--3. 1. "PI_BIST_PAT_NUM,Sets the max used pattern number of BIST from a total of 8 built-in patterns." line.long 0x8C "DDRSS_PI_126" bitfld.long 0x8C 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0x8C 0.--29. 1. "PI_BIST_STAGE_0,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4." line.long 0x90 "DDRSS_PI_127" bitfld.long 0x90 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0x90 0.--29. 1. "PI_BIST_STAGE_1,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4." line.long 0x94 "DDRSS_PI_128" bitfld.long 0x94 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0x94 0.--29. 1. "PI_BIST_STAGE_2,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4." line.long 0x98 "DDRSS_PI_129" bitfld.long 0x98 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0x98 0.--29. 1. "PI_BIST_STAGE_3,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4." line.long 0x9C "DDRSS_PI_130" bitfld.long 0x9C 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0x9C 0.--29. 1. "PI_BIST_STAGE_4,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4." line.long 0xA0 "DDRSS_PI_131" bitfld.long 0xA0 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0xA0 0.--29. 1. "PI_BIST_STAGE_5,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4." line.long 0xA4 "DDRSS_PI_132" bitfld.long 0xA4 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0xA4 0.--29. 1. "PI_BIST_STAGE_6,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4." line.long 0xA8 "DDRSS_PI_133" bitfld.long 0xA8 30.--31. "RESERVED" "0,1,2,3" hexmask.long 0xA8 0.--29. 1. "PI_BIST_STAGE_7,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4." line.long 0xAC "DDRSS_PI_134" hexmask.long.byte 0xAC 25.--31. 1. "RESERVED" bitfld.long 0xAC 24. "PI_SREFRESH_EXIT_NO_REFRESH,Disables the automatic refresh request associated with self-refresh exit." "0,1" newline hexmask.long.byte 0xAC 17.--23. 1. "RESERVED" bitfld.long 0xAC 16. "PI_PWRUP_SREFRESH_EXIT,Allow powerup via self-refresh instead of full memory initialization." "0,1" newline hexmask.long.byte 0xAC 9.--15. 1. "RESERVED" bitfld.long 0xAC 8. "PI_SELF_REFRESH_EN,Control for PI to enable self refresh mode." "0,1" newline hexmask.long.byte 0xAC 4.--7. 1. "RESERVED" hexmask.long.byte 0xAC 0.--3. 1. "PI_COL_DIFF,Difference between number of column pins available and number being used." line.long 0xB0 "DDRSS_PI_135" hexmask.long.byte 0xB0 25.--31. 1. "RESERVED" bitfld.long 0xB0 24. "PI_NO_PHY_IND_TRAIN_INIT,Disable PHY Independent Training during initialization." "0,1" newline hexmask.long.byte 0xB0 17.--23. 1. "RESERVED" bitfld.long 0xB0 16. "PI_NO_MRW_INIT,Disable MRW commands after training during initialization." "0,1" newline hexmask.long.byte 0xB0 9.--15. 1. "RESERVED" bitfld.long 0xB0 8. "PI_NO_MRW_BT_INIT,Disable MRW commands before training during initialization." "0,1" newline hexmask.long.byte 0xB0 1.--7. 1. "RESERVED" bitfld.long 0xB0 0. "PI_SREF_ENTRY_REQ,In PI power up data retention PI can issued sref entry command." "0,1" line.long 0xB4 "DDRSS_PI_136" hexmask.long 0xB4 1.--31. 1. "RESERVED" bitfld.long 0xB4 0. "PI_NO_AUTO_MRR_INIT,Disable MRR commands during initialization." "0,1" line.long 0xB8 "DDRSS_PI_137" hexmask.long 0xB8 0.--31. 1. "PI_TRST_PWRON,Duration of memory reset during power-on initialization." line.long 0xBC "DDRSS_PI_138" hexmask.long 0xBC 0.--31. 1. "PI_CKE_INACTIVE,Number of cycles after reset before CKE will be active." line.long 0xC0 "DDRSS_PI_139" hexmask.long.word 0xC0 16.--31. 1. "PI_DLL_RST_DELAY,Minimum cycles required for DLL reset signal dll_rst_n to be held." hexmask.long.byte 0xC0 9.--15. 1. "RESERVED" newline bitfld.long 0xC0 8. "PI_DRAM_INIT_EN,Control for the initialization of DRAM by the PI." "0,1" hexmask.long.byte 0xC0 1.--7. 1. "RESERVED" newline bitfld.long 0xC0 0. "PI_DLL_RST,Enables use of the DLL reset (dll_rst_n)." "0,1" line.long 0xC4 "DDRSS_PI_140" hexmask.long.tbyte 0xC4 8.--31. 1. "RESERVED" hexmask.long.byte 0xC4 0.--7. 1. "PI_DLL_RST_ADJ_DLY,Minimum cycles after setting master delay in DLL until the DLL reset signal dll_rst_n may be asserted." line.long 0xC8 "DDRSS_PI_141" hexmask.long.byte 0xC8 26.--31. 1. "RESERVED" hexmask.long 0xC8 0.--25. 1. "PI_WRITE_MODEREG,Write memory mode register data to the DRAMs." line.long 0xCC "DDRSS_PI_142" hexmask.long.byte 0xCC 25.--31. 1. "RESERVED" hexmask.long.tbyte 0xCC 8.--24. 1. "PI_READ_MODEREG,Read the specified memory mode register from specified chip when start bit set." newline hexmask.long.byte 0xCC 0.--7. 1. "PI_MRW_STATUS,Write memory mode register status." line.long 0xD0 "DDRSS_PI_143" hexmask.long.byte 0xD0 25.--31. 1. "RESERVED" bitfld.long 0xD0 24. "PI_NO_ZQ_INIT,Disable ZQ operations during initialization." "0,1" newline hexmask.long.tbyte 0xD0 0.--23. 1. "PI_PERIPHERAL_MRR_DATA_0,Data and chip returned from memory mode register read requested by the READ_MODEREG parameter Bits (" line.long 0xD4 "DDRSS_PI_144" hexmask.long.byte 0xD4 25.--31. 1. "RESERVED" bitfld.long 0xD4 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xD4 17.--23. 1. "RESERVED" rbitfld.long 0xD4 16. "PI_ZQ_REQ_PENDING,Indicates that a ZQ command is currently in progress or waiting to run." "0,1" newline hexmask.long.byte 0xD4 12.--15. 1. "RESERVED" hexmask.long.byte 0xD4 8.--11. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xD4 4.--7. 1. "RESERVED" hexmask.long.byte 0xD4 0.--3. 1. "RESERVED,Reserved" line.long 0xD8 "DDRSS_PI_145" hexmask.long.byte 0xD8 24.--31. 1. "PI_MONITOR_0,Monitor register 0." hexmask.long.byte 0xD8 17.--23. 1. "RESERVED" newline bitfld.long 0xD8 16. "PI_MONITOR_CAP_SEL_0,Selection of captures for pi_monitor_0." "0,1" hexmask.long.byte 0xD8 12.--15. 1. "RESERVED" newline hexmask.long.byte 0xD8 8.--11. 1. "PI_MONITOR_SRC_SEL_0,Selection of sources for pi_monitor_0." hexmask.long.byte 0xD8 3.--7. 1. "RESERVED" newline bitfld.long 0xD8 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" line.long 0xDC "DDRSS_PI_146" hexmask.long.byte 0xDC 28.--31. 1. "RESERVED" hexmask.long.byte 0xDC 24.--27. 1. "PI_MONITOR_SRC_SEL_2,Selection of sources for pi_monitor_2." newline hexmask.long.byte 0xDC 16.--23. 1. "PI_MONITOR_1,Monitor register 1." hexmask.long.byte 0xDC 9.--15. 1. "RESERVED" newline bitfld.long 0xDC 8. "PI_MONITOR_CAP_SEL_1,Selection of captures for pi_monitor_1." "0,1" hexmask.long.byte 0xDC 4.--7. 1. "RESERVED" newline hexmask.long.byte 0xDC 0.--3. 1. "PI_MONITOR_SRC_SEL_1,Selection of sources for pi_monitor_1." line.long 0xE0 "DDRSS_PI_147" hexmask.long.byte 0xE0 25.--31. 1. "RESERVED" bitfld.long 0xE0 24. "PI_MONITOR_CAP_SEL_3,Selection of captures for pi_monitor_3." "0,1" newline hexmask.long.byte 0xE0 20.--23. 1. "RESERVED" hexmask.long.byte 0xE0 16.--19. 1. "PI_MONITOR_SRC_SEL_3,Selection of sources for pi_monitor_3." newline hexmask.long.byte 0xE0 8.--15. 1. "PI_MONITOR_2,Monitor register 2." hexmask.long.byte 0xE0 1.--7. 1. "RESERVED" newline bitfld.long 0xE0 0. "PI_MONITOR_CAP_SEL_2,Selection of captures for pi_monitor_2." "0,1" line.long 0xE4 "DDRSS_PI_148" hexmask.long.byte 0xE4 24.--31. 1. "PI_MONITOR_4,Monitor register 4." hexmask.long.byte 0xE4 17.--23. 1. "RESERVED" newline bitfld.long 0xE4 16. "PI_MONITOR_CAP_SEL_4,Selection of captures for pi_monitor_4." "0,1" hexmask.long.byte 0xE4 12.--15. 1. "RESERVED" newline hexmask.long.byte 0xE4 8.--11. 1. "PI_MONITOR_SRC_SEL_4,Selection of sources for pi_monitor_4." hexmask.long.byte 0xE4 0.--7. 1. "PI_MONITOR_3,Monitor register 3." line.long 0xE8 "DDRSS_PI_149" hexmask.long.byte 0xE8 28.--31. 1. "RESERVED" hexmask.long.byte 0xE8 24.--27. 1. "PI_MONITOR_SRC_SEL_6,Selection of sources for pi_monitor_6." newline hexmask.long.byte 0xE8 16.--23. 1. "PI_MONITOR_5,Monitor register 5." hexmask.long.byte 0xE8 9.--15. 1. "RESERVED" newline bitfld.long 0xE8 8. "PI_MONITOR_CAP_SEL_5,Selection of captures for pi_monitor_5." "0,1" hexmask.long.byte 0xE8 4.--7. 1. "RESERVED" newline hexmask.long.byte 0xE8 0.--3. 1. "PI_MONITOR_SRC_SEL_5,Selection of sources for pi_monitor_5." line.long 0xEC "DDRSS_PI_150" hexmask.long.byte 0xEC 25.--31. 1. "RESERVED" bitfld.long 0xEC 24. "PI_MONITOR_CAP_SEL_7,Selection of captures for pi_monitor_7." "0,1" newline hexmask.long.byte 0xEC 20.--23. 1. "RESERVED" hexmask.long.byte 0xEC 16.--19. 1. "PI_MONITOR_SRC_SEL_7,Selection of sources for pi_monitor_7." newline hexmask.long.byte 0xEC 8.--15. 1. "PI_MONITOR_6,Monitor register 6." hexmask.long.byte 0xEC 1.--7. 1. "RESERVED" newline bitfld.long 0xEC 0. "PI_MONITOR_CAP_SEL_6,Selection of captures for pi_monitor_6." "0,1" rgroup.long 0x225C++0x3 line.long 0x0 "DDRSS_PI_151" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "PI_MONITOR_7,Monitor register 7." wgroup.long 0x2260++0x3 line.long 0x0 "DDRSS_PI_152" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "PI_MONITOR_STROBE,Strobe the pi_monitor once." group.long 0x2264++0x24B line.long 0x0 "DDRSS_PI_153" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "PI_FREQ_RETENTION_NUM,Monitor active freq number in PI for data_retention" newline bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "PI_FREQ_NUMBER_STATUS,Monitor active freq number in PI." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" rbitfld.long 0x0 0. "PI_DLL_LOCK,Monitor dfi_init_complete from PHY." "0,1" line.long 0x4 "DDRSS_PI_154" hexmask.long.byte 0x4 25.--31. 1. "RESERVED" bitfld.long 0x4 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 17.--23. 1. "RESERVED" bitfld.long 0x4 16. "PI_POWER_REDUC_EN,PI Power reduction enable " "0,1" newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" bitfld.long 0x4 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" bitfld.long 0x4 0.--1. "PI_PHYMSTR_TYPE,Defines how the controller should set the state of DRAM before turning control of the DFI bus over to the PI." "0,1,2,3" line.long 0x8 "DDRSS_PI_155" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x8 17.--23. 1. "RESERVED" bitfld.long 0x8 16. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x8 9.--15. 1. "RESERVED" bitfld.long 0x8 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x8 1.--7. 1. "RESERVED" bitfld.long 0x8 0. "RESERVED,Reserved" "0,1" line.long 0xC "DDRSS_PI_156" hexmask.long.byte 0xC 25.--31. 1. "RESERVED" bitfld.long 0xC 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xC 17.--23. 1. "RESERVED" bitfld.long 0xC 16. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xC 9.--15. 1. "RESERVED" bitfld.long 0xC 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0xC 1.--7. 1. "RESERVED" bitfld.long 0xC 0. "RESERVED,Reserved" "0,1" line.long 0x10 "DDRSS_PI_157" hexmask.long.byte 0x10 25.--31. 1. "RESERVED" bitfld.long 0x10 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x10 17.--23. 1. "RESERVED" bitfld.long 0x10 16. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x10 9.--15. 1. "RESERVED" bitfld.long 0x10 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x10 1.--7. 1. "RESERVED" bitfld.long 0x10 0. "RESERVED,Reserved" "0,1" line.long 0x14 "DDRSS_PI_158" hexmask.long.byte 0x14 25.--31. 1. "RESERVED" bitfld.long 0x14 24. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x14 17.--23. 1. "RESERVED" bitfld.long 0x14 16. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x14 9.--15. 1. "RESERVED" bitfld.long 0x14 8. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x14 1.--7. 1. "RESERVED" bitfld.long 0x14 0. "RESERVED,Reserved" "0,1" line.long 0x18 "DDRSS_PI_159" hexmask.long.word 0x18 17.--31. 1. "RESERVED" hexmask.long.word 0x18 8.--16. 1. "PI_TREFBW_THR,Threshold value to control the AREF command interval." newline hexmask.long.byte 0x18 0.--7. 1. "PI_WRLVL_MAX_STROBE_PEND,Defines the maximum number of wrlvl_strobes that be accumulated before an AREF is prevented from being generated." line.long 0x1C "DDRSS_PI_160" hexmask.long 0x1C 5.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--4. 1. "PI_FREQ_CHANGE_REG_COPY,In non-DFI 4.0 mode contains the frequency copy value." line.long 0x20 "DDRSS_PI_161" hexmask.long.byte 0x20 28.--31. 1. "RESERVED" hexmask.long.byte 0x20 24.--27. 1. "PI_CATR,It indicates LP4 DRAM CA terminition ON/OFF state." newline hexmask.long.byte 0x20 17.--23. 1. "RESERVED" bitfld.long 0x20 16. "PI_PARALLEL_CALVL_EN,Enable parallel channel CA training for LPDDR4." "0,1" newline bitfld.long 0x20 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 8.--12. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x20 1.--7. 1. "RESERVED" bitfld.long 0x20 0. "PI_FREQ_SEL_FROM_REGIF,In non-DFI 4.0 mode user select the frequency copies from pi_freq_change_reg_copy." "0,1" line.long 0x24 "DDRSS_PI_162" hexmask.long.byte 0x24 25.--31. 1. "RESERVED" bitfld.long 0x24 24. "PI_NOTCARE_MC_INIT_START,Defines whether PI waits for the controller to initiate dfi_init_start before PI memory initialization " "0,1" newline hexmask.long.byte 0x24 17.--23. 1. "RESERVED" bitfld.long 0x24 16. "PI_DISCONNECT_MC,PI disconnects the controller from the PHY " "0,1" newline hexmask.long.byte 0x24 9.--15. 1. "RESERVED" bitfld.long 0x24 8. "PI_MASK_INIT_COMPLETE,Enable the masking of the dfi_init_complete signal back to the controller " "0,1" newline hexmask.long.byte 0x24 1.--7. 1. "RESERVED" bitfld.long 0x24 0. "PI_NO_CATR_READ,Defines how the LPDDR4 termination status is determined." "0,1" line.long 0x28 "DDRSS_PI_163" hexmask.long.byte 0x28 24.--31. 1. "PI_TSDO_F2,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 2 in PI clocks" hexmask.long.byte 0x28 16.--23. 1. "PI_TSDO_F1,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 1 in PI clocks" newline hexmask.long.byte 0x28 8.--15. 1. "PI_TSDO_F0,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 0 in PI clocks" hexmask.long.byte 0x28 1.--7. 1. "RESERVED" newline bitfld.long 0x28 0. "PI_TRACE_MC_MR13,Defines whether PI monitors controller mr13 mrw or not." "0,1" line.long 0x2C "DDRSS_PI_164" hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED" hexmask.long.byte 0x2C 0.--7. 1. "PI_TDELAY_RDWR_2_BUS_IDLE_F0,The delay from read or write to bus idle for frequency set 0." line.long 0x30 "DDRSS_PI_165" hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED" hexmask.long.byte 0x30 0.--7. 1. "PI_TDELAY_RDWR_2_BUS_IDLE_F1,The delay from read or write to bus idle for frequency set 1." line.long 0x34 "DDRSS_PI_166" hexmask.long.word 0x34 20.--31. 1. "RESERVED" hexmask.long.word 0x34 8.--19. 1. "PI_ZQINIT_F0,Number of cycles needed for a ZQINIT command for frequency set 0." newline hexmask.long.byte 0x34 0.--7. 1. "PI_TDELAY_RDWR_2_BUS_IDLE_F2,The delay from read or write to bus idle for frequency set 2." line.long 0x38 "DDRSS_PI_167" hexmask.long.byte 0x38 28.--31. 1. "RESERVED" hexmask.long.word 0x38 16.--27. 1. "PI_ZQINIT_F2,Number of cycles needed for a ZQINIT command for frequency set 2." newline hexmask.long.byte 0x38 12.--15. 1. "RESERVED" hexmask.long.word 0x38 0.--11. 1. "PI_ZQINIT_F1,Number of cycles needed for a ZQINIT command for frequency set 1." line.long 0x3C "DDRSS_PI_168" bitfld.long 0x3C 31. "RESERVED" "0,1" hexmask.long.byte 0x3C 24.--30. 1. "PI_CASLAT_LIN_F1,Sets latency from read command sent to data received from/to controller for frequency set 1." newline bitfld.long 0x3C 23. "RESERVED" "0,1" hexmask.long.byte 0x3C 16.--22. 1. "PI_WRLAT_F1,DRAM WRLAT value in cycles for frequency set 1." newline bitfld.long 0x3C 15. "RESERVED" "0,1" hexmask.long.byte 0x3C 8.--14. 1. "PI_CASLAT_LIN_F0,Sets latency from read command sent to data received from/to controller for frequency set 0." newline bitfld.long 0x3C 7. "RESERVED" "0,1" hexmask.long.byte 0x3C 0.--6. 1. "PI_WRLAT_F0,DRAM WRLAT value in cycles for frequency set 0." line.long 0x40 "DDRSS_PI_169" hexmask.long.byte 0x40 26.--31. 1. "RESERVED" hexmask.long.word 0x40 16.--25. 1. "PI_TRFC_F0,DRAM tRFC value in memory clocks for frequency set 0." newline bitfld.long 0x40 15. "RESERVED" "0,1" hexmask.long.byte 0x40 8.--14. 1. "PI_CASLAT_LIN_F2,Sets latency from read command sent to data received from/to controller for frequency set 2." newline bitfld.long 0x40 7. "RESERVED" "0,1" hexmask.long.byte 0x40 0.--6. 1. "PI_WRLAT_F2,DRAM WRLAT value in cycles for frequency set 2." line.long 0x44 "DDRSS_PI_170" hexmask.long.word 0x44 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x44 0.--19. 1. "PI_TREF_F0,DRAM tREF value in memory clocks for frequency set 0." line.long 0x48 "DDRSS_PI_171" hexmask.long.tbyte 0x48 10.--31. 1. "RESERVED" hexmask.long.word 0x48 0.--9. 1. "PI_TRFC_F1,DRAM tRFC value in memory clocks for frequency set 1." line.long 0x4C "DDRSS_PI_172" hexmask.long.word 0x4C 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x4C 0.--19. 1. "PI_TREF_F1,DRAM tREF value in memory clocks for frequency set 1." line.long 0x50 "DDRSS_PI_173" hexmask.long.tbyte 0x50 10.--31. 1. "RESERVED" hexmask.long.word 0x50 0.--9. 1. "PI_TRFC_F2,DRAM tRFC value in memory clocks for frequency set 2." line.long 0x54 "DDRSS_PI_174" hexmask.long.byte 0x54 28.--31. 1. "RESERVED" hexmask.long.byte 0x54 24.--27. 1. "PI_TDFI_CTRL_DELAY_F0,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 0 the delay between a DFI command change and a memory command." newline hexmask.long.byte 0x54 20.--23. 1. "RESERVED" hexmask.long.tbyte 0x54 0.--19. 1. "PI_TREF_F2,DRAM tREF value in memory clocks for frequency set 2." line.long 0x58 "DDRSS_PI_175" hexmask.long.byte 0x58 26.--31. 1. "RESERVED" bitfld.long 0x58 24.--25. "PI_WRLVL_EN_F1,Enable the PI write leveling module for frequency set 1." "0,1,2,3" newline hexmask.long.byte 0x58 18.--23. 1. "RESERVED" bitfld.long 0x58 16.--17. "PI_WRLVL_EN_F0,Enable the PI write leveling module for frequency set 0." "0,1,2,3" newline hexmask.long.byte 0x58 12.--15. 1. "RESERVED" hexmask.long.byte 0x58 8.--11. 1. "PI_TDFI_CTRL_DELAY_F2,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 2 the delay between a DFI command change and a memory command." newline hexmask.long.byte 0x58 4.--7. 1. "RESERVED" hexmask.long.byte 0x58 0.--3. 1. "PI_TDFI_CTRL_DELAY_F1,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 1 the delay between a DFI command change and a memory command." line.long 0x5C "DDRSS_PI_176" hexmask.long.word 0x5C 18.--31. 1. "RESERVED" hexmask.long.word 0x5C 8.--17. 1. "PI_TDFI_WRLVL_WW_F0,Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 0 the minimum cycles between dfi_wrlvl_strobe assertions." newline hexmask.long.byte 0x5C 2.--7. 1. "RESERVED" bitfld.long 0x5C 0.--1. "PI_WRLVL_EN_F2,Enable the PI write leveling module for frequency set 2." "0,1,2,3" line.long 0x60 "DDRSS_PI_177" hexmask.long.byte 0x60 26.--31. 1. "RESERVED" hexmask.long.word 0x60 16.--25. 1. "PI_TDFI_WRLVL_WW_F2,Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 2 the minimum cycles between dfi_wrlvl_strobe assertions." newline hexmask.long.byte 0x60 10.--15. 1. "RESERVED" hexmask.long.word 0x60 0.--9. 1. "PI_TDFI_WRLVL_WW_F1,Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 1 the minimum cycles between dfi_wrlvl_strobe assertions." line.long 0x64 "DDRSS_PI_178" hexmask.long.byte 0x64 25.--31. 1. "RESERVED" bitfld.long 0x64 24. "PI_ODT_EN_F1,Enable support of DRAM ODT." "0,1" newline hexmask.long.byte 0x64 16.--23. 1. "PI_TODTL_2CMD_F1,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command for frequency set 1." hexmask.long.byte 0x64 9.--15. 1. "RESERVED" newline bitfld.long 0x64 8. "PI_ODT_EN_F0,Enable support of DRAM ODT." "0,1" hexmask.long.byte 0x64 0.--7. 1. "PI_TODTL_2CMD_F0,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command for frequency set 0." line.long 0x68 "DDRSS_PI_179" hexmask.long.byte 0x68 28.--31. 1. "RESERVED" hexmask.long.byte 0x68 24.--27. 1. "PI_TODTON_MIN_F0,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 0." newline hexmask.long.byte 0x68 20.--23. 1. "RESERVED" hexmask.long.byte 0x68 16.--19. 1. "PI_ODTLON_F0,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 0." newline hexmask.long.byte 0x68 9.--15. 1. "RESERVED" bitfld.long 0x68 8. "PI_ODT_EN_F2,Enable support of DRAM ODT." "0,1" newline hexmask.long.byte 0x68 0.--7. 1. "PI_TODTL_2CMD_F2,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command for frequency set 2." line.long 0x6C "DDRSS_PI_180" hexmask.long.byte 0x6C 28.--31. 1. "RESERVED" hexmask.long.byte 0x6C 24.--27. 1. "PI_TODTON_MIN_F2,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 2." newline hexmask.long.byte 0x6C 20.--23. 1. "RESERVED" hexmask.long.byte 0x6C 16.--19. 1. "PI_ODTLON_F2,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 2." newline hexmask.long.byte 0x6C 12.--15. 1. "RESERVED" hexmask.long.byte 0x6C 8.--11. 1. "PI_TODTON_MIN_F1,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 1." newline hexmask.long.byte 0x6C 4.--7. 1. "RESERVED" hexmask.long.byte 0x6C 0.--3. 1. "PI_ODTLON_F1,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 1." line.long 0x70 "DDRSS_PI_181" hexmask.long.byte 0x70 26.--31. 1. "RESERVED" bitfld.long 0x70 24.--25. "PI_RDLVL_GATE_EN_F1,Enable the PI gate training module for frequency set 1." "0,1,2,3" newline hexmask.long.byte 0x70 18.--23. 1. "RESERVED" bitfld.long 0x70 16.--17. "PI_RDLVL_EN_F1,Enable the PI data eye training module for frequency set 1." "0,1,2,3" newline hexmask.long.byte 0x70 10.--15. 1. "RESERVED" bitfld.long 0x70 8.--9. "PI_RDLVL_GATE_EN_F0,Enable the PI gate training module for frequency set 0." "0,1,2,3" newline hexmask.long.byte 0x70 2.--7. 1. "RESERVED" bitfld.long 0x70 0.--1. "PI_RDLVL_EN_F0,Enable the PI data eye training module for frequency set 0." "0,1,2,3" line.long 0x74 "DDRSS_PI_182" hexmask.long.byte 0x74 26.--31. 1. "RESERVED" bitfld.long 0x74 24.--25. "PI_RDLVL_RXCAL_EN_F0,Enable RX Offset calibration (PATTERN 14 15) for read training for frequency set 0." "0,1,2,3" newline hexmask.long.byte 0x74 18.--23. 1. "RESERVED" bitfld.long 0x74 16.--17. "PI_RDLVL_PAT0_EN_F0,Enable PATTERN-0 for read training for frequency set 0." "0,1,2,3" newline hexmask.long.byte 0x74 10.--15. 1. "RESERVED" bitfld.long 0x74 8.--9. "PI_RDLVL_GATE_EN_F2,Enable the PI gate training module for frequency set 2." "0,1,2,3" newline hexmask.long.byte 0x74 2.--7. 1. "RESERVED" bitfld.long 0x74 0.--1. "PI_RDLVL_EN_F2,Enable the PI data eye training module for frequency set 2." "0,1,2,3" line.long 0x78 "DDRSS_PI_183" hexmask.long.byte 0x78 26.--31. 1. "RESERVED" bitfld.long 0x78 24.--25. "PI_RDLVL_RXCAL_EN_F1,Enable RX Offset calibration (PATTERN 14 15) for read training for frequency set 1." "0,1,2,3" newline hexmask.long.byte 0x78 18.--23. 1. "RESERVED" bitfld.long 0x78 16.--17. "PI_RDLVL_PAT0_EN_F1,Enable PATTERN-0 for read training for frequency set 1." "0,1,2,3" newline hexmask.long.byte 0x78 10.--15. 1. "RESERVED" bitfld.long 0x78 8.--9. "PI_RDLVL_MULTI_EN_F0,Enable Multi-pattern (from PI_RDLVL_PATTERN_START total PI_RDLVL_PATTERN_NUM) for read training for frequency set 0." "0,1,2,3" newline hexmask.long.byte 0x78 2.--7. 1. "RESERVED" bitfld.long 0x78 0.--1. "PI_RDLVL_DFE_EN_F0,Enable DFE (PATTERN 8 9) for read training for frequency set 0." "0,1,2,3" line.long 0x7C "DDRSS_PI_184" hexmask.long.byte 0x7C 26.--31. 1. "RESERVED" bitfld.long 0x7C 24.--25. "PI_RDLVL_RXCAL_EN_F2,Enable RX Offset calibration (PATTERN 14 15) for read training for frequency set 2." "0,1,2,3" newline hexmask.long.byte 0x7C 18.--23. 1. "RESERVED" bitfld.long 0x7C 16.--17. "PI_RDLVL_PAT0_EN_F2,Enable PATTERN-0 for read training for frequency set 2." "0,1,2,3" newline hexmask.long.byte 0x7C 10.--15. 1. "RESERVED" bitfld.long 0x7C 8.--9. "PI_RDLVL_MULTI_EN_F1,Enable Multi-pattern (from PI_RDLVL_PATTERN_START total PI_RDLVL_PATTERN_NUM) for read training for frequency set 1." "0,1,2,3" newline hexmask.long.byte 0x7C 2.--7. 1. "RESERVED" bitfld.long 0x7C 0.--1. "PI_RDLVL_DFE_EN_F1,Enable DFE (PATTERN 8 9) for read training for frequency set 1." "0,1,2,3" line.long 0x80 "DDRSS_PI_185" bitfld.long 0x80 31. "RESERVED" "0,1" hexmask.long.byte 0x80 24.--30. 1. "PI_RDLAT_ADJ_F1,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 1." newline bitfld.long 0x80 23. "RESERVED" "0,1" hexmask.long.byte 0x80 16.--22. 1. "PI_RDLAT_ADJ_F0,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 0." newline hexmask.long.byte 0x80 10.--15. 1. "RESERVED" bitfld.long 0x80 8.--9. "PI_RDLVL_MULTI_EN_F2,Enable Multi-pattern (from PI_RDLVL_PATTERN_START total PI_RDLVL_PATTERN_NUM) for read training for frequency set 2." "0,1,2,3" newline hexmask.long.byte 0x80 2.--7. 1. "RESERVED" bitfld.long 0x80 0.--1. "PI_RDLVL_DFE_EN_F2,Enable DFE (PATTERN 8 9) for read training for frequency set 2." "0,1,2,3" line.long 0x84 "DDRSS_PI_186" bitfld.long 0x84 31. "RESERVED" "0,1" hexmask.long.byte 0x84 24.--30. 1. "PI_WRLAT_ADJ_F2,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 2." newline bitfld.long 0x84 23. "RESERVED" "0,1" hexmask.long.byte 0x84 16.--22. 1. "PI_WRLAT_ADJ_F1,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 1." newline bitfld.long 0x84 15. "RESERVED" "0,1" hexmask.long.byte 0x84 8.--14. 1. "PI_WRLAT_ADJ_F0,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 0." newline bitfld.long 0x84 7. "RESERVED" "0,1" hexmask.long.byte 0x84 0.--6. 1. "PI_RDLAT_ADJ_F2,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 2." line.long 0x88 "DDRSS_PI_187" hexmask.long.word 0x88 19.--31. 1. "RESERVED" bitfld.long 0x88 16.--18. "PI_TDFI_PHY_WRDATA_F2,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 2 the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x88 11.--15. 1. "RESERVED" bitfld.long 0x88 8.--10. "PI_TDFI_PHY_WRDATA_F1,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 1 the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x88 3.--7. 1. "RESERVED" bitfld.long 0x88 0.--2. "PI_TDFI_PHY_WRDATA_F0,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 0 the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal." "0,1,2,3,4,5,6,7" line.long 0x8C "DDRSS_PI_188" hexmask.long.byte 0x8C 26.--31. 1. "RESERVED" hexmask.long.word 0x8C 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F0,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 0 the minimum cycles between a calibration command and a dfi_calvl_capture pulse." newline hexmask.long.byte 0x8C 10.--15. 1. "RESERVED" hexmask.long.word 0x8C 0.--9. 1. "PI_TDFI_CALVL_CC_F0,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 0 the minimum cycles between calibration commands." line.long 0x90 "DDRSS_PI_189" hexmask.long.byte 0x90 26.--31. 1. "RESERVED" hexmask.long.word 0x90 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F1,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 1 the minimum cycles between a calibration command and a dfi_calvl_capture pulse." newline hexmask.long.byte 0x90 10.--15. 1. "RESERVED" hexmask.long.word 0x90 0.--9. 1. "PI_TDFI_CALVL_CC_F1,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 1 the minimum cycles between calibration commands." line.long 0x94 "DDRSS_PI_190" hexmask.long.byte 0x94 26.--31. 1. "RESERVED" hexmask.long.word 0x94 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F2,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 2 the minimum cycles between a calibration command and a dfi_calvl_capture pulse." newline hexmask.long.byte 0x94 10.--15. 1. "RESERVED" hexmask.long.word 0x94 0.--9. 1. "PI_TDFI_CALVL_CC_F2,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 2 the minimum cycles between calibration commands." line.long 0x98 "DDRSS_PI_191" bitfld.long 0x98 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x98 24.--28. 1. "PI_TMRZ_F0,Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 0." newline hexmask.long.byte 0x98 18.--23. 1. "RESERVED" bitfld.long 0x98 16.--17. "PI_CALVL_EN_F2,Enable the PI CA training module." "0,1,2,3" newline hexmask.long.byte 0x98 10.--15. 1. "RESERVED" bitfld.long 0x98 8.--9. "PI_CALVL_EN_F1,Enable the PI CA training module." "0,1,2,3" newline hexmask.long.byte 0x98 2.--7. 1. "RESERVED" bitfld.long 0x98 0.--1. "PI_CALVL_EN_F0,Enable the PI CA training module." "0,1,2,3" line.long 0x9C "DDRSS_PI_192" hexmask.long.word 0x9C 21.--31. 1. "RESERVED" hexmask.long.byte 0x9C 16.--20. 1. "PI_TMRZ_F1,Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 1." newline bitfld.long 0x9C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x9C 0.--13. 1. "PI_TCAENT_F0,Defines the DRAM tCAENT term in memory clocks for frequency set 0." line.long 0xA0 "DDRSS_PI_193" hexmask.long.word 0xA0 21.--31. 1. "RESERVED" hexmask.long.byte 0xA0 16.--20. 1. "PI_TMRZ_F2,Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 2." newline bitfld.long 0xA0 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0xA0 0.--13. 1. "PI_TCAENT_F1,Defines the DRAM tCAENT term in memory clocks for frequency set 1." line.long 0xA4 "DDRSS_PI_194" bitfld.long 0xA4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA4 24.--28. 1. "PI_TDFI_CASEL_F0,Defines the DFI tcalvl_ca_sel timing parameter the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 0." newline bitfld.long 0xA4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA4 16.--20. 1. "PI_TDFI_CACSCA_F0,Defines the DFI tcalvl_cs_ca timing parameter the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 0." newline bitfld.long 0xA4 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0xA4 0.--13. 1. "PI_TCAENT_F2,Defines the DRAM tCAENT term in memory clocks for frequency set 2." line.long 0xA8 "DDRSS_PI_195" hexmask.long.byte 0xA8 26.--31. 1. "RESERVED" hexmask.long.word 0xA8 16.--25. 1. "PI_TVREF_LONG_F0,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 0." newline hexmask.long.byte 0xA8 10.--15. 1. "RESERVED" hexmask.long.word 0xA8 0.--9. 1. "PI_TVREF_SHORT_F0,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 0." line.long 0xAC "DDRSS_PI_196" hexmask.long.byte 0xAC 26.--31. 1. "RESERVED" hexmask.long.word 0xAC 16.--25. 1. "PI_TVREF_SHORT_F1,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 1." newline bitfld.long 0xAC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xAC 8.--12. 1. "PI_TDFI_CASEL_F1,Defines the DFI tcalvl_ca_sel timing parameter the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 1." newline bitfld.long 0xAC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xAC 0.--4. 1. "PI_TDFI_CACSCA_F1,Defines the DFI tcalvl_cs_ca timing parameter the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 1." line.long 0xB0 "DDRSS_PI_197" bitfld.long 0xB0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB0 24.--28. 1. "PI_TDFI_CASEL_F2,Defines the DFI tcalvl_ca_sel timing parameter the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 2." newline bitfld.long 0xB0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB0 16.--20. 1. "PI_TDFI_CACSCA_F2,Defines the DFI tcalvl_cs_ca timing parameter the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 2." newline hexmask.long.byte 0xB0 10.--15. 1. "RESERVED" hexmask.long.word 0xB0 0.--9. 1. "PI_TVREF_LONG_F1,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 1." line.long 0xB4 "DDRSS_PI_198" hexmask.long.byte 0xB4 26.--31. 1. "RESERVED" hexmask.long.word 0xB4 16.--25. 1. "PI_TVREF_LONG_F2,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 2." newline hexmask.long.byte 0xB4 10.--15. 1. "RESERVED" hexmask.long.word 0xB4 0.--9. 1. "PI_TVREF_SHORT_F2,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 2." line.long 0xB8 "DDRSS_PI_199" bitfld.long 0xB8 31. "RESERVED" "0,1" hexmask.long.byte 0xB8 24.--30. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F1,The end point of initial training for the Vref(ca) training for frequency set 1 { vrefca_range vref_ca_setting" newline bitfld.long 0xB8 23. "RESERVED" "0,1" hexmask.long.byte 0xB8 16.--22. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F1,The start point of initial training for the Vref(ca) training for frequency set 1 { vrefca_range vref_ca_setting" newline bitfld.long 0xB8 15. "RESERVED" "0,1" hexmask.long.byte 0xB8 8.--14. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F0,The end point of initial training for the Vref(ca) training for frequency set 0 { vrefca_range vref_ca_setting" newline bitfld.long 0xB8 7. "RESERVED" "0,1" hexmask.long.byte 0xB8 0.--6. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F0,The start point of initial training for the Vref(ca) training for frequency set 0 { vrefca_range vref_ca_setting" line.long 0xBC "DDRSS_PI_200" hexmask.long.byte 0xBC 28.--31. 1. "RESERVED" hexmask.long.byte 0xBC 24.--27. 1. "PI_CALVL_VREF_DELTA_F1,The delta fro the current CA vref for non-initial CA training for frequency set 1." newline hexmask.long.byte 0xBC 20.--23. 1. "RESERVED" hexmask.long.byte 0xBC 16.--19. 1. "PI_CALVL_VREF_DELTA_F0,The delta fro the current CA vref for non-initial CA training for frequency set 0." newline bitfld.long 0xBC 15. "RESERVED" "0,1" hexmask.long.byte 0xBC 8.--14. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F2,The end point of initial training for the Vref(ca) training for frequency set 2 { vrefca_range vref_ca_setting" newline bitfld.long 0xBC 7. "RESERVED" "0,1" hexmask.long.byte 0xBC 0.--6. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F2,The start point of initial training for the Vref(ca) training for frequency set 2 { vrefca_range vref_ca_setting" line.long 0xC0 "DDRSS_PI_201" hexmask.long.byte 0xC0 24.--31. 1. "PI_TMRWCKEL_F0,Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 0." bitfld.long 0xC0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC0 16.--20. 1. "PI_TXP_F0,CKE assert to next valid command delay for frequency set 0." hexmask.long.byte 0xC0 12.--15. 1. "RESERVED" newline hexmask.long.byte 0xC0 8.--11. 1. "PI_TDFI_CALVL_STROBE_F0,Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 0." hexmask.long.byte 0xC0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0xC0 0.--3. 1. "PI_CALVL_VREF_DELTA_F2,The delta fro the current CA vref for non-initial CA training for frequency set 2." line.long 0xC4 "DDRSS_PI_202" hexmask.long.byte 0xC4 24.--31. 1. "PI_TMRWCKEL_F1,Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 1." bitfld.long 0xC4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC4 16.--20. 1. "PI_TXP_F1,CKE assert to next valid command delay for frequency set 1." hexmask.long.byte 0xC4 12.--15. 1. "RESERVED" newline hexmask.long.byte 0xC4 8.--11. 1. "PI_TDFI_CALVL_STROBE_F1,Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 1." bitfld.long 0xC4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC4 0.--4. 1. "PI_TCKELCK_F0,Valid Clock Requirement after CKE deassert for frequency set 0." line.long 0xC8 "DDRSS_PI_203" hexmask.long.byte 0xC8 24.--31. 1. "PI_TMRWCKEL_F2,Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 2." bitfld.long 0xC8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 16.--20. 1. "PI_TXP_F2,CKE assert to next valid command delay for frequency set 2." hexmask.long.byte 0xC8 12.--15. 1. "RESERVED" newline hexmask.long.byte 0xC8 8.--11. 1. "PI_TDFI_CALVL_STROBE_F2,Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 2." bitfld.long 0xC8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 0.--4. 1. "PI_TCKELCK_F1,Valid Clock Requirement after CKE deassert for frequency set 1." line.long 0xCC "DDRSS_PI_204" hexmask.long.word 0xCC 18.--31. 1. "RESERVED" hexmask.long.word 0xCC 8.--17. 1. "PI_TDFI_INIT_START_F0,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 0 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY." newline bitfld.long 0xCC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xCC 0.--4. 1. "PI_TCKELCK_F2,Valid Clock Requirement after CKE deassert for frequency set 2." line.long 0xD0 "DDRSS_PI_205" hexmask.long.byte 0xD0 26.--31. 1. "RESERVED" hexmask.long.word 0xD0 16.--25. 1. "PI_TDFI_INIT_START_F1,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 1 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY." newline hexmask.long.word 0xD0 0.--15. 1. "PI_TDFI_INIT_COMPLETE_F0,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 0 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY." line.long 0xD4 "DDRSS_PI_206" hexmask.long.byte 0xD4 26.--31. 1. "RESERVED" hexmask.long.word 0xD4 16.--25. 1. "PI_TDFI_INIT_START_F2,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 2 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY." newline hexmask.long.word 0xD4 0.--15. 1. "PI_TDFI_INIT_COMPLETE_F1,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 1 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY." line.long 0xD8 "DDRSS_PI_207" hexmask.long.word 0xD8 22.--31. 1. "RESERVED" hexmask.long.byte 0xD8 16.--21. 1. "PI_TCKEHDQS_F0,The DRAM timing tCKEHDQS minimum delay from CKE high to strobe high impedance for frequency set 0." newline hexmask.long.word 0xD8 0.--15. 1. "PI_TDFI_INIT_COMPLETE_F2,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 2 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY." line.long 0xDC "DDRSS_PI_208" hexmask.long.word 0xDC 22.--31. 1. "RESERVED" hexmask.long.byte 0xDC 16.--21. 1. "PI_TCKEHDQS_F1,The DRAM timing tCKEHDQS minimum delay from CKE high to strobe high impedance for frequency set 1." newline hexmask.long.byte 0xDC 10.--15. 1. "RESERVED" hexmask.long.word 0xDC 0.--9. 1. "PI_TFC_F0,The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 0." line.long 0xE0 "DDRSS_PI_209" hexmask.long.word 0xE0 22.--31. 1. "RESERVED" hexmask.long.byte 0xE0 16.--21. 1. "PI_TCKEHDQS_F2,The DRAM timing tCKEHDQS minimum delay from CKE high to strobe high impedance for frequency set 2." newline hexmask.long.byte 0xE0 10.--15. 1. "RESERVED" hexmask.long.word 0xE0 0.--9. 1. "PI_TFC_F1,The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 1." line.long 0xE4 "DDRSS_PI_210" hexmask.long.byte 0xE4 26.--31. 1. "RESERVED" hexmask.long.word 0xE4 16.--25. 1. "PI_TDFI_WDQLVL_WR_F0,Switch time from write to read for frequency set 0." newline hexmask.long.byte 0xE4 10.--15. 1. "RESERVED" hexmask.long.word 0xE4 0.--9. 1. "PI_TFC_F2,The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 2." line.long 0xE8 "DDRSS_PI_211" bitfld.long 0xE8 31. "RESERVED" "0,1" hexmask.long.byte 0xE8 24.--30. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0,Write DQ training vref initial training stop value for frequency set 0." newline bitfld.long 0xE8 23. "RESERVED" "0,1" hexmask.long.byte 0xE8 16.--22. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F0,Write DQ training vref initial training start value for frequency set 0." newline hexmask.long.byte 0xE8 10.--15. 1. "RESERVED" hexmask.long.word 0xE8 0.--9. 1. "PI_TDFI_WDQLVL_RW_F0,Switch time from read to write for frequency set 0." line.long 0xEC "DDRSS_PI_212" hexmask.long.word 0xEC 18.--31. 1. "RESERVED" bitfld.long 0xEC 16.--17. "PI_NTP_TRAIN_EN_F0,Indicates whether the no topology WDQ training is enabled." "0,1,2,3" newline hexmask.long.byte 0xEC 10.--15. 1. "RESERVED" bitfld.long 0xEC 8.--9. "PI_WDQLVL_EN_F0,Indicates if Write DQ leveling is enabled for frequency set 0." "0,1,2,3" newline hexmask.long.byte 0xEC 4.--7. 1. "RESERVED" hexmask.long.byte 0xEC 0.--3. 1. "PI_WDQLVL_VREF_DELTA_F0,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 0." line.long 0xF0 "DDRSS_PI_213" hexmask.long.byte 0xF0 26.--31. 1. "RESERVED" hexmask.long.word 0xF0 16.--25. 1. "PI_TDFI_WDQLVL_RW_F1,Switch time from read to write for frequency set 1." newline hexmask.long.byte 0xF0 10.--15. 1. "RESERVED" hexmask.long.word 0xF0 0.--9. 1. "PI_TDFI_WDQLVL_WR_F1,Switch time from write to read for frequency set 1." line.long 0xF4 "DDRSS_PI_214" hexmask.long.byte 0xF4 26.--31. 1. "RESERVED" bitfld.long 0xF4 24.--25. "PI_WDQLVL_EN_F1,Indicates if Write DQ leveling is enabled for frequency set 1." "0,1,2,3" newline hexmask.long.byte 0xF4 20.--23. 1. "RESERVED" hexmask.long.byte 0xF4 16.--19. 1. "PI_WDQLVL_VREF_DELTA_F1,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 1." newline bitfld.long 0xF4 15. "RESERVED" "0,1" hexmask.long.byte 0xF4 8.--14. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1,Write DQ training vref initial training stop value for frequency set 1." newline bitfld.long 0xF4 7. "RESERVED" "0,1" hexmask.long.byte 0xF4 0.--6. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F1,Write DQ training vref initial training start value for frequency set 1." line.long 0xF8 "DDRSS_PI_215" hexmask.long.word 0xF8 18.--31. 1. "RESERVED" hexmask.long.word 0xF8 8.--17. 1. "PI_TDFI_WDQLVL_WR_F2,Switch time from write to read for frequency set 2." newline hexmask.long.byte 0xF8 2.--7. 1. "RESERVED" bitfld.long 0xF8 0.--1. "PI_NTP_TRAIN_EN_F1,Indicates whether the no topology WDQ training is enabled." "0,1,2,3" line.long 0xFC "DDRSS_PI_216" bitfld.long 0xFC 31. "RESERVED" "0,1" hexmask.long.byte 0xFC 24.--30. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2,Write DQ training vref initial training stop value for frequency set 2." newline bitfld.long 0xFC 23. "RESERVED" "0,1" hexmask.long.byte 0xFC 16.--22. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F2,Write DQ training vref initial training start value for frequency set 2." newline hexmask.long.byte 0xFC 10.--15. 1. "RESERVED" hexmask.long.word 0xFC 0.--9. 1. "PI_TDFI_WDQLVL_RW_F2,Switch time from read to write for frequency set 2." line.long 0x100 "DDRSS_PI_217" hexmask.long.byte 0x100 24.--31. 1. "PI_TRTP_F0,DRAM tRTP value in cycles for frequency set 0." hexmask.long.byte 0x100 18.--23. 1. "RESERVED" newline bitfld.long 0x100 16.--17. "PI_NTP_TRAIN_EN_F2,Indicates whether the no topology WDQ training is enabled." "0,1,2,3" hexmask.long.byte 0x100 10.--15. 1. "RESERVED" newline bitfld.long 0x100 8.--9. "PI_WDQLVL_EN_F2,Indicates if Write DQ leveling is enabled for frequency set 2." "0,1,2,3" hexmask.long.byte 0x100 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x100 0.--3. 1. "PI_WDQLVL_VREF_DELTA_F2,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 2." line.long 0x104 "DDRSS_PI_218" hexmask.long.byte 0x104 24.--31. 1. "PI_TWR_F0,DRAM tWR value in cycles for frequency set 0." bitfld.long 0x104 22.--23. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x104 16.--21. 1. "PI_TWTR_F0,DRAM tWTR value in cycles for frequency set 0." hexmask.long.byte 0x104 8.--15. 1. "PI_TRCD_F0,DRAM tRCD value in cycles for frequency set 0." newline hexmask.long.byte 0x104 0.--7. 1. "PI_TRP_F0,DRAM tRP value in cycles for frequency set 0." line.long 0x108 "DDRSS_PI_219" hexmask.long.byte 0x108 24.--31. 1. "PI_TRAS_MIN_F0,DRAM tRAS_MIN value in cycles for frequency set 0." hexmask.long.byte 0x108 17.--23. 1. "RESERVED" newline hexmask.long.tbyte 0x108 0.--16. 1. "PI_TRAS_MAX_F0,DRAM tRAS_MAX value in cycles for frequency set 0." line.long 0x10C "DDRSS_PI_220" hexmask.long.byte 0x10C 24.--31. 1. "PI_TMRD_F0,DRAM tMRD value in cycles for frequency set 0." hexmask.long.byte 0x10C 16.--23. 1. "PI_TSR_F0,Min cycles from sref entry to sref exit for frequency set 0." newline bitfld.long 0x10C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x10C 8.--13. 1. "PI_TCCDMW_F0,LPDDR4 DRAM tCCDMW in cycles for frequency set 0." newline hexmask.long.byte 0x10C 4.--7. 1. "RESERVED" hexmask.long.byte 0x10C 0.--3. 1. "PI_TDQSCK_MAX_F0,Additional delay needed for tDQSCK for frequency set 0." line.long 0x110 "DDRSS_PI_221" hexmask.long.byte 0x110 24.--31. 1. "PI_TRCD_F1,DRAM tRCD value in cycles for frequency set 1." hexmask.long.byte 0x110 16.--23. 1. "PI_TRP_F1,DRAM tRP value in cycles for frequency set 1." newline hexmask.long.byte 0x110 8.--15. 1. "PI_TRTP_F1,DRAM tRTP value in cycles for frequency set 1." hexmask.long.byte 0x110 0.--7. 1. "PI_TMRW_F0,DRAM tMRW value in cycles for frequency set 0." line.long 0x114 "DDRSS_PI_222" hexmask.long.word 0x114 16.--31. 1. "RESERVED" hexmask.long.byte 0x114 8.--15. 1. "PI_TWR_F1,DRAM tWR value in cycles for frequency set 1." newline bitfld.long 0x114 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x114 0.--5. 1. "PI_TWTR_F1,DRAM tWTR value in cycles for frequency set 1." line.long 0x118 "DDRSS_PI_223" hexmask.long.byte 0x118 24.--31. 1. "PI_TRAS_MIN_F1,DRAM tRAS_MIN value in cycles for frequency set 1." hexmask.long.byte 0x118 17.--23. 1. "RESERVED" newline hexmask.long.tbyte 0x118 0.--16. 1. "PI_TRAS_MAX_F1,DRAM tRAS_MAX value in cycles for frequency set 1." line.long 0x11C "DDRSS_PI_224" hexmask.long.byte 0x11C 24.--31. 1. "PI_TMRD_F1,DRAM tMRD value in cycles for frequency set 1." hexmask.long.byte 0x11C 16.--23. 1. "PI_TSR_F1,Min cycles from sref entry to sref exit for frequency set 1." newline bitfld.long 0x11C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x11C 8.--13. 1. "PI_TCCDMW_F1,LPDDR4 DRAM tCCDMW in cycles for frequency set 1." newline hexmask.long.byte 0x11C 4.--7. 1. "RESERVED" hexmask.long.byte 0x11C 0.--3. 1. "PI_TDQSCK_MAX_F1,Additional delay needed for tDQSCK for frequency set 1." line.long 0x120 "DDRSS_PI_225" hexmask.long.byte 0x120 24.--31. 1. "PI_TRCD_F2,DRAM tRCD value in cycles for frequency set 2." hexmask.long.byte 0x120 16.--23. 1. "PI_TRP_F2,DRAM tRP value in cycles for frequency set 2." newline hexmask.long.byte 0x120 8.--15. 1. "PI_TRTP_F2,DRAM tRTP value in cycles for frequency set 2." hexmask.long.byte 0x120 0.--7. 1. "PI_TMRW_F1,DRAM tMRW value in cycles for frequency set 1." line.long 0x124 "DDRSS_PI_226" hexmask.long.word 0x124 16.--31. 1. "RESERVED" hexmask.long.byte 0x124 8.--15. 1. "PI_TWR_F2,DRAM tWR value in cycles for frequency set 2." newline bitfld.long 0x124 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x124 0.--5. 1. "PI_TWTR_F2,DRAM tWTR value in cycles for frequency set 2." line.long 0x128 "DDRSS_PI_227" hexmask.long.byte 0x128 24.--31. 1. "PI_TRAS_MIN_F2,DRAM tRAS_MIN value in cycles for frequency set 2." hexmask.long.byte 0x128 17.--23. 1. "RESERVED" newline hexmask.long.tbyte 0x128 0.--16. 1. "PI_TRAS_MAX_F2,DRAM tRAS_MAX value in cycles for frequency set 2." line.long 0x12C "DDRSS_PI_228" hexmask.long.byte 0x12C 24.--31. 1. "PI_TMRD_F2,DRAM tMRD value in cycles for frequency set 2." hexmask.long.byte 0x12C 16.--23. 1. "PI_TSR_F2,Min cycles from sref entry to sref exit for frequency set 2." newline bitfld.long 0x12C 14.--15. "RESERVED" "0,1,2,3" hexmask.long.byte 0x12C 8.--13. 1. "PI_TCCDMW_F2,LPDDR4 DRAM tCCDMW in cycles for frequency set 2." newline hexmask.long.byte 0x12C 4.--7. 1. "RESERVED" hexmask.long.byte 0x12C 0.--3. 1. "PI_TDQSCK_MAX_F2,Additional delay needed for tDQSCK for frequency set 2." line.long 0x130 "DDRSS_PI_229" bitfld.long 0x130 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x130 8.--28. 1. "PI_TDFI_CTRLUPD_MAX_F0,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 0 the maximum cycles that dfi_ctrlupd_req can be asserted." newline hexmask.long.byte 0x130 0.--7. 1. "PI_TMRW_F2,DRAM tMRW value in cycles for frequency set 2." line.long 0x134 "DDRSS_PI_230" hexmask.long 0x134 0.--31. 1. "PI_TDFI_CTRLUPD_INTERVAL_F0,Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) for frequency set 0 the maximum cycles between dfi_ctrlupd_req assertions." line.long 0x138 "DDRSS_PI_231" hexmask.long.word 0x138 21.--31. 1. "RESERVED" hexmask.long.tbyte 0x138 0.--20. 1. "PI_TDFI_CTRLUPD_MAX_F1,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 1 the maximum cycles that dfi_ctrlupd_req can be asserted." line.long 0x13C "DDRSS_PI_232" hexmask.long 0x13C 0.--31. 1. "PI_TDFI_CTRLUPD_INTERVAL_F1,Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) for frequency set 1 the maximum cycles between dfi_ctrlupd_req assertions." line.long 0x140 "DDRSS_PI_233" hexmask.long.word 0x140 21.--31. 1. "RESERVED" hexmask.long.tbyte 0x140 0.--20. 1. "PI_TDFI_CTRLUPD_MAX_F2,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 2 the maximum cycles that dfi_ctrlupd_req can be asserted." line.long 0x144 "DDRSS_PI_234" hexmask.long 0x144 0.--31. 1. "PI_TDFI_CTRLUPD_INTERVAL_F2,Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) for frequency set 2 the maximum cycles between dfi_ctrlupd_req assertions." line.long 0x148 "DDRSS_PI_235" hexmask.long.word 0x148 16.--31. 1. "PI_TXSR_F1,DRAM TXSR value for frequency set 1 in cycles." hexmask.long.word 0x148 0.--15. 1. "PI_TXSR_F0,DRAM TXSR value for frequency set 0 in cycles." line.long 0x14C "DDRSS_PI_236" bitfld.long 0x14C 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14C 24.--29. 1. "PI_TEXCKE_F1,DRAM CKE low after SREF command timing for frequency set 1." newline bitfld.long 0x14C 22.--23. "RESERVED" "0,1,2,3" hexmask.long.byte 0x14C 16.--21. 1. "PI_TEXCKE_F0,DRAM CKE low after SREF command timing for frequency set 0." newline hexmask.long.word 0x14C 0.--15. 1. "PI_TXSR_F2,DRAM TXSR value for frequency set 2 in cycles." line.long 0x150 "DDRSS_PI_237" hexmask.long.tbyte 0x150 8.--31. 1. "PI_TINIT_F0,DRAM tINIT value for frequency set 0 in cycles." bitfld.long 0x150 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x150 0.--5. 1. "PI_TEXCKE_F2,DRAM CKE low after SREF command timing for frequency set 2." line.long 0x154 "DDRSS_PI_238" hexmask.long.byte 0x154 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x154 0.--23. 1. "PI_TINIT3_F0,DRAM tINIT3 value for frequency set 0 in cycles." line.long 0x158 "DDRSS_PI_239" hexmask.long.byte 0x158 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x158 0.--23. 1. "PI_TINIT4_F0,DRAM tINIT4 value for frequency set 0 in cycles." line.long 0x15C "DDRSS_PI_240" hexmask.long.byte 0x15C 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x15C 0.--23. 1. "PI_TINIT5_F0,DRAM tINIT5 value for frequency set 0 in cycles." line.long 0x160 "DDRSS_PI_241" hexmask.long.word 0x160 16.--31. 1. "RESERVED" hexmask.long.word 0x160 0.--15. 1. "PI_TXSNR_F0,DRAM tXSNR value for frequency set 0 in cycles." line.long 0x164 "DDRSS_PI_242" hexmask.long.byte 0x164 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x164 0.--23. 1. "PI_TINIT_F1,DRAM tINIT value for frequency set 1 in cycles." line.long 0x168 "DDRSS_PI_243" hexmask.long.byte 0x168 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x168 0.--23. 1. "PI_TINIT3_F1,DRAM tINIT3 value for frequency set 1 in cycles." line.long 0x16C "DDRSS_PI_244" hexmask.long.byte 0x16C 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x16C 0.--23. 1. "PI_TINIT4_F1,DRAM tINIT4 value for frequency set 1 in cycles." line.long 0x170 "DDRSS_PI_245" hexmask.long.byte 0x170 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x170 0.--23. 1. "PI_TINIT5_F1,DRAM tINIT5 value for frequency set 1 in cycles." line.long 0x174 "DDRSS_PI_246" hexmask.long.word 0x174 16.--31. 1. "RESERVED" hexmask.long.word 0x174 0.--15. 1. "PI_TXSNR_F1,DRAM tXSNR value for frequency set 1 in cycles." line.long 0x178 "DDRSS_PI_247" hexmask.long.byte 0x178 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x178 0.--23. 1. "PI_TINIT_F2,DRAM tINIT value for frequency set 2 in cycles." line.long 0x17C "DDRSS_PI_248" hexmask.long.byte 0x17C 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x17C 0.--23. 1. "PI_TINIT3_F2,DRAM tINIT3 value for frequency set 2 in cycles." line.long 0x180 "DDRSS_PI_249" hexmask.long.byte 0x180 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x180 0.--23. 1. "PI_TINIT4_F2,DRAM tINIT4 value for frequency set 2 in cycles." line.long 0x184 "DDRSS_PI_250" hexmask.long.byte 0x184 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x184 0.--23. 1. "PI_TINIT5_F2,DRAM tINIT5 value for frequency set 2 in cycles." line.long 0x188 "DDRSS_PI_251" hexmask.long.byte 0x188 28.--31. 1. "RESERVED" hexmask.long.word 0x188 16.--27. 1. "RESERVED,Reserved" newline hexmask.long.word 0x188 0.--15. 1. "PI_TXSNR_F2,DRAM tXSNR value for frequency set 2 in cycles." line.long 0x18C "DDRSS_PI_252" hexmask.long.byte 0x18C 28.--31. 1. "RESERVED" hexmask.long.word 0x18C 16.--27. 1. "PI_TZQCAL_F0,Holds the DRAM ZQCAL value for frequency set 0 in cycles." newline hexmask.long.byte 0x18C 12.--15. 1. "RESERVED" hexmask.long.word 0x18C 0.--11. 1. "RESERVED,Reserved" line.long 0x190 "DDRSS_PI_253" hexmask.long.word 0x190 20.--31. 1. "RESERVED" hexmask.long.word 0x190 8.--19. 1. "RESERVED,Reserved" newline bitfld.long 0x190 7. "RESERVED" "0,1" hexmask.long.byte 0x190 0.--6. 1. "PI_TZQLAT_F0,Holds the DRAM ZQLAT value for frequency set 0 in cycles." line.long 0x194 "DDRSS_PI_254" hexmask.long.byte 0x194 28.--31. 1. "RESERVED" hexmask.long.word 0x194 16.--27. 1. "PI_TZQCAL_F1,Holds the DRAM ZQCAL value for frequency set 1 in cycles." newline hexmask.long.byte 0x194 12.--15. 1. "RESERVED" hexmask.long.word 0x194 0.--11. 1. "RESERVED,Reserved" line.long 0x198 "DDRSS_PI_255" hexmask.long.word 0x198 20.--31. 1. "RESERVED" hexmask.long.word 0x198 8.--19. 1. "RESERVED,Reserved" newline bitfld.long 0x198 7. "RESERVED" "0,1" hexmask.long.byte 0x198 0.--6. 1. "PI_TZQLAT_F1,Holds the DRAM ZQLAT value for frequency set 1 in cycles." line.long 0x19C "DDRSS_PI_256" hexmask.long.byte 0x19C 28.--31. 1. "RESERVED" hexmask.long.word 0x19C 16.--27. 1. "PI_TZQCAL_F2,Holds the DRAM ZQCAL value for frequency set 2 in cycles." newline hexmask.long.byte 0x19C 12.--15. 1. "RESERVED" hexmask.long.word 0x19C 0.--11. 1. "RESERVED,Reserved" line.long 0x1A0 "DDRSS_PI_257" hexmask.long.word 0x1A0 20.--31. 1. "RESERVED" hexmask.long.word 0x1A0 8.--19. 1. "RESERVED,Reserved" newline bitfld.long 0x1A0 7. "RESERVED" "0,1" hexmask.long.byte 0x1A0 0.--6. 1. "PI_TZQLAT_F2,Holds the DRAM ZQLAT value for frequency set 2 in cycles." line.long 0x1A4 "DDRSS_PI_258" hexmask.long.byte 0x1A4 28.--31. 1. "RESERVED" hexmask.long.word 0x1A4 16.--27. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1A4 12.--15. 1. "RESERVED" hexmask.long.word 0x1A4 0.--11. 1. "RESERVED,Reserved" line.long 0x1A8 "DDRSS_PI_259" hexmask.long.byte 0x1A8 24.--31. 1. "PI_MR13_DATA_0,Data to program into memory mode register 13 for chip select 0." hexmask.long.byte 0x1A8 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x1A8 16.--19. 1. "PI_WDQ_OSC_DELTA_INDEX_F2,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 2." hexmask.long.byte 0x1A8 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x1A8 8.--11. 1. "PI_WDQ_OSC_DELTA_INDEX_F1,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 1." hexmask.long.byte 0x1A8 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x1A8 0.--3. 1. "PI_WDQ_OSC_DELTA_INDEX_F0,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 0." line.long 0x1AC "DDRSS_PI_260" hexmask.long.byte 0x1AC 24.--31. 1. "PI_MR20_DATA_0,Data to program into memory mode register 20 for chip select 0." hexmask.long.byte 0x1AC 16.--23. 1. "PI_MR17_DATA_0,Data to program into memory mode register 17 for chip select 0." newline hexmask.long.byte 0x1AC 8.--15. 1. "PI_MR16_DATA_0,Data to program into memory mode register 16 for chip select 0." hexmask.long.byte 0x1AC 0.--7. 1. "PI_MR15_DATA_0,Data to program into memory mode register 15 for chip select 0." line.long 0x1B0 "DDRSS_PI_261" hexmask.long.byte 0x1B0 24.--31. 1. "PI_MR15_DATA_1,Data to program into memory mode register 15 for chip select 1." hexmask.long.byte 0x1B0 16.--23. 1. "PI_MR13_DATA_1,Data to program into memory mode register 13 for chip select 1." newline hexmask.long.byte 0x1B0 8.--15. 1. "PI_MR40_DATA_0,Data to program into memory mode register 40 for chip select 0." hexmask.long.byte 0x1B0 0.--7. 1. "PI_MR32_DATA_0,Data to program into memory mode register 32 for chip select 0." line.long 0x1B4 "DDRSS_PI_262" hexmask.long.byte 0x1B4 24.--31. 1. "PI_MR32_DATA_1,Data to program into memory mode register 32 for chip select 1." hexmask.long.byte 0x1B4 16.--23. 1. "PI_MR20_DATA_1,Data to program into memory mode register 20 for chip select 1." newline hexmask.long.byte 0x1B4 8.--15. 1. "PI_MR17_DATA_1,Data to program into memory mode register 17 for chip select 1." hexmask.long.byte 0x1B4 0.--7. 1. "PI_MR16_DATA_1,Data to program into memory mode register 16 for chip select 1." line.long 0x1B8 "DDRSS_PI_263" hexmask.long.byte 0x1B8 24.--31. 1. "PI_MR16_DATA_2,Data to program into memory mode register 16 for chip select 2." hexmask.long.byte 0x1B8 16.--23. 1. "PI_MR15_DATA_2,Data to program into memory mode register 15 for chip select 2." newline hexmask.long.byte 0x1B8 8.--15. 1. "PI_MR13_DATA_2,Data to program into memory mode register 13 for chip select 2." hexmask.long.byte 0x1B8 0.--7. 1. "PI_MR40_DATA_1,Data to program into memory mode register 40 for chip select 1." line.long 0x1BC "DDRSS_PI_264" hexmask.long.byte 0x1BC 24.--31. 1. "PI_MR40_DATA_2,Data to program into memory mode register 40 for chip select 2." hexmask.long.byte 0x1BC 16.--23. 1. "PI_MR32_DATA_2,Data to program into memory mode register 32 for chip select 2." newline hexmask.long.byte 0x1BC 8.--15. 1. "PI_MR20_DATA_2,Data to program into memory mode register 20 for chip select 2." hexmask.long.byte 0x1BC 0.--7. 1. "PI_MR17_DATA_2,Data to program into memory mode register 17 for chip select 2." line.long 0x1C0 "DDRSS_PI_265" hexmask.long.byte 0x1C0 24.--31. 1. "PI_MR17_DATA_3,Data to program into memory mode register 17 for chip select 3." hexmask.long.byte 0x1C0 16.--23. 1. "PI_MR16_DATA_3,Data to program into memory mode register 16 for chip select 3." newline hexmask.long.byte 0x1C0 8.--15. 1. "PI_MR15_DATA_3,Data to program into memory mode register 15 for chip select 3." hexmask.long.byte 0x1C0 0.--7. 1. "PI_MR13_DATA_3,Data to program into memory mode register 13 for chip select 3." line.long 0x1C4 "DDRSS_PI_266" hexmask.long.byte 0x1C4 28.--31. 1. "RESERVED" hexmask.long.byte 0x1C4 24.--27. 1. "PI_CKE_MUX_0,Command pin CKE_0 mux selector" newline hexmask.long.byte 0x1C4 16.--23. 1. "PI_MR40_DATA_3,Data to program into memory mode register 40 for chip select 3." hexmask.long.byte 0x1C4 8.--15. 1. "PI_MR32_DATA_3,Data to program into memory mode register 32 for chip select 3." newline hexmask.long.byte 0x1C4 0.--7. 1. "PI_MR20_DATA_3,Data to program into memory mode register 20 for chip select 3." line.long 0x1C8 "DDRSS_PI_267" hexmask.long.byte 0x1C8 28.--31. 1. "RESERVED" hexmask.long.byte 0x1C8 24.--27. 1. "PI_CS_MUX_0,Command pin CS_0 mux selector" newline hexmask.long.byte 0x1C8 20.--23. 1. "RESERVED" hexmask.long.byte 0x1C8 16.--19. 1. "PI_CKE_MUX_3,Command pin CKE_3 mux selector" newline hexmask.long.byte 0x1C8 12.--15. 1. "RESERVED" hexmask.long.byte 0x1C8 8.--11. 1. "PI_CKE_MUX_2,Command pin CKE_2 mux selector" newline hexmask.long.byte 0x1C8 4.--7. 1. "RESERVED" hexmask.long.byte 0x1C8 0.--3. 1. "PI_CKE_MUX_1,Command pin CKE_1 mux selector" line.long 0x1CC "DDRSS_PI_268" hexmask.long.byte 0x1CC 28.--31. 1. "RESERVED" hexmask.long.byte 0x1CC 24.--27. 1. "PI_RESET_N_MUX_0,Command pin RESET_N_0 mux selector" newline hexmask.long.byte 0x1CC 20.--23. 1. "RESERVED" hexmask.long.byte 0x1CC 16.--19. 1. "PI_CS_MUX_3,Command pin CS_3 mux selector" newline hexmask.long.byte 0x1CC 12.--15. 1. "RESERVED" hexmask.long.byte 0x1CC 8.--11. 1. "PI_CS_MUX_2,Command pin CS_2 mux selector" newline hexmask.long.byte 0x1CC 4.--7. 1. "RESERVED" hexmask.long.byte 0x1CC 0.--3. 1. "PI_CS_MUX_1,Command pin CS_1 mux selector" line.long 0x1D0 "DDRSS_PI_269" hexmask.long.byte 0x1D0 24.--31. 1. "PI_MRSINGLE_DATA_0,Data to program into memory mode register single write to chip select 0." hexmask.long.byte 0x1D0 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x1D0 16.--19. 1. "PI_RESET_N_MUX_3,Command pin RESET_N_3 mux selector" hexmask.long.byte 0x1D0 12.--15. 1. "RESERVED" newline hexmask.long.byte 0x1D0 8.--11. 1. "PI_RESET_N_MUX_2,Command pin RESET_N_2 mux selector" hexmask.long.byte 0x1D0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x1D0 0.--3. 1. "PI_RESET_N_MUX_1,Command pin RESET_N_1 mux selector" line.long 0x1D4 "DDRSS_PI_270" hexmask.long.byte 0x1D4 28.--31. 1. "RESERVED" hexmask.long.byte 0x1D4 24.--27. 1. "PI_ZQ_CAL_START_MAP_0,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 0 of the ZQ START initialization and periodic command sequences." newline hexmask.long.byte 0x1D4 16.--23. 1. "PI_MRSINGLE_DATA_3,Data to program into memory mode register single write to chip select 3." hexmask.long.byte 0x1D4 8.--15. 1. "PI_MRSINGLE_DATA_2,Data to program into memory mode register single write to chip select 2." newline hexmask.long.byte 0x1D4 0.--7. 1. "PI_MRSINGLE_DATA_1,Data to program into memory mode register single write to chip select 1." line.long 0x1D8 "DDRSS_PI_271" hexmask.long.byte 0x1D8 28.--31. 1. "RESERVED" hexmask.long.byte 0x1D8 24.--27. 1. "PI_ZQ_CAL_START_MAP_2,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 2 of the ZQ START initialization and periodic command sequences." newline hexmask.long.byte 0x1D8 20.--23. 1. "RESERVED" hexmask.long.byte 0x1D8 16.--19. 1. "PI_ZQ_CAL_LATCH_MAP_1,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 1 of the ZQ LATCH initialization and periodic command sequences." newline hexmask.long.byte 0x1D8 12.--15. 1. "RESERVED" hexmask.long.byte 0x1D8 8.--11. 1. "PI_ZQ_CAL_START_MAP_1,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 1 of the ZQ START initialization and periodic command sequences." newline hexmask.long.byte 0x1D8 4.--7. 1. "RESERVED" hexmask.long.byte 0x1D8 0.--3. 1. "PI_ZQ_CAL_LATCH_MAP_0,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 0 of the ZQ LATCH initialization and periodic command sequences." line.long 0x1DC "DDRSS_PI_272" hexmask.long.word 0x1DC 20.--31. 1. "RESERVED" hexmask.long.byte 0x1DC 16.--19. 1. "PI_ZQ_CAL_LATCH_MAP_3,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 3 of the ZQ LATCH initialization and periodic command sequences." newline hexmask.long.byte 0x1DC 12.--15. 1. "RESERVED" hexmask.long.byte 0x1DC 8.--11. 1. "PI_ZQ_CAL_START_MAP_3,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 3 of the ZQ START initialization and periodic command sequences." newline hexmask.long.byte 0x1DC 4.--7. 1. "RESERVED" hexmask.long.byte 0x1DC 0.--3. 1. "PI_ZQ_CAL_LATCH_MAP_2,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 2 of the ZQ LATCH initialization and periodic command sequences." line.long 0x1E0 "DDRSS_PI_273" hexmask.long.word 0x1E0 16.--31. 1. "PI_DQS_OSC_BASE_VALUE_1_0,Base value for comparison of oscillator measurement for device 1 of rank 0" hexmask.long.word 0x1E0 0.--15. 1. "PI_DQS_OSC_BASE_VALUE_0_0,Base value for comparison of oscillator measurement for device 0 of rank 0" line.long 0x1E4 "DDRSS_PI_274" hexmask.long.word 0x1E4 16.--31. 1. "PI_DQS_OSC_BASE_VALUE_1_1,Base value for comparison of oscillator measurement for device 1 of rank 1" hexmask.long.word 0x1E4 0.--15. 1. "PI_DQS_OSC_BASE_VALUE_0_1,Base value for comparison of oscillator measurement for device 0 of rank 1" line.long 0x1E8 "DDRSS_PI_275" hexmask.long.byte 0x1E8 24.--31. 1. "PI_MR11_DATA_F0_0,Data to program into memory mode register 11 for chip select 0 for frequency set 0." hexmask.long.byte 0x1E8 16.--23. 1. "PI_MR3_DATA_F0_0,Data to program into memory mode register 3 for chip select 0 for frequency set 0." newline hexmask.long.byte 0x1E8 8.--15. 1. "PI_MR2_DATA_F0_0,Data to program into memory mode register 2 for chip select 0 for frequency set 0." hexmask.long.byte 0x1E8 0.--7. 1. "PI_MR1_DATA_F0_0,Data to program into memory mode register 1 for chip select 0 for frequency set 0." line.long 0x1EC "DDRSS_PI_276" hexmask.long.byte 0x1EC 24.--31. 1. "PI_MR23_DATA_F0_0,Data to program into memory mode register 23 for chip select 0 for frequency set 0." hexmask.long.byte 0x1EC 16.--23. 1. "PI_MR22_DATA_F0_0,Data to program into memory mode register 22 for chip select 0 for frequency set 0." newline hexmask.long.byte 0x1EC 8.--15. 1. "PI_MR14_DATA_F0_0,Data to program into memory mode register 14 for chip select 0 for frequency set 0." hexmask.long.byte 0x1EC 0.--7. 1. "PI_MR12_DATA_F0_0,Data to program into memory mode register 12 for chip select 0 for frequency set 0." line.long 0x1F0 "DDRSS_PI_277" hexmask.long.byte 0x1F0 24.--31. 1. "PI_MR11_DATA_F1_0,Data to program into memory mode register 11 for chip select 0 for frequency set 1." hexmask.long.byte 0x1F0 16.--23. 1. "PI_MR3_DATA_F1_0,Data to program into memory mode register 3 for chip select 0 for frequency set 1." newline hexmask.long.byte 0x1F0 8.--15. 1. "PI_MR2_DATA_F1_0,Data to program into memory mode register 2 for chip select 0 for frequency set 1." hexmask.long.byte 0x1F0 0.--7. 1. "PI_MR1_DATA_F1_0,Data to program into memory mode register 1 for chip select 0 for frequency set 1." line.long 0x1F4 "DDRSS_PI_278" hexmask.long.byte 0x1F4 24.--31. 1. "PI_MR23_DATA_F1_0,Data to program into memory mode register 23 for chip select 0 for frequency set 1." hexmask.long.byte 0x1F4 16.--23. 1. "PI_MR22_DATA_F1_0,Data to program into memory mode register 22 for chip select 0 for frequency set 1." newline hexmask.long.byte 0x1F4 8.--15. 1. "PI_MR14_DATA_F1_0,Data to program into memory mode register 14 for chip select 0 for frequency set 1." hexmask.long.byte 0x1F4 0.--7. 1. "PI_MR12_DATA_F1_0,Data to program into memory mode register 12 for chip select 0 for frequency set 1." line.long 0x1F8 "DDRSS_PI_279" hexmask.long.byte 0x1F8 24.--31. 1. "PI_MR11_DATA_F2_0,Data to program into memory mode register 11 for chip select 0 for frequency set 2." hexmask.long.byte 0x1F8 16.--23. 1. "PI_MR3_DATA_F2_0,Data to program into memory mode register 3 for chip select 0 for frequency set 2." newline hexmask.long.byte 0x1F8 8.--15. 1. "PI_MR2_DATA_F2_0,Data to program into memory mode register 2 for chip select 0 for frequency set 2." hexmask.long.byte 0x1F8 0.--7. 1. "PI_MR1_DATA_F2_0,Data to program into memory mode register 1 for chip select 0 for frequency set 2." line.long 0x1FC "DDRSS_PI_280" hexmask.long.byte 0x1FC 24.--31. 1. "PI_MR23_DATA_F2_0,Data to program into memory mode register 23 for chip select 0 for frequency set 2." hexmask.long.byte 0x1FC 16.--23. 1. "PI_MR22_DATA_F2_0,Data to program into memory mode register 22 for chip select 0 for frequency set 2." newline hexmask.long.byte 0x1FC 8.--15. 1. "PI_MR14_DATA_F2_0,Data to program into memory mode register 14 for chip select 0 for frequency set 2." hexmask.long.byte 0x1FC 0.--7. 1. "PI_MR12_DATA_F2_0,Data to program into memory mode register 12 for chip select 0 for frequency set 2." line.long 0x200 "DDRSS_PI_281" hexmask.long.byte 0x200 24.--31. 1. "PI_MR11_DATA_F0_1,Data to program into memory mode register 11 for chip select 1 for frequency set 0." hexmask.long.byte 0x200 16.--23. 1. "PI_MR3_DATA_F0_1,Data to program into memory mode register 3 for chip select 1 for frequency set 0." newline hexmask.long.byte 0x200 8.--15. 1. "PI_MR2_DATA_F0_1,Data to program into memory mode register 2 for chip select 1 for frequency set 0." hexmask.long.byte 0x200 0.--7. 1. "PI_MR1_DATA_F0_1,Data to program into memory mode register 1 for chip select 1 for frequency set 0." line.long 0x204 "DDRSS_PI_282" hexmask.long.byte 0x204 24.--31. 1. "PI_MR23_DATA_F0_1,Data to program into memory mode register 23 for chip select 1 for frequency set 0." hexmask.long.byte 0x204 16.--23. 1. "PI_MR22_DATA_F0_1,Data to program into memory mode register 22 for chip select 1 for frequency set 0." newline hexmask.long.byte 0x204 8.--15. 1. "PI_MR14_DATA_F0_1,Data to program into memory mode register 14 for chip select 1 for frequency set 0." hexmask.long.byte 0x204 0.--7. 1. "PI_MR12_DATA_F0_1,Data to program into memory mode register 12 for chip select 1 for frequency set 0." line.long 0x208 "DDRSS_PI_283" hexmask.long.byte 0x208 24.--31. 1. "PI_MR11_DATA_F1_1,Data to program into memory mode register 11 for chip select 1 for frequency set 1." hexmask.long.byte 0x208 16.--23. 1. "PI_MR3_DATA_F1_1,Data to program into memory mode register 3 for chip select 1 for frequency set 1." newline hexmask.long.byte 0x208 8.--15. 1. "PI_MR2_DATA_F1_1,Data to program into memory mode register 2 for chip select 1 for frequency set 1." hexmask.long.byte 0x208 0.--7. 1. "PI_MR1_DATA_F1_1,Data to program into memory mode register 1 for chip select 1 for frequency set 1." line.long 0x20C "DDRSS_PI_284" hexmask.long.byte 0x20C 24.--31. 1. "PI_MR23_DATA_F1_1,Data to program into memory mode register 23 for chip select 1 for frequency set 1." hexmask.long.byte 0x20C 16.--23. 1. "PI_MR22_DATA_F1_1,Data to program into memory mode register 22 for chip select 1 for frequency set 1." newline hexmask.long.byte 0x20C 8.--15. 1. "PI_MR14_DATA_F1_1,Data to program into memory mode register 14 for chip select 1 for frequency set 1." hexmask.long.byte 0x20C 0.--7. 1. "PI_MR12_DATA_F1_1,Data to program into memory mode register 12 for chip select 1 for frequency set 1." line.long 0x210 "DDRSS_PI_285" hexmask.long.byte 0x210 24.--31. 1. "PI_MR11_DATA_F2_1,Data to program into memory mode register 11 for chip select 1 for frequency set 2." hexmask.long.byte 0x210 16.--23. 1. "PI_MR3_DATA_F2_1,Data to program into memory mode register 3 for chip select 1 for frequency set 2." newline hexmask.long.byte 0x210 8.--15. 1. "PI_MR2_DATA_F2_1,Data to program into memory mode register 2 for chip select 1 for frequency set 2." hexmask.long.byte 0x210 0.--7. 1. "PI_MR1_DATA_F2_1,Data to program into memory mode register 1 for chip select 1 for frequency set 2." line.long 0x214 "DDRSS_PI_286" hexmask.long.byte 0x214 24.--31. 1. "PI_MR23_DATA_F2_1,Data to program into memory mode register 23 for chip select 1 for frequency set 2." hexmask.long.byte 0x214 16.--23. 1. "PI_MR22_DATA_F2_1,Data to program into memory mode register 22 for chip select 1 for frequency set 2." newline hexmask.long.byte 0x214 8.--15. 1. "PI_MR14_DATA_F2_1,Data to program into memory mode register 14 for chip select 1 for frequency set 2." hexmask.long.byte 0x214 0.--7. 1. "PI_MR12_DATA_F2_1,Data to program into memory mode register 12 for chip select 1 for frequency set 2." line.long 0x218 "DDRSS_PI_287" hexmask.long.byte 0x218 24.--31. 1. "PI_MR11_DATA_F0_2,Data to program into memory mode register 11 for chip select 2 for frequency set 0." hexmask.long.byte 0x218 16.--23. 1. "PI_MR3_DATA_F0_2,Data to program into memory mode register 3 for chip select 2 for frequency set 0." newline hexmask.long.byte 0x218 8.--15. 1. "PI_MR2_DATA_F0_2,Data to program into memory mode register 2 for chip select 2 for frequency set 0." hexmask.long.byte 0x218 0.--7. 1. "PI_MR1_DATA_F0_2,Data to program into memory mode register 1 for chip select 2 for frequency set 0." line.long 0x21C "DDRSS_PI_288" hexmask.long.byte 0x21C 24.--31. 1. "PI_MR23_DATA_F0_2,Data to program into memory mode register 23 for chip select 2 for frequency set 0." hexmask.long.byte 0x21C 16.--23. 1. "PI_MR22_DATA_F0_2,Data to program into memory mode register 22 for chip select 2 for frequency set 0." newline hexmask.long.byte 0x21C 8.--15. 1. "PI_MR14_DATA_F0_2,Data to program into memory mode register 14 for chip select 2 for frequency set 0." hexmask.long.byte 0x21C 0.--7. 1. "PI_MR12_DATA_F0_2,Data to program into memory mode register 12 for chip select 2 for frequency set 0." line.long 0x220 "DDRSS_PI_289" hexmask.long.byte 0x220 24.--31. 1. "PI_MR11_DATA_F1_2,Data to program into memory mode register 11 for chip select 2 for frequency set 1." hexmask.long.byte 0x220 16.--23. 1. "PI_MR3_DATA_F1_2,Data to program into memory mode register 3 for chip select 2 for frequency set 1." newline hexmask.long.byte 0x220 8.--15. 1. "PI_MR2_DATA_F1_2,Data to program into memory mode register 2 for chip select 2 for frequency set 1." hexmask.long.byte 0x220 0.--7. 1. "PI_MR1_DATA_F1_2,Data to program into memory mode register 1 for chip select 2 for frequency set 1." line.long 0x224 "DDRSS_PI_290" hexmask.long.byte 0x224 24.--31. 1. "PI_MR23_DATA_F1_2,Data to program into memory mode register 23 for chip select 2 for frequency set 1." hexmask.long.byte 0x224 16.--23. 1. "PI_MR22_DATA_F1_2,Data to program into memory mode register 22 for chip select 2 for frequency set 1." newline hexmask.long.byte 0x224 8.--15. 1. "PI_MR14_DATA_F1_2,Data to program into memory mode register 14 for chip select 2 for frequency set 1." hexmask.long.byte 0x224 0.--7. 1. "PI_MR12_DATA_F1_2,Data to program into memory mode register 12 for chip select 2 for frequency set 1." line.long 0x228 "DDRSS_PI_291" hexmask.long.byte 0x228 24.--31. 1. "PI_MR11_DATA_F2_2,Data to program into memory mode register 11 for chip select 2 for frequency set 2." hexmask.long.byte 0x228 16.--23. 1. "PI_MR3_DATA_F2_2,Data to program into memory mode register 3 for chip select 2 for frequency set 2." newline hexmask.long.byte 0x228 8.--15. 1. "PI_MR2_DATA_F2_2,Data to program into memory mode register 2 for chip select 2 for frequency set 2." hexmask.long.byte 0x228 0.--7. 1. "PI_MR1_DATA_F2_2,Data to program into memory mode register 1 for chip select 2 for frequency set 2." line.long 0x22C "DDRSS_PI_292" hexmask.long.byte 0x22C 24.--31. 1. "PI_MR23_DATA_F2_2,Data to program into memory mode register 23 for chip select 2 for frequency set 2." hexmask.long.byte 0x22C 16.--23. 1. "PI_MR22_DATA_F2_2,Data to program into memory mode register 22 for chip select 2 for frequency set 2." newline hexmask.long.byte 0x22C 8.--15. 1. "PI_MR14_DATA_F2_2,Data to program into memory mode register 14 for chip select 2 for frequency set 2." hexmask.long.byte 0x22C 0.--7. 1. "PI_MR12_DATA_F2_2,Data to program into memory mode register 12 for chip select 2 for frequency set 2." line.long 0x230 "DDRSS_PI_293" hexmask.long.byte 0x230 24.--31. 1. "PI_MR11_DATA_F0_3,Data to program into memory mode register 11 for chip select 3 for frequency set 0." hexmask.long.byte 0x230 16.--23. 1. "PI_MR3_DATA_F0_3,Data to program into memory mode register 3 for chip select 3 for frequency set 0." newline hexmask.long.byte 0x230 8.--15. 1. "PI_MR2_DATA_F0_3,Data to program into memory mode register 2 for chip select 3 for frequency set 0." hexmask.long.byte 0x230 0.--7. 1. "PI_MR1_DATA_F0_3,Data to program into memory mode register 1 for chip select 3 for frequency set 0." line.long 0x234 "DDRSS_PI_294" hexmask.long.byte 0x234 24.--31. 1. "PI_MR23_DATA_F0_3,Data to program into memory mode register 23 for chip select 3 for frequency set 0." hexmask.long.byte 0x234 16.--23. 1. "PI_MR22_DATA_F0_3,Data to program into memory mode register 22 for chip select 3 for frequency set 0." newline hexmask.long.byte 0x234 8.--15. 1. "PI_MR14_DATA_F0_3,Data to program into memory mode register 14 for chip select 3 for frequency set 0." hexmask.long.byte 0x234 0.--7. 1. "PI_MR12_DATA_F0_3,Data to program into memory mode register 12 for chip select 3 for frequency set 0." line.long 0x238 "DDRSS_PI_295" hexmask.long.byte 0x238 24.--31. 1. "PI_MR11_DATA_F1_3,Data to program into memory mode register 11 for chip select 3 for frequency set 1." hexmask.long.byte 0x238 16.--23. 1. "PI_MR3_DATA_F1_3,Data to program into memory mode register 3 for chip select 3 for frequency set 1." newline hexmask.long.byte 0x238 8.--15. 1. "PI_MR2_DATA_F1_3,Data to program into memory mode register 2 for chip select 3 for frequency set 1." hexmask.long.byte 0x238 0.--7. 1. "PI_MR1_DATA_F1_3,Data to program into memory mode register 1 for chip select 3 for frequency set 1." line.long 0x23C "DDRSS_PI_296" hexmask.long.byte 0x23C 24.--31. 1. "PI_MR23_DATA_F1_3,Data to program into memory mode register 23 for chip select 3 for frequency set 1." hexmask.long.byte 0x23C 16.--23. 1. "PI_MR22_DATA_F1_3,Data to program into memory mode register 22 for chip select 3 for frequency set 1." newline hexmask.long.byte 0x23C 8.--15. 1. "PI_MR14_DATA_F1_3,Data to program into memory mode register 14 for chip select 3 for frequency set 1." hexmask.long.byte 0x23C 0.--7. 1. "PI_MR12_DATA_F1_3,Data to program into memory mode register 12 for chip select 3 for frequency set 1." line.long 0x240 "DDRSS_PI_297" hexmask.long.byte 0x240 24.--31. 1. "PI_MR11_DATA_F2_3,Data to program into memory mode register 11 for chip select 3 for frequency set 2." hexmask.long.byte 0x240 16.--23. 1. "PI_MR3_DATA_F2_3,Data to program into memory mode register 3 for chip select 3 for frequency set 2." newline hexmask.long.byte 0x240 8.--15. 1. "PI_MR2_DATA_F2_3,Data to program into memory mode register 2 for chip select 3 for frequency set 2." hexmask.long.byte 0x240 0.--7. 1. "PI_MR1_DATA_F2_3,Data to program into memory mode register 1 for chip select 3 for frequency set 2." line.long 0x244 "DDRSS_PI_298" hexmask.long.byte 0x244 24.--31. 1. "PI_MR23_DATA_F2_3,Data to program into memory mode register 23 for chip select 3 for frequency set 2." hexmask.long.byte 0x244 16.--23. 1. "PI_MR22_DATA_F2_3,Data to program into memory mode register 22 for chip select 3 for frequency set 2." newline hexmask.long.byte 0x244 8.--15. 1. "PI_MR14_DATA_F2_3,Data to program into memory mode register 14 for chip select 3 for frequency set 2." hexmask.long.byte 0x244 0.--7. 1. "PI_MR12_DATA_F2_3,Data to program into memory mode register 12 for chip select 3 for frequency set 2." line.long 0x248 "DDRSS_PI_299" hexmask.long.tbyte 0x248 11.--31. 1. "RESERVED" hexmask.long.word 0x248 0.--10. 1. "PI_PARITY_ERROR_REGIF,Inject parity error to regisster interface signals for PI." tree.end tree "COMPUTE_CLUSTER0_DMSC_BOOT" base ad:0x45A00000 rgroup.long 0x0++0x7 line.long 0x0 "CC_REVISION,Compute Cluster Revision Register" hexmask.long 0x0 0.--31. 1. "REV,TI internal data." line.long 0x4 "CC_MSMC_DEF,MSMC Definition Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "NUM_COREPAC,Denotes the number of corepacs connected to compute cluster.0h - Two corepacs" group.long 0x8++0x7 line.long 0x0 "CC_GIC_CONFIG,GIC Configuration Register. GIC0 has input signals cpu_active_X_N (where X = A72SS number; N = Core number) which indicate when a core is active and available for routing SPIs unlike being in a software-transparent low-power mode in which.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "CP0_CPU_ACTIVE,A72SS0 Cores activeBits [11-10]: ReservedBit [9]:0h - A72SS0 Core 1 is in software-transparent low-power mode such as retention1h - A72SS0 Core 1 is active and available for shared SPIsBit [8]:0h - A72SS0 Core 0 is in software-transparent.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "GIC_FFI_MODE_DIS,Disables AXI auto responses to ARM in FFI mode." "0,1" bitfld.long 0x0 0. "GIC_SECURE,Not used on this SoC" "0,1" line.long 0x4 "CC_MISC_CONFIG,MISC Configuration Register." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "DISABLE_EN_RDATA_FORWARDING,Disable control for AXI2VBUSMC return data forwarding feature" "0,1" bitfld.long 0x4 2. "DISABLE_NRT_ESCALATION,Disable control for MSMC NRT escalation feature" "0,1" newline bitfld.long 0x4 1. "NOGATE_MSMC_CFG,No gate control for the Configuration Interconnect (see" "0,1" bitfld.long 0x4 0. "NOGATE_MSMC_DMSC,No gate control for the DMSC Interconnect (see" "0,1" rgroup.long 0x1000++0x3 line.long 0x0 "CC_DEF_j,Compute Cluster Definition Register for MSMC port j Offset = 1000h*(j + 1); where j = 0h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 24.--27. 1. "SRAM_SIZE,SRAM size (if present in the corepac)0h - 0 bytes" hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16.--17. "NUM_CORES,Number of cores in the corepac0h - One core1h - Two cores2h - Four cores3h - Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--15. 1. "COREPAC_TYPE_DSP,Not used on this SoC" hexmask.long.byte 0x0 0.--7. 1. "COREPAC_TYPE_ARM,MSMC port 'j' configuration0h - A53 corepac connected to MSMC port 'j'1h - A72 corepac connected to MSMC port 'j'2h to FEh - ReservedFFh - Port not used for ARM" group.long 0x1004++0x13 line.long 0x0 "CC_CP_CONFIG_j,Compute Cluster Configuration Register for MSMC port j Offset = 1004h*(j + 1); where j = 0h" bitfld.long 0x0 31. "ENDIAN,Not used on this SoC" "0,1" rbitfld.long 0x0 29.--30. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 25.--28. 1. "L2ACCESS_LAT,Not used on this SoC" newline hexmask.long.byte 0x0 21.--24. 1. "L2PIPELINE_LAT,Not used on this SoC" hexmask.long.word 0x0 12.--20. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "CP15DISABLE,Disable write access to some secure CP15 registers. Valid only for Arm corepacs." newline hexmask.long.byte 0x0 4.--7. 1. "CONFIGTE,Enable T32 exceptions. It sets the initial value of the TE bit in the CP15 SCTLR register. This pin is sampled only during reset of the processor. Valid only for Arm corepacs.Bits [7-6]: ReservedBit [5]:0h - TE bit is LOW for core 1 of A72SS01h.." hexmask.long.byte 0x0 0.--3. 1. "AARCH,Arm Architecture. Valid only for Arm corepacs.Bits [3-2]: ReservedBit [1]:0h - AArch32 for core 1 of A72SS01h - AArch64 for core 1 of A72SS0Bit [0]:0h - AArch32 for core 0 of A72SS01h - AArch64 for core 0 of A72SS0" line.long 0x4 "CC_RST_VEC_LO_CP0_j,Core 0 Boot Vector Register (Low) for MSMC port j Offset = 1008h*(j + 1); where j = 0h" hexmask.long 0x4 0.--31. 1. "RESET_BASE_VECTOR_LO,Low reset base vector (bits [33-2]) for Core 0 of a corepac connected to MSMC port j." line.long 0x8 "CC_RST_VEC_HI_CP0_j,Core 0 Boot Vector Register (High) for MSMC port j Offset = 100Ch*(j + 1); where j = 0h" hexmask.long.word 0x8 17.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x8 0.--16. 1. "RESET_BASE_VECTOR_HI,High reset base vector (bits [39-34]) for Core 0 of a corepac connected to MSMC port j." line.long 0xC "CC_RST_VEC_LO_CP1_j,Core 1 Boot Vector Register (Low) for MSMC port j. Offset = 1010h*(j + 1); where j = 0h" hexmask.long 0xC 0.--31. 1. "RESET_BASE_VECTOR_LO,Low reset base vector (bits [33-2]) for Core 1 of a corepac connected to MSMC port j." line.long 0x10 "CC_RST_VEC_HI_CP1_j,Core 1 Boot Vector Register (High) for MSMC port j. Offset = 1014h*(j + 1); where j = 0h" hexmask.long.word 0x10 17.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x10 0.--16. 1. "RESET_BASE_VECTOR_HI,High reset base vector (bits [39-34]) for Core 1 of a corepac connected to MSMC port j." group.long 0x1028++0x3 line.long 0x0 "CC_PM_CONFIG_j,Power Management Configuration Register for MSMC port j. Offset = 1028h*(j + 1); where j = 0h" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "DBGPWRUP0,Core power upBits [11-10]: ReservedBit [9]:0h - A72SSj Core 1 is powered down1h - A72SSj Core 1 is powered upBit [8]:0h - A72SSj Core 0 is powered down1h - A72SSj Core 0 is powered up" bitfld.long 0x0 7. "DBGL1RSTDISABLE0,Disable L1 data cache automatic invalidate on reset. This pin is sampled only during reset of the processor.0h - Enable automatic invalidation of L1 data cache on reset1h - Disable automatic invalidation of L1 data cache on reset" "0,1" newline bitfld.long 0x0 6. "CLEAR_MON0,Request to clear the external global exclusive monitor. This sends a WFE wake-up event to all cores in the cluster. When set HIGH the global exclusive monitor in the system is requesting the processor EVENT registers to be set HIGH." "0,1" bitfld.long 0x0 5. "L2_FLUSHREQ0,ARM L2 hardware flush request" "0,1" bitfld.long 0x0 4. "BROADCAST_INNER0,Enable broadcasting of inner shareable and outer sharable transactions0h - Broadcasting disabled1h - Broadcasting enabled" "0,1" newline bitfld.long 0x0 3. "CACHE_BROADCAST0,Enable Broadcasting of cache maintenance transactions0h - Broadcasting disabled1h - Broadcasting enabled" "0,1" bitfld.long 0x0 2. "SYS_BARR0,Disable broadcasting of barriers0h - Broadcasting enabled1h - Broadcasting disabled" "0,1" bitfld.long 0x0 1. "ACP_MASTER0,ACP master is inactive and is not participating in coherency0h - ACP Master is active1h - ACP Master is inactiveNOTE: There must be no outstanding transactions when the master asserts this signal and while it is asserted the master must not.." "0,1" newline bitfld.long 0x0 0. "SNOOP_IF0,Snoop interface is inactive and not participating in coherency0h - Snoop interface is active1h - Snoop interface is inactive" "0,1" rgroup.long 0x102C++0x3 line.long 0x0 "CC_PM_STATUS_j,Power Management Status Register for MSMC port j. Offset = 102Ch*(j + 1); where j = 0h" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 14. "CLEAR_MONITOR_ACK0,Clearing of the external global exclusive monitor acknowledge. When set HIGH the processor EVENT registers have been set HIGH." "0,1" bitfld.long 0x0 13. "STANDBY_WFI_L20,L2 in WFI low power state indication" "0,1" newline bitfld.long 0x0 12. "L2_HW_FLUSH0,L2 hardware flush complete" "0,1" hexmask.long.byte 0x0 8.--11. 1. "SMPEN0,Corepac taking part in coherency indication" bitfld.long 0x0 7. "CPU3_WFE0,Reserved" "0,1" newline bitfld.long 0x0 6. "CPU2_WFE0,Reserved" "0,1" bitfld.long 0x0 5. "CPU1_WFE0,CPU in WFE state" "0,1" bitfld.long 0x0 4. "CPU0_WFE0,CPU in WFE state" "0,1" newline bitfld.long 0x0 3. "CPU3_WFI0,Reserved" "0,1" bitfld.long 0x0 2. "CPU2_WFI0,Reserved" "0,1" bitfld.long 0x0 1. "CPU1_WFI0,CPU in WFI state" "0,1" newline bitfld.long 0x0 0. "CPU0_WFI0,CPU in WFI state" "0,1" group.long 0x1030++0x7 line.long 0x0 "CC_PM_FFI_CONFIG_j,Power Management FFI Configuration Register for MSMC port j. Offset = 1030h*(j + 1); where j = 0h" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--6. "TIMEOUT_VAL,Selects one of the 8 timeout values in number of cycles.0h - 10241h - 40962h - 163843h - 655364h - 2621445h - 10485766h - 20971527h - 4194303" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "FORCE_TIMEOUT,Forces timeout interrupt." "0,1" newline bitfld.long 0x0 2. "EN_TIMEOUT_DETECT,Enables timeout detect for snoop commands in AXI2VBUSMC." "0,1" bitfld.long 0x0 1. "DIS_EGLN_EXTERNAL_FLUSH_CNTRL,Disables AXI2VBUSMC external port control to trigger FFI mode." "0,1" bitfld.long 0x0 0. "FFI_MODE_EN,Enables FFI mode." "0,1" line.long 0x4 "CC_MISC_CORE_CONFIG_j,MISC Core Configuration Register for MSMC port j. Offset = 1034h*(j + 1); where j = 0h" hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1.--2. "ARM_ALLOCATE_VALUE,Override value for allocation hint." "0,1,2,3" bitfld.long 0x4 0. "ARM_ALLOCATE_OVERRIDE,Control to override arm outer allocation hint." "0,1" tree.end tree "COMPUTE_CLUSTER0_ECC_AGGR" base ad:0x4D200C0000 rgroup.long 0x0++0x3 line.long 0x0 "GIC_ECC_AGGR_REV,IP revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "GIC_ECC_AGGR_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "GIC_ECC_AGGR_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator" group.long 0x3C++0x7 line.long 0x0 "GIC_ECC_AGGR_SEC_EOI_REG,EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "GIC_ECC_AGGR_SEC_STATUS_REG0,SEC interrupt status register 0." hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 5. "WRITE_PEND,Interrupt pending status for write_pend" "0,1" bitfld.long 0x4 4. "READ_PEND,Interrupt pending status for read_pend" "0,1" bitfld.long 0x4 3. "EDC_CTRL_PEND,Interrupt pending status for edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "LPI_RAMECC_PEND,Interrupt pending status for lpi_ramecc_pend" "0,1" bitfld.long 0x4 1. "ITE_RAMECC_PEND,Interrupt pending status for ite_ramecc_pend" "0,1" bitfld.long 0x4 0. "ICB_RAMECC_PEND,Interrupt pending status for icb_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "GIC_ECC_AGGR_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 5. "WRITE_ENABLE_SET,Interrupt enable set for write_pend" "0,1" bitfld.long 0x0 4. "READ_ENABLE_SET,Interrupt enable set for read_pend" "0,1" bitfld.long 0x0 3. "EDC_CTRL_ENABLE_SET,Interrupt enable set for edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_SET,Interrupt enable set for lpi_ramecc_pend" "0,1" bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_SET,Interrupt enable set for ite_ramecc_pend" "0,1" bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_SET,Interrupt enable set for icb_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "GIC_ECC_AGGR_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 5. "WRITE_ENABLE_CLR,Interrupt enable clear for write_pend" "0,1" bitfld.long 0x0 4. "READ_ENABLE_CLR,Interrupt enable clear for read_pend" "0,1" bitfld.long 0x0 3. "EDC_CTRL_ENABLE_CLR,Interrupt enable clear for edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_CLR,Interrupt enable clear for lpi_ramecc_pend" "0,1" bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_CLR,Interrupt enable clear for ite_ramecc_pend" "0,1" bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_CLR,Interrupt enable clear for icb_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "GIC_ECC_AGGR_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "GIC_ECC_AGGR_DED_STATUS_REG0,DED interrupt status register 0." hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 5. "WRITE_PEND,Interrupt pending status for write_pend" "0,1" bitfld.long 0x4 4. "READ_PEND,Interrupt pending status for read_pend" "0,1" bitfld.long 0x4 3. "EDC_CTRL_PEND,Interrupt pending status for edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "LPI_RAMECC_PEND,Interrupt pending status for lpi_ramecc_pend" "0,1" bitfld.long 0x4 1. "ITE_RAMECC_PEND,Interrupt pending status for ite_ramecc_pend" "0,1" bitfld.long 0x4 0. "ICB_RAMECC_PEND,Interrupt pending status for icb_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "GIC_ECC_AGGR_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 5. "WRITE_ENABLE_SET,Interrupt enable set for write_pend" "0,1" bitfld.long 0x0 4. "READ_ENABLE_SET,Interrupt enable set for read_pend" "0,1" bitfld.long 0x0 3. "EDC_CTRL_ENABLE_SET,Interrupt enable set for edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_SET,Interrupt enable set for lpi_ramecc_pend" "0,1" bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_SET,Interrupt enable set for ite_ramecc_pend" "0,1" bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_SET,Interrupt enable set for icb_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "GIC_ECC_AGGR_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 5. "WRITE_ENABLE_CLR,Interrupt enable clear for write_pend" "0,1" bitfld.long 0x0 4. "READ_ENABLE_CLR,Interrupt enable clear for read_pend" "0,1" bitfld.long 0x0 3. "EDC_CTRL_ENABLE_CLR,Interrupt enable clear for edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_CLR,Interrupt enable clear for lpi_ramecc_pend" "0,1" bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_CLR,Interrupt enable clear for ite_ramecc_pend" "0,1" bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_CLR,Interrupt enable clear for icb_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "GIC_ECC_AGGR_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "GIC_ECC_AGGR_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "GIC_ECC_AGGR_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "GIC_ECC_AGGR_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "COMPUTE_CLUSTER0_ECC_AGGR_CFG" base ad:0x4D200B0800 rgroup.long 0x0++0x3 line.long 0x0 "DDRSS_REV,Return to the . Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "DDRSS_VECTOR,Return to the . ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "DDRSS_STAT,Return to the . Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "DDRSS_RESERVED_SVBUS_y,Return to the . Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "DDRSS_SEC_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DDRSS_SEC_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 5. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "DDRSS_SEC_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "DDRSS_SEC_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "DDRSS_DED_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DDRSS_DED_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 5. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x4 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x4 3. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x4 2. "DST_M2P_BUSECC_PEND,Interrupt Pending Status for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x4 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x4 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "DDRSS_DED_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x0 3. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "DDRSS_DED_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1" newline bitfld.long 0x0 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x0 3. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1" newline bitfld.long 0x0 2. "DST_M2P_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_busecc_pend" "0,1" newline bitfld.long 0x0 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1" newline bitfld.long 0x0 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1" group.long 0x200++0xF line.long 0x0 "DDRSS_AGGR_ENABLE_SET,Return to the . AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "DDRSS_AGGR_ENABLE_CLR,Return to the . AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "DDRSS_AGGR_STATUS_SET,Return to the . AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "DDRSS_AGGR_STATUS_CLR,Return to the . AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "COMPUTE_CLUSTER0_ECC_AGGR_CTL" base ad:0x4D200B0000 rgroup.long 0x0++0x3 line.long 0x0 "DDRSS_REV,Return to the . Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "DDRSS_VECTOR,Return to the . ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "DDRSS_STAT,Return to the . Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "DDRSS_RESERVED_SVBUS_y,Return to the . Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "DDRSS_SEC_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DDRSS_SEC_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 3. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1" newline bitfld.long 0x4 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1" newline bitfld.long 0x4 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "DDRSS_SEC_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 3. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "DDRSS_SEC_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 3. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "DDRSS_DED_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DDRSS_DED_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x4 3. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1" newline bitfld.long 0x4 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1" newline bitfld.long 0x4 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "DDRSS_DED_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 3. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "DDRSS_DED_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1" newline bitfld.long 0x0 3. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1" newline bitfld.long 0x0 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1" newline bitfld.long 0x0 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1" newline bitfld.long 0x0 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1" group.long 0x200++0xF line.long 0x0 "DDRSS_AGGR_ENABLE_SET,Return to the . AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "DDRSS_AGGR_ENABLE_CLR,Return to the . AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "DDRSS_AGGR_STATUS_SET,Return to the . AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "DDRSS_AGGR_STATUS_CLR,Return to the . AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "COMPUTE_CLUSTER0_ECC_AGGR_VBUS" base ad:0x4D200B0400 rgroup.long 0x0++0x3 line.long 0x0 "DDRSS_REV,Return to the . Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "DDRSS_VECTOR,Return to the . ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "DDRSS_STAT,Return to the . Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "DDRSS_RESERVED_SVBUS_y,Return to the . Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "DDRSS_SEC_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DDRSS_SEC_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "DDRSS_SEC_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "DDRSS_SEC_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "DDRSS_DED_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "DDRSS_DED_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "DDRSS_DED_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "DDRSS_DED_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1" group.long 0x200++0xF line.long 0x0 "DDRSS_AGGR_ENABLE_SET,Return to the . AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "DDRSS_AGGR_ENABLE_CLR,Return to the . AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "DDRSS_AGGR_STATUS_SET,Return to the . AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "DDRSS_AGGR_STATUS_CLR,Return to the . AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "COMPUTE_CLUSTER0_MSMC_CFGS0" base ad:0x6E000000 rgroup.quad 0x0++0x7 line.quad 0x0 "MSMC_PID,Peripheral ID Register." hexmask.quad.long 0x0 32.--63. 1. "RESERVED,Reserved" hexmask.quad.long 0x0 0.--31. 1. "REVISION,PID Revision" group.quad 0x1000++0x7 line.quad 0x0 "MSMC_CACHE_CTRL,Cache Control Register." hexmask.quad 0x0 11.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 10. "ALLOCATION_POLICY,Allocation Policy" "0,1" rbitfld.quad 0x0 9. "RESERVED,Reserved" "0,1" newline bitfld.quad 0x0 8. "REPLACEMENT_POLICY,Replacement Policy" "0,1" rbitfld.quad 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.quad 0x0 4. "SZ_TRANSITION,Cache Size Change in Progress" "0,1" newline hexmask.quad.byte 0x0 0.--3. 1. "CACHE_SIZE,Cache Size Control" group.quad 0x1010++0xF line.quad 0x0 "MSMC_RT_WAY_SELECT,Real Time Way Select." hexmask.quad 0x0 7.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 5.--6. "OR_MASK,OR mask for way-select" "0,1,2,3" rbitfld.quad 0x0 2.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x0 0.--1. "AND_MASK,AND mask for way-select" "0,1,2,3" line.quad 0x8 "MSMC_NRT_WAY_SELECT,Non Real Time Way Select." hexmask.quad 0x8 7.--63. 1. "RESERVED,Reserved" bitfld.quad 0x8 5.--6. "OR_MASK,OR mask for way-select" "0,1,2,3" rbitfld.quad 0x8 2.--4. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x8 0.--1. "AND_MASK,AND mask for way-select" "0,1,2,3" group.quad 0x2048++0x7 line.quad 0x0 "MSMC_COHCTRL,Coherence Control Register." hexmask.quad 0x0 1.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 0. "BCM,Broadcast Mode" "0,1" group.quad 0x3080++0x7 line.quad 0x0 "MSMC_SMEDCC,Scrub Rate Register." hexmask.quad.long 0x0 32.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 31. "SEN,Scrub Engine Enable" "0,1" hexmask.quad.tbyte 0x0 8.--30. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x0 0.--7. 1. "REFDEL,Number of Clock Cycles Between Scrubs" rgroup.quad 0x5000++0xF line.quad 0x0 "MSMC_SMESTAT,Interrupt Enabled Status register. ANDed value of and ." hexmask.quad 0x0 1.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 0. "NULL_SLV,Null slave error is enabled and pending" "0,1" line.quad 0x8 "MSMC_SMIRSTAT,Interrupt raw status register." hexmask.quad 0x8 1.--63. 1. "RESERVED,Reserved" bitfld.quad 0x8 0. "NULL_SLV,Null slave error flagged" "0,1" group.quad 0x5008++0xF line.quad 0x0 "MSMC_SMIRWS,Set interrupt raw status register." hexmask.quad 0x0 1.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 0. "NULL_SLV,Set software null slave error" "0,1" line.quad 0x8 "MSMC_SMIRC,Interrupt clear register." hexmask.quad 0x8 1.--63. 1. "RESERVED,Reserved" bitfld.quad 0x8 0. "NULL_SLV,Clear null slave error flag" "0,1" rgroup.quad 0x5018++0x7 line.quad 0x0 "MSMC_SMIESTAT,Interrupt raw status register." hexmask.quad 0x0 1.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 0. "NULL_SLV,Null slave error interrupt is enabled" "0,1" group.quad 0x5018++0xF line.quad 0x0 "MSMC_SMIEWS,Set interrupt raw status register." hexmask.quad 0x0 1.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 0. "NULL_SLV,Enable null slave error" "0,1" line.quad 0x8 "MSMC_SMIEC,Interrupt clear register." hexmask.quad 0x8 1.--63. 1. "RESERVED,Reserved" bitfld.quad 0x8 0. "NULL_SLV,clear null slave error interrupt enable" "0,1" group.quad 0x6000++0x67 line.quad 0x0 "MSMC_SBNDCOH0,Starvation Bound for Coherent Port 0." hexmask.quad.byte 0x0 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x0 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x0 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x0 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x8 "MSMC_SBNDCOH1,Starvation Bound for Coherent Port 1. Not used on this device." hexmask.quad.byte 0x8 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x8 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x8 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x8 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x8 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x8 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x8 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x10 "MSMC_SBNDCOH2,Starvation Bound for Coherent Port 2. Not used on this device." hexmask.quad.byte 0x10 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x10 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x10 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x10 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x10 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x10 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x10 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x10 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x18 "MSMC_SBNDCOH3,Starvation Bound for Coherent Port 3. Not used on this device." hexmask.quad.byte 0x18 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x18 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x18 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x18 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x18 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x18 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x18 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x18 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x20 "MSMC_SBNDCOH4,Starvation Bound for Coherent Port 4. Not used on this device." hexmask.quad.byte 0x20 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x20 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x20 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x20 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x20 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x20 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x20 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x20 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x28 "MSMC_SBNDCOH5,Starvation Bound for Coherent Port 5. Not used on this device." hexmask.quad.byte 0x28 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x28 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x28 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x28 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x28 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x28 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x28 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x28 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x30 "MSMC_SBNDCOH6,Starvation Bound for Coherent Port 6. Not used on this device." hexmask.quad.byte 0x30 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x30 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x30 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x30 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x30 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x30 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x30 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x30 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x38 "MSMC_SBNDCOH7,Starvation Bound for Coherent Port 7. Not used on this device." hexmask.quad.byte 0x38 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x38 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x38 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x38 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x38 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x38 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x38 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x38 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x40 "MSMC_SBNDCOH8,Starvation Bound for Coherent Port 8. Not used on this device." hexmask.quad.byte 0x40 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x40 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x40 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x40 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x40 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x40 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x40 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x40 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x48 "MSMC_SBNDCOH9,Starvation Bound for Coherent Port 9. Not used on this device." hexmask.quad.byte 0x48 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x48 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x48 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x48 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x48 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x48 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x48 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x48 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x50 "MSMC_SBNDCOH10,Starvation Bound for Coherent Port 10. Not used on this device." hexmask.quad.byte 0x50 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x50 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x50 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x50 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x50 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x50 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x50 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x50 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x58 "MSMC_SBNDCOH11,Starvation Bound for Coherent Port 11." hexmask.quad.byte 0x58 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x58 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x58 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x58 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x58 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x58 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x58 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x58 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" line.quad 0x60 "MSMC_SBNDCOH12,Starvation Bound for Coherent Port 12." hexmask.quad.byte 0x60 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x60 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x60 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x60 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x60 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x60 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x60 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x60 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" group.quad 0x6100++0x7 line.quad 0x0 "MSMC_SBNDDRU,Starvation Bound for Data Routing Unit. Not used on this device." hexmask.quad.byte 0x0 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x0 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x0 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x0 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" group.quad 0x6200++0x7 line.quad 0x0 "MSMC_SBNDRESP,Starvation Bound for Read Response." hexmask.quad.byte 0x0 56.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory" hexmask.quad.byte 0x0 40.--47. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x0 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory" hexmask.quad.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory" newline hexmask.quad.byte 0x0 8.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory" group.quad 0x7000++0x7 line.quad 0x0 "MSMC_DBGTAGCTL,Debug Tag View Control." hexmask.quad.tbyte 0x0 41.--63. 1. "RESERVED,Reserved" bitfld.quad 0x0 40. "L3CACHE,Level 3 Cache Tag Select" "0,1" hexmask.quad.byte 0x0 34.--39. 1. "RESERVED,Reserved" newline bitfld.quad 0x0 32.--33. "BANK,Physical Bank Select" "0,1,2,3" rbitfld.quad 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.quad.word 0x0 16.--29. 1. "INDEX,Index Select" newline hexmask.quad.word 0x0 5.--15. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 0.--4. 1. "WAY,Way Select" rgroup.quad 0x7080++0x7 line.quad 0x0 "MSMC_DBGTAGVIEW,Debug Tag View Read." hexmask.quad.byte 0x0 59.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 54.--58. 1. "SF,Snoop Filter" bitfld.quad 0x0 53. "RESERVED,Reserved" "0,1" newline bitfld.quad 0x0 52. "DIRTY,Dirty" "0,1" bitfld.quad 0x0 51. "RESERVED,Reserved" "0,1" bitfld.quad 0x0 50. "DATA_VALID,Data Valid" "0,1" newline bitfld.quad 0x0 49. "RESERVED,Reserved" "0,1" bitfld.quad 0x0 48. "ADDR_VALID,Address Valid" "0,1" hexmask.quad 0x0 0.--47. 1. "ADDRESS,Tag Address" rgroup.quad 0xA000++0xF line.quad 0x0 "MSMC_NULL_SLV_STAT0,Null Slave Status 0." hexmask.quad 0x0 0.--63. 1. "ADDR,Address" line.quad 0x8 "MSMC_NULL_SLV_STAT1,Null Slave Status 1." hexmask.quad.word 0x8 54.--63. 1. "RESERVED,Reserved" bitfld.quad 0x8 52.--53. "PRIV,Privilege" "0,1,2,3" bitfld.quad 0x8 49.--51. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x8 48. "SECURE,Secure" "0,1" bitfld.quad 0x8 45.--47. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.quad 0x8 44. "EMU,Emulation" "0,1" newline bitfld.quad 0x8 42.--43. "RESERVED,Reserved" "0,1,2,3" bitfld.quad 0x8 40.--41. "MEMTYPE,Memory Type" "0,1,2,3" bitfld.quad 0x8 38.--39. "RESERVED,Reserved" "0,1,2,3" newline hexmask.quad.byte 0x8 32.--37. 1. "OPCODE,Opcode" hexmask.quad.byte 0x8 24.--31. 1. "PRIVID,Priv ID" hexmask.quad.word 0x8 12.--23. 1. "ROUTEID,Route ID" newline bitfld.quad 0x8 10.--11. "RESERVED,Reserved" "0,1,2,3" hexmask.quad.word 0x8 0.--9. 1. "BYTECNT,Byte Count" group.quad 0xA018++0x7 line.quad 0x0 "MSMC_NULL_SLV_CNT,Null Slave Error Count." hexmask.quad 0x0 8.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 0.--7. 1. "COUNT,Count" tree.end tree "COMPUTE_CLUSTER0_SS_CFG" base ad:0x2980000 rgroup.long 0x0++0x3 line.long 0x0 "DDRSS_SS_ID_REV_REG,Return to the . The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem." hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version" bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision" group.long 0x4++0x3 line.long 0x0 "DDRSS_SS_CTL_REG,Return to the . The Subsystem Control Register contains fields for control functions required for submodules in the subsystem." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "PHY_PLL_BYPASS,DDR PHY De-Skew PLL bypass.Write 1 to bypass PLL." "0,1" group.long 0x20++0x1F line.long 0x0 "DDRSS_V2A_CTL_REG,Return to the . The MSMC2DDR Bridge Control register contains control functions required for the MSMC2DDR Bridge submodule." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 17.--21. 1. "WR_LO_BLK_THR,Write data threshold in 64 byte quantas.The MSMC2DDR bridge will block all Low Priority Thread writes to DDR when the total number of write data bytes sent to the DDR controller is greater than this value. The reset value of this field is.." hexmask.long.byte 0x0 12.--16. 1. "CRIT_THRESH,Critical threshold.The MSMC2DDR bridge will block all Low Priority Thread traffic to DDR when the total number of commands sent to the DDR controller is greater than this value. The reset value of this field is optimal however it can be.." newline rbitfld.long 0x0 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0 10. "SDRAM_3QT,Setting this field to a 1 will modify SDRAM Index to be 3/4 its programmed value to support 3 6 12 and 24 GB sizes." "0,1" hexmask.long.byte 0x0 5.--9. 1. "SDRAM_IDX,SDRAM Index = log2(connected SDRAM size) - 16.The sdram_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Max size supported is.." newline hexmask.long.byte 0x0 0.--4. 1. "REGION_IDX,Region Index = log2(CBA region size) - 16.The region_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Max size supported is.." line.long 0x4 "DDRSS_V2A_R1_MAT_REG,Return to the . The Range 1 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 1 Match Register uses.." bitfld.long 0x4 31. "RANGE1_RANGEEN_A,The range1_rangeen_a enables the RouteID AND'd with range1_mask_a to match the range1_routeid_a" "0,1" bitfld.long 0x4 28.--30. "RANGE1_MASK_A,The range1_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 16.--27. 1. "RANGE1_ROUTEID_A,The range1_routeid_a is the value that is compared to the RouteID arriving on the command interface" newline bitfld.long 0x4 15. "RANGE1_RANGEEN_B,The range1_rangeen_b enables the RouteID AND'd with range1_mask_b to match the range1_routeid_b" "0,1" bitfld.long 0x4 12.--14. "RANGE1_MASK_B,The range1_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--11. 1. "RANGE1_ROUTEID_B,The range1_routeid_b is the value that is compared to the RouteID arriving on the command interface" line.long 0x8 "DDRSS_V2A_R2_MAT_REG,Return to the . The Range 2 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 2 Match Register uses.." bitfld.long 0x8 31. "RANGE2_RANGEEN_A,The range2_rangeen_a enables the RouteID AND'd with range2_mask_a to match the range2_routeid_a" "0,1" bitfld.long 0x8 28.--30. "RANGE2_MASK_A,The range2_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--27. 1. "RANGE2_ROUTEID_A,The range2_routeid_a is the value that is compared to the RouteID arriving on the command interface" newline bitfld.long 0x8 15. "RANGE2_RANGEEN_B,The range2_rangeen_b enables the RouteID AND'd with range2_mask_b to match the range2_routeid_b" "0,1" bitfld.long 0x8 12.--14. "RANGE2_MASK_B,The range2_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--11. 1. "RANGE2_ROUTEID_B,The range2_routeid_b is the value that is compared to the RouteID arriving on the command interface" line.long 0xC "DDRSS_V2A_R3_MAT_REG,Return to the . The Range 3 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 3 Match Register uses.." bitfld.long 0xC 31. "RANGE3_RANGEEN_A,The range3_rangeen_a enables the RouteID AND'd with range3_mask_a to match the range3_routeid_a" "0,1" bitfld.long 0xC 28.--30. "RANGE3_MASK_A,The range3_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7" hexmask.long.word 0xC 16.--27. 1. "RANGE3_ROUTEID_A,The range3_routeid_a is the value that is compared to the RouteID arriving on the command interface" newline bitfld.long 0xC 15. "RANGE3_RANGEEN_B,The range3_rangeen_b enables the RouteID AND'd with range3_mask_b to match the range3_routeid_b" "0,1" bitfld.long 0xC 12.--14. "RANGE3_MASK_B,The range3_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7" hexmask.long.word 0xC 0.--11. 1. "RANGE3_ROUTEID_B,The range3_routeid_b is the value that is compared to the RouteID arriving on the command interface" line.long 0x10 "DDRSS_V2A_LPT_DEF_PRI_MAP_REG,Return to the . The LPT Default Priority Mapping Register is the default map for the inbound VBUSM.C priority on the Low Priority Thread to AXI priority." rbitfld.long 0x10 31. "RESERVED,Reserved" "0,1" bitfld.long 0x10 28.--30. "LPT_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x10 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 24.--26. "LPT_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x10 23. "RESERVED,Reserved" "0,1" bitfld.long 0x10 20.--22. "LPT_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x10 19. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--18. "LPT_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x10 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 12.--14. "LPT_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x10 11. "RESERVED,Reserved" "0,1" bitfld.long 0x10 8.--10. "LPT_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--6. "LPT_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x10 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 0.--2. "LPT_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x14 "DDRSS_V2A_LPT_R1_PRI_MAP_REG,Return to the . The LPT Range 1 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 1 occurs. This allows the priority level to be changed from.." rbitfld.long 0x14 31. "RESERVED,Reserved" "0,1" bitfld.long 0x14 28.--30. "LPT_RANGE1_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x14 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 24.--26. "LPT_RANGE1_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x14 23. "RESERVED,Reserved" "0,1" bitfld.long 0x14 20.--22. "LPT_RANGE1_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x14 19. "RESERVED,Reserved" "0,1" bitfld.long 0x14 16.--18. "LPT_RANGE1_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 12.--14. "LPT_RANGE1_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x14 11. "RESERVED,Reserved" "0,1" bitfld.long 0x14 8.--10. "LPT_RANGE1_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--6. "LPT_RANGE1_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x14 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 0.--2. "LPT_RANGE1_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x18 "DDRSS_V2A_LPT_R2_PRI_MAP_REG,Return to the . The LPT Range 2 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 2 occurs. This allows the priority level to be changed from.." rbitfld.long 0x18 31. "RESERVED,Reserved" "0,1" bitfld.long 0x18 28.--30. "LPT_RANGE2_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x18 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x18 24.--26. "LPT_RANGE2_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x18 23. "RESERVED,Reserved" "0,1" bitfld.long 0x18 20.--22. "LPT_RANGE2_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x18 19. "RESERVED,Reserved" "0,1" bitfld.long 0x18 16.--18. "LPT_RANGE2_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x18 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x18 12.--14. "LPT_RANGE2_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x18 11. "RESERVED,Reserved" "0,1" bitfld.long 0x18 8.--10. "LPT_RANGE2_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--6. "LPT_RANGE2_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x18 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x18 0.--2. "LPT_RANGE2_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x1C "DDRSS_V2A_LPT_R3_PRI_MAP_REG,Return to the . The LPT Range 3 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 3 occurs. This allows the priority level to be changed from.." rbitfld.long 0x1C 31. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 28.--30. "LPT_RANGE3_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x1C 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x1C 24.--26. "LPT_RANGE3_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x1C 23. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 20.--22. "LPT_RANGE3_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x1C 19. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 16.--18. "LPT_RANGE3_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x1C 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x1C 12.--14. "LPT_RANGE3_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x1C 11. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 8.--10. "LPT_RANGE3_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--6. "LPT_RANGE3_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x1C 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x1C 0.--2. "LPT_RANGE3_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" group.long 0x4C++0xF line.long 0x0 "DDRSS_V2A_HPT_DEF_PRI_MAP_REG,Return to the . The HPT Default Priority Mapping Register is the default map for the inbound VBUSM.C priority on the High Priority Thread to the AXI priority." rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" bitfld.long 0x0 28.--30. "HPT_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 24.--26. "HPT_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x0 23. "RESERVED,Reserved" "0,1" bitfld.long 0x0 20.--22. "HPT_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x0 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0 16.--18. "HPT_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 12.--14. "HPT_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x0 11. "RESERVED,Reserved" "0,1" bitfld.long 0x0 8.--10. "HPT_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0 4.--6. "HPT_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "HPT_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x4 "DDRSS_V2A_HPT_R1_PRI_MAP_REG,Return to the . The HPT Range 1 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 1 occurs. This allows the priority level to be changed.." rbitfld.long 0x4 31. "RESERVED,Reserved" "0,1" bitfld.long 0x4 28.--30. "HPT_RANGE1_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x4 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24.--26. "HPT_RANGE1_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x4 23. "RESERVED,Reserved" "0,1" bitfld.long 0x4 20.--22. "HPT_RANGE1_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x4 19. "RESERVED,Reserved" "0,1" bitfld.long 0x4 16.--18. "HPT_RANGE1_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x4 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 12.--14. "HPT_RANGE1_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x4 11. "RESERVED,Reserved" "0,1" bitfld.long 0x4 8.--10. "HPT_RANGE1_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "HPT_RANGE1_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 0.--2. "HPT_RANGE1_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 1.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x8 "DDRSS_V2A_HPT_R2_PRI_MAP_REG,Return to the . The HPT Range 2 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 2 occurs. This allows the priority level to be changed.." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 28.--30. "HPT_RANGE2_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x8 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 24.--26. "HPT_RANGE2_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" bitfld.long 0x8 20.--22. "HPT_RANGE2_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x8 19. "RESERVED,Reserved" "0,1" bitfld.long 0x8 16.--18. "HPT_RANGE2_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x8 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 12.--14. "HPT_RANGE2_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x8 11. "RESERVED,Reserved" "0,1" bitfld.long 0x8 8.--10. "HPT_RANGE2_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0x8 7. "RESERVED,Reserved" "0,1" bitfld.long 0x8 4.--6. "HPT_RANGE2_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0x8 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 0.--2. "HPT_RANGE2_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 2.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0xC "DDRSS_V2A_HPT_R3_PRI_MAP_REG,Return to the . The HPT Range 3 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 3 occurs. This allows the priority level to be changed.." rbitfld.long 0xC 31. "RESERVED,Reserved" "0,1" bitfld.long 0xC 28.--30. "HPT_RANGE3_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0xC 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC 24.--26. "HPT_RANGE3_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0xC 23. "RESERVED,Reserved" "0,1" bitfld.long 0xC 20.--22. "HPT_RANGE3_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0xC 19. "RESERVED,Reserved" "0,1" bitfld.long 0xC 16.--18. "HPT_RANGE3_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0xC 15. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC 12.--14. "HPT_RANGE3_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0xC 11. "RESERVED,Reserved" "0,1" bitfld.long 0xC 8.--10. "HPT_RANGE3_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline rbitfld.long 0xC 7. "RESERVED,Reserved" "0,1" bitfld.long 0xC 4.--6. "HPT_RANGE3_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" rbitfld.long 0xC 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC 0.--2. "HPT_RANGE3_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 3.0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" group.long 0x70++0x3 line.long 0x0 "DDRSS_V2A_AERR_LOG1_REG,Return to the . The Address Error Log 1 register displays the RouteID and lsb of the address for the first VBUSM.C command that was outside the programmed addressing range. Writing a 0x1 will clear all fields. Writing any other.." hexmask.long.word 0x0 16.--31. 1. "AERR_ADDR_LSB,Address[15:0] of the VBUSM.C command" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "AERR_ROUTE_ID,RouteID of the VBUSM.C write command" rgroup.long 0x74++0x3 line.long 0x0 "DDRSS_V2A_AERR_LOG2_REG,Return to the . The Address Error Log 2 registers displays the msb of the address for the first VBUSM.C command that was outside the programmed addressing range. This register will be cleared upon writing the Address Error Log 1.." hexmask.long 0x0 0.--31. 1. "AERR_ADDR_MSB,Address[34:16] of the VBUSM.C command" group.long 0x78++0x3 line.long 0x0 "DDRSS_V2A_OERR_LOG_REG,Return to the . The Opcode Error Log register displays the RouteID and opcode for the first VBUSM.C command that had an unsupported opcode. Writing a 0x1 will clear all fields. Writing any other value has no effect." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--17. 1. "OERR_OP_CODE,Opcode of the VBUSM.C command" hexmask.long.word 0x0 0.--11. 1. "OERR_ROUTE_ID,RouteID of the VBUSM.C command" group.long 0x80++0x7 line.long 0x0 "DDRSS_V2A_1B_ERR_CNT_REG,Return to the . MSMC2DDR Bridge 1-Bit EDC Error Count Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "EDC_1B_ERR_CNT,16-bit counter that displays number of 1-bit EDC errors on write data received on the VBUSM.C interface. Writing a 0x1 will clear this count. Writing any other value has no effect." line.long 0x4 "DDRSS_V2A_1B_ERR_LOG1_REG,Return to the . The 1-Bit EDC Error Log 1 register displays the RouteID and error position of the first VBUSM.C write that incurred 1-bit EDC error. Writing a 0x1 will clear all fields. Writing any other value has no effect. The.." hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 16.--24. 1. "ERR_POS_1B,Bit error position" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "ROUTE_ID_1B,RouteID of the VBUSM.C write command" rgroup.long 0x88++0x3 line.long 0x0 "DDRSS_V2A_1B_ERR_LOG2_REG,Return to the . The 1-Bit EDC Error Log 2 registers displays the address of the first VBUSM.C write that incurred 1-bit EDC error. This register will be cleared upon writing the 1-Bit EDC Error Log 1 register." bitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long 0x0 0.--29. 1. "ADDR_MSB_1B,Address[34:5] of the VBUSM.C write command" group.long 0x8C++0x3 line.long 0x0 "DDRSS_V2A_2B_ERR_LOG1_REG,Return to the . The 2-Bit EDC Error Log 1 register displays the RouteID of the first VBUSM.C write that incurred 2-bit EDC error. Writing a 0x1 clear all fields. Writing any other value has no effect. The 2-Bit EDC Error Log 2.." hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "ROUTE_ID_2B,RouteID of the VBUSM.C write command" rgroup.long 0x90++0x3 line.long 0x0 "DDRSS_V2A_2B_ERR_LOG2_REG,Return to the . The 2-Bit EDC Error Log 1 register displays the address of the first VBUSM.C write that incurred 2-bit EDC error. This register will be cleared upon writing the 2-Bit EDC Error Log 1 register." bitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long 0x0 0.--29. 1. "ADR_MSB_2B,Address[34:5] of the VBUSM.C write command" group.long 0x9C++0x17 line.long 0x0 "DDRSS_V2A_BUS_TO,Return to the . MSMC2DDR Bridge Bus Timeout Register" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x0 0.--23. 1. "BUS_TIMER,AXI bus timeout value.Number of DDR clock cycles after which the MSMC2DDR bridge times out if a hang on the controller AXI interface is detected. A value of N will be equal to N x 16 clocks. Writing a 0 will disable the timeout feature." line.long 0x4 "DDRSS_V2A_INT_RAW_REG,Return to the . MSMC2DDR Bridge Interrupt Raw Status Register" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 5. "ECCM1BERR,Raw status of SDRAM ECC multi 1-bit errors in same SDRAM burst.Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x4 4. "ECC2BERR,Raw status of SDRAM ECC 2-bit error.Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 3. "ECC1BERR,Raw status of SDRAM ECC 1-bit error.Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x4 2. "TOERR,Raw status of MSMC2DDR Bridge interrupt for controller AXI interface timeout.Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x4 1. "AERR,Raw status of MSMC2DDR Bridge interrupt for VBUSM.C address outside the programmed range.Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 0. "OERR,Raw status of MSMC2DDR Bridge interrupt for VBUSM.C unsupported opcode.Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" line.long 0x8 "DDRSS_V2A_INT_STAT_REG,Return to the . MSMC2DDR Bridge Interrupt Status Register" hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 5. "ECCM1BERR,Enabled status of SDRAM ECC multi 1-bit errors in same SDRAM burst.Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x8 4. "ECC2BERR,Enabled status of SDRAM ECC 2-bit error.Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 3. "ECC1BERR,Enabled status of SDRAM ECC 1-bit error.Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "TOERR,Enabled status of MSMC2DDR Bridge interrupt for controller AXI interface timeout.Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x8 1. "AERR,Enabled status of MSMC2DDR Bridge interrupt for VBUSM.C address outside the programmed range.Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "OERR,Enabled status of MSMC2DDR Bridge interrupt for VBUSM.C unsupported opcode.Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" line.long 0xC "DDRSS_V2A_INT_SET_REG,Return to the . MSMC2DDR Bridge Interrupt Enable Set Register" hexmask.long 0xC 6.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 5. "ECCM1BERR_EN,Enable set for SDRAM ECC multi1-bit errors in same SDRAM burst. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 4. "ECC2BERR_EN,Enable set for SDRAM ECC2-bit error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 3. "ECC1BERR_EN,Enable set for SDRAM ECC1-bit error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 2. "TOERR_EN,Enable set for MSMC2DDR Bridge interrupt for controller AXI interface timeout.Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0xC 1. "AERR_EN,Enable set for MSMC2DDR Bridge interrupt for VBUSM.C address outside the programmed range.Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "OERR_EN,Enable set for MSMC2DDR Bridge interrupt for VBUSM.C unsupported opcode.Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0x10 "DDRSS_V2A_INT_CLR_REG,Return to the . MSMC2DDR Bridge Interrupt Enable Clear Register" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 5. "ECCM1BERR_EN,Enable clear for SDRAM ECC multi1-bit errors in same SDRAM burst. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 4. "ECC2BERR_EN,Enable clear for SDRAM ECC2-bit error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 3. "ECC1BERR_EN,Enable clear for SDRAM ECC1-bit error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "TOERR_EN,Enable clear for MSMC2DDR Bridge interrupt for controller AXI interface timeout.Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x10 1. "AERR_EN,Enable clear for MSMC2DDR Bridge interrupt for VBUSM.C address outside the programmed range.Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "OERR_EN,Enable clear for MSMC2DDR Bridge interrupt for VBUSM.C unsupported opcode.Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" line.long 0x14 "DDRSS_V2A_EOI_REG,Return to the . MSMC2DDR Bridge End of Interrupt Register" hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "EOI,Software End Of Interrupt (EOI) control.Write 0 for aerr/oerr/toerr interrupt. Write 1 for ecc1b interrupt. Write 2 for ecc2b interrupt. This field always reads 0 (no EOI memory)." "0,1,2,3" group.long 0x100++0x3 line.long 0x0 "DDRSS_PERF_CNT_SEL_REG,Return to the . The Performance Counter Select register is used to select the statistic type to be counted in the corresponding Performance Counter register." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "CNT4_SEL,Statistic select for Performance Counter 4 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every Precharge.." rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "CNT3_SEL,Statistic select for Performance Counter 3 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every Precharge.." rbitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "CNT2_SEL,Statistic select for Performance Counter 2 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every Precharge.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "CNT1_SEL,Statistic select for Performance Counter 1 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every Precharge.." rgroup.long 0x104++0xF line.long 0x0 "DDRSS_PERF_CNT1_REG,Return to the . Performance Counter 1 Register" hexmask.long 0x0 0.--31. 1. "CNT1,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register." line.long 0x4 "DDRSS_PERF_CNT2_REG,Return to the . Performance Counter 2 Register" hexmask.long 0x4 0.--31. 1. "CNT2,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register." line.long 0x8 "DDRSS_PERF_CNT3_REG,Return to the . Performance Counter 3 Register" hexmask.long 0x8 0.--31. 1. "CNT3,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register." line.long 0xC "DDRSS_PERF_CNT4_REG,Return to the . Performance Counter 4 Register" hexmask.long 0xC 0.--31. 1. "CNT4,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register." group.long 0x120++0xB line.long 0x0 "DDRSS_ECC_CTRL_REG,Return to the . ECC Control Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "COR_ECC_THRESH,Threshold for1-bit ECC errors in multiple data words in an SDRAM burst that create an uncorrected error fault indication. Value of 0/1 means 2 or more 1-bit errors in multiple data words will result in an uncorrected error fault.." rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "WR_ALLOC,When set to 1 an unassigned ECC cache-line will be allocated for a write with routeID that do not match any of the mapped routeID's." "0,1" rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" bitfld.long 0x0 2. "ECC_CK,Set 1 to enable ECC verification for read accesses when ecc_en=1.The value of this field is ignored when ecc_en=0. This bit must be set and kept static before using DDR." "0,1" newline bitfld.long 0x0 1. "RMW_EN,Read modify write enable.Set 1 to enable RMW functionality for sub-quanta accesses when ecc_en=1. This bit must be set to 1 if ecc_en is set to a 1 to ensure subquanta accesses to DRAM do not result in ECC errors. This bit must be set and kept.." "0,1" bitfld.long 0x0 0. "ECC_EN,DRAM ECC enable.Setting a 1 causes ECC to be written to DRAM. This bit must be set and kept static before using DDR." "0,1" line.long 0x4 "DDRSS_ECC_RID_INDX_REG,Return to the . ECC Cache RouteID Index Register" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--5. 1. "ECCRID_ADR,This index specifies the ECC cache entry number that the eccrid_val is mapped to." line.long 0x8 "DDRSS_ECC_RID_VAL_REG,Return to the . ECC Cache RouteID Write Value Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "ECCRID_VAL_VLD,A 1 in this field indicates that value in eccrid_val is valid." "0,1" rbitfld.long 0x8 12.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--11. 1. "ECCRID_VAL,RouteID value written or read." group.long 0x130++0x17 line.long 0x0 "DDRSS_ECC_R0_STR_ADDR_REG,Return to the . ECC Range 0 Start Address Register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x0 0.--18. 1. "ECC_STR_ADR_0,Start caddress[34:16] for ECC range 0. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0x4 "DDRSS_ECC_R0_END_ADDR_REG,Return to the . ECC Range 0 End Address Register" hexmask.long.word 0x4 19.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--18. 1. "ECC_END_ADR_0,End caddress[34:16] for ECC range 0. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0x8 "DDRSS_ECC_R1_STR_ADDR_REG,Return to the . ECC Range 1 Start Address Register" hexmask.long.word 0x8 19.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x8 0.--18. 1. "ECC_STR_ADR_1,Start caddress[34:16] for ECC range 1. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0xC "DDRSS_ECC_R1_END_ADDR_REG,Return to the . ECC Range 1 End Address Register" hexmask.long.word 0xC 19.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0xC 0.--18. 1. "ECC_END_ADR_1,End caddress[34:16] for ECC range 1. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0x10 "DDRSS_ECC_R2_STR_ADDR_REG,Return to the . ECC Range 2 Start Address Register" hexmask.long.word 0x10 19.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x10 0.--18. 1. "ECC_STR_ADR_2,Start caddress[34:16] for ECC range 2. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0x14 "DDRSS_ECC_R2_END_ADDR_REG,Return to the . ECC Range 2 End Address Register" hexmask.long.word 0x14 19.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x14 0.--18. 1. "ECC_END_ADR_2,End caddress[34:16] for ECC range 2. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." group.long 0x150++0xB line.long 0x0 "DDRSS_ECC_1B_ERR_CNT_REG,Return to the . ECC 1-Bit Error Count Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "ECC_1B_ERR_CNT,16-bit counter that displays number of 1-bit ECC errors on SDRAM data. Writing a 0x1 will clear this count. Writing any other value has no effect." line.long 0x4 "DDRSS_ECC_1B_ERR_THRSH_REG,Return to the . ECC 1-Bit Error Threshold Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "ECC_1B_ERR_THRSH,ECC1-bit error threshold. The bridge will generate an interrupt when the ECC 1-bit error count is equal to or greater than this threshold. A value of 0 will disable the generation of interrupt." line.long 0x8 "DDRSS_ECC_1B_ERR_ADR_LOG_REG,Return to the . ECC 1-Bit Error Address Log Register" rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long 0x8 0.--29. 1. "ECC_1B_ERR_ADR,ECC1-bit error address. 32-byte aligned address that had the 1-bit ECC error. This field displays the first address logged in the 2 deep logging FIFO. Writing a 0x1 will pop the top element of the FIFO. Writing any other value has no effect." rgroup.long 0x15C++0x3 line.long 0x0 "DDRSS_ECC_1B_ERR_MSK_LOG_REG,Return to the . ECC 1-Bit Error Mask Log Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "ECC_1B_ERR_MSK,ECC1-bit error mask. Mask for the 64-byte data block that had the 1-bit ECC errors. Each bit represents an ECC quanta (8 bytes) in the 64-byte data block starting at address specified by ecc_1b_err_adr. Value of 1 on the bit represents an.." group.long 0x160++0x3 line.long 0x0 "DDRSS_ECC_2B_ERR_ADR_LOG_REG,Return to the . ECC 2-Bit Error Address Log Register" rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long 0x0 0.--29. 1. "ECC_2B_ERR_ADR,ECC2-bit error address. 32-byte aligned address that had the 2-bit ECC error. Writing a 0x1 will clear this field and the ecc_2b_err_msk field. Writing any other value has no effect." rgroup.long 0x164++0x3 line.long 0x0 "DDRSS_ECC_2B_ERR_MSK_LOG_REG,Return to the . ECC 2-Bit Error Mask Log Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "ECC_2B_ERR_MSK,ECC2-bit error mask. Mask for the 64-byte data block that had the 2-bit ECC errors. Each bit represents an ECC quanta (8 bytes) in the 64-byte data block starting at address specified by ecc_2b_err_adr. Value of 1 on the bit represents an.." group.long 0x180++0x3 line.long 0x0 "DDRSS_PHY_BIST_CTRL_REG,Return to the . PHY BIST Control Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "BIST_TSEL_SELECT,This field controls the bist_tsel_select input of the PHY.For details please refer to the PHY specification." tree.end tree.end tree "CPSW" base ad:0x0 tree "CPSW0_ECC" base ad:0x2A21000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_ECC_REV,Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "CPSW_ECC_VECTOR,ECC Vector Register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address." bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "CPSW_ECC_STAT,Misc Status." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator." group.long 0x10++0x3 line.long 0x0 "CPSW_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data." group.long 0x3C++0x7 line.long 0x0 "CPSW_ECC_SEC_EOI_REG,EOI Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register." "0,1" line.long 0x4 "CPSW_ECC_SEC_STATUS_REG0,Interrupt Status Register 0." hexmask.long.word 0x4 20.--31. 1. "RESERVED" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend." "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend." "0,1" bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend." "0,1" newline bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend." "0,1" bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend." "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend." "0,1" bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend." "0,1" newline bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend." "0,1" bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend." "0,1" bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend." "0,1" bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend." "0,1" newline bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend." "0,1" bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend." "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend." "0,1" bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend." "0,1" newline bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend." "0,1" bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend." "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend." "0,1" bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend." "0,1" newline bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "CPSW_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend." "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend." "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend." "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend." "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend." "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend." "0,1" bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend." "0,1" newline bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend." "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend." "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend." "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend." "0,1" newline bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend." "0,1" bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend." "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend." "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend." "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend." "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend." "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend." "0,1" bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend." "0,1" newline bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend." "0,1" group.long 0xC0++0x3 line.long 0x0 "CPSW_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend." "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend." "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend." "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend." "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend." "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend." "0,1" bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend." "0,1" newline bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend." "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend." "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend." "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend." "0,1" newline bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend." "0,1" bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend." "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend." "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend." "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend." "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend." "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend." "0,1" bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend." "0,1" newline bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend." "0,1" group.long 0x13C++0x7 line.long 0x0 "CPSW_ECC_DED_EOI_REG,EOI Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register." "0,1" line.long 0x4 "CPSW_ECC_DED_STATUS_REG0,Interrupt Status Register 0." hexmask.long.word 0x4 20.--31. 1. "RESERVED" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend." "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend." "0,1" bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend." "0,1" newline bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend." "0,1" bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend." "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend." "0,1" bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend." "0,1" newline bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend." "0,1" bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend." "0,1" bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend." "0,1" bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend." "0,1" newline bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend." "0,1" bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend." "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend." "0,1" bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend." "0,1" newline bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend." "0,1" bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend." "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend." "0,1" bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend." "0,1" newline bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "CPSW_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend." "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend." "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend." "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend." "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend." "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend." "0,1" bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend." "0,1" newline bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend." "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend." "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend." "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend." "0,1" newline bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend." "0,1" bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend." "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend." "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend." "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend." "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend." "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend." "0,1" bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend." "0,1" newline bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend." "0,1" group.long 0x1C0++0x3 line.long 0x0 "CPSW_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend." "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend." "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend." "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend." "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend." "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend." "0,1" bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend." "0,1" newline bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend." "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend." "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend." "0,1" newline bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend." "0,1" bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend." "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend." "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend." "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend." "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend." "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend." "0,1" bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend." "0,1" newline bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend." "0,1" group.long 0x200++0xF line.long 0x0 "CPSW_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for SVBUS timeout errors." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors." "0,1" line.long 0x4 "CPSW_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register." hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for SVBUS timeout errors." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors." "0,1" line.long 0x8 "CPSW_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register." hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for SVBUS timeout errors." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors." "0,1,2,3" line.long 0xC "CPSW_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register." hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for SVBUS timeout errors." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors." "0,1,2,3" tree.end tree "CPSW0_NUSS_ALE" base ad:0xC000000 rgroup.long 0x3E000++0x7 line.long 0x0 "CPSW_ALE_MOD_VER,The Module and Version Register identifies the module identifier and revision of the ALE module." hexmask.long.word 0x0 16.--31. 1. "MODULE_ID,ALE module ID." hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version." bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision." line.long 0x4 "CPSW_ALE_STATUS,The ALE status provides information on the ALE configuration and state. The RAMDEPTH is used to determine how IPv6 entries are stored in the table. IPv6 entries are stored in two entries where IPv6 Entry Hi is designated by the odd slice.." bitfld.long 0x4 31. "UREGANDREGMSK12,When set the unregistered multicast field is a mask versus an index on 12 bit boundary in the ALE table." "0,1" bitfld.long 0x4 30. "UREGANDREGMSK08,When set the unregistered multicast field is a mask versus an index on 8 bit boundary in the ALE table." "0,1" hexmask.long.word 0x4 16.--29. 1. "RESERVED" newline hexmask.long.byte 0x4 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8." bitfld.long 0x4 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both ramdepth128 and ramdepth32 are zero the depth is 64." "0,1" bitfld.long 0x4 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both ramdepth128 and ramdepth32 are zero the depth is 64." "0,1" newline bitfld.long 0x4 5. "RESERVED" "0,1" hexmask.long.byte 0x4 0.--4. 1. "KLUENTRIES,This is the number of table entries total divided by 1024." group.long 0x3E008++0xF line.long 0x0 "CPSW_ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports." bitfld.long 0x0 31. "ENABLE_ALE,Enable ALE." "0,1" bitfld.long 0x0 30. "CLEAR_TABLE,Clear ALE address table. Setting this bit causes the ALE hardware to write all table bit values to zero." "0,1" bitfld.long 0x0 29. "AGE_OUT_NOW,Age Out Address Table Now. Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit." "0,1" newline bitfld.long 0x0 27.--28. "RESERVED" "0,1,2,3" bitfld.long 0x0 24.--26. "MIRROR_DP,Mirror Destination Port. This field defines the port to which destination traffic destined will be duplicated." "0,1,2,3,4,5,6,7" bitfld.long 0x0 21.--23. "UPD_BW_CTRL,The UPD_BW_CTRL field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19.--20. "RESERVED" "0,1,2,3" bitfld.long 0x0 16.--18. "MIRROR_TOP,Mirror To Port. This field defines the destination port for the mirror traffic." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "UPD_STATIC,Update Static Entries. A static Entry is an entry that is not agable." "0,1" newline bitfld.long 0x0 14. "RESERVED" "0,1" bitfld.long 0x0 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn. This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled." "0,1" bitfld.long 0x0 12. "MIRROR_MEN,Mirror Match Entry Enable. This field enables the match mirror option." "0,1" newline bitfld.long 0x0 11. "MIRROR_DEN,Mirror Destination Port Enable. This field enables the destination port mirror option." "0,1" bitfld.long 0x0 10. "MIRROR_SEN,Mirror Source Port Enable. This field enables the source port mirror option." "0,1" bitfld.long 0x0 9. "RESERVED" "0,1" newline bitfld.long 0x0 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host." "0,1" bitfld.long 0x0 7. "LEARN_NO_VLANID,Learn No VID." "0,1" bitfld.long 0x0 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode." "0,1" newline bitfld.long 0x0 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode. When set any packet with a non-matching OUI source address will be dropped to the host unless the packet destination address matches a supervisory destination address table entry." "0,1" bitfld.long 0x0 4. "ENABLE_BYPASS,ALE Bypass. When set packets received on non-host ports are sent to the host." "0,1" bitfld.long 0x0 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode." "0,1" newline bitfld.long 0x0 2. "ALE_VLAN_AWARE,ALE VLAN Aware. Determines how traffic is forwarded using VLAN rules." "0,1" bitfld.long 0x0 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode. Mac authorization mode requires that all table entries be made by the host software." "0,1" bitfld.long 0x0 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit" "0,1" line.long 0x4 "CPSW_ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports." bitfld.long 0x4 31. "TRK_EN_DST,Trunk Enable Destination Address. This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" bitfld.long 0x4 30. "TRK_EN_SRC,Trunk Enable Source Address. This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" bitfld.long 0x4 29. "TRK_EN_PRI,Trunk Enable Priority. This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" newline bitfld.long 0x4 28. "RESERVED" "0,1" bitfld.long 0x4 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN. This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" bitfld.long 0x4 26. "RESERVED" "0,1" newline bitfld.long 0x4 25. "TRK_EN_SIP,Trunk Enable Source IP Address. This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" bitfld.long 0x4 24. "TRK_EN_DIP,Trunk Enable Destination IP Address. This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" bitfld.long 0x4 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet." "0,1" newline bitfld.long 0x4 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set." "0,1" bitfld.long 0x4 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found." "0,1" bitfld.long 0x4 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match the" "0,1" newline bitfld.long 0x4 19. "RESERVED" "0,1" bitfld.long 0x4 16.--18. "TRK_BASE,Trunk Base - This field is the hash formula starting value." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 9.--15. 1. "RESERVED" newline hexmask.long.word 0x4 0.--8. 1. "MIRROR_MIDX,Mirror Index. This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the MIRROR_TOP port." line.long 0x8 "CPSW_ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "ALE_PRESCALE,ALE Prescale. The input clock is divided by this value for use in the multicast/broadcast rate limiters." line.long 0xC "CPSW_ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur. This value specifies the minimum time between aging starts." bitfld.long 0xC 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable. When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1" bitfld.long 0xC 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable. When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1" hexmask.long.byte 0xC 24.--29. 1. "RESERVED" newline hexmask.long.tbyte 0xC 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer." group.long 0x3E01C++0x7 line.long 0x0 "CPSW_ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header. It is enabled via the DEFLMTNXTHDR bit in the VLAN entry. All four IP_NXT_HDR0 to IP_NXT_HDR3 bits are compared when enabled. so if.." hexmask.long.byte 0x0 24.--31. 1. "IP_NXT_HDR3,The IP_NXT_HDR3 is the forth protocol or next header compared when enabled." hexmask.long.byte 0x0 16.--23. 1. "IP_NXT_HDR2,The IP_NXT_HDR2 is the third protocol or next header compared when enabled." hexmask.long.byte 0x0 8.--15. 1. "IP_NXT_HDR1,The IP_NXT_HDR1 is the second protocol or next header compared when enabled." newline hexmask.long.byte 0x0 0.--7. 1. "IP_NXT_HDR0,The IP_NXT_HDR0 is the first protocol or next header compared when enabled." line.long 0x4 "CPSW_ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries. After writing to this register any read or write to any ALE register will be stalled until the read or write operation completes." bitfld.long 0x4 31. "TABLEWR,Table Write. This bit is used to write the table words to the lookup table." "0,1" hexmask.long.tbyte 0x4 9.--30. 1. "RESERVED" hexmask.long.word 0x4 0.--8. 1. "TABLEIDX,The table index is used to determine which lookup table entry is read or written." group.long 0x3E034++0xF line.long 0x0 "CPSW_ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry." hexmask.long 0x0 7.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--6. 1. "TABLEWRD2,Table Entry bits [71:64]" line.long 0x4 "CPSW_ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry." hexmask.long 0x4 0.--31. 1. "TABLEWRD1,Table Entry bits [63:32]." line.long 0x8 "CPSW_ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry." hexmask.long 0x8 0.--31. 1. "TABLEWRD0,Table Entry bits [31:0]." line.long 0xC "CPSW_Iy_ALE_PORTCTL0_y,The ALE Port Control Register sets the port specific modes of operation. Offset = 0003E040h + (y * 4h); where y = 0h to 4h" hexmask.long.byte 0xC 24.--31. 1. "Iy_REG_Py_BCAST_LIMIT,Broadcast Packet Rate Limit. Each prescale pulse loads this field into the port broadcast rate limit counter." hexmask.long.byte 0xC 16.--23. 1. "Iy_REG_Py_MCAST_LIMIT,Multicast Packet Rate Limit. Each prescale pulse loads this field into the port multicast rate limit counter." bitfld.long 0xC 15. "Iy_REG_Py_DROP_DOUBLE_VLAN,Drop Double VLAN. When set cause any received packet with double VLANs to be dropped." "0,1" newline bitfld.long 0xC 14. "Iy_REG_Py_DROP_DUAL_VLAN,Drop Dual VLAN. When set will cause any received packet with dual VLAN stag followed by ctag to be dropped." "0,1" bitfld.long 0xC 13. "Iy_REG_Py_MACONLY_CAF,Mac Only Copy All Frames. When set a Mac Only port will transfer all received good frames to the host." "0,1" bitfld.long 0xC 12. "Iy_REG_Py_DIS_PAUTHMOD,Disable Port authorization. When set will allow unknown addresses to arrive on a switch in authorization mode." "0,1" newline bitfld.long 0xC 11. "Iy_REG_Py_MACONLY,MAC Only. When set enables this port be treated like a MAC port for the host." "0,1" bitfld.long 0xC 10. "Iy_REG_Py_TRUNKEN,Trunk Enable. This field is used to enable a port into a trunk." "0,1" bitfld.long 0xC 8.--9. "Iy_REG_Py_TRUNKNUM,Trunk Number. This field is used as the trunk number when the Iy_REG_Py_TRUNKEN is also set." "0,1,2,3" newline bitfld.long 0xC 7. "Iy_REG_Py_MIRROR_SP,Mirror Source Port. This field enables the source port mirror option." "0,1" bitfld.long 0xC 6. "RESERVED" "0,1" bitfld.long 0xC 5. "Iy_REG_Py_NO_SA_UPDATE,No Source Address Update. When set will not update the source addresses for this port." "0,1" newline bitfld.long 0xC 4. "Iy_REG_Py_NO_LEARN,No Learn. When set will not learn the source addresses for this port." "0,1" bitfld.long 0xC 3. "Iy_REG_Py_VID_INGRESS_CHECK,VLAN Ingress Check. When set if a packet received is not a member of the VLAN the packet will be dropped." "0,1" bitfld.long 0xC 2. "Iy_REG_Py_DROP_UN_TAGGED,If Drop Untagged. When set will drop packets without a VLAN tag." "0,1" newline bitfld.long 0xC 0.--1. "Iy_REG_Py_PORTSTATE,Port State. Defins the current port state used for lookup operations." "0,1,2,3" group.long 0x3E090++0xF line.long 0x0 "CPSW_ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID." hexmask.long 0x0 5.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List." line.long 0x4 "CPSW_ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID." hexmask.long 0x4 5.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--4. 1. "UVLAN_UNREG_MCAST_FLOOD_MASK,Unknown VLAN Unregister Multicast Flood Mask." line.long 0x8 "CPSW_ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID." hexmask.long 0x8 5.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--4. 1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask. Each bit represents the port to which registered multicast are sent for unregistered VLANs." line.long 0xC "CPSW_ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed." hexmask.long 0xC 5.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--4. 1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask. Each bit represents the port where the VLAN will be removed for unregistered VLANs." group.long 0x3E0B8++0x7 line.long 0x0 "CPSW_ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters. This register is for diagnostice only." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "PBCAST_DIAG,When set and the PORT_DIAG is set to zero will allow all ports to see the same stat diagnostic increment." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED" newline bitfld.long 0x0 8.--10. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" hexmask.long.byte 0x0 0.--3. 1. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received." line.long 0x4 "CPSW_ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port." hexmask.long 0x4 5.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--4. 1. "OAM_LB_CTRL,The OAM_LB_CTRL bit field allows any port to be put into OAM loopback that is any packet received will be returned to the same port with an" group.long 0x3E0FC++0x17 line.long 0x0 "CPSW_ALE_EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions. If the packet was destined for the host. but matches a clasifier that has a.." hexmask.long.byte 0x0 24.--31. 1. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations 0h = NOP : 1-n: Defines which egress Operation will be performed. This allows Inter VLAN routing to be configured for high bandwidth traffic reducing CPU.." bitfld.long 0x0 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well." "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions." "0,1" newline hexmask.long.word 0x0 5.--19. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to." line.long 0x4 "CPSW_ALE_POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching." bitfld.long 0x4 31. "PORT_MEN,Port Match Enable." "0,1" bitfld.long 0x4 30. "TRUNKID,Trunk ID." "0,1" bitfld.long 0x4 28.--29. "RESERVED" "0,1,2,3" newline bitfld.long 0x4 25.--27. "PORT_NUM,Port Number." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 20.--24. 1. "RESERVED" bitfld.long 0x4 19. "PRI_MEN,Priority Match Enable." "0,1" newline bitfld.long 0x4 16.--18. "PRI_VAL,Priority Value." "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "ONU_MEN,OUI Match Enable." "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED" newline hexmask.long.word 0x4 0.--8. 1. "ONU_INDEX,OUI Table Entry Index." line.long 0x8 "CPSW_ALE_POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses." bitfld.long 0x8 31. "DST_MEN,Destination Address Match Enable - Enables frame L2 destination address match for the selected policing/classifier entry" "0,1" hexmask.long.byte 0x8 25.--30. 1. "RESERVED" hexmask.long.word 0x8 16.--24. 1. "DST_INDEX,Destination Address Table Entry Index - Specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry" newline bitfld.long 0x8 15. "SRC_MEN,Source Address Match Enable - Enables frame L2 source address match for the selected policing/classifier entry" "0,1" hexmask.long.byte 0x8 9.--14. 1. "RESERVED" hexmask.long.word 0x8 0.--8. 1. "SRC_INDEX,Source Address Table Entry Index - Specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry" line.long 0xC "CPSW_ALE_POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses." bitfld.long 0xC 31. "OVLAN_MEN,Outer VLAN Match Enable." "0,1" hexmask.long.byte 0xC 25.--30. 1. "RESERVED" hexmask.long.word 0xC 16.--24. 1. "OVLAN_INDEX,Outer VLAN Table Entry Index." newline bitfld.long 0xC 15. "IVLAN_MEN,Inner VLAN Match Enable." "0,1" hexmask.long.byte 0xC 9.--14. 1. "RESERVED" hexmask.long.word 0xC 0.--8. 1. "IVLAN_INDEX,Inner VLAN Table Entry Index." line.long 0x10 "CPSW_ALE_POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address." bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable." "0,1" hexmask.long.byte 0x10 25.--30. 1. "RESERVED" hexmask.long.word 0x10 16.--24. 1. "ETHERTYPE_INDEX,EtherType Table Entry Index." newline bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable." "0,1" hexmask.long.byte 0x10 9.--14. 1. "RESERVED" hexmask.long.word 0x10 0.--8. 1. "IPSRC_INDEX,IP Source Address Table Entry Index." line.long 0x14 "CPSW_ALE_POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address." bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable." "0,1" hexmask.long.byte 0x14 25.--30. 1. "RESERVED" hexmask.long.word 0x14 16.--24. 1. "IPDST_INDEX,IP Destination Address Table Entry Index." newline hexmask.long.word 0x14 0.--15. 1. "RESERVED" group.long 0x3E118++0x13 line.long 0x0 "CPSW_ALE_POLICECFG6,The PIR counter is a 37-bit internal counter where PIR_IDLE_INC_VAL is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time. If the counter is negative the packet will be marked RED. else it can.." hexmask.long 0x0 0.--31. 1. "PIR_IDLE_INC_VAL,Peak Information Rate Idle Increment Value." line.long 0x4 "CPSW_ALE_POLICECFG7,The CIR counter is a 37-bit internal counter where CIR_IDLE_INC_VAL is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time. If the counter is positive the packet will be marked GREEN..." hexmask.long 0x4 0.--31. 1. "CIR_IDLE_INC_VAL,Committed Information Idle Increment Value." line.long 0x8 "CPSW_ALE_POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry. The selected policing/classifier entry is only read or written after this register is written based on the value of the WRITE_ENABLE bit." bitfld.long 0x8 31. "WRITE_ENABLE,Write Enable - Setting this bit will write the" "0,1" hexmask.long 0x8 6.--30. 1. "RESERVED" hexmask.long.byte 0x8 0.--5. 1. "POL_TBL_IDX,Policer Entry Index - This field specifies the policing/classifier entry to be read or written." line.long 0xC "CPSW_ALE_POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules." bitfld.long 0xC 31. "POLICING_EN,Policing Enable." "0,1" bitfld.long 0xC 30. "RESERVED" "0,1" bitfld.long 0xC 29. "RED_DROP_EN,RED Drop Enable." "0,1" newline bitfld.long 0xC 28. "YELLOW_DROP_EN,WELLOW Drop Enable." "0,1" bitfld.long 0xC 27. "RESERVED" "0,1" bitfld.long 0xC 24.--26. "YELLOWTHRESH,Yellow Threshold." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 22.--23. "POLMCHMODE,Policing Match Mode." "0,1,2,3" bitfld.long 0xC 21. "PRIORITY_THREAD_EN,Priority Thread Enable." "0,1" bitfld.long 0xC 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable." "0,1" newline hexmask.long.tbyte 0xC 0.--19. 1. "RESERVED" line.long 0x10 "CPSW_ALE_POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition." bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear. This bit clears all the policing/ classifier hit bits." "0,1" bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED. This bit clears all the policing/ classifier RED hit bits." "0,1" bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW. This bit clears all the policing/ classifier YELLOW hit bits." "0,1" newline bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected. This bit clears the selected policing/ classifier hit redhit and yellowhit bits." "0,1" hexmask.long.tbyte 0x10 6.--27. 1. "RESERVED" hexmask.long.byte 0x10 0.--5. 1. "POL_TEST_IDX,Policer Test Index. This field selects which policing/ classifier hit bits will be read or written." rgroup.long 0x3E12C++0x3 line.long 0x0 "CPSW_ALE_POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier." bitfld.long 0x0 31. "POL_HIT,Policer Hit." "0,1" bitfld.long 0x0 30. "POL_REDHIT,Policer Hit RED." "0,1" bitfld.long 0x0 29. "POL_YELLOWHIT,Policer Hit YELLOW." "0,1" newline hexmask.long 0x0 0.--28. 1. "RESERVED" group.long 0x3E134++0xB line.long 0x0 "CPSW_ALE_THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "DEFTHREAD_EN,Default Tread Enable." "0,1" hexmask.long.word 0x0 6.--14. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--5. 1. "DEFTHREADVAL,Default Thread Value." line.long 0x4 "CPSW_ALE_THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host. This allows particular classifier matched traffic to be placed an a particular hosts queue." hexmask.long 0x4 6.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "CLASSINDEX,Classifier Index - This is the classifier index entry that the thread enable and thread value will be read or written by the Classifier Index." line.long 0x8 "CPSW_ALE_THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry." hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "THREAD_EN,Thread Enable." "0,1" hexmask.long.word 0x8 6.--14. 1. "RESERVED" newline hexmask.long.byte 0x8 0.--5. 1. "THREADVAL,Thread Value." tree.end tree "CPSW0_NUSS_CONTROL" base ad:0xC000000 rgroup.long 0x20000++0x3 line.long 0x0 "CPSW_ID_VER_REG,CPSW ID Version Register." hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification Value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version Value" bitfld.long 0x0 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor Version Value" group.long 0x20004++0x3 line.long 0x0 "CPSW_CONTROL_REG,CPSW Switch Control" bitfld.long 0x0 31. "ECC_CRC_MODE,ECC CRC Mode." "0,1" hexmask.long.word 0x0 19.--30. 1. "RESERVED" bitfld.long 0x0 18. "EST_ENABLE,Enhanced Scheduled Traffic enable (EST)" "0,1" newline bitfld.long 0x0 17. "IET_ENABLE,Intersperced Express Traffic enable (IET)" "0,1" bitfld.long 0x0 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1" bitfld.long 0x0 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1" newline bitfld.long 0x0 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1" bitfld.long 0x0 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove." "0,1" bitfld.long 0x0 12. "P0_TX_CRC_TYPE" "0,1" newline bitfld.long 0x0 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1" bitfld.long 0x0 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1" bitfld.long 0x0 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1" bitfld.long 0x0 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1" bitfld.long 0x0 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1" bitfld.long 0x0 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1" bitfld.long 0x0 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 2. "P0_ENABLE,Port 0 Enable" "0,1" bitfld.long 0x0 1. "VLAN_AWARE,VLAN Aware Mode:" "0,1" bitfld.long 0x0 0. "S_CN_SWITCH,Service or Customer VLAN switch." "0,1" group.long 0x20010++0x37 line.long 0x0 "CPSW_EM_CONTROL_REG,CPSW Emulation Control Register." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_STAT_PORT_EN_REG,CPSW Statistics Port Enable Register." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "P8_STAT_EN,Port 8 Statistics Enable (if N &gt; 8)" "0,1" bitfld.long 0x4 7. "P7_STAT_EN,Port 7 Statistics Enable (if N &gt; 7)" "0,1" newline bitfld.long 0x4 6. "P6_STAT_EN,Port 6 Statistics Enable (if N &gt; 6)" "0,1" bitfld.long 0x4 5. "P5_STAT_EN,Port 5 Statistics Enable (if N &gt; 5)" "0,1" bitfld.long 0x4 4. "P4_STAT_EN,Port 4 Statistics Enable (if N &gt; 4)" "0,1" newline bitfld.long 0x4 3. "P3_STAT_EN,Port 3 Statistics Enable (if N &gt; 3)" "0,1" bitfld.long 0x4 2. "P2_STAT_EN,Port 2 Statistics Enable (if N &gt; 2)" "0,1" bitfld.long 0x4 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1" newline bitfld.long 0x4 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1" line.long 0x8 "CPSW_PTYPE_REG,CPSW Transmit Priority Type." hexmask.long.word 0x8 17.--31. 1. "RESERVED" bitfld.long 0x8 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate (if N &gt; 8)" "0,1" bitfld.long 0x8 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate (if N &gt; 7)" "0,1" newline bitfld.long 0x8 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate (if N &gt; 6)" "0,1" bitfld.long 0x8 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate (if N &gt; 5)" "0,1" bitfld.long 0x8 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate (if N &gt; 4)" "0,1" newline bitfld.long 0x8 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate (if N &gt; 3)" "0,1" bitfld.long 0x8 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate (if N &gt; 2)" "0,1" bitfld.long 0x8 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1" newline bitfld.long 0x8 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1" bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "ESC_PRI_LD_VAL,Escalate Priority Load Value" line.long 0xC "CPSW_SOFT_IDLE_REG,CPSW Software Idle Register." hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "SOFT_IDLE,Software Idle." "0,1" line.long 0x10 "CPSW_THRU_RATE_REG,CPSW Thru Rate Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 12.--15. 1. "SL_RX_THRU_RATE,Ethernet Port Switch FIFO receive through rate." hexmask.long.byte 0x10 4.--11. 1. "RESERVED" newline hexmask.long.byte 0x10 0.--3. 1. "P0_RX_THRU_RATE,CPPI FIFO (port 0) receive through rate." line.long 0x14 "CPSW_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold Register." hexmask.long 0x14 5.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--4. 1. "GAP_THRESH,Ethernet Port Short Gap Threshold." line.long 0x18 "CPSW_TX_START_WDS_REG,CPSW Transmit FIFO Start Words Register" hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED" hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit (egress) Start Words." line.long 0x1C "CPSW_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value Register." hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED" hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value" line.long 0x20 "CPSW_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set" hexmask.long.byte 0x20 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" hexmask.long.byte 0x20 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" hexmask.long.byte 0x20 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" newline hexmask.long.byte 0x20 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" hexmask.long.byte 0x20 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" hexmask.long.byte 0x20 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x20 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" hexmask.long.byte 0x20 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0x24 "CPSW_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear Register." hexmask.long.byte 0x24 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" hexmask.long.byte 0x24 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" hexmask.long.byte 0x24 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" newline hexmask.long.byte 0x24 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" hexmask.long.byte 0x24 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" hexmask.long.byte 0x24 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x24 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" hexmask.long.byte 0x24 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0x28 "CPSW_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low Register." hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" newline hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x2C "CPSW_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High Register." hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" newline hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" line.long 0x30 "CPSW_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low Register." hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" newline hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x34 "CPSW_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High Register." hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" newline hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" group.long 0x20050++0x7 line.long 0x0 "CPSW_VLAN_LTYPE_REG,VLAN LTYPE Outer and Inner Register." hexmask.long.word 0x0 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType" hexmask.long.word 0x0 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType" line.long 0x4 "CPSW_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain Register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain." group.long 0x20100++0x1F line.long 0x0 "CPSW_TX_PRI0_MAXLEN_REG,Priority 0 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Packet Length" line.long 0x4 "CPSW_TX_PRI1_MAXLEN_REG,Priority 1 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Packet Length" line.long 0x8 "CPSW_TX_PRI2_MAXLEN_REG,Priority 2 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Packet Length" line.long 0xC "CPSW_TX_PRI3_MAXLEN_REG,Priority 3 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Packet Length" line.long 0x10 "CPSW_TX_PRI4_MAXLEN_REG,Priority 4 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Packet Length" line.long 0x14 "CPSW_TX_PRI5_MAXLEN_REG,Priority 5 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Packet Length" line.long 0x18 "CPSW_TX_PRI6_MAXLEN_REG,Priority 6 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED" hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Packet Length" line.long 0x1C "CPSW_TX_PRI7_MAXLEN_REG,Priority 7 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED" hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Packet Length." group.long 0x21004++0x7 line.long 0x0 "CPSW_P0_CONTROL_REG,CPPI Port 0 Control Register." hexmask.long.word 0x0 19.--31. 1. "RESERVED" bitfld.long 0x0 18. "RX_REMAP_DSCP_V6,Port 0 receive remap thread to DSCP IPV6 priority." "0,1" bitfld.long 0x0 17. "RX_REMAP_DSCP_V4,Port 0 receive remap thread to DSCP IPV6 priority." "0,1" newline bitfld.long 0x0 16. "RX_REMAP_VLAN,Port 0 receive remap thread to VLAN." "0,1" bitfld.long 0x0 15. "RX_ECC_ERR_EN,Port 0 receive ECC Error Enable" "0,1" bitfld.long 0x0 14. "TX_ECC_ERR_EN,Port 0 transmit ECC Error Enable" "0,1" newline hexmask.long.word 0x0 3.--13. 1. "RESERVED" bitfld.long 0x0 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1" bitfld.long 0x0 1. "DSCP_IPV4_EN,Port 0 IPV4 DSCP enable" "0,1" newline bitfld.long 0x0 0. "RX_CHECKSUM_EN,Port 0 Receive (port 0 ingress) Checksum Enable" "0,1" line.long 0x4 "CPSW_P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Flow ID Offset Register." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0" rgroup.long 0x21010++0x3 line.long 0x0 "CPSW_P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count Register." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED" hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Port 0 Transmit Block Count Usage." bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT,Port 0 Receive Block Count Usage." group.long 0x21014++0x17 line.long 0x0 "CPSW_P0_PORT_VLAN_REG,CPPI Port 0 VLAN" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x4 "CPSW_P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping." bitfld.long 0x4 31. "RESERVED" "0,1" bitfld.long 0x4 28.--30. "PRI7,Priority 7." "0,1,2,3,4,5,6,7" bitfld.long 0x4 27. "RESERVED" "0,1" newline bitfld.long 0x4 24.--26. "PRI6,Priority 6." "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "RESERVED" "0,1" bitfld.long 0x4 20.--22. "PRI5,Priority 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED" "0,1" bitfld.long 0x4 16.--18. "PRI4,Priority 4." "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "RESERVED" "0,1" newline bitfld.long 0x4 12.--14. "PRI3,Priority 3." "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "RESERVED" "0,1" bitfld.long 0x4 8.--10. "PRI2,Priority 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RESERVED" "0,1" bitfld.long 0x4 4.--6. "PRI1,Priority 1." "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "RESERVED" "0,1" newline bitfld.long 0x4 0.--2. "PRI0,Priority 0." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_P0_PRI_CTL_REG,CPPI Port 0 Priority Control." hexmask.long.byte 0x8 24.--31. 1. "RESERVED" hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)." hexmask.long.byte 0x8 9.--15. 1. "RESERVED" newline bitfld.long 0x8 8. "RX_PTYPE,Receive Priority Type" "0,1" hexmask.long.byte 0x8 0.--7. 1. "RESERVED" line.long 0xC "CPSW_P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map" bitfld.long 0xC 31. "RESERVED" "0,1" bitfld.long 0xC 28.--30. "PRI7,Priority 7." "0,1,2,3,4,5,6,7" bitfld.long 0xC 27. "RESERVED" "0,1" newline bitfld.long 0xC 24.--26. "PRI6,Priority 6." "0,1,2,3,4,5,6,7" bitfld.long 0xC 23. "RESERVED" "0,1" bitfld.long 0xC 20.--22. "PRI5,Priority 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 19. "RESERVED" "0,1" bitfld.long 0xC 16.--18. "PRI4,Priority 4." "0,1,2,3,4,5,6,7" bitfld.long 0xC 15. "RESERVED" "0,1" newline bitfld.long 0xC 12.--14. "PRI3,Priority 3." "0,1,2,3,4,5,6,7" bitfld.long 0xC 11. "RESERVED" "0,1" bitfld.long 0xC 8.--10. "PRI2,Priority 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 7. "RESERVED" "0,1" bitfld.long 0xC 4.--6. "PRI1,Priority 1." "0,1,2,3,4,5,6,7" bitfld.long 0xC 3. "RESERVED" "0,1" newline bitfld.long 0xC 0.--2. "PRI0,Priority 0." "0,1,2,3,4,5,6,7" line.long 0x10 "CPSW_P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length." hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length." line.long 0x14 "CPSW_P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority Register." hexmask.long.byte 0x14 28.--31. 1. "PRI7,Priority 7 Port Transmit Blocks" hexmask.long.byte 0x14 24.--27. 1. "PRI6,Priority 6 Port Transmit Blocks" hexmask.long.byte 0x14 20.--23. 1. "PRI5,Priority 5 Port Transmit Blocks" newline hexmask.long.byte 0x14 16.--19. 1. "PRI4,Priority 4 Port Transmit Blocks" hexmask.long.byte 0x14 12.--15. 1. "PRI3,Priority 3 Port Transmit Blocks" hexmask.long.byte 0x14 8.--11. 1. "PRI2,Priority 2 Port Transmit Blocks" newline hexmask.long.byte 0x14 4.--7. 1. "PRI1,Priority 1 Port Transmit Blocks" hexmask.long.byte 0x14 0.--3. 1. "PRI0,Priority 0 Port Transmit Blocks" group.long 0x21030++0x7 line.long 0x0 "CPSW_P0_IDLE2LPI_REG,Port 0 EEE LPI to wake counter load value." hexmask.long.byte 0x0 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value" line.long 0x4 "CPSW_P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value" rgroup.long 0x21038++0x3 line.long 0x0 "CPSW_P0_EEE_STATUS_REG,Port 0 EEE status." hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "TX_FIFO_EMPTY,CPPI (Port 0) Transmit FIFO packet count zero." "0,1" bitfld.long 0x0 5. "RX_FIFO_EMPTY,CPPI (Port 0) Receive FIFO packet count zero." "0,1" newline bitfld.long 0x0 4. "TX_FIFO_HOLD,CPPI (Port 0) Transmit FIFO hold." "0,1" bitfld.long 0x0 3. "TX_WAKE,CPPI (Port 0) Receive Wake Time." "0,1" bitfld.long 0x0 2. "TX_LPI,CPPI (Port 0) transmit LPI state." "0,1" newline bitfld.long 0x0 1. "RX_LPI,CPPI (Port 0) receive LPI state." "0,1" bitfld.long 0x0 0. "WAIT_IDLE2LPI,CPPI (Port 0) Transmit Wait Idle to LPI." "0,1" rgroup.long 0x21050++0x3 line.long 0x0 "CPSW_P0_FIFO_STATUS_REG,Port 0 FIFO Status" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,Port 0 Transmit FIFO Priority Active." group.long 0x21120++0x3 line.long 0x0 "CPSW_P0_RX_DSCP_MAP_REG_y,CPPI Port 0 Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers. Offset = 00021120h + (y * 4h); where y = 0h to 7h" bitfld.long 0x0 31. "RESERVED" "0,1" bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "RESERVED" "0,1" newline bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "RESERVED" "0,1" bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "RESERVED" "0,1" bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "RESERVED" "0,1" newline bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "RESERVED" "0,1" bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "RESERVED" "0,1" bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RESERVED" "0,1" newline bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7" group.long 0x21140++0x3 line.long 0x0 "CPSW_P0_PRI_CIR_REG_y,CPPI Port 0 Rx Priority 0 to Priority 7 Committed Information Rate Registers. Offset = 00021140h + (y * 4h); where y = 0h to 7h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority 'y' Committed Information Rate Count Value" group.long 0x21160++0x3 line.long 0x0 "CPSW_P0_PRI_EIR_REG_y,CPPI Port 0 Rx Priority 0 to Priority 7 Excess Information Rate. Offset = 00021160h + (y * 4h); where y = 0h to 7h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority N EIR" group.long 0x21180++0x1F line.long 0x0 "CPSW_P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x4 "CPSW_P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" bitfld.long 0x4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" bitfld.long 0x4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x8 "CPSW_P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low" bitfld.long 0x8 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" bitfld.long 0x8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" bitfld.long 0x8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0xC "CPSW_P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High" bitfld.long 0xC 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" bitfld.long 0xC 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" bitfld.long 0xC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline bitfld.long 0xC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" line.long 0x10 "CPSW_P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low" bitfld.long 0x10 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" bitfld.long 0x10 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" bitfld.long 0x10 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline bitfld.long 0x10 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x14 "CPSW_P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High" bitfld.long 0x14 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" bitfld.long 0x14 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" bitfld.long 0x14 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline bitfld.long 0x14 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x18 "CPSW_P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" bitfld.long 0x18 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline bitfld.long 0x18 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0x1C "CPSW_P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" bitfld.long 0x1C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" bitfld.long 0x1C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline bitfld.long 0x1C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" group.long 0x21300++0x7 line.long 0x0 "CPSW_P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A." hexmask.long.byte 0x0 24.--31. 1. "PORT4,Port 4 CPPI Info Word0 Source ID Value." hexmask.long.byte 0x0 16.--23. 1. "PORT3,Port 3 CPPI Info Word0 Source ID Value." hexmask.long.byte 0x0 8.--15. 1. "PORT2,Port 2 CPPI Info Word0 Source ID Value." newline hexmask.long.byte 0x0 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value." line.long 0x4 "CPSW_P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B." hexmask.long.byte 0x4 24.--31. 1. "PORT8,Port 8 CPPI Info Word0 Source ID Value." hexmask.long.byte 0x4 16.--23. 1. "PORT7,Port 7 CPPI Info Word0 Source ID Value." hexmask.long.byte 0x4 8.--15. 1. "PORT6,Port 6 CPPI Info Word0 Source ID Value." newline hexmask.long.byte 0x4 0.--7. 1. "PORT5,Port 5 CPPI Info Word0 Source ID Value." group.long 0x21320++0x3 line.long 0x0 "CPSW_P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority" hexmask.long.byte 0x0 28.--31. 1. "PRI7,Priority 7 Host Blocks" hexmask.long.byte 0x0 24.--27. 1. "PRI6,Priority 6 Host Blocks" hexmask.long.byte 0x0 20.--23. 1. "PRI5,Priority 5 Host Blocks" newline hexmask.long.byte 0x0 16.--19. 1. "PRI4,Priority 4 Host Blocks" hexmask.long.byte 0x0 12.--15. 1. "PRI3,Priority 3 Host Blocks" hexmask.long.byte 0x0 8.--11. 1. "PRI2,Priority 2 Host Blocks" newline hexmask.long.byte 0x0 4.--7. 1. "PRI1,Priority 1 Host Blocks" hexmask.long.byte 0x0 0.--3. 1. "PRI0,Priority 0 Host Blocks" rgroup.long 0x22000++0x3 line.long 0x0 "CPSW_PN_RESERVED_REG_k,Reserved." hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved register for memory map alignment" group.long 0x22004++0x7 line.long 0x0 "CPSW_PN_CONTROL_REG_k,Enet Port N Control. Offset = 00022004h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x0 18.--31. 1. "RESERVED" bitfld.long 0x0 17. "EST_PORT_EN,EST Port Enable." "0,1" bitfld.long 0x0 16. "IET_PORT_EN,Intersperced Express Traffic (IET) Port Enable." "0,1" newline bitfld.long 0x0 15. "RX_ECC_ERR_EN,Port N receive ECC Error Enable" "0,1" bitfld.long 0x0 14. "TX_ECC_ERR_EN,Port N transmit ECC Error Enable" "0,1" bitfld.long 0x0 13. "RESERVED" "0,1" newline bitfld.long 0x0 12. "TX_LPI_CLKSTOP_EN,Transmit LPI Clock Stop Enable." "0,1" hexmask.long.word 0x0 3.--11. 1. "RESERVED" bitfld.long 0x0 2. "DSCP_IPV6_EN,IPV6 DSCP enable" "0,1" newline bitfld.long 0x0 1. "DSCP_IPV4_EN,IPV4 DSCP enable" "0,1" bitfld.long 0x0 0. "RESERVED" "0,1" line.long 0x4 "CPSW_PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 8.--15. 1. "TX_MAX_BLKS,Transmit Max Blocks." hexmask.long.byte 0x4 0.--7. 1. "RX_MAX_BLKS,Receive Max Blocks." rgroup.long 0x22010++0x3 line.long 0x0 "CPSW_PN_BLK_CNT_REG_k,Enet Port N FIFO Block Usage Count Offset = 00022010h + (N * 1000h); where k = 0h to 3h" hexmask.long.word 0x0 22.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--21. 1. "RX_BLK_CNT_P,Receive Express Block Count Usage." bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Transmit Block Count Usage." bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT_E,Receive Express Block Count Usage." group.long 0x22014++0x17 line.long 0x0 "CPSW_PN_PORT_VLAN_REG_k,Enet Port N VLAN Offset = 00022014h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x4 "CPSW_PN_TX_PRI_MAP_REG_k,Enet Port N Tx Header Pri to Switch Pri Mapping Offset = 00022018h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x4 31. "RESERVED" "0,1" bitfld.long 0x4 28.--30. "PRI7,Priority 7. A packet header priority of 7h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 27. "RESERVED" "0,1" newline bitfld.long 0x4 24.--26. "PRI6,Priority 6. A packet header priority of 6h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "RESERVED" "0,1" bitfld.long 0x4 20.--22. "PRI5,Priority 5. A packet header priority of 5h is given this switch queue pri." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED" "0,1" bitfld.long 0x4 16.--18. "PRI4,Priority 4. A packet header priority of 4h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "RESERVED" "0,1" newline bitfld.long 0x4 12.--14. "PRI3,Priority 3. A packet header priority of 3h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "RESERVED" "0,1" bitfld.long 0x4 8.--10. "PRI2,Priority 2. A packet header priority of 2h is given this switch queue pri." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RESERVED" "0,1" bitfld.long 0x4 4.--6. "PRI1,Priority 1. A packet header priority of 1h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "RESERVED" "0,1" newline bitfld.long 0x4 0.--2. "PRI0,Priority 0. A packet header priority of 0h is given this switch queue pri." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_PN_PRI_CTL_REG_k,Enet Port N Priority Control Offset = 0002201Ch + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x8 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)" hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)" hexmask.long.byte 0x8 12.--15. 1. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" newline hexmask.long.word 0x8 0.--11. 1. "RESERVED" line.long 0xC "CPSW_PN_RX_PRI_MAP_REG_k,Enet Port N RX Pkt Pri to Header Pri Map Offset = 00022020h + (k * 1000h); where k = 0h to 3h" bitfld.long 0xC 31. "RESERVED" "0,1" bitfld.long 0xC 28.--30. "PRI7,Priority 7." "0,1,2,3,4,5,6,7" bitfld.long 0xC 27. "RESERVED" "0,1" newline bitfld.long 0xC 24.--26. "PRI6,Priority 6." "0,1,2,3,4,5,6,7" bitfld.long 0xC 23. "RESERVED" "0,1" bitfld.long 0xC 20.--22. "PRI5,Priority 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 19. "RESERVED" "0,1" bitfld.long 0xC 16.--18. "PRI4,Priority 4." "0,1,2,3,4,5,6,7" bitfld.long 0xC 15. "RESERVED" "0,1" newline bitfld.long 0xC 12.--14. "PRI3,Priority 3." "0,1,2,3,4,5,6,7" bitfld.long 0xC 11. "RESERVED" "0,1" bitfld.long 0xC 8.--10. "PRI2,Priority 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 7. "RESERVED" "0,1" bitfld.long 0xC 4.--6. "PRI1,Priority 1." "0,1,2,3,4,5,6,7" bitfld.long 0xC 3. "RESERVED" "0,1" newline bitfld.long 0xC 0.--2. "PRI0,Priority 0." "0,1,2,3,4,5,6,7" line.long 0x10 "CPSW_PN_RX_MAXLEN_REG_k,Enet Port N Receive Frame Max Length. Offset = 00022024h + (k * 1000h); where k = 0h to 3h" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length." line.long 0x14 "CPSW_PN_TX_BLKS_PRI_REG_k,Enet Port N Transmit Block Sub Per Priority Offset = 00022028h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x14 28.--31. 1. "PRI7,Priority 7 Port Transmit Blocks" hexmask.long.byte 0x14 24.--27. 1. "PRI6,Priority 6 Port Transmit Blocks" hexmask.long.byte 0x14 20.--23. 1. "PRI5,Priority 5 Port Transmit Blocks" newline hexmask.long.byte 0x14 16.--19. 1. "PRI4,Priority 4 Port Transmit Blocks" hexmask.long.byte 0x14 12.--15. 1. "PRI3,Priority 3 Port Transmit Blocks" hexmask.long.byte 0x14 8.--11. 1. "PRI2,Priority 2 Port Transmit Blocks" newline hexmask.long.byte 0x14 4.--7. 1. "PRI1,Priority 1 Port Transmit Blocks" hexmask.long.byte 0x14 0.--3. 1. "PRI0,Priority 0 Port Transmit Blocks" group.long 0x22030++0x7 line.long 0x0 "CPSW_PN_IDLE2LPI_REG_k,Enet Port N EEE Idle to LPI counter Offset = 00022030h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,EEE Idle to LPI counter load value" line.long 0x4 "CPSW_PN_LPI2WAKE_REG_k,Enet Port N EEE LPI to wake counter Offset = 00022034h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,EEE LPI to wake counter load value" rgroup.long 0x22038++0x3 line.long 0x0 "CPSW_PN_EEE_STATUS_REG_k,Enet Port N EEE status Offset = 00022038h + (k * 1000h); where k = 0h to 3h" hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "TX_FIFO_EMPTY,Port N Transmit FIFO packet count zero." "0,1" bitfld.long 0x0 5. "RX_FIFO_EMPTY,Port N Receive FIFO packet count zero." "0,1" newline bitfld.long 0x0 4. "TX_FIFO_HOLD,Port N Transmit FIFO hold." "0,1" bitfld.long 0x0 3. "TX_WAKE,Port N Receive Wake Time." "0,1" bitfld.long 0x0 2. "TX_LPI,Port N Transmit LPI." "0,1" newline bitfld.long 0x0 1. "RX_LPI,Port N Receive LPI." "0,1" bitfld.long 0x0 0. "WAIT_IDLE2LPI,Transmit Wait Idle to LPI." "0,1" group.long 0x22040++0x3 line.long 0x0 "CPSW_PN_IET_CONTROL_REG_k,Enet Port N IET Control Offset = 00022040h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "MAC_PREMPT,Mac Preempt Queue – Indicates which transmit FIFO queues are sent to the preempt MAC. Bit 0 indicates queue zero bit 1 queue 1 and so on. Packets will be sent to the preempt MAC only when MAC_PENABLE is set and when MAC_VERIFIED.." hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8.--10. "MAC_ADDFRAGSIZE,Mac Fragment Size – An integer in the range 0:7 indicating as a multiple of 64 the minimum additional length for nonfinal mPackets. 0 = 64 1 = 128 2 = 192 3 = 256 4 = 320 5 = 384 6 = 448 7 = 512" "0: 64,1: 128,2: 192,3: 256,4: 320,5: 384,6: 448,7: 512" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "MAC_LINKFAIL,Mac Link Fail – Link Fail Indicator to reset the verify state machine. This bit is reset high. Verify and response frames will be sent/allowed when this bit is cleared." "0,1" newline bitfld.long 0x0 2. "MAC_DISABLEVERIFY,Mac Disable Verify – Disables verification on the port when set. If this bit is set then packets will be sent to the preempt Mac when MAC_PENABLE is set (This is a forced mode with no IET verification)." "0,1" bitfld.long 0x0 1. "MAC_HOLD,Mac Hold – Hold Preemption on the port." "0,1" bitfld.long 0x0 0. "MAC_PENABLE,Mac Preemption Enable – Port Preemption Enable. This takes effect only when IET_PORT_EN is set." "0,1" rgroup.long 0x22044++0x3 line.long 0x0 "CPSW_PN_IET_STATUS_REG_k,Enet Port N IET Status Offset = 00022044h + (k * 1000h); where k = 0h to 3h" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "MAC_VERIFY_ERR,Mac Received Verify Packet with Errors – Set when a verify packet with errors is received. Cleared when MAC_PENABLE is cleared to zero." "0,1" bitfld.long 0x0 2. "MAC_RESPOND_ERR,Mac Received Respond Packet with Errors – Set when a respond packet with errors is received. Cleared when MAC_PENABLE is cleared to zero." "0,1" newline bitfld.long 0x0 1. "MAC_VERIFY_FAIL,Mac Verification Failed – Indication that verification was unsuccessful." "0,1" bitfld.long 0x0 0. "MAC_VERIFIED,Mac Verified – Indication that verification was successful." "0,1" group.long 0x22048++0x3 line.long 0x0 "CPSW_PN_IET_VERIFY_REG_k,Enet Port N IET VERIFY Offset = 00022048h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x0 0.--23. 1. "MAC_VERIFY_CNT,Mac Verify Timeout Count – The number of wireside clocks contained in the verify timeout counter. The default is 0x1312D0 (10ms at 125MHz in gig mode)." rgroup.long 0x22050++0x3 line.long 0x0 "CPSW_PN_FIFO_STATUS_REG_k,Enet Port N FIFO STATUS Offset = 00022050h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x0 19.--31. 1. "RESERVED" bitfld.long 0x0 18. "EST_BUFACT,EST RAM active buffer." "0,1" bitfld.long 0x0 17. "EST_ADD_ERR,EST Address Error." "0,1" newline bitfld.long 0x0 16. "EST_CNT_ERR,EST Fetch Count Error." "0,1" hexmask.long.byte 0x0 8.--15. 1. "TX_E_MAC_ALLOW,EST transmit MAC allow." hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,EST Transmit Priority Active." group.long 0x22060++0x3 line.long 0x0 "CPSW_PN_EST_CONTROL_REG_k,Enet Port N EST CONTROL Offset = 00022060h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x0 26.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--25. 1. "EST_FILL_MARGIN,EST Fill Margin." hexmask.long.byte 0x0 9.--15. 1. "EST_PREMPT_COMP,EST Prempt Comparison Value." newline bitfld.long 0x0 8. "EST_FILL_EN,EST Fill Enable." "0,1" bitfld.long 0x0 5.--7. "EST_TS_PRI,EST Timestamp Express Priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "EST_TS_ONEPRI,EST Timestamp One Express Priority." "0,1" newline bitfld.long 0x0 3. "EST_TS_FIRST,EST Timestamp First Express Packet only." "0,1" bitfld.long 0x0 2. "EST_TS_EN,EST Timestamp Enable." "0,1" bitfld.long 0x0 1. "EST_BUFSEL,EST Buffer Select." "0,1" newline bitfld.long 0x0 0. "EST_ONEBUF,EST One Fetch Buffer." "0,1" group.long 0x22120++0x3 line.long 0x0 "CPSW_PN_RX_DSCP_MAP_REG_k_y,Enet Port N Receive IPV4/IPV6 DSCP Map M Offset = 00022120h + (k * 1000h) + (y * 4h); where k = 0h to 3h. y = 0h to 7h" bitfld.long 0x0 31. "RESERVED" "0,1" bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "RESERVED" "0,1" newline bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "RESERVED" "0,1" bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "RESERVED" "0,1" bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "RESERVED" "0,1" newline bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "RESERVED" "0,1" bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "RESERVED" "0,1" bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RESERVED" "0,1" newline bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7" group.long 0x22140++0x3 line.long 0x0 "CPSW_PN_PRI_CIR_REG_k_y,Enet Port N Rx Priority P Committed Information Rate Value Offset = 00022140h + (k * 1000h) + (y * 4h); where k = 0h to 3h. y = 0h to 7h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority N committed information rate" group.long 0x22160++0x3 line.long 0x0 "CPSW_PN_PRI_EIR_REG_k_y,Enet Port N Rx Priority P Excess Informatoin Rate Value. Offset = 00022160h + (k * 1000h) + (y * 4h); where k = 0h to 3h. y = 0h to 7h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate count" group.long 0x22180++0x1F line.long 0x0 "CPSW_PN_TX_D_THRESH_SET_L_REG_k,Enet Port N Tx PFC Destination Threshold Set Low. Offset = 00022180h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x4 "CPSW_PN_TX_D_THRESH_SET_H_REG_k,Enet Port N Tx PFC Destination Threshold Set High. Offset = 00022184h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" bitfld.long 0x4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" bitfld.long 0x4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x8 "CPSW_PN_TX_D_THRESH_CLR_L_REG_k,Enet Port N Tx PFC Destination Threshold Clr Low. Offset = 00022188h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x8 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" bitfld.long 0x8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" bitfld.long 0x8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0xC "CPSW_PN_TX_D_THRESH_CLR_H_REG_k,Enet Port N Tx PFC Destination Threshold Clr High. Offset = 0002218Ch + (k * 1000h); where k = 0h to 3h" bitfld.long 0xC 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" bitfld.long 0xC 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" bitfld.long 0xC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline bitfld.long 0xC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" line.long 0x10 "CPSW_PN_TX_G_BUF_THRESH_SET_L_REG_k,Enet Port N Tx PFC Global Buffer Threshold Set Low. Offset = 00022190h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x10 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" bitfld.long 0x10 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" bitfld.long 0x10 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline bitfld.long 0x10 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x14 "CPSW_PN_TX_G_BUF_THRESH_SET_H_REG_k,Enet Port N Tx PFC Global Buffer Threshold Set High. Offset = 00022194h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x14 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" bitfld.long 0x14 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" bitfld.long 0x14 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline bitfld.long 0x14 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x18 "CPSW_PN_TX_G_BUF_THRESH_CLR_L_REG_k,Enet Port N Tx PFC Global Buffer Threshold Clr Low Offset = 00022198h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" bitfld.long 0x18 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline bitfld.long 0x18 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0x1C "CPSW_PN_TX_G_BUF_THRESH_CLR_H_REG_k,Enet Port N Tx PFC Global Buffer Threshold Clr High Offset = 0002219Ch + (k * 1000h); where k = 0h to 3h" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" bitfld.long 0x1C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" bitfld.long 0x1C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline bitfld.long 0x1C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" group.long 0x22300++0x23 line.long 0x0 "CPSW_PN_TX_D_OFLOW_ADDVAL_L_REG_k,Enet Port N Tx Destination Out Flow Add Values Low. Offset = 00022300h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" line.long 0x4 "CPSW_PN_TX_D_OFLOW_ADDVAL_H_REG_k,Enet Port N Tx Destination Out Flow Add Values High. Offset = 00022304h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" bitfld.long 0x4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" bitfld.long 0x4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" newline bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" line.long 0x8 "CPSW_PN_SA_L_REG_k,Enet Port N Tx Pause Frame Source Address Low Offset = 00022308h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" hexmask.long.byte 0x8 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15-8 (byte 1)" line.long 0xC "CPSW_PN_SA_H_REG_k,Enet Port N Tx Pause Frame Source Address High. Offset = 0002230Ch + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0xC 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23-16 (byte 2)" hexmask.long.byte 0xC 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31-24 (byte 3)" hexmask.long.byte 0xC 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39-32 (byte 4)" newline hexmask.long.byte 0xC 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47-40 (byte 5)" line.long 0x10 "CPSW_PN_TS_CTL_REG_k,Enet Port N Time Sync Control Offset = 00022310h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable." hexmask.long.byte 0x10 12.--15. 1. "RESERVED" bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable." "0,1" newline bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Sync Transmit Annex E enable." "0,1" bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Sync Receive Annex E enable." "0,1" bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable (transmit and receive)." "0,1" newline bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Sync Transmit Annex D enable." "0,1" bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_EN,Time Sync Transmit VLAN LTYPE 2 enable." "0,1" bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_EN,Time Sync Transmit VLAN LTYPE 1 enable." "0,1" newline bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Sync Transmit Annex F enable." "0,1" bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Sync Receive Annex D enable." "0,1" bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_EN,Time Sync Receive VLAN LTYPE 2 enable." "0,1" newline bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_EN,Time Sync Receive VLAN LTYPE 1 enable." "0,1" bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Sync Receive Annex F Enable." "0,1" line.long 0x14 "CPSW_PN_TS_SEQ_LTYPE_REG_k,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET). Offset = 00022314h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x14 22.--31. 1. "RESERVED" hexmask.long.byte 0x14 16.--21. 1. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1" line.long 0x18 "CPSW_PN_TS_VLAN_LTYPE_REG_k,Enet Port N Time Sync VLAN2 and VLAN2. Offset = 00022318h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2" hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1" line.long 0x1C "CPSW_PN_TS_CTL_LTYPE2_REG_k,Enet Port N Time Sync Control and LTYPE 2. Offset = 0002231Ch + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1" bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1" newline bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1" bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1" bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1" newline bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1" bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1" bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1" newline bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1" hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2" line.long 0x20 "CPSW_PN_TS_CTL2_REG_k,Enet Port N Time Sync Control 2. Offset = 00022320h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x20 22.--31. 1. "RESERVED" hexmask.long.byte 0x20 16.--21. 1. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable" group.long 0x22330++0x3 line.long 0x0 "CPSW_PN_MAC_CONTROL_REG_k,Enet Port N Mac Control. Offset = 00022330h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x0 26.--31. 1. "RESERVED" bitfld.long 0x0 25. "EXT_EN_XGIG,10G External Enable" "0,1" bitfld.long 0x0 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable." "0,1" newline bitfld.long 0x0 23. "RX_CSF_EN,RX Copy Short Frames Enable." "0,1" bitfld.long 0x0 22. "RX_CEF_EN,RX Copy Error Frames Enable." "0,1" bitfld.long 0x0 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1" newline bitfld.long 0x0 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable." "0,1" bitfld.long 0x0 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable." "0,1" bitfld.long 0x0 18. "EXT_EN,External Control Enable." "0,1" newline bitfld.long 0x0 17. "GIG_FORCE,Gigabit Mode Force." "0,1" bitfld.long 0x0 16. "IFCTL_B,Interface Control B." "0,1" bitfld.long 0x0 15. "IFCTL_A,Interface Control A." "0,1" newline bitfld.long 0x0 14. "RESERVED" "0,1" bitfld.long 0x0 13. "XGMII_EN,XGMII Enable." "0,1" bitfld.long 0x0 12. "CRC_TYPE,Port CRC Type." "0,1" newline bitfld.long 0x0 11. "CMD_IDLE,Command Idle." "0,1" bitfld.long 0x0 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable." "0,1" bitfld.long 0x0 9. "RESERVED" "0,1" newline bitfld.long 0x0 8. "XGIG,10 Gigabit Mode.Note: 10 Gigabit Mode is not supported on this device." "0,1" bitfld.long 0x0 7. "GIG,Gigabit Mode." "0,1" bitfld.long 0x0 6. "TX_PACE,Transmit Pacing Enable" "0,1" newline bitfld.long 0x0 5. "GMII_EN,GMII Enable." "0,1" bitfld.long 0x0 4. "TX_FLOW_EN,Transmit Flow Control Enable." "0,1" bitfld.long 0x0 3. "RX_FLOW_EN,Receive Flow Control Enable." "0,1" newline bitfld.long 0x0 2. "MTEST,Manufacturing Test mode." "0,1" bitfld.long 0x0 1. "LOOPBACK,Loop Back Mode." "0,1" bitfld.long 0x0 0. "FULLDUPLEX,Full Duplex mode." "0,1" rgroup.long 0x22334++0x3 line.long 0x0 "CPSW_PN_MAC_STATUS_REG_k,Enet Port N Mac Status Offset = 00022334h + (k * 1000h); where k = 0h to 3h" bitfld.long 0x0 31. "IDLE,Enet IDLE." "0,1" bitfld.long 0x0 30. "E_IDLE,Express MAC is Idle." "0,1" bitfld.long 0x0 29. "P_IDLE,Prempt MAC is Idle." "0,1" newline bitfld.long 0x0 28. "MAC_TX_IDLE,Mac Transmit Idle." "0,1" bitfld.long 0x0 27. "TORF,Top of receive FIFO flow control trigger occurred." "0,1" bitfld.long 0x0 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)" hexmask.long.byte 0x0 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)" bitfld.long 0x0 7. "RESERVED" "0,1" newline bitfld.long 0x0 6. "EXT_RX_FLOW_EN,External Receive Flow Control Enable." "0,1" bitfld.long 0x0 5. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable." "0,1" bitfld.long 0x0 4. "EXT_GIG,External GIG." "0,1" newline bitfld.long 0x0 3. "EXT_FULLDUPLEX,External Fullduplex." "0,1" bitfld.long 0x0 2. "RESERVED" "0,1" bitfld.long 0x0 1. "RX_FLOW_ACT,Receive Flow Control Active." "0,1" newline bitfld.long 0x0 0. "TX_FLOW_ACT,Transmit Flow Control Active." "0,1" group.long 0x22338++0xB line.long 0x0 "CPSW_PN_MAC_SOFT_RESET_REG_k,Enet Port N Mac Soft Reset. Offset = 00022338h + (k * 1000h); where k = 0h to 3h" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Software reset." "0,1" line.long 0x4 "CPSW_PN_MAC_BOFFTEST_REG_k,Enet Port N Mac Backoff Test Offset = 0002233Ch + (k * 1000h); where k = 0h to 3h" bitfld.long 0x4 31. "RESERVED" "0,1" hexmask.long.byte 0x4 26.--30. 1. "PACEVAL,Pacing Current Value." hexmask.long.word 0x4 16.--25. 1. "RNDNUM,Backoff Random Number Generator." newline hexmask.long.byte 0x4 12.--15. 1. "COLL_COUNT,Collision Count." bitfld.long 0x4 10.--11. "RESERVED" "0,1,2,3" hexmask.long.word 0x4 0.--9. 1. "TX_BACKOFF,Backoff Count." line.long 0x8 "CPSW_PN_MAC_RX_PAUSETIMER_REG_k,Enet Port N 802.3 Receive Pause Timer Offset = 00022340h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value." group.long 0x22350++0x3 line.long 0x0 "CPSW_PN_MAC_RXN_PAUSETIMER_REG_k_y,Ethernet Port N PFC Priority 0 to Priority 7 Rx Pause Timer Registers. Offset = 00022350h + (k * 1000h) + (y * 4h); where k = 0h to 3h. y = 0h to 7h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "RX_PAUSETIMER,Rx “y” Pause Timer Value." group.long 0x22370++0x3 line.long 0x0 "CPSW_PN_MAC_TX_PAUSETIMER_REG_k,Enet Port N 802.3 Tx Pause Timer. Offset = 00022370h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,802.3 Tx Pause Timer Value." group.long 0x22380++0x3 line.long 0x0 "CPSW_PN_MAC_TXN_PAUSETIMER_REG_k_y,Ethernet Port N PFC Priority 0 to Priority 7 Tx Pause Timer Registers. Offset = 00022380h + (k * 1000h) + (y * 4h); where k = 0h to 3h. y = 0h to 7h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,PFC Tx ”y” Pause Timer Value." group.long 0x223A0++0x7 line.long 0x0 "CPSW_PN_MAC_EMCONTROL_REG_k,Enet Port N Emulation Control. Offset = 000223A0h + (k * 1000h); where k = 0h to 3h" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_PN_MAC_TX_GAP_REG_k,Enet Port N Tx Inter Packet Gap. Offset = 000223A4h + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap" rgroup.long 0x223A8++0x3 line.long 0x0 "CPSW_PN_MAC_PORT_CONFIG_k,Return to the . Enet Port N Port Configuration Offset = 000223A8h + (k * 1000h); where k = 0h to 3h" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" bitfld.long 0x0 9. "IET,Intersperced Express Traffic (IET) is supported on this port when read high." "0,1" bitfld.long 0x0 8. "XGMII,XGMII is supported on this port when set." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "INTERVLAN_ROUTES,This is the number of InterVLAN routes supported on this port (egress)." group.long 0x223AC++0x13 line.long 0x0 "CPSW_PN_INTERVLAN_OPX_POINTER_REG_k,Enet Port N Tx Egress InterVLAN Operation Pointer Offset = 000223ACh + (k * 1000h); where k = 0h to 3h" hexmask.long 0x0 5.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "POINTER,InterVLAN location pointer: This field points to the InterVLAN location that will be read/written by accesses to Enet_Pn_InterVLANx_A/B." line.long 0x4 "CPSW_PN_INTERVLAN_OPX_A_REG_k,Enet Port N Tx Egress InterVLAN A Offset = 000223B0h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x4 24.--31. 1. "DA_23_16,Destination Address bits 23:16 – DA byte 4 on wire" hexmask.long.byte 0x4 16.--23. 1. "DA_31_24,Destination Address bits 31:24 – DA byte 3 on wire" hexmask.long.byte 0x4 8.--15. 1. "DA_39_32,Destination Address bits 39:32 – DA byte 2 on wire" newline hexmask.long.byte 0x4 0.--7. 1. "DA_47_40,Destination Address bits 47:40 – DA byte 1 on wire" line.long 0x8 "CPSW_PN_INTERVLAN_OPX_B_REG_k,Enet Port N Tx Egress InterVLAN B Offset = 000223B4h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0x8 24.--31. 1. "SA_39_32,Source Address bits 39:32 – SA byte 2 on wire" hexmask.long.byte 0x8 16.--23. 1. "SA_47_40,Source Address bits 47:40 – SA byte 1 on wire" hexmask.long.byte 0x8 8.--15. 1. "DA_7_0,Destination Address bits 7:0 – DA byte 6 on wire" newline hexmask.long.byte 0x8 0.--7. 1. "DA_15_8,Destination Address bits 15:8 – DA byte 5 on wire" line.long 0xC "CPSW_PN_INTERVLAN_OPX_C_REG_k,Enet Port N Tx Egress InterVLAN C Offset = 000223B8h + (k * 1000h); where k = 0h to 3h" hexmask.long.byte 0xC 24.--31. 1. "SA_7_0,Source Address bits 7:0 – DA byte 6 on wire" hexmask.long.byte 0xC 16.--23. 1. "SA_15_8,Source Address bits 15:8 – DA byte 5 on wire" hexmask.long.byte 0xC 8.--15. 1. "SA_23_16,Source Address bits 23:16 – DA byte 4 on wire" newline hexmask.long.byte 0xC 0.--7. 1. "SA_31_24,Source Address bits 31:24 – DA byte 3 on wire" line.long 0x10 "CPSW_PN_INTERVLAN_OPX_D_REG_k,Enet Port N Tx Egress InterVLAN D. Offset = 000223BCh + (k * 1000h); where k = 0h to 3h" hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "DECREMENT_TTL,Decrement Time To Live.IPV4 – Decrement the TTL byte and update the Header ChecksumIPV6 – Decrement the Hop Limit.Note: When this bit is set the ALE should be configured to send any IPv4/6 packet with a zero or one TTL field to the.." "0,1" bitfld.long 0x10 14. "DEST_FORCE_UNTAGGED_EGRESS,Destination VLAN Force Untagged Egress." "0,1" newline bitfld.long 0x10 13. "REPLACE_DA_SA,Replace Destination Address and Source Address." "0,1" bitfld.long 0x10 12. "REPLACE_VID,Replace VLAN ID." "0,1" hexmask.long.word 0x10 0.--11. 1. "VID,VLAN ID" tree.end tree "CPSW0_NUSS_CPINT" base ad:0xC000000 rgroup.long 0x1000++0x3 line.long 0x0 "CPSW_INT_REVISION,Register." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" group.long 0x1010++0x3 line.long 0x0 "CPSW_INT_EOI_REG,End of Interrupt Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector." rgroup.long 0x1014++0x3 line.long 0x0 "CPSW_INT_INTR_VECTOR_REG,Interrupt Vector Register." hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" group.long 0x1100++0x3 line.long 0x0 "CPSW_INT_ENABLE_REG_OUT_PULSE_0,Enable Register 0." hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA,Enable Set for out_pulse_en_stat_penda." "0,1" newline bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA,Enable Set for out_pulse_en_mdio_penda." "0,1" bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA,Enable Set for out_pulse_en_evnt_penda." "0,1" group.long 0x1300++0x3 line.long 0x0 "CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0,Enable Clear Register 0." hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR,Enable Clear for out_pulse_en_stat_penda." "0,1" newline bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR,Enable Clear for out_pulse_en_mdio_penda." "0,1" bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR,Enable Clear for out_pulse_en_evnt_penda." "0,1" rgroup.long 0x1500++0x3 line.long 0x0 "CPSW_INT_STATUS_REG_OUT_PULSE_0,Status Register 0." hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 2. "STATUS_OUT_PULSE_STAT_PENDA,Status for out_pulse_en_stat_penda." "0,1" newline bitfld.long 0x0 1. "STATUS_OUT_PULSE_MDIO_PENDA,Status for out_pulse_en_mdio_penda." "0,1" bitfld.long 0x0 0. "STATUS_OUT_PULSE_EVNT_PENDA,Status for out_pulse_en_evnt_penda." "0,1" rgroup.long 0x1A80++0x3 line.long 0x0 "CPSW_INT_INTR_VECTOR_REG_OUT_PULSE,Interrupt Vector for out_pulse." hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_OUT_PULSE,Interrupt Vector." tree.end tree "CPSW0_NUSS_CPTS" base ad:0xC000000 rgroup.long 0x3D000++0x3 line.long 0x0 "CPSW_CPTS_IDVER_REG,CPSW0_NUSS CPTS Identification and Version Register." hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value." bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value." group.long 0x3D004++0x7 line.long 0x0 "CPSW_CPTS_CONTROL_REG,Time Sync Control Register." hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output time stamp counter bit select." hexmask.long.word 0x0 18.--27. 1. "RESERVED" bitfld.long 0x0 17. "TS_GENF_CLR_EN,GENF (and ESTF) Clear Enable. 0h = A CPTS_GENFn output is not cleared when the associated CPSW_GENF0_LENGTH_REG/ CPSW_GENF1_LENGTH_REG[31:0] is cleared to zero. 1h = A CPTS_GENFn output is cleared when the associated CPSW_GENF0_LENGTH_REG/.." "0,1" bitfld.long 0x0 16. "TS_RX_NO_EVENT,Timestamp Ethernet Receive produces no events." "0,1" newline bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable." "0,1" bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable." "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable." "0,1" bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable." "0,1" newline bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable." "0,1" bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable." "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable." "0,1" bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable." "0,1" newline bitfld.long 0x0 7. "TS_PPM_DIR,PPM Correction Direction." "0,1" bitfld.long 0x0 6. "TS_COMP_TOG,Time Stamp Compare Toggle mode." "0,1" bitfld.long 0x0 5. "MODE,64-Bit Mode." "0,1" bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable." "0,1" newline bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Time Stamp Enable." "0,1" bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP Polarity." "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt Test." "0,1" bitfld.long 0x0 0. "CPTS_EN,Time Sync Enable." "0,1" line.long 0x4 "CPSW_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register." hexmask.long 0x4 5.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select. This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference. 0h = Selects CPSWHSDIV_CLKOUT2 clock 1h = Selects MAINHSDIV_CLKOUT3 clock 2h = Selects.." wgroup.long 0x3D00C++0x3 line.long 0x0 "CPSW_CPTS_TS_PUSH_REG,Time Stamp Event Push Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push." "0,1" group.long 0x3D010++0x3 line.long 0x0 "CPSW_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register." hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value." wgroup.long 0x3D014++0x3 line.long 0x0 "CPSW_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_LOAD_EN,Time Stamp Load Enable." "0,1" group.long 0x3D018++0xB line.long 0x0 "CPSW_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value (lower 32-bits) Register." hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time Stamp Comparison Low Value." line.long 0x4 "CPSW_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register." hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time Stamp Comparison Length." line.long 0x8 "CPSW_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw." hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)." "0,1" rgroup.long 0x3D024++0x3 line.long 0x0 "CPSW_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)." "0,1" group.long 0x3D028++0x7 line.long 0x0 "CPSW_CPTS_INT_ENABLE_REG,Interrupt Enable Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable." "0,1" line.long 0x4 "CPSW_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Value Register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,Time stamp Comparison Nudge Value." wgroup.long 0x3D030++0x3 line.long 0x0 "CPSW_CPTS_EVENT_POP_REG,Event Interrupt Pop Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EVENT_POP,Event Pop." "0,1" rgroup.long 0x3D034++0xF line.long 0x0 "CPSW_CPTS_EVENT_0_REG,Lower 32-bits of the Event Value Register." hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp." line.long 0x4 "CPSW_CPTS_EVENT_1_REG,Lower Middle 32-bits of the Event Value Register." bitfld.long 0x4 30.--31. "RESERVED" "0,1,2,3" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port Number." hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Time Sync Event Type" newline hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type." hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID." line.long 0x8 "CPSW_CPTS_EVENT_2_REG,Upper Middle 32-bits of the Event Value Register." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain." line.long 0xC "CPSW_CPTS_EVENT_3_REG,Upper 32-bits of the Event Value Register." hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp." group.long 0x3D044++0x17 line.long 0x0 "CPSW_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value (upper 32-bits) Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time Stamp Load high Value." line.long 0x4 "CPSW_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value (upper 32-bits) Register." hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time Stamp Comparison High Value." line.long 0x8 "CPSW_CPTS_TS_ADD_VAL_REG,TS Add Value Register." hexmask.long 0x8 3.--31. 1. "RESERVED" bitfld.long 0x8 0.--2. "ADD_VAL,The ts_add_value[2:0] is added to 1 to comprise the time stamp increment value." "0,1,2,3,4,5,6,7" line.long 0xC "CPSW_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Load Low Value (lower 32-bits) Register." hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time Stamp PPM Low Value." line.long 0x10 "CPSW_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM Load High Value (upper 32-bits) Register." hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time Stamp PPM High Value." line.long 0x14 "CPSW_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register." hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge Value. The minimum value of the Time Stamp PPM is 0x400 (all 42 bits:" group.long 0x3D0E0++0x1B line.long 0x0 "CPSW_GENF0_COMP_LOW_REG,Time Stamp Generate Function (GENF0) Comparison Low Value (lower 32-bits)." hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value (lower 32-bits)." line.long 0x4 "CPSW_GENF0_COMP_HIGH_REG,Time Stamp Generate Function (GENF0) Comparison high Value (upper 32-bits)." hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value (upper 32-bits)." line.long 0x8 "CPSW_GENF0_CONTROL_REG,Time Stamp Generate Function (GENF0) Control Registers." hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction." "0,1" line.long 0xC "CPSW_GENF0_LENGTH_REG,Time Stamp Generate Function (GENF0) Length Value." hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value." line.long 0x10 "CPSW_GENF0_PPM_LOW_REG,Time Stamp Generate Function (GENF0) PPM Low Value (lower 32-bits)." hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value." line.long 0x14 "CPSW_GENF0_PPM_HIGH_REG,Time Stamp Generate Function (GENF0) PPM High Value (upper 32-bits)." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value." line.long 0x18 "CPSW_GENF0_NUDGE_REG,Time Stamp Generate Function (GENF0) Nudge Value Registers." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value." group.long 0x3D100++0x1B line.long 0x0 "CPSW_GENF1_COMP_LOW_REG,Time Stamp Generate Function (GENF1) Comparison Low Value." hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function (GENF1) Comparison Low Value (lower 32-bits)." line.long 0x4 "CPSW_GENF1_COMP_HIGH_REG,Time Stamp Generate Function (GENF1) Comparison high Value (upper 32-bits)." hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function (GENF1) Comparison High Value (upper 32-bits)." line.long 0x8 "CPSW_GENF1_CONTROL_REG,Time Stamp Generate Function (GENF1) Control Register." hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function (GENF1) Polarity Invert." "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function (GENF1) PPM Direction." "0,1" line.long 0xC "CPSW_GENF1_LENGTH_REG,Time Stamp Generate Function (GENF1) Length Value." hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function (GENF1) Length Value." line.long 0x10 "CPSW_GENF1_PPM_LOW_REG,Time Stamp Generate Function (GENF1) PPM Low Value (lower 32-bits)." hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function (GENF1) PPM Low Value" line.long 0x14 "CPSW_GENF1_PPM_HIGH_REG,Time Stamp Generate Function (GENF1) PPM High Value (upper 32-bits)." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function (GENF1) PPM High Value." line.long 0x18 "CPSW_GENF1_NUDGE_REG,Time Stamp Generate Function (GENF1) Nudge Value." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function (GENF1) Nudge Value ." group.long 0x3D200++0x1B line.long 0x0 "CPSW_ESTF_COMP_LOW_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 4) Comparison Low Value. Offset = 0003D200h + (l * 20h); where l = 0h to 3h." hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function (ESTFn where n = 1 to 4) Comparison Low Value (lower 32-bits)." line.long 0x4 "CPSW_ESTF_COMP_HIGH_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 4) Comparison high Value (upper 32-bits). Offset = 0003D204h + (l * 20h); where l = 0h to 3h." hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function (ESTFn where n = 1 to 4) Comparison High Value (upper 32-bits)." line.long 0x8 "CPSW_ESTF_CONTROL_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 4) Control Register. Offset = 0003D208h + (l * 20h); where l = 0h to 3h." hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function (ESTFn where n = 1 to 4) Polarity Invert." "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function (ESTFn where n = 1 to 4) PPM Direction." "0,1" line.long 0xC "CPSW_ESTF_LENGTH_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 4) Length Value. Offset = 0003D20Ch + (l * 20h); where l = 0h to 3h." hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTFn (n = 1 to 4) Generate Function Length Value." line.long 0x10 "CPSW_ESTF_PPM_LOW_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 4) PPM Low Value (lower 32-bits). Offset = 0003D210h + (l * 20h); where l = 0h to 3h." hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTFn (n = 1 to 4) Generate Function PPM Low Value." line.long 0x14 "CPSW_ESTF_PPM_HIGH_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 4) PPM High Value (upper 32-bits). Offset = 0003D214h + (l * 20h); where l = 0h to 3h." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTFn (n = 1 to 4) Generate Function PPM High Value." line.long 0x18 "CPSW_ESTF_NUDGE_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 4) Nudge Value. Offset = 0003D218h + (l * 20h); where l = 0h to 3h." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTFn (n = 1 to 4) Generate Function Nudge Value." tree.end tree "CPSW0_NUSS_MDIO" base ad:0xC000000 rgroup.long 0xF00++0x3 line.long 0x0 "CPSW_MDIO_VERSION_REG,MDIO Version Register." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0xF04++0x7 line.long 0x0 "CPSW_MDIO_CONTROL_REG,MDIO Control Register" rbitfld.long 0x0 31. "IDLE,MDIO state machine IDLE." "0,1" bitfld.long 0x0 30. "ENABLE,Enable control." "0,1" bitfld.long 0x0 29. "RESERVED" "0,1" hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel." newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "PREAMBLE,Preamble disable." "0,1" bitfld.long 0x0 19. "FAULT,Fault indicator." "0,1" bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable." "0,1" newline bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable." "0,1" bitfld.long 0x0 16. "RESERVED" "0,1" hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock Divider." line.long 0x4 "CPSW_MDIO_ALIVE_REG,MDIO Alive Register." hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO Alive." rgroup.long 0xF0C++0x3 line.long 0x0 "CPSW_MDIO_LINK_REG,MDIO Link Register." hexmask.long 0x0 0.--31. 1. "LINK,MDIO Link state." group.long 0xF10++0x37 line.long 0x0 "CPSW_MDIO_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value." "0,1,2,3" line.long 0x4 "CPSW_MDIO_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register." hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value." "0,1,2,3" line.long 0x8 "CPSW_MDIO_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register." hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set." "0,1" line.long 0xC "CPSW_MDIO_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register." hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear." "0,1" line.long 0x10 "CPSW_MDIO_USER_INT_RAW_REG,MDIO User Interrupt Raw Register." hexmask.long 0x10 2.--31. 1. "RESERVED" bitfld.long 0x10 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively." "0,1,2,3" line.long 0x14 "CPSW_MDIO_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register." hexmask.long 0x14 2.--31. 1. "RESERVED" bitfld.long 0x14 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively." "0,1,2,3" line.long 0x18 "CPSW_MDIO_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register." hexmask.long 0x18 2.--31. 1. "RESERVED" bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for" "0,1,2,3" line.long 0x1C "CPSW_MDIO_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register" hexmask.long 0x1C 2.--31. 1. "RESERVED" bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user command complete interrupt mask clear for" "0,1,2,3" line.long 0x20 "CPSW_MDIO_MANUAL_IF_REG,MDIO Manual Interface Register." hexmask.long 0x20 3.--31. 1. "RESERVED" bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output." "0,1" bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable." "0,1" bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin Value." "0,1" line.long 0x24 "CPSW_MDIO_POLL_REG,MDIO Poll Register." bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode." "0,1" bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode." "0,1" hexmask.long.tbyte 0x24 8.--29. 1. "RESERVED" hexmask.long.byte 0x24 0.--7. 1. "IPG,Polling Inter Packet Gap Value." line.long 0x28 "CPSW_MDIO_POLL_EN_REG,MDIO Poll Enable Register." hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable." line.long 0x2C "CPSW_MDIO_CLAUS45_REG,MDIO Clause45 Enable Register." hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO clause 45 mode." line.long 0x30 "CPSW_MDIO_USER_ADDR0_REG,MDIO Address 0 Register." hexmask.long.word 0x30 16.--31. 1. "RESERVED" hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO User Address 0." line.long 0x34 "CPSW_MDIO_USER_ADDR1_REG,MDIO Address 1 Register." hexmask.long.word 0x34 16.--31. 1. "RESERVED" hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO User Address 1." group.long 0xF80++0x7 line.long 0x0 "CPSW_MDIO_USER_ACCESS_REG_k,MDIO User Access Register. Offset = F80h + (k * 8h); where k = 0h to 1h" bitfld.long 0x0 31. "GO,Go." "0,1" bitfld.long 0x0 30. "WRITE,Write enable." "0,1" bitfld.long 0x0 29. "ACK,Acknowledge." "0,1" bitfld.long 0x0 26.--28. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 21.--25. 1. "REGADR,Register address." hexmask.long.byte 0x0 16.--20. 1. "PHYADR,PHY address." hexmask.long.word 0x0 0.--15. 1. "DATA,User data." line.long 0x4 "CPSW_MDIO_USER_PHY_SEL_REG_k,MDIO User PHY Select Register Offset = F84h + (k * 8h); where k = 0h to 1h" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "LINKSEL,Link status determination select." "0,1" bitfld.long 0x4 6. "LINKINT_ENABLE,Link change interrupt enable." "0,1" bitfld.long 0x4 5. "RESERVED" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "PHYADR_MON,PHY address whose link status is monitored." tree.end tree "CPSW0_NUSS_PCSR" base ad:0xC000000 group.long 0x2100++0xB line.long 0x0 "CPSW_PCSR_TX_CTL_REG,PCSR Transmit Control Register." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "TX_DATAPATH_EN,PCSR Transmit Datapath Enable." "0,1" bitfld.long 0x0 7. "TX_SCR_BPYASS,PCSR Transmit SCR Bypass." "0,1" bitfld.long 0x0 6. "TX_TEST_EN,PCSR Transmit Test Enable." "0,1" newline bitfld.long 0x0 5. "TX_TEST_SEL,PCSR Transmit Test Select." "0,1" bitfld.long 0x0 4. "TX_TEST_DAT_SEL,PCSR Transmit Test Data Select." "0,1" bitfld.long 0x0 3. "TX_PRBS31_EN,PCSR Transmit PRBS31 Enable." "0,1" bitfld.long 0x0 2. "TX_PRBS9_EN,PCSR Transmit PRBS9 Enable." "0,1" newline bitfld.long 0x0 1. "TX_LOOPBACK_EN,PCSR Transmit Loopback Enable." "0,1" bitfld.long 0x0 0. "TX_SCR_LOOPBK_EN,PCSR Transmit SCR Loopback Enable." "0,1" line.long 0x4 "CPSW_PCSR_TX_STATUS_REG,PCSR Transmit Status Register." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "TX_FAULT,PCSR Transmit Fault Hold Register - write 1 to clear." "0,1" hexmask.long.byte 0x4 0.--7. 1. "RESERVED" line.long 0x8 "CPSW_PCSR_RX_CTL_REG,PCSR Receive Control Register." hexmask.long.tbyte 0x8 9.--31. 1. "RESERVED" bitfld.long 0x8 8. "RX_PRBS9_EN,PCSR Receive PRBS9 Enable." "0,1" bitfld.long 0x8 7. "RX_TEST_EN,PCSR Receive Test Enable." "0,1" bitfld.long 0x8 6. "RX_TEST_DAT_SEL,PCSR Receive Test Data Select." "0,1" newline bitfld.long 0x8 5. "RX_PRBS31_EN,PCSR Receive PRBS31 Enable." "0,1" bitfld.long 0x8 4. "RX_ERR_BLK_CNT_RST,PCSR Receive Error Block Count Reset." "0,1" bitfld.long 0x8 3. "RX_BER_CNT_RST,PCSR Receive BER Count Reset." "0,1" bitfld.long 0x8 2. "RX_TEST_CNT_PRE,PCSR Receive Test Count Pre." "0,1" newline bitfld.long 0x8 1. "RX_TEST_CNT_125US,PCSR Receive Test Count 125us." "0,1" bitfld.long 0x8 0. "RX_TPTER_CNT_RST,PCSR Receive TPTER Count Reset" "0,1" rgroup.long 0x210C++0x3 line.long 0x0 "CPSW_PCSR_RX_STATUS_REG,PCSR Receive Status Register." bitfld.long 0x0 31. "RX_HI_BER,PCSR Receive High BER." "0,1" bitfld.long 0x0 30. "RX_BLOCK_LOCK,PCSR Receive Block Lock." "0,1" hexmask.long.byte 0x0 24.--29. 1. "RX_BER_COUNT,PCSR Receive BER Count." hexmask.long.byte 0x0 16.--23. 1. "RX_ERR_BLK_CNT,PCSR Error Block Count." newline hexmask.long.word 0x0 0.--15. 1. "RX_TPT_ERR_CNT,PCSR TPT Error Count." group.long 0x2110++0x1F line.long 0x0 "CPSW_PCSR_SEED_A_LO_REG,PCSR Seed A Low Register." hexmask.long 0x0 0.--31. 1. "SEED_A_LO,PCSR Seed A Low." line.long 0x4 "CPSW_PCSR_SEED_A_HI_REG,PCSR Seed A High Register." hexmask.long.byte 0x4 26.--31. 1. "RESERVED" hexmask.long 0x4 0.--25. 1. "SEED_A_HI,PCSR Seed A High." line.long 0x8 "CPSW_PCSR_SEED_B_LO_REG,PCSR Seed B Low Register." hexmask.long 0x8 0.--31. 1. "SEED_B_LO,PCSR Seed B Low." line.long 0xC "CPSW_PCSR_SEED_B_HI_REG,PCSR Seed B High Register." hexmask.long.byte 0xC 26.--31. 1. "RESERVED" hexmask.long 0xC 0.--25. 1. "SEED_B_HI,PCSR Seed B High." line.long 0x10 "CPSW_PCSR_FEC_REG,PCSR FEC Register." hexmask.long 0x10 2.--31. 1. "RESERVED" bitfld.long 0x10 1. "FEC_ENA_ERR_IND,PCSR FEC ENA Error Ind." "0,1" bitfld.long 0x10 0. "FEC_ENABLE,PCSR FEC Enable." "0,1" line.long 0x14 "CPSW_PCSR_CTL_REG,PCSR Control Register." hexmask.long 0x14 2.--31. 1. "RESERVED" bitfld.long 0x14 1. "SIGNAL_OK_EN,PCSR Signal OK Enable." "0,1" bitfld.long 0x14 0. "SIGNAL_OK,PCSR Signal OK." "0,1" line.long 0x18 "CPSW_PCSR_FEC_CNT_REG,PCSR FEC Count Register." hexmask.long.word 0x18 16.--31. 1. "FEC_CORR_CNT,PCSR FEC Corrected Error Count." hexmask.long.word 0x18 0.--15. 1. "FEC_UNCORRCNT,PCSR FEC Uncorrected Error Count." line.long 0x1C "CPSW_PCSR_ERROR_FIFO_REG,PCSR Error FIFO Register." hexmask.long 0x1C 1.--31. 1. "RESERVED" bitfld.long 0x1C 0. "ERROR_FIFO_CTC,PCSR Error FIFO CTC." "0,1" tree.end tree "CPSW0_NUSS_RAM" base ad:0xC000000 group.long 0x32000++0x3 line.long 0x0 "CPSW_FETCH_LOC_y,These are the RAM locations for one Ethernet port. Offset = 00032000h + (y * 4h); where y = 0h to 3FFh" hexmask.long.word 0x0 22.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location." tree.end tree "CPSW0_NUSS_SGMII" base ad:0xC000000 rgroup.long 0x100++0x3 line.long 0x0 "CPSW_SGMII_IDVER_REG_j,SGMII IDVER register. Offset = 100h + (j * 100h); where j = 0h to 7h." hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,MODULE value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x104++0x3 line.long 0x0 "CPSW_SGMII_SOFT_RESET_REG_j,SGMII Soft Reset Register. Offset = 104h + (j * 100h); where j = 0h to 7h." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "RT_SOFT_RESET,Transmit and Receive Software Reset.This bit is intended to be used when changing between loopback mode and normal mode of operation." "0,1" bitfld.long 0x0 0. "SOFT_RESET,Software Reset." "0,1" group.long 0x110++0x3 line.long 0x0 "CPSW_SGMII_CONTROL_REG_j,SGMII Control Register Offset = 110h + (j * 100h); where j = 0h to 7h." hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "TEST_PATTERN_EN,Test Pattern Enable." "0,1" bitfld.long 0x0 5. "MASTER,Master Mode." "0,1" bitfld.long 0x0 4. "LOOPBACK,Loopback mode." "0,1" newline bitfld.long 0x0 3. "MR_NP_LOADED,Next Page Loaded." "0,1" bitfld.long 0x0 2. "FAST_LINK_TIMER,Fast Link Timer." "0,1" bitfld.long 0x0 1. "MR_AN_RESTART,Auto Negotiation Restart." "0,1" bitfld.long 0x0 0. "MR_AN_ENABLE,Auto Negotiation Enable." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "CPSW_SGMII_STATUS_REG_j,SGMII Status Register Offset = 114h + (j * 100h); where j = 0h to 7h." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "FIB_SIG_DETECT,Fiber Signal Detect." "0,1" bitfld.long 0x0 4. "LOCK,Lock." "0,1" bitfld.long 0x0 3. "MR_PAGE_RX,Next Page Received." "0,1" newline bitfld.long 0x0 2. "MR_AN_COMPLETE,Auto negotiation complete." "0,1" bitfld.long 0x0 1. "AN_ERROR,Auto negotiation error." "0,1" bitfld.long 0x0 0. "LINK,Link indicator." "0,1" group.long 0x118++0x7 line.long 0x0 "CPSW_SGMII_MR_ADV_ABILITY_REG_j,SGMII MR Advertized Ability Register. Offset = 118h + (j * 100h); where j = 0h to 7h." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "MR_ADV_ABILITY,Advertised Ability." line.long 0x4 "CPSW_SGMII_MR_NP_TX_REG_j,SGMII Next Pate Transmit Register. Offset = 11Ch + (j * 100h); where j = 0h to 7h." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "MR_NP_TX,Next Page Transmit." rgroup.long 0x120++0x7 line.long 0x0 "CPSW_SGMII_MR_LP_ADV_ABILITY_REG_j,SGMII Link Partner Advertized Ability Register. Offset = 120h + (j * 100h); where j = 0h to 7h." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "MR_LP_ADV_ABILITY,Link Partner Advertised Ability." line.long 0x4 "CPSW_SGMII_MR_LP_NP_RX_REG_j,SGMII Link Partner Next Page Receive Register Offset = 124h + (j * 100h); where j = 0h to 7h." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received." group.long 0x130++0xB line.long 0x0 "CPSW_SGMII_TX_CFG_REG_j,SGMII Transmit Configuration Register Offset = 130h + (j * 100h); where j = 0h to 7h." hexmask.long 0x0 0.--31. 1. "TX_CFG,Transmit configuration register output" line.long 0x4 "CPSW_SGMII_RX_CFG_REG_j,SGMII Receive Configuration Register Offset = 134h + (j * 100h); where j = 0h to 7h." hexmask.long 0x4 0.--31. 1. "RX_CFG,Receive configuration register output" line.long 0x8 "CPSW_SGMII_AUX_CFG_REG_j,SGMII Auxiliary Configuration Register. Offset = 138h + (j * 100h); where j = 0h to 7h." hexmask.long 0x8 0.--31. 1. "AUX_CFG,Auxiliary configuration register output" group.long 0x140++0x7 line.long 0x0 "CPSW_SGMII_DIAG_CLEAR_REG_j,SGMII Diagnostics Clear Register Offset = 140h + (j * 100h); where j = 0h to 7h" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "DIAG_CLEAR,Diagnostics Clear." "0,1" line.long 0x4 "CPSW_SGMII_DIAG_CONTROL_REG_j,SGMII Diagnostics Control Register Offset = 144h + (j * 100h); where j = 0h to 7h." hexmask.long 0x4 7.--31. 1. "RESERVED" bitfld.long 0x4 4.--6. "DIAG_SM_SEL,Diagnostic Select." "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "RESERVED" "0,1,2,3" bitfld.long 0x4 0.--1. "DIAG_EDGE_SEL,Diagnostis Hold Signals Edge Select" "0,1,2,3" rgroup.long 0x148++0x3 line.long 0x0 "CPSW_SGMII_DIAG_STATUS_REG_j,SGMII Diagnostics Status Register Offset = 148h + (j * 100h); where j = 0h to 7h." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "DIAG_STATUS,Diagnostics status." tree.end tree "CPSW0_NUSS_SS" base ad:0xC000000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_SS_CPSW_NUSS_IDVER_REG,ID Version Register." hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x4++0x13 line.long 0x0 "CPSW_SS_SYNCE_COUNT_REG,SyncE Count Register" hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,Sync E Count Value" line.long 0x4 "CPSW_SS_SYNCE_MUX_REG,SyncE Mux Register" hexmask.long 0x4 6.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "SYNCE_SEL,Sync E Select Value" line.long 0x8 "CPSW_SS_CONTROL_REG,Control Register" hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode:" "0,1" bitfld.long 0x8 0. "EEE_EN,Energy Efficient Ethernet Enable:" "0,1" line.long 0xC "CPSW_SS_SGMII_NON_FIBER_MODE_REG,SGMII NON FIBER Mode Register" hexmask.long 0xC 4.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--3. 1. "SGMII_NON_FIBER_MODE,This register bit goes to the CPSGMII mode input only" line.long 0x10 "CPSW_SS_SERDES_RESET_ISO_REG,SyncE Mux Register." hexmask.long 0x10 4.--31. 1. "RESERVED" hexmask.long.byte 0x10 0.--3. 1. "SERDES_RESET_ISO,These bits control whether the SERDES ignores the hard reset for isolation or not" rgroup.long 0x1C++0x7 line.long 0x0 "CPSW_SS_SUBSSYSTEM_STATUS_REG,Subsystem Status Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW." "0,1" line.long 0x4 "CPSW_SS_SUBSYSTEM_CONFIG_REG,Return to the . Subsystem Configuration Register" hexmask.long.byte 0x4 28.--31. 1. "RESERVED" hexmask.long.byte 0x4 20.--27. 1. "XGMII,The Number of XGMII Ports included in the CPSW_NUSS" bitfld.long 0x4 19. "QSGMII,QSGMII is included in the CPSW_NUSS" "0,1" bitfld.long 0x4 18. "SGMII,SGMII is included in the CPSW_NUSS" "0,1" newline bitfld.long 0x4 17. "RGMII,RGMII is included in the CPSW_NUSS" "0,1" bitfld.long 0x4 16. "RMII,RMII is included in the CPSW_NUSS" "0,1" bitfld.long 0x4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "NUM_GENF,The number of CPTS GENF outputs" newline hexmask.long.byte 0x4 0.--7. 1. "NUM_PORTS,The total number of ports including the host port 0" rgroup.long 0x30++0xF line.long 0x0 "CPSW_SS_RGMII1_STATUS_REG,RGMII Port 1 Status Register." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "FULLDUPLEX,RGMII Port 1 full duplex:" "0,1" bitfld.long 0x0 1.--2. "SPEED,RGMII Port 1 speed:" "0,1,2,3" bitfld.long 0x0 0. "LINK,RGMII Port 1 link indicator:" "0,1" line.long 0x4 "CPSW_SS_RGMII2_STATUS_REG,RGMII Port 2 Status Register." hexmask.long 0x4 4.--31. 1. "RESERVED" bitfld.long 0x4 3. "FULLDUPLEX,RGMII Port 2 full dulex:" "0,1" bitfld.long 0x4 1.--2. "SPEED,RGMII Port 2 speed:" "0,1,2,3" bitfld.long 0x4 0. "LINK,RGMII Port 2 link indicator:" "0,1" line.long 0x8 "CPSW_SS_RGMII3_STATUS_REG,RGMII 3 Port Status Register." hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 3. "FULLDUPLEX,RGMII Port 3 full dulex:" "0,1" bitfld.long 0x8 1.--2. "SPEED,RGMII Port 3 speed:" "0,1,2,3" bitfld.long 0x8 0. "LINK,RGMII Port 3 link indicator:" "0,1" line.long 0xC "CPSW_SS_RGMII4_STATUS_REG,RGMII Port 4 Status Register." hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 3. "FULLDUPLEX,RGMII Port 4 full dulex:" "0,1" bitfld.long 0xC 1.--2. "SPEED,RGMII Port 4 speed:" "0,1,2,3" bitfld.long 0xC 0. "LINK,RGMII Port 4 link indicator:" "0,1" group.long 0x60++0x3 line.long 0x0 "CPSW_SS_QSGMII_CONTROL_REG,QSGMII Control Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "Q0_RDCD,QSGMII0 Running Disparity Check Disable" "0,1" rgroup.long 0x64++0x3 line.long 0x0 "CPSW_SS_QSGMII_STATUS_REG,QSGMII Status Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "Q0_RX_SYNC,QSGMII0 RX Sync Detected" "0,1" rgroup.long 0x74++0x7 line.long 0x0 "CPSW_SS_STATUS_XGMII_LINK_REG,XGMII Link Status Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "XGMII1_LINK,Port 1 XGMII Link Indicator" "0,1" line.long 0x4 "CPSW_SS_STATUS_SGMII_LINK_REG,SGMII Link Status Register." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "SGMII1_LINK,Port 1 SGMII Link Indicator" "0,1" group.long 0x80++0x3 line.long 0x0 "CPSW_SS_SUBSYSTEM_USXGMII0_CONTROL,Return to the . USXGMII0 Control Register" hexmask.long 0x0 5.--31. 1. "RESERVED" bitfld.long 0x0 4. "USXGMII_HALF_RATE_PCSR,USXGMII Half Rate PCSR" "0,1" bitfld.long 0x0 3. "RESERVED" "0,1" bitfld.long 0x0 0.--2. "USXGMII_REP_RATE,USXGMII Rep Rate" "0,1,2,3,4,5,6,7" tree.end tree "CPSW0_NUSS_STAT" base ad:0xC000000 group.long 0x3A000++0xDF line.long 0x0 "CPSW_STAT_RXGOODFRAMES_k,The total number of good frames received on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Had a length of 64.." hexmask.long 0x0 0.--31. 1. "COUNT,Total number of good frames received." line.long 0x4 "CPSW_STAT_RXBROADCASTFRAMES_k,The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF- Had a length of [13-0] RX_MAXLEN.." hexmask.long 0x4 0.--31. 1. "COUNT,Total number of good broadcast frames received." line.long 0x8 "CPSW_STAT_RXMULTICASTFRAMES_k,The total number of good multicast frames received on the port. A good multicast frame is defined to be:- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF- Had a length of.." hexmask.long 0x8 0.--31. 1. "COUNT,Total number of good multicast frames received." line.long 0xC "CPSW_STAT_RXPAUSEFRAMES_k,Total number of pause frames received Offset = 0003A00Ch + (k * 200h); where k = 0h to 4h" hexmask.long 0xC 0.--31. 1. "COUNT,Total number of pause frames received." line.long 0x10 "CPSW_STAT_RXCRCERRORS_k,The total number of frames received on the port that experienced a CRC error. Such a frame:- Was any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Was of.." hexmask.long 0x10 0.--31. 1. "COUNT,Total number of CRC errors frames received" line.long 0x14 "CPSW_STAT_RXALIGNCODEERRORS_k,Total number of alignment/code errors received Offset = 0003A014h + (k * 200h); where k = 0h to 4h" hexmask.long 0x14 0.--31. 1. "COUNT,Total number of alignment/code errors received" line.long 0x18 "CPSW_STAT_RXOVERSIZEDFRAMES_k,The total number of oversized frames received on the port. An oversized frame is defined to be:- Was any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode-.." hexmask.long 0x18 0.--31. 1. "COUNT,Total number of oversized frames received." line.long 0x1C "CPSW_STAT_RXJABBERFRAMES_k,Total number of jabber frames received Offset = 0003A01Ch + (k * 200h); where k = 0h to 4h" hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of jabber frames received" line.long 0x20 "CPSW_STAT_RXUNDERSIZEDFRAMES_k,The total number of undersized frames received on the port. An undersized frame is defined to be:- Was any data frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Was less.." hexmask.long 0x20 0.--31. 1. "COUNT,Total number of undersized frames received" line.long 0x24 "CPSW_STAT_RXFRAGMENTS_k,The total number of frame fragments received on the port. A frame fragment is defined to be:- Any data frame (address matching does not matter)- Less than 64 bytes long- Having a CRC error. an alignment error. or a code error- Not.." hexmask.long 0x24 0.--31. 1. "COUNT,Total number of fragmented frames received." line.long 0x28 "CPSW_STAT_ALE_DROP_k,Total number of frames dropped by the ALE. Offset = 0003A028h + (k * 200h); where k = 0h to 4h" hexmask.long 0x28 0.--31. 1. "COUNT,Total number of frames dropped by the ALE." line.long 0x2C "CPSW_STAT_ALE_OVERRUN_DROP_k,Total number of overrun frames dropped by the ALE. Offset = 0003A02Ch + (k * 200h); where k = 0h to 4h" hexmask.long 0x2C 0.--31. 1. "COUNT,Total number of overrun frames dropped by the ALE." line.long 0x30 "CPSW_STAT_RXOCTETS_k,The total number of bytes in all good frames received on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Of length.." hexmask.long 0x30 0.--31. 1. "COUNT,Total number of received bytes in good frames" line.long 0x34 "CPSW_STAT_TXGOODFRAMES_k,The total number of good frames transmitted on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Any length- Had.." hexmask.long 0x34 0.--31. 1. "COUNT,Total number of good frames transmitted" line.long 0x38 "CPSW_STAT_TXBROADCASTFRAMES_k,The total number of good broadcast frames transmitted on the port. A good broadcast frame is defined to be:- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF- Any length- Had no late or.." hexmask.long 0x38 0.--31. 1. "COUNT,Total number of good broadcast frames transmitted" line.long 0x3C "CPSW_STAT_TXMULTICASTFRAMES_k,The total number of good multicast frames transmitted on the port. A good multicast frame is defined to be:- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF- Any length-.." hexmask.long 0x3C 0.--31. 1. "COUNT,Total number of good multicast frames transmitted" line.long 0x40 "CPSW_STAT_TXPAUSEFRAMES_k,Total number of pause frames transmitted Offset = 0003A040h + (k * 200h); where k = 0h to 4h" hexmask.long 0x40 0.--31. 1. "COUNT,Total number of pause frames transmitted" line.long 0x44 "CPSW_STAT_TXDEFERREDFRAMES_k,Total number of deferred frames transmitted Offset = 0003A044h + (k * 200h); where k = 0h to 4h" hexmask.long 0x44 0.--31. 1. "COUNT,Total number of deferred frames transmitted" line.long 0x48 "CPSW_STAT_TXCOLLISIONFRAMES_k,Total number of transmitted frames experiencing a collision Offset = 0003A048h + (k * 200h); where k = 0h to 4h" hexmask.long 0x48 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a collision" line.long 0x4C "CPSW_STAT_TXSINGLECOLLFRAMES_k,Total number of transmitted frames experiencing a single collision Offset = 0003A04Ch + (k * 200h); where k = 0h to 4h" hexmask.long 0x4C 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a single collision" line.long 0x50 "CPSW_STAT_TXMULTCOLLFRAMES_k,Total number of transmitted frames experiencing multiple collisions Offset = 0003A050h + (k * 200h); where k = 0h to 4h" hexmask.long 0x50 0.--31. 1. "COUNT,Total number of transmitted frames experiencing multiple collisions" line.long 0x54 "CPSW_STAT_TXEXCESSIVECOLLISIONS_k,Total number of transmitted frames abandoned due to excessive collisions Offset = 0003A054h + (k * 200h); where k = 0h to 4h" hexmask.long 0x54 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to excessive collisions" line.long 0x58 "CPSW_STAT_TXLATECOLLISIONS_k,Total number of transmitted frames abandoned due to a late collision Offset = 0003A058h + (k * 200h); where k = 0h to 4h" hexmask.long 0x58 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to a late collision" line.long 0x5C "CPSW_STAT_RXIPGERROR_k,Total number of receive inter-packet gap errors (10G only) Offset = 0003A05Ch + (k * 200h); where k = 0h to 4h" hexmask.long 0x5C 0.--31. 1. "COUNT,Total number of receive inter-packet gap errors (10G only)" line.long 0x60 "CPSW_STAT_TXCARRIERSENSEERRORS_k,Total number of transmitted frames that experienced a carrier loss Offset = 0003A060h + (k * 200h); where k = 0h to 4h" hexmask.long 0x60 0.--31. 1. "COUNT,Total number of transmitted frames that experienced a carrier loss" line.long 0x64 "CPSW_STAT_TXOCTETS_k,The total number of bytes in all good frames transmitted on the port. A good frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Was any size- Had no late or.." hexmask.long 0x64 0.--31. 1. "COUNT,Total number of bytes in all good frames transmitted" line.long 0x68 "CPSW_STAT_OCTETFRAMES64_k,The total number of 64-byte frames received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did not experience late.." hexmask.long 0x68 0.--31. 1. "COUNT,Total number of 64-byte frames received and transmitted" line.long 0x6C "CPSW_STAT_OCTETFRAMES65T127_k,The total number of frames of size 65 to 127 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0x6C 0.--31. 1. "COUNT,Total number of frames of size 65 to 127 bytes received and transmitted" line.long 0x70 "CPSW_STAT_OCTETFRAMES128T255_k,The total number of frames of size 128 to 255 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0x70 0.--31. 1. "COUNT,Total number of frames of size 128 to 255 bytes received and transmitted" line.long 0x74 "CPSW_STAT_OCTETFRAMES256T511_k,The total number of frames of size 256 to 511 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0x74 0.--31. 1. "COUNT,Total number of frames of size 256 to 511 bytes received and transmitted" line.long 0x78 "CPSW_STAT_OCTETFRAMES512T1023_k,The total number of frames of size 512 to 1023 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address-.." hexmask.long 0x78 0.--31. 1. "COUNT,Total number of frames of size 512 to 1023 bytes received and transmitted" line.long 0x7C "CPSW_STAT_OCTETFRAMES1024TUP_k,The total number of frames of size 1024 to [13-0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast.." hexmask.long 0x7C 0.--31. 1. "COUNT,Total number of frames of size 1024 to" line.long 0x80 "CPSW_STAT_NETOCTETS_k,The total number of bytes of frame data received and transmitted on the port. Each frame counted:- was any data or MAC control frame destined for any unicast. broadcast or multicast address (address match does not matter)- Any.." hexmask.long 0x80 0.--31. 1. "COUNT,Total number of bytes received and transmitted" line.long 0x84 "CPSW_STAT_RX_BOTTOM_OF_FIFO_DROP_k,Receive Bottom of FIFO Drop. Offset = 0003A084h + (k * 200h); where k = 0h to 4h" hexmask.long 0x84 0.--31. 1. "COUNT,Receive Bottom of FIFO Drop." line.long 0x88 "CPSW_STAT_PORTMASK_DROP_k,Total number of dropped frames received due to portmask. Offset = 0003A088h + (k * 200h); where k = 0h to 4h" hexmask.long 0x88 0.--31. 1. "COUNT,Total number of dropped frames received due to portmask." line.long 0x8C "CPSW_STAT_RX_TOP_OF_FIFO_DROP_k,Receive Top of FIFO Drop. Offset = 0003A08Ch + (k * 200h); where k = 0h to 4h" hexmask.long 0x8C 0.--31. 1. "COUNT,Receive Top of FIFO Drop." line.long 0x90 "CPSW_STAT_ALE_RATE_LIMIT_DROP_k,Total number of dropped frames due to ALE Rate Limiting. Offset = 0003A090h + (k * 200h); where k = 0h to 4h" hexmask.long 0x90 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Rate Limiting." line.long 0x94 "CPSW_STAT_ALE_VID_INGRESS_DROP_k,Total number of dropped frames due to ALE VID Ingress. Offset = 0003A094h + (k * 200h); where k = 0h to 4h" hexmask.long 0x94 0.--31. 1. "COUNT,Total number of dropped frames due to ALE VID Ingress." line.long 0x98 "CPSW_STAT_ALE_DA_EQ_SA_DROP_k,Total number of dropped frames due to DA=SA. Offset = 0003A098h + (k * 200h); where k = 0h to 4h" hexmask.long 0x98 0.--31. 1. "COUNT,Total number of dropped frames due to DA=SA." line.long 0x9C "CPSW_STAT_ALE_BLOCK_DROP_k,Total number of dropped frames due to ALE Block Mode. Offset = 0003A09Ch + (k * 200h); where k = 0h to 4h" hexmask.long 0x9C 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Block Mode." line.long 0xA0 "CPSW_STAT_ALE_SECURE_DROP_k,Total number of dropped frames due to ALE Secure Mode. Offset = 0003A0A0h + (k * 200h); where k = 0h to 4h" hexmask.long 0xA0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Secure Mode." line.long 0xA4 "CPSW_STAT_ALE_AUTH_DROP_k,Total number of dropped frames due to ALE Authentication. Offset = 0003A0A4h + (k * 200h); where k = 0h to 4h" hexmask.long 0xA4 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Authentication." line.long 0xA8 "CPSW_STAT_ALE_UNKN_UNI_k,ALE Receive Unknown Unicast. Offset = 0003A0A8h + (k * 200h); where k = 0h to 4h" hexmask.long 0xA8 0.--31. 1. "COUNT,ALE Receive Unknown Unicast." line.long 0xAC "CPSW_STAT_ALE_UNKN_UNI_BCNT_k,ALE Receive Unknown Unicast Bytecount. Offset = 0003A0ACh + (k * 200h); where k = 0h to 4h" hexmask.long 0xAC 0.--31. 1. "COUNT,ALE Receive Unknown Unicast Bytecount." line.long 0xB0 "CPSW_STAT_ALE_UNKN_MLT_K,ALE Receive Unknown Multicast. Offset = 0003A0B0h + (k * 200h); where k = 0h to 4h" hexmask.long 0xB0 0.--31. 1. "COUNT,ALE Receive Unknown Multicast." line.long 0xB4 "CPSW_STAT_ALE_UNKN_MLT_BCNT_k,ALE Receive Unknown Multicast Bytecount. Offset = 0003A0B4h + (k * 200h); where k = 0h to 4h" hexmask.long 0xB4 0.--31. 1. "COUNT,ALE Receive Unknown Multicast Bytecount." line.long 0xB8 "CPSW_STAT_ALE_UNKN_BRD_k,ALE Receive Unknown Broadcast. Offset = 0003A0B8h + (k * 200h); where k = 0h to 4h" hexmask.long 0xB8 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast." line.long 0xBC "CPSW_STAT_ALE_UNKN_BRD_BCNT_k,ALE Receive Unknown Broadcast Bytecount. Offset = 0003A0BCh + (k * 200h); where k = 0h to 4h" hexmask.long 0xBC 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast Bytecount." line.long 0xC0 "CPSW_STAT_ALE_POL_MATCH_k,ALE Policer Matched. Offset = 0003A0C0h + (k * 200h); where k = 0h to 4h" hexmask.long 0xC0 0.--31. 1. "COUNT,ALE Policer Matched." line.long 0xC4 "CPSW_STAT_ALE_POL_MATCH_RED_k,ALE Policer Matched and Condition Red. Offset = 0003A0C4h + (k * 200h); where k = 0h to 4h" hexmask.long 0xC4 0.--31. 1. "COUNT,ALE Policer Matched and Condition Red." line.long 0xC8 "CPSW_STAT_ALE_POL_MATCH_YELLOW_k,ALE Policer Matched and Condition Yellow. Offset = 0003A0C8h + (k * 200h); where k = 0h to 4h" hexmask.long 0xC8 0.--31. 1. "COUNT,ALE Policer Matched and Condition Yellow." line.long 0xCC "CPSW_STAT_ALE_MULT_SA_DROP_k,ALE Multicast Source Address Drop. Offset = 0003A0CCh + (k * 200h); where k = 0h to 4h" hexmask.long 0xCC 0.--31. 1. "COUNT,ALE Multicast Source Address drop." line.long 0xD0 "CPSW_STAT_ALE_DUAL_VLAN_DROP_k,ALE Dual VLAN Drop. Offset = 0003A0D0h + (k * 200h); where k = 0h to 4h" hexmask.long 0xD0 0.--31. 1. "COUNT,ALE Dual VLAN drop." line.long 0xD4 "CPSW_STAT_ALE_LEN_ERROR_DROP_k,ALE Length Error Drop. Offset = 0003A0D4h + (k * 200h); where k = 0h to 4h" hexmask.long 0xD4 0.--31. 1. "COUNT,ALE Length Error drop." line.long 0xD8 "CPSW_STAT_ALE_IP_NEXT_HDR_DROP_k,ALE IP Next Header Drop. Offset = 0003A0D8h + (k * 200h); where k = 0h to 4h" hexmask.long 0xD8 0.--31. 1. "COUNT,ALE Next Header drop." line.long 0xDC "CPSW_STAT_ALE_IPV4_FRAG_DROP_k,ALE IPV4 Frag Drop. Offset = 0003A0DCh + (k * 200h); where k = 0h to 4h" hexmask.long 0xDC 0.--31. 1. "COUNT,ALE IPV4 Fragment drop." group.long 0x3A140++0x17 line.long 0x0 "CPSW_STAT_IET_RX_ASSEMBLY_ERROR_REG_k,IET Receive Assembly Error. Offset = 0003A140h + (k * 200h); where k = 0h to 4h Note: IET functionallity is not supported for CPSW0 Port 0." hexmask.long 0x0 0.--31. 1. "IET_RX_ASSEMBLY_ERROR,IET Receive Assembly Error.Note: IET functionallity is not supported for CPSW0 Port 0." line.long 0x4 "CPSW_STAT_IET_RX_ASSEMBLY_OK_REG_k,IET Receive Assembly Ok. Offset = 0003A144h + (k * 200h); where k = 0h to 4h Note: IET functionallity is not supported for CPSW0 Port 0." hexmask.long 0x4 0.--31. 1. "IET_RX_ASSEMBLY_OK,IET Receive Assembly Ok.Note: IET functionallity is not supported for CPSW0 Port 0." line.long 0x8 "CPSW_STAT_IET_RX_SMD_ERROR_REG_k,IET Receive Smd Error. Offset = 0003A148h + (k * 200h); where k = 0h to 4h Note: IET functionallity is not supported for CPSW0 Port 0." hexmask.long 0x8 0.--31. 1. "IET_RX_SMD_ERROR,IET Receive Smd Error.Note: IET functionallity is not supported for CPSW0 Port 0." line.long 0xC "CPSW_STAT_IET_RX_FRAG_REG_k,IET Receive Frag. Offset = 0003A14Ch + (k * 200h); where k = 0h to 4h Note: IET functionallity is not supported for CPSW0 Port 0." hexmask.long 0xC 0.--31. 1. "IET_RX_FRAG,IET Receive Frag.Note: IET functionallity is not supported for CPSW0 Port 0." line.long 0x10 "CPSW_STAT_IET_TX_HOLD_REG_k,IET Transmit Hold. Offset = 0003A150h + (k * 200h); where k = 0h to 4h Note: IET functionallity is not supported for CPSW0 Port 0." hexmask.long 0x10 0.--31. 1. "IET_TX_HOLD,IET Transmit Hold.Note: IET functionallity is not supported for CPSW0 Port 0." line.long 0x14 "CPSW_STAT_IET_TX_FRAG_REG_k,IET Transmit Frag. Offset = 0003A154h + (k * 200h); where k = 0h to 4h Note: IET functionallity is not supported for CPSW0 Port 0." hexmask.long 0x14 0.--31. 1. "IET_TX_FRAG,IET Transmit Frag.Note: IET functionallity is not supported for CPSW0 Port 0." group.long 0x3A17C++0x7 line.long 0x0 "CPSW_STAT_TX_MEMORY_PROTECT_ERROR_k,Transmit Memory Protect CRC Error. Offset = 0003A17Ch + (k * 200h); where k = 0h to 4h" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error.Note: If there is a memorry protect error then this COUNT value will increment and issue a STAT_PEND0 interrupt when this bit field is non-zero.That is different from the other stats which only issue an interrupt.." line.long 0x4 "CPSW_STAT_ENET_PN_TX_PRI_REG_k_y,ENET Port n PRIORITY N Packet Count. Offset = 0003A180h + (k * 200h) + (y * 4h); where k = 0h to 4h. y = 0h to 7h" hexmask.long 0x4 0.--31. 1. "PN_TX_PRIN,ENET TX Priority Packet Count." group.long 0x3A1A0++0x3 line.long 0x0 "CPSW_STAT_ENET_PN_TX_PRI_BCNT_REG_k_y,ENET Port n PRIORITY N Packet Byte Count. Offset = 0003A1A0h + (k * 200h) + (y * 4h); where k = 0h to 4h. y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_BCNT,ENET Port n PRIORITY N Packet Byte Count." group.long 0x3A1C0++0x3 line.long 0x0 "CPSW_STAT_ENET_PN_TX_PRI_DROP_REG_k_y,ENET Port n PRIORITY N Packet Drop Count. Offset = 0003A1C0h + (k * 200h) + (y * 4h); where k = 0h to 4h. y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP,ENET Port n PRIORITY N Packet Drop Count." group.long 0x3A1E0++0x3 line.long 0x0 "CPSW_STAT_ENET_PN_TX_PRI_DROP_BCNT_REG_k_y,ENET Port n PRIORITY N Packet Drop Byte Count. Offset = 0003A1E0h + (k * 200h) + (y * 4h); where k = 0h to 4h. y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP_BCNT,ENET Port n PRIORITY N Packet Drop Byte Count." tree.end tree.end tree "CTRL_MMR0_CFG0" base ad:0x100000 rgroup.long 0x2000++0x3 line.long 0x0 "CTRLMMR_PID" bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module functional identifier - CTRL MMR" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL revision number" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision number" rgroup.long 0x2008++0x3 line.long 0x0 "CTRLMMR_MMR_CFG1" bitfld.long 0x0 31. "PROXY_EN,Proxy addressing enabled" "0,1" hexmask.long.tbyte 0x0 8.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "PARTITIONS,Indicates present partitions" group.long 0x2030++0x3 line.long 0x0 "CTRLMMR_MAIN_DEVSTAT" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "BOOTMODE,Specifies the device Primary and Backup boot media." rgroup.long 0x2034++0x3 line.long 0x0 "CTRLMMR_MAIN_BOOTCFG" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "BOOTMODE,Specifies the device Primary and Backup boot media as latched at PORz" rgroup.long 0x2044++0x3 line.long 0x0 "CTRLMMR_MAIN_FEATURE_STAT1" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "MCAN_FD_EN,FD mode is supported on MAIN MCAN interfaces when set" "0,1" hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" group.long 0x2120++0x7 line.long 0x0 "CTRLMMR_IPC_SET8" hexmask.long 0x0 4.--31. 1. "IPC_SRC_SET,Read returns current value" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "IPC_SET,Read returns 0" "0,1" line.long 0x4 "CTRLMMR_IPC_SET9" hexmask.long 0x4 4.--31. 1. "IPC_SRC_SET,Read returns current value" rbitfld.long 0x4 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "IPC_SET,Read returns 0" "0,1" group.long 0x2140++0x7 line.long 0x0 "CTRLMMR_IPC_SET16" hexmask.long 0x0 4.--31. 1. "IPC_SRC_SET,Read returns current value" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "IPC_SET,Read returns 0" "0,1" line.long 0x4 "CTRLMMR_IPC_SET17" hexmask.long 0x4 4.--31. 1. "IPC_SRC_SET,Read returns current value" rbitfld.long 0x4 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "IPC_SET,Read returns 0" "0,1" group.long 0x21A0++0x7 line.long 0x0 "CTRLMMR_IPC_CLR8" hexmask.long 0x0 4.--31. 1. "IPC_SRC_CLR,Read returns current value" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "IPC_CLR,Read returns current value" "0,1" line.long 0x4 "CTRLMMR_IPC_CLR9" hexmask.long 0x4 4.--31. 1. "IPC_SRC_CLR,Read returns current value" rbitfld.long 0x4 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "IPC_CLR,Read returns current value" "0,1" group.long 0x21C0++0x7 line.long 0x0 "CTRLMMR_IPC_CLR16" hexmask.long 0x0 4.--31. 1. "IPC_SRC_CLR,Read returns current value" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "IPC_CLR,Read returns current value" "0,1" line.long 0x4 "CTRLMMR_IPC_CLR17" hexmask.long 0x4 4.--31. 1. "IPC_SRC_CLR,Read returns current value" rbitfld.long 0x4 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "IPC_CLR,Read returns current value" "0,1" group.long 0x2210++0x3 line.long 0x0 "CTRLMMR_PCI_DEVICE_ID" hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Product ID" hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,TI Vendor ID" group.long 0x2220++0x3 line.long 0x0 "CTRLMMR_USB_DEVICE_ID" hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Product ID" hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,TI Vendor ID" group.long 0x3008++0x1B line.long 0x0 "CTRLMMR_LOCK0_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" line.long 0x8 "CTRLMMR_INTR_RAW_STAT" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "PROXY_ERR,Proxy violation occurred (attempt to write a Proxy1 claimed register through its Proxy0 address)" "0,1" bitfld.long 0x8 2. "LOCK_ERR,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Address violation occurred (attempt to read or write an invalid register address)" "0,1" bitfld.long 0x8 0. "PROT_ERR,Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)" "0,1" line.long 0xC "CTRLMMR_INTR_STAT_CLR" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 3. "EN_PROXY_ERR,Enabled proxy interrupt event status" "0,1" bitfld.long 0xC 2. "EN_LOCK_ERR,Enabled lock interrupt event status" "0,1" newline bitfld.long 0xC 1. "EN_ADDR_ERR,Enabled address interrupt event status" "0,1" bitfld.long 0xC 0. "EN_PROT_ERR,Enabled protection interrupt event status" "0,1" line.long 0x10 "CTRLMMR_INTR_EN_SET" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 3. "PROXY_ERR_EN_SET,Proxy interrupt enable" "0,1" bitfld.long 0x10 2. "LOCK_ERR_EN_SET,Lock interrupt enable" "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_SET,Address interrupt enable" "0,1" bitfld.long 0x10 0. "PROT_ERR_EN_SET,Protection interrupt enable" "0,1" line.long 0x14 "CTRLMMR_INTR_EN_CLR" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy interrupt disable" "0,1" bitfld.long 0x14 2. "LOCK_ERR_EN_CLR,Lock interrupt disable" "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Address interrupt disable" "0,1" bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection interrupt disable" "0,1" line.long 0x18 "CTRLMMR_EOI" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x18 0.--7. 1. "VECTOR" rgroup.long 0x3024++0xB line.long 0x0 "CTRLMMR_FAULT_ADDR" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address of the faulted access" line.long 0x4 "CTRLMMR_FAULT_TYPE" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--5. 1. "TYPE,Type of access which faulted 0h - No fault 1h - User execute access 2h - User write access 4h - User read access 8h - Supervisor execute access 10h - Supervisor write access 20h - Supervisor read access" line.long 0x8 "CTRLMMR_FAULT_ATTR" hexmask.long.word 0x8 20.--31. 1. "XID,Transaction ID" hexmask.long.word 0x8 8.--19. 1. "ROUTEID,Route ID" hexmask.long.byte 0x8 0.--7. 1. "PRIVID,Privilege ID" group.long 0x3030++0x3 line.long 0x0 "CTRLMMR_FAULT_CLR" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CLEAR,Fault clear" "0,1" group.long 0x3100++0x17 line.long 0x0 "CTRLMMR_P0_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_P0_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_P0_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_P0_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_P0_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_P0_CLAIM5" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x6000++0x3 line.long 0x0 "CTRLMMR_USB0_CTRL" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 27. "SERDES_SEL,Serdes Selection." "0,1" hexmask.long 0x0 0.--26. 1. "RESERVED,Reserved" group.long 0x6008++0x3 line.long 0x0 "CTRLMMR_USB0_PHY_CTRL" bitfld.long 0x0 31. "CORE_VOLTAGE,Selects the USB PHY core voltage" "0,1" hexmask.long 0x0 0.--30. 1. "RESERVED,Reserved" group.long 0x6044++0xF line.long 0x0 "CTRLMMR_ENET1_CTRL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "RGMII_ID_MODE,Port1 RGMII internal transmit delay selection" "0,1" rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port1 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII 4h - QSGMII 5h - XFI (not supported) 6h - QSGMII_SUB 7h - Reserved" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_ENET2_CTRL" hexmask.long 0x4 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 4. "RGMII_ID_MODE,Port2 RGMII internal transmit delay selection" "0,1" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port2 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII 4h - QSGMII 5h - XFI (not supported) 6h - QSGMII_SUB 7h - Reserved" "0,1,2,3,4,5,6,7" line.long 0x8 "CTRLMMR_ENET3_CTRL" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 4. "RGMII_ID_MODE,Port3 RGMII internal transmit delay selection" "0,1" rbitfld.long 0x8 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port3 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII 4h - QSGMII 5h - XFI (not supported) 6h - QSGMII_SUB 7h - Reserved" "0,1,2,3,4,5,6,7" line.long 0xC "CTRLMMR_ENET4_CTRL" hexmask.long 0xC 5.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 4. "RGMII_ID_MODE,Port4 RGMII internal transmit delay selection" "0,1" rbitfld.long 0xC 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port4 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII 4h - QSGMII 5h - XFI (not supported) 6h - QSGMII_SUB 7h - Reserved" "0,1,2,3,4,5,6,7" group.long 0x6074++0x3 line.long 0x0 "CTRLMMR_PCIE1_CTRL" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "LANE_COUNT,Configures the PCIe lane count" "0,1,2,3" bitfld.long 0x0 7. "MODE_SEL,Selects the operating mode" "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "GENERATION_SEL,Configures the PCIe generation support in the PCIe capabilities linked-list 1h - Gen2 - Controller advertises Gen1 &amp; Gen2 capability and link operates at either speed 2h - Gen3 - Controller advertises Gen1 Gen2 &amp; Gen3.." "0,1,2,3" group.long 0x6080++0xF line.long 0x0 "CTRLMMR_SERDES0_LN0_CTRL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "LANE_FUNC_SEL,Selects the SERDES0 lane0 function 0h - IP1 - Enet Switch Q/SGMII Lane 3 1h - IP2 - PCIe1 Lane0 2h - IP3 - Not used 3h - IP4 - Not used" "0,1,2,3" line.long 0x4 "CTRLMMR_SERDES0_LN1_CTRL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--1. "LANE_FUNC_SEL,Selects the SERDES0 lane1 function 0h - IP1 - Enet Switch Q/SGMII Lane 4 1h - IP2 - PCIe1 Lane1 2h - IP3 - USB3 3h - IP4 - Not Used" "0,1,2,3" line.long 0x8 "CTRLMMR_SERDES0_LN2_CTRL" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--1. "LANE_FUNC_SEL,Selects the SERDES0 lane2 function 0h - IP1 - Enet Switch Q/SGMII Lane 1 1h - IP2 - PCIe1 Lane2 2h - IP3 - Not Used 3h - IP4 - Not Used" "0,1,2,3" line.long 0xC "CTRLMMR_SERDES0_LN3_CTRL" hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0.--1. "LANE_FUNC_SEL,Selects the SERDES0 lane3 function 0h - IP1 - Enet Switch Q/SGMII Lane 2 1h - IP2 - PCIe1 Lane3 2h - IP3 - USB3 3h - IP4 - Not Used" "0,1,2,3" group.long 0x60E0++0x3 line.long 0x0 "CTRLMMR_SERDES0_CTRL" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "RET_EN,Retention enable" "0,1" hexmask.long.byte 0x0 0.--7. 1. "RESERVED,Reserved" group.long 0x6140++0x17 line.long 0x0 "CTRLMMR_EPWM0_CTRL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1" line.long 0x4 "CTRLMMR_EPWM1_CTRL" hexmask.long 0x4 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1" rbitfld.long 0x4 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1" line.long 0x8 "CTRLMMR_EPWM2_CTRL" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1" rbitfld.long 0x8 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1" line.long 0xC "CTRLMMR_EPWM3_CTRL" hexmask.long.tbyte 0xC 11.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 8.--10. "SYNCIN_SEL,Selects the source of the PWM3 synchronization input 0h - PWM3_SYNCIN Pin 1h - PWM2 syncout signal daisy chained 2h - None 3h - None 4h - None 5h - None 6h - None 7h - None" "0,1,2,3,4,5,6,7" rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1" rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1" line.long 0x10 "CTRLMMR_EPWM4_CTRL" hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1" rbitfld.long 0x10 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1" line.long 0x14 "CTRLMMR_EPWM5_CTRL" hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1" rbitfld.long 0x14 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1" group.long 0x6160++0x7 line.long 0x0 "CTRLMMR_SOCA_SEL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "SOCA_SEL,Selects the SOC A output source 0h - OR of all eHRPWM SOCA outputs 1h - None 2h - None 3h - None" "0,1,2,3" line.long 0x4 "CTRLMMR_SOCB_SEL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--1. "SOCB_SEL,Selects the SOC B output source 0h - OR of all eHRPWM SOCB ouputs 1h - None 2h - None 3h - None" "0,1,2,3" rgroup.long 0x61A0++0x3 line.long 0x0 "CTRLMMR_EQEP_STAT" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "PHASE_ERR2,eQEP2 Phase error status" "0,1" bitfld.long 0x0 1. "PHASE_ERR1,eQEP1 Phase error status" "0,1" newline bitfld.long 0x0 0. "PHASE_ERR0,eQEP0 Phase error status" "0,1" group.long 0x61B4++0x3 line.long 0x0 "CTRLMMR_SDIO1_CTRL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "DRV_STR,Selects the SDIO drive strength" group.long 0x6200++0x4F line.long 0x0 "CTRLMMR_TIMER0_CTRL" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_TIMER1_CTRL" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "CASCADE_EN,Enables cascading of TIMER1 to TIMER0" "0,1" hexmask.long.byte 0x4 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x8 "CTRLMMR_TIMER2_CTRL" hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0xC "CTRLMMR_TIMER3_CTRL" hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "CASCADE_EN,Enables cascading of TIMER3 to TIMER2" "0,1" hexmask.long.byte 0xC 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x10 "CTRLMMR_TIMER4_CTRL" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x14 "CTRLMMR_TIMER5_CTRL" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 8. "CASCADE_EN,Enables cascading of TIMER5 to TIMER4" "0,1" hexmask.long.byte 0x14 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x18 "CTRLMMR_TIMER6_CTRL" hexmask.long 0x18 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x1C "CTRLMMR_TIMER7_CTRL" hexmask.long.tbyte 0x1C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 8. "CASCADE_EN,Enables cascading of TIMER7 to TIMER6" "0,1" hexmask.long.byte 0x1C 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x20 "CTRLMMR_TIMER8_CTRL" hexmask.long 0x20 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x24 "CTRLMMR_TIMER9_CTRL" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 8. "CASCADE_EN,Enables cascading of TIMER9 to TIMER8" "0,1" hexmask.long.byte 0x24 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x24 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x28 "CTRLMMR_TIMER10_CTRL" hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER10 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x2C "CTRLMMR_TIMER11_CTRL" hexmask.long.tbyte 0x2C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 8. "CASCADE_EN,Enables cascading of TIMER11 to TIMER10" "0,1" hexmask.long.byte 0x2C 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER11 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x30 "CTRLMMR_TIMER12_CTRL" hexmask.long 0x30 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER12 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x34 "CTRLMMR_TIMER13_CTRL" hexmask.long.tbyte 0x34 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 8. "CASCADE_EN,Enables cascading of TIMER13 to TIMER12" "0,1" hexmask.long.byte 0x34 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x34 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER13 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x38 "CTRLMMR_TIMER14_CTRL" hexmask.long 0x38 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER14 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x3C "CTRLMMR_TIMER15_CTRL" hexmask.long.tbyte 0x3C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 8. "CASCADE_EN,Enables cascading of TIMER15 to TIMER14" "0,1" hexmask.long.byte 0x3C 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x3C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER15 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x40 "CTRLMMR_TIMER16_CTRL" hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER16 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x44 "CTRLMMR_TIMER17_CTRL" hexmask.long.tbyte 0x44 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 8. "CASCADE_EN,Enables cascading of TIMER17 to TIMER16" "0,1" hexmask.long.byte 0x44 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x44 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER17 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x48 "CTRLMMR_TIMER18_CTRL" hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER18 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" line.long 0x4C "CTRLMMR_TIMER19_CTRL" hexmask.long.tbyte 0x4C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 8. "CASCADE_EN,Enables cascading of TIMER19 to TIMER18" "0,1" hexmask.long.byte 0x4C 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x4C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER19 is configured for capture operation. 0h - Use TIMERIO0 pin 1h - Use TIMERIO1 pin 2h - Use TIMERIO2 pin 3h - Use TIMERIO3 pin 4h - Use TIMERIO4 pin 5h -.." "0,1,2,3,4,5,6,7" group.long 0x6280++0x1F line.long 0x0 "CTRLMMR_TIMERIO0_CTRL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "OUT_SEL,Selects the source of the TIMERIO0 output 0h - TIMERIO0 is driven by TIMER0 output 1h - TIMERIO0 is driven by TIMER1 output 2h - TIMERIO0 is driven by TIMER2 output 3h - TIMERIO0 is driven by TIMER3 output 4h - TIMERIO0 is driven by TIMER4 output.." line.long 0x4 "CTRLMMR_TIMERIO1_CTRL" hexmask.long 0x4 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "OUT_SEL,Selects the source of the TIMERIO1 output 0h - TIMERIO1 is driven by TIMER0 output 1h - TIMERIO1 is driven by TIMER1 output 2h - TIMERIO1 is driven by TIMER2 output 3h - TIMERIO1 is driven by TIMER3 output 4h - TIMERIO1 is driven by TIMER4 output.." line.long 0x8 "CTRLMMR_TIMERIO2_CTRL" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--4. 1. "OUT_SEL,Selects the source of the TIMERIO2 output 0h - TIMERIO2 is driven by TIMER0 output 1h - TIMERIO2 is driven by TIMER1 output 2h - TIMERIO2 is driven by TIMER2 output 3h - TIMERIO2 is driven by TIMER3 output 4h - TIMERIO2 is driven by TIMER4 output.." line.long 0xC "CTRLMMR_TIMERIO3_CTRL" hexmask.long 0xC 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--4. 1. "OUT_SEL,Selects the source of the TIMERIO3 output 0h - TIMERIO3 is driven by TIMER0 output 1h - TIMERIO3 is driven by TIMER1 output 2h - TIMERIO3 is driven by TIMER2 output 3h - TIMERIO3 is driven by TIMER3 output 4h - TIMERIO3 is driven by TIMER4 output.." line.long 0x10 "CTRLMMR_TIMERIO4_CTRL" hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--4. 1. "OUT_SEL,Selects the source of the TIMERIO4 output 0h - TIMERIO4 is driven by TIMER0 output 1h - TIMERIO4 is driven by TIMER1 output 2h - TIMERIO4 is driven by TIMER2 output 3h - TIMERIO4 is driven by TIMER3 output 4h - TIMERIO4 is driven by TIMER4 output.." line.long 0x14 "CTRLMMR_TIMERIO5_CTRL" hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 0.--4. 1. "OUT_SEL,Selects the source of the TIMERIO5 output 0h - TIMERIO5 is driven by TIMER0 output 1h - TIMERIO5 is driven by TIMER1 output 2h - TIMERIO5 is driven by TIMER2 output 3h - TIMERIO5 is driven by TIMER3 output 4h - TIMERIO5 is driven by TIMER4 output.." line.long 0x18 "CTRLMMR_TIMERIO6_CTRL" hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x18 0.--4. 1. "OUT_SEL,Selects the source of the TIMERIO6 output 0h - TIMERIO6 is driven by TIMER0 output 1h - TIMERIO6 is driven by TIMER1 output 2h - TIMERIO6 is driven by TIMER2 output 3h - TIMERIO6 is driven by TIMER3 output 4h - TIMERIO6 is driven by TIMER4 output.." line.long 0x1C "CTRLMMR_TIMERIO7_CTRL" hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x1C 0.--4. 1. "OUT_SEL,Selects the source of the TIMERIO7 output 0h - TIMERIO7 is driven by TIMER0 output 1h - TIMERIO7 is driven by TIMER1 output 2h - TIMERIO7 is driven by TIMER2 output 3h - TIMERIO7 is driven by TIMER3 output 4h - TIMERIO7 is driven by TIMER4 output.." group.long 0x62C0++0x7 line.long 0x0 "CTRLMMR_I3C0_CTRL0" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" hexmask.long.word 0x0 16.--30. 1. "PID_MFR_ID,Manufacturer ID" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "ROLE,Master Role" "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "PID_INSTANCE,Provisional ID Instance. This input corresponds to bits[15:12] of the Provisional ID. It is intended to provide a way of differentiating several I3C devices if there would be no other way to have each manufactured device have a unique.." line.long 0x4 "CTRLMMR_I3C0_CTRL1" hexmask.long.byte 0x4 24.--31. 1. "BUS_AVAIL_TIME,Indicates the number of sclk cycles in the Bus Available condition" hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--17. 1. "BUS_IDLE_TIME,Indicates the number of sclk cycles in the Bus Idle condition" group.long 0x62E0++0x3 line.long 0x0 "CTRLMMR_I2C0_CTRL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "HS_MCS_EN,HS Mode master current source enable." "0,1" group.long 0x6584++0x7 line.long 0x0 "CTRLMMR_MCASP1_CTRL" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "AXR15_EN,Enable AXR15 receive data." "0,1" hexmask.long.byte 0x0 19.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16.--18. "AXR15_SRC,Selects one of the AFSX or AFSR inputs as the AXR15 data input 0h - McASP0_AFSR 1h - McASP0_AFSX 2h - McASP1_AFSR 3h - McASP1_AFSX 4h - McASP2_AFSR 5h - McASP2_AFSX 6h - '0' 7h - '0'" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 7. "AXR14_EN,Enable AXR14 receive data." "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "AXR14_SRC,Selects one of the AFSX or AFSR inputs as the AXR14 data input 0h - McASP0_AFSR 1h - McASP0_AFSX 2h - McASP1_AFSR 3h - McASP1_AFSX 4h - McASP2_AFSR 5h - McASP2_AFSX 6h - '0' 7h - '0'" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_MCASP2_CTRL" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 23. "AXR15_EN,Enable AXR15 receive data." "0,1" hexmask.long.byte 0x4 19.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x4 16.--18. "AXR15_SRC,Selects one of the AFSX or AFSR inputs as the AXR15 data input 0h - McASP0_AFSR 1h - McASP0_AFSX 2h - McASP1_AFSR 3h - McASP1_AFSX 4h - McASP2_AFSR 5h - McASP2_AFSX 6h - '0' 7h - '0'" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 7. "AXR14_EN,Enable AXR14 receive data." "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "AXR14_SRC,Selects one of the AFSX or AFSR inputs as the AXR14 data input 0h - McASP0_AFSR 1h - McASP0_AFSX 2h - McASP1_AFSR 3h - McASP1_AFSX 4h - McASP2_AFSR 5h - McASP2_AFSX 6h - '0' 7h - '0'" "0,1,2,3,4,5,6,7" group.long 0x6600++0x17 line.long 0x0 "CTRLMMR_MAIN_MTOG0_CTRL" rbitfld.long 0x0 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x0 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x0 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_MAIN_MTOG1_CTRL" rbitfld.long 0x4 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x4 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x4 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x8 "CTRLMMR_MAIN_MTOG2_CTRL" rbitfld.long 0x8 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x8 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x8 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x8 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0xC "CTRLMMR_MAIN_MTOG3_CTRL" rbitfld.long 0xC 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0xC 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0xC 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0xC 3.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x10 "CTRLMMR_MAIN_MTOG4_CTRL" rbitfld.long 0x10 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x10 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x10 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x10 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x10 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x14 "CTRLMMR_MAIN_MTOG5_CTRL" rbitfld.long 0x14 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x14 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x14 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x14 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" group.long 0x6628++0x13 line.long 0x0 "CTRLMMR_MAIN_MTOG10_CTRL" rbitfld.long 0x0 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x0 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x0 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_MAIN_MTOG11_CTRL" rbitfld.long 0x4 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x4 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x4 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x8 "CTRLMMR_MAIN_MTOG12_CTRL" rbitfld.long 0x8 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x8 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x8 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x8 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0xC "CTRLMMR_MAIN_MTOG13_CTRL" rbitfld.long 0xC 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0xC 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0xC 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0xC 3.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x10 "CTRLMMR_MAIN_MTOG14_CTRL" rbitfld.long 0x10 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x10 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x10 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x10 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x10 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" group.long 0x6640++0xF line.long 0x0 "CTRLMMR_MAIN_MTOG16_CTRL" rbitfld.long 0x0 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x0 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x0 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_MAIN_MTOG17_CTRL" rbitfld.long 0x4 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x4 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x4 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0x8 "CTRLMMR_MAIN_MTOG18_CTRL" rbitfld.long 0x8 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x8 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0x8 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x8 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" line.long 0xC "CTRLMMR_MAIN_MTOG19_CTRL" rbitfld.long 0xC 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0xC 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 16.--23. 1. "FORCE_TIMEOUT,Force Timout" newline bitfld.long 0xC 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0xC 3.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" group.long 0x66C0++0x3 line.long 0x0 "CTRLMMR_CC_EN_FLUSH_CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "FLUSH,Flush ARM / MSMC Interface Transactions" group.long 0x7008++0x7 line.long 0x0 "CTRLMMR_LOCK1_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_LOCK1_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers" group.long 0x7100++0x1F line.long 0x0 "CTRLMMR_P1_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_P1_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_P1_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_P1_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_P1_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_P1_CLAIM5" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x18 "CTRLMMR_P1_CLAIM6" hexmask.long 0x18 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x1C "CTRLMMR_P1_CLAIM7" hexmask.long 0x1C 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x7128++0x17 line.long 0x0 "CTRLMMR_P1_CLAIM10" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_P1_CLAIM11" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_P1_CLAIM12" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_P1_CLAIM13" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_P1_CLAIM14" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_P1_CLAIM15" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0xA000++0x7 line.long 0x0 "CTRLMMR_OBSCLK0_CTRL" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.byte 0x0 8.--15. 1. "CLK_DIV,OBSCLK0 output divider" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "CLK_SEL,OBSCLK0 clock source selection. 0h - MAIN_PLL0_HSDIV0_CLKOUT 1h - MAIN_PLL1_HSDIV0_CLKOUT 2h - MAIN_PLL2_HSDIV1_CLKOUT 3h - MAIN_PLL3_HSDIV0_CLKOUT 4h - MAIN_PLL4_HSDIV0_CLKOUT 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch -.." line.long 0x4 "CTRLMMR_OBSCLK1_CTRL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--1. "CLK_SEL,OBSCLK1_OUT signal output clock source selection 0h - '0' 1h - MAIN_PLL8_HSDIV0_CLKOUT / DIV8 2h - '0' 3h - '0'" "0,1,2,3" group.long 0xA010++0x3 line.long 0x0 "CTRLMMR_CLKOUT_CTRL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "CLK_EN,When set enables CLKOUT output" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "CLK_SEL,Selects CLKOUT clock source" "0,1" group.long 0xA030++0x3 line.long 0x0 "CTRLMMR_GTC_CLKSEL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "CLK_SEL,Selects the GTC timebase clock source 0h - MAIN_PLL3_HSDIV1_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h - EXT_REFCLK1 (pin) 6h - SERDES0_IP2_LN0_TXMCLK 7h -.." group.long 0xA03C++0x3 line.long 0x0 "CTRLMMR_EFUSE_CLKSEL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CLK_SEL,Selects the clock source 0h - HFOSC0_CLKOUT 1h - MAIN_SYSCLK0 / 4" "0,1" group.long 0xA084++0x3 line.long 0x0 "CTRLMMR_PCIE1_CLKSEL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "CPTS_CLKSEL,Selects the clock source for the PCIE1 Common Platform Time Stamp module 0h - MAIN_PLL3_HSDIV1_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h - EXT_REFCLK1 (pin) 6h -.." group.long 0xA090++0x3 line.long 0x0 "CTRLMMR_CPSW_CLKSEL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "CPTS_CLKSEL,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module 0h - MAIN_PLL3_HSDIV1_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h - EXT_REFCLK1.." group.long 0xA098++0x3 line.long 0x0 "CTRLMMR_NAVSS_CLKSEL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "CPTS_CLKSEL,Selects the clock source for the SoC] Common Platform Time Stamp module located within the Nav Subsystem 0h - MAIN_PLL3_HSDIV1_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin).." group.long 0xA0B0++0x7 line.long 0x0 "CTRLMMR_EMMC0_CLKSEL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "CLK_SEL,eMMC XIN_CLK selection" "0,1,2,3" line.long 0x4 "CTRLMMR_EMMC1_CLKSEL" hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "LB_CLKSEL,eMMC Loopback clock selection" "0,1" hexmask.long.word 0x4 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0.--1. "CLK_SEL,eMMC XIN_CLK selection" "0,1,2,3" group.long 0xA0D0++0x3 line.long 0x0 "CTRLMMR_GPMC_CLKSEL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "CLK_SEL,Selects the GPMC clock source" "0,1,2,3" group.long 0xA0E0++0x3 line.long 0x0 "CTRLMMR_USB0_CLKSEL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "REFCLK_SEL,Selects the clock source for the USB0 ref_clk." "0,1" group.long 0xA100++0x4F line.long 0x0 "CTRLMMR_TIMER0_CLKSEL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x4 "CTRLMMR_TIMER1_CLKSEL" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x8 "CTRLMMR_TIMER2_CLKSEL" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0xC "CTRLMMR_TIMER3_CLKSEL" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x10 "CTRLMMR_TIMER4_CLKSEL" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x14 "CTRLMMR_TIMER5_CLKSEL" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x18 "CTRLMMR_TIMER6_CLKSEL" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x18 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x1C "CTRLMMR_TIMER7_CLKSEL" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x1C 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x20 "CTRLMMR_TIMER8_CLKSEL" hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x20 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x24 "CTRLMMR_TIMER9_CLKSEL" hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x24 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x28 "CTRLMMR_TIMER10_CLKSEL" hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x28 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x2C "CTRLMMR_TIMER11_CLKSEL" hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x2C 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x30 "CTRLMMR_TIMER12_CLKSEL" hexmask.long 0x30 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x30 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x34 "CTRLMMR_TIMER13_CLKSEL" hexmask.long 0x34 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x34 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x38 "CTRLMMR_TIMER14_CLKSEL" hexmask.long 0x38 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x38 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x3C "CTRLMMR_TIMER15_CLKSEL" hexmask.long 0x3C 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x3C 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x40 "CTRLMMR_TIMER16_CLKSEL" hexmask.long.byte 0x40 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 23. "AFS_SRC_EN,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set." "0,1" hexmask.long.byte 0x40 19.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x40 16.--18. "AFS_SRC_SEL,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. 0h - McASP0_AFSR 1h - McASP0_AFSX 2h - McASP1_AFSR 3h - McASP1_AFSX 4h - McASP2_AFSR 5h - McASP2_AFSX 6h - '0' 7h - '0'" "0,1,2,3,4,5,6,7" hexmask.long.word 0x40 4.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x40 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x44 "CTRLMMR_TIMER17_CLKSEL" hexmask.long.byte 0x44 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 23. "AFS_SRC_EN,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set." "0,1" hexmask.long.byte 0x44 19.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x44 16.--18. "AFS_SRC_SEL,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. 0h - McASP0_AFSR 1h - McASP0_AFSX 2h - McASP1_AFSR 3h - McASP1_AFSX 4h - McASP2_AFSR 5h - McASP2_AFSX 6h - '0' 7h - '0'" "0,1,2,3,4,5,6,7" hexmask.long.word 0x44 4.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x44 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x48 "CTRLMMR_TIMER18_CLKSEL" hexmask.long.byte 0x48 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x48 23. "AFS_SRC_EN,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set." "0,1" hexmask.long.byte 0x48 19.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x48 16.--18. "AFS_SRC_SEL,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. 0h - McASP0_AFSR 1h - McASP0_AFSX 2h - McASP1_AFSR 3h - McASP1_AFSX 4h - McASP2_AFSR 5h - McASP2_AFSX 6h - '0' 7h - '0'" "0,1,2,3,4,5,6,7" hexmask.long.word 0x48 4.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x48 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." line.long 0x4C "CTRLMMR_TIMER19_CLKSEL" hexmask.long.byte 0x4C 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x4C 23. "AFS_SRC_EN,Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set." "0,1" hexmask.long.byte 0x4C 19.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x4C 16.--18. "AFS_SRC_SEL,Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set. 0h - McASP0_AFSR 1h - McASP0_AFSX 2h - McASP1_AFSR 3h - McASP1_AFSX 4h - McASP2_AFSR 5h - McASP2_AFSX 6h - '0' 7h - '0'" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4C 4.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4C 0.--3. 1. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL0_HSDIV1_CLKOUT 3h - CLK_12M_RC 4h - MAIN_PLL3_HSDIV3_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - LFXOSC_CLKOUT 8h - CPTS_RFT_CLK.." group.long 0xA190++0xF line.long 0x0 "CTRLMMR_SPI0_CLKSEL" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_SPI1_CLKSEL" hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" hexmask.long.word 0x4 0.--15. 1. "RESERVED,Reserved" line.long 0x8 "CTRLMMR_SPI2_CLKSEL" hexmask.long.word 0x8 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" hexmask.long.word 0x8 0.--15. 1. "RESERVED,Reserved" line.long 0xC "CTRLMMR_SPI3_CLKSEL" hexmask.long.word 0xC 17.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" hexmask.long.word 0xC 0.--15. 1. "RESERVED,Reserved" group.long 0xA1A4++0xB line.long 0x0 "CTRLMMR_SPI5_CLKSEL" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_SPI6_CLKSEL" hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" hexmask.long.word 0x4 0.--15. 1. "RESERVED,Reserved" line.long 0x8 "CTRLMMR_SPI7_CLKSEL" hexmask.long.word 0x8 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" hexmask.long.word 0x8 0.--15. 1. "RESERVED,Reserved" group.long 0xA1C0++0x27 line.long 0x0 "CTRLMMR_USART0_CLK_CTRL" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x0 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0x4 "CTRLMMR_USART1_CLK_CTRL" hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x4 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0x8 "CTRLMMR_USART2_CLK_CTRL" hexmask.long.word 0x8 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x8 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x8 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0xC "CTRLMMR_USART3_CLK_CTRL" hexmask.long.word 0xC 17.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0xC 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0x10 "CTRLMMR_USART4_CLK_CTRL" hexmask.long.word 0x10 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x10 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x10 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0x14 "CTRLMMR_USART5_CLK_CTRL" hexmask.long.word 0x14 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x14 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0x18 "CTRLMMR_USART6_CLK_CTRL" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x18 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x18 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0x1C "CTRLMMR_USART7_CLK_CTRL" hexmask.long.word 0x1C 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x1C 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0x20 "CTRLMMR_USART8_CLK_CTRL" hexmask.long.word 0x20 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x20 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x20 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" line.long 0x24 "CTRLMMR_USART9_CLK_CTRL" hexmask.long.word 0x24 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 16. "CLK_DIV_LD,Load the output divider value" "0,1" hexmask.long.word 0x24 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x24 0.--1. "CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4" "0,1,2,3" group.long 0xA200++0xB line.long 0x0 "CTRLMMR_MCASP0_CLKSEL" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "AUXCLK_SEL,Selects the McASP0 auxclk clock source 0h - MAIN_PLL4_HSDIV0_CLKOUT 1h - MAIN_PLL2_HSDIV2_CLKOUT 2h - '0' 3h - '0' 4h - ATCLK0 5h - ATCLK1 6h - ATCLK2 7h - ATCLK3" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_MCASP1_CLKSEL" hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "AUXCLK_SEL,Selects the McASP1 auxclk clock source 0h - MAIN_PLL4_HSDIV0_CLKOUT 1h - MAIN_PLL2_HSDIV2_CLKOUT 2h - '0' 3h - '0' 4h - ATCLK0 5h - ATCLK1 6h - ATCLK2 7h - ATCLK3" "0,1,2,3,4,5,6,7" line.long 0x8 "CTRLMMR_MCASP2_CLKSEL" hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--2. "AUXCLK_SEL,Selects the McASP2 auxclk clock source 0h - MAIN_PLL4_HSDIV0_CLKOUT 1h - MAIN_PLL2_HSDIV2_CLKOUT 2h - '0' 3h - '0' 4h - ATCLK0 5h - ATCLK1 6h - ATCLK2 7h - ATCLK3" "0,1,2,3,4,5,6,7" group.long 0xA240++0xB line.long 0x0 "CTRLMMR_MCASP0_AHCLKSEL" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "AHCLKX_SEL,Selects the AHCLKX input source for McASP0 0h - HFOSC1_CLKOUT 1h - HFOSC0_CLKOUT 2h - AUDIO_EXT_REFCLK0_IN 3h - AUDIO_EXT_REFCLK1_IN 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - ATCLK0 9h - ATCLK1 Ah - ATCLK2 Bh - ATCLK3" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "AHCLKR_SEL,Selects the AHCLKR input source for McASP0 0h - HFOSC1_CLKOUT 1h - HFOSC0_CLKOUT 2h - AUDIO_EXT_REFCLK0_IN 3h - AUDIO_EXT_REFCLK1_IN 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - ATCLK0 9h - ATCLK1 Ah - ATCLK2 Bh - ATCLK3 Ch - '0' Dh - '0' Eh - '0'.." line.long 0x4 "CTRLMMR_MCASP1_AHCLKSEL" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 8.--11. 1. "AHCLKX_SEL,Selects the AHCLKX input source for McASP1 0h - HFOSC1_CLKOUT 1h - HFOSC0_CLKOUT 2h - AUDIO_EXT_REFCLK0_IN 3h - AUDIO_EXT_REFCLK1_IN 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - ATCLK0 9h - ATCLK1 Ah - ATCLK2 Bh - ATCLK3" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "AHCLKR_SEL,Selects the AHCLKR input source for McASP1 0h - HFOSC1_CLKOUT 1h - HFOSC0_CLKOUT 2h - AUDIO_EXT_REFCLK0_IN 3h - AUDIO_EXT_REFCLK1_IN 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - ATCLK0 9h - ATCLK1 Ah - ATCLK2 Bh - ATCLK3 Ch - '0' Dh - '0' Eh - '0'.." line.long 0x8 "CTRLMMR_MCASP2_AHCLKSEL" hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--11. 1. "AHCLKX_SEL,Selects the AHCLKX input source for McASP2 0h - HFOSC1_CLKOUT 1h - HFOSC0_CLKOUT 2h - AUDIO_EXT_REFCLK0_IN 3h - AUDIO_EXT_REFCLK1_IN 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - ATCLK0 9h - ATCLK1 Ah - ATCLK2 Bh - ATCLK3" hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "AHCLKR_SEL,Selects the AHCLKR input source for McASP2 0h - HFOSC1_CLKOUT 1h - HFOSC0_CLKOUT 2h - AUDIO_EXT_REFCLK0_IN 3h - AUDIO_EXT_REFCLK1_IN 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - ATCLK0 9h - ATCLK1 Ah - ATCLK2 Bh - ATCLK3 Ch - '0' Dh - '0' Eh - '0'.." group.long 0xA2A0++0x23 line.long 0x0 "CTRLMMR_ATL_BWS0_SEL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "WD_SEL,BWS source signal 0h - McASP0 AFSR Pin Input 1h - McASP1 AFSR Pin Input 2h - McASP2 AFSR Pin Input 3h - '0' 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch - McASP0 AFSX Pin Input Dh - McASP1 AFSX Pin Input Eh - McASP2.." line.long 0x4 "CTRLMMR_ATL_BWS1_SEL" hexmask.long 0x4 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "WD_SEL,BWS source signal 0h - McASP0 AFSR Pin Input 1h - McASP1 AFSR Pin Input 2h - McASP2 AFSR Pin Input 3h - '0' 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch - McASP0 AFSX Pin Input Dh - McASP1 AFSX Pin Input Eh - McASP2.." line.long 0x8 "CTRLMMR_ATL_BWS2_SEL" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--4. 1. "WD_SEL,BWS source signal 0h - McASP0 AFSR Pin Input 1h - McASP1 AFSR Pin Input 2h - McASP2 AFSR Pin Input 3h - '0' 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch - McASP0 AFSX Pin Input Dh - McASP1 AFSX Pin Input Eh - McASP2.." line.long 0xC "CTRLMMR_ATL_BWS3_SEL" hexmask.long 0xC 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--4. 1. "WD_SEL,BWS source signal 0h - McASP0 AFSR Pin Input 1h - McASP1 AFSR Pin Input 2h - McASP2 AFSR Pin Input 3h - '0' 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch - McASP0 AFSX Pin Input Dh - McASP1 AFSX Pin Input Eh - McASP2.." line.long 0x10 "CTRLMMR_ATL_AWS0_SEL" hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--4. 1. "WD_SEL,AWS source signal 0h - McASP0 AFSX Pin Input 1h - McASP1 AFSX Pin Input 2h - McASP2 AFSX Pin Input 3h - '0' 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch - McASP0 AFSX Pin Input Dh - McASP1 AFSX Pin Input Eh - McASP2.." line.long 0x14 "CTRLMMR_ATL_AWS1_SEL" hexmask.long 0x14 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 0.--4. 1. "WD_SEL,AWS source signal 0h - McASP0 AFSX Pin Input 1h - McASP1 AFSX Pin Input 2h - McASP2 AFSX Pin Input 3h - '0' 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch - McASP0 AFSX Pin Input Dh - McASP1 AFSX Pin Input Eh - McASP2.." line.long 0x18 "CTRLMMR_ATL_AWS2_SEL" hexmask.long 0x18 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x18 0.--4. 1. "WD_SEL,AWS source signal 0h - McASP0 AFSX Pin Input 1h - McASP1 AFSX Pin Input 2h - McASP2 AFSX Pin Input 3h - '0' 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch - McASP0 AFSX Pin Input Dh - McASP1 AFSX Pin Input Eh - McASP2.." line.long 0x1C "CTRLMMR_ATL_AWS3_SEL" hexmask.long 0x1C 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x1C 0.--4. 1. "WD_SEL,AWS source signal 0h - McASP0 AFSX Pin Input 1h - McASP1 AFSX Pin Input 2h - McASP2 AFSX Pin Input 3h - '0' 4h - '0' 5h - '0' 6h - '0' 7h - '0' 8h - '0' 9h - '0' Ah - '0' Bh - '0' Ch - McASP0 AFSX Pin Input Dh - McASP1 AFSX Pin Input Eh - McASP2.." line.long 0x20 "CTRLMMR_ATL_CLKSEL" hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x20 0.--3. 1. "PCLK_SEL,Selects the PCLK clock source 0h - MAIN_PLL4_HSDIV1_CLKOUT 1h - MAIN_PLL2_HSDIV2_CLKOUT 2h - '0' 3h - '0' 4h - MAIN_PLL0_HSDIV7_CLKOUT 5h - MCU_EXT_REFCLK0 (pin) 6h - EXT_REFCLK1 (pin) 7h - '0'" group.long 0xA2E0++0x7 line.long 0x0 "CTRLMMR_AUDIO_REFCLK0_CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,AUDIO_REFCLK 0 output enable" "0,1" hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "CLK_SEL,Clock source 0h - MCASP0 AHCLKR Output 1h - MCASP1 AHCLKR Output 2h - MCASP2 AHCLKR Output 3h - Reserved 4h - Reserved 5h - Reserved 6h - Reserved 7h - Reserved 8h - Reserved 9h - Reserved Ah - Reserved Bh - Reserved Ch - MCASP0 AHCLKX Output Dh.." line.long 0x4 "CTRLMMR_AUDIO_REFCLK1_CTRL" hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,AUDIO_REFCLK 1 output enable" "0,1" hexmask.long.word 0x4 5.--14. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--4. 1. "CLK_SEL,Clock source 0h - MCASP0 AHCLKR Output 1h - MCASP1 AHCLKR Output 2h - MCASP2 AHCLKR Output 3h - Reserved 4h - Reserved 5h - Reserved 6h - Reserved 7h - Reserved 8h - Reserved 9h - Reserved Ah - Reserved Bh - Reserved Ch - MCASP0 AHCLKX Output Dh.." group.long 0xA380++0x7 line.long 0x0 "CTRLMMR_WWD0_CLKSEL" bitfld.long 0x0 31. "WRTLOCK,When set locks" "0,1" hexmask.long 0x0 3.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - LFXOSC_CLKOUT 2h - CLK_12M_RC 3h - CLK_32K 4h - HFOSC1_CLKOUT 5h - reserved (HFOSC1_CLKOUT) 6h - reserved (HFOSC1_CLKOUT) 7h - reserved (HFOSC1_CLKOUT)" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_WWD1_CLKSEL" bitfld.long 0x4 31. "WRTLOCK,When set locks" "0,1" hexmask.long 0x4 3.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - LFXOSC_CLKOUT 2h - CLK_12M_RC 3h - CLK_32K 4h - HFOSC1_CLKOUT 5h - reserved (HFOSC1_CLKOUT) 6h - reserved (HFOSC1_CLKOUT) 7h - reserved (HFOSC1_CLKOUT)" "0,1,2,3,4,5,6,7" group.long 0xA3F0++0x7 line.long 0x0 "CTRLMMR_WWD28_CLKSEL" bitfld.long 0x0 31. "WRTLOCK,When set locks" "0,1" hexmask.long 0x0 3.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - LFXOSC_CLKOUT 2h - CLK_12M_RC 3h - CLK_32K 4h - HFOSC1_CLKOUT 5h - reserved (HFOSC1_CLKOUT) 6h - reserved (HFOSC1_CLKOUT) 7h - reserved (HFOSC1_CLKOUT)" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_WWD29_CLKSEL" bitfld.long 0x4 31. "WRTLOCK,When set locks" "0,1" hexmask.long 0x4 3.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - LFXOSC_CLKOUT 2h - CLK_12M_RC 3h - CLK_32K 4h - HFOSC1_CLKOUT 5h - reserved (HFOSC1_CLKOUT) 6h - reserved (HFOSC1_CLKOUT) 7h - reserved (HFOSC1_CLKOUT)" "0,1,2,3,4,5,6,7" group.long 0xA400++0x3 line.long 0x0 "CTRLMMR_SERDES0_CLKSEL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "CORE_REFCLK_SEL,Selects the source for the core_refclk input 0h - HFOSC0_CLKOUT 1h - HFOSC1_CLKOUT 2h - MAIN_PLL3_HSDIV4_CLKOUT 3h - MAIN_PLL2_HSDIV4_CLKOUT" "0,1,2,3" group.long 0xA480++0x47 line.long 0x0 "CTRLMMR_MCAN0_CLKSEL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x4 "CTRLMMR_MCAN1_CLKSEL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x8 "CTRLMMR_MCAN2_CLKSEL" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0xC "CTRLMMR_MCAN3_CLKSEL" hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x10 "CTRLMMR_MCAN4_CLKSEL" hexmask.long 0x10 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x14 "CTRLMMR_MCAN5_CLKSEL" hexmask.long 0x14 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x18 "CTRLMMR_MCAN6_CLKSEL" hexmask.long 0x18 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x1C "CTRLMMR_MCAN7_CLKSEL" hexmask.long 0x1C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x20 "CTRLMMR_MCAN8_CLKSEL" hexmask.long 0x20 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x24 "CTRLMMR_MCAN9_CLKSEL" hexmask.long 0x24 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x28 "CTRLMMR_MCAN10_CLKSEL" hexmask.long 0x28 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x28 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x2C "CTRLMMR_MCAN11_CLKSEL" hexmask.long 0x2C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x2C 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x30 "CTRLMMR_MCAN12_CLKSEL" hexmask.long 0x30 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x30 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x34 "CTRLMMR_MCAN13_CLKSEL" hexmask.long 0x34 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x34 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x38 "CTRLMMR_MCAN14_CLKSEL" hexmask.long 0x38 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x38 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x3C "CTRLMMR_MCAN15_CLKSEL" hexmask.long 0x3C 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x3C 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x40 "CTRLMMR_MCAN16_CLKSEL" hexmask.long 0x40 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x40 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" line.long 0x44 "CTRLMMR_MCAN17_CLKSEL" hexmask.long 0x44 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x44 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3" group.long 0xB008++0x7 line.long 0x0 "CTRLMMR_LOCK2_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_LOCK2_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers" group.long 0xB100++0x27 line.long 0x0 "CTRLMMR_P2_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_P2_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_P2_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_P2_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_P2_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_P2_CLAIM5" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x18 "CTRLMMR_P2_CLAIM6" hexmask.long 0x18 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x1C "CTRLMMR_P2_CLAIM7" hexmask.long 0x1C 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x20 "CTRLMMR_P2_CLAIM8" hexmask.long 0x20 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x24 "CTRLMMR_P2_CLAIM9" hexmask.long 0x24 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0xE000++0x1B line.long 0x0 "CTRLMMR_MCU0_LBIST_CTRL" bitfld.long 0x0 31. "BIST_RESET,Reset LBIST macro" "0,1" rbitfld.long 0x0 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--27. 1. "BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "RUNBIST_MODE,Runbist mode enable if all bits are 1" rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" bitfld.long 0x0 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" rbitfld.long 0x0 5.--6. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--4. 1. "DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CTRLMMR_MCU0_LBIST_PATCOUNT" rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x4 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "SET_PC_DEF,Number of set patterns to run" hexmask.long.byte 0x4 4.--7. 1. "RESET_PC_DEF,Number of reset patterns to run" hexmask.long.byte 0x4 0.--3. 1. "SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CTRLMMR_MCU0_LBIST_SEED0" hexmask.long 0x8 0.--31. 1. "PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CTRLMMR_MCU0_LBIST_SEED1" hexmask.long.word 0xC 21.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0xC 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CTRLMMR_MCU0_LBIST_SPARE0" hexmask.long 0x10 2.--31. 1. "SPARE0,LBIST spare bits" bitfld.long 0x10 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1" bitfld.long 0x10 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CTRLMMR_MCU0_LBIST_SPARE1" hexmask.long 0x14 0.--31. 1. "SPARE1,LBIST spare bits" line.long 0x18 "CTRLMMR_MCU0_LBIST_STAT" rbitfld.long 0x18 31. "BIST_DONE,LBIST is done" "0,1" hexmask.long.word 0x18 16.--30. 1. "RESERVED,Reserved" rbitfld.long 0x18 15. "BIST_RUNNING,LBIST is running" "0,1" newline hexmask.long.byte 0x18 10.--14. 1. "RESERVED,Reserved" bitfld.long 0x18 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3" hexmask.long.byte 0x18 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE01C++0x3 line.long 0x0 "CTRLMMR_MCU0_LBIST_MISR" hexmask.long 0x0 0.--31. 1. "MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" group.long 0xE100++0x1B line.long 0x0 "CTRLMMR_MPU0_LBIST_CTRL" bitfld.long 0x0 31. "BIST_RESET,Reset LBIST macro" "0,1" rbitfld.long 0x0 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--27. 1. "BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "RUNBIST_MODE,Runbist mode enable if all bits are 1" rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" bitfld.long 0x0 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" rbitfld.long 0x0 5.--6. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--4. 1. "DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CTRLMMR_MPU0_LBIST_PATCOUNT" rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x4 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "SET_PC_DEF,Number of set patterns to run" hexmask.long.byte 0x4 4.--7. 1. "RESET_PC_DEF,Number of reset patterns to run" hexmask.long.byte 0x4 0.--3. 1. "SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CTRLMMR_MPU0_LBIST_SEED0" hexmask.long 0x8 0.--31. 1. "PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CTRLMMR_MPU0_LBIST_SEED1" hexmask.long.word 0xC 21.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0xC 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CTRLMMR_MPU0_LBIST_SPARE0" hexmask.long 0x10 2.--31. 1. "SPARE0,LBIST spare bits" bitfld.long 0x10 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1" bitfld.long 0x10 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CTRLMMR_MPU0_LBIST_SPARE1" hexmask.long 0x14 0.--31. 1. "SPARE1,LBIST spare bits" line.long 0x18 "CTRLMMR_MPU0_LBIST_STAT" rbitfld.long 0x18 31. "BIST_DONE,LBIST is done" "0,1" hexmask.long.word 0x18 16.--30. 1. "RESERVED,Reserved" rbitfld.long 0x18 15. "BIST_RUNNING,LBIST is running" "0,1" newline hexmask.long.byte 0x18 10.--14. 1. "RESERVED,Reserved" bitfld.long 0x18 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3" hexmask.long.byte 0x18 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE11C++0x3 line.long 0x0 "CTRLMMR_MPU0_LBIST_MISR" hexmask.long 0x0 0.--31. 1. "MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE280++0x3 line.long 0x0 "CTRLMMR_MCU0_LBIST_SIG" hexmask.long 0x0 0.--31. 1. "MISR_SIG,MISR signature" rgroup.long 0xE2A0++0x3 line.long 0x0 "CTRLMMR_MPU0_LBIST_SIG" hexmask.long 0x0 0.--31. 1. "MISR_SIG,MISR signature" rgroup.long 0xE320++0x3 line.long 0x0 "CTRLMMR_FUSE_CRC_STAT" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 7. "CRC_ERR_7,Indicates eFuse CRC error on chain 7" "0,1" bitfld.long 0x0 6. "CRC_ERR_6,Indicates eFuse CRC error on chain 6" "0,1" newline bitfld.long 0x0 5. "CRC_ERR_5,Indicates eFuse CRC error on chain 5" "0,1" bitfld.long 0x0 4. "CRC_ERR_4,Indicates eFuse CRC error on chain 4" "0,1" bitfld.long 0x0 3. "CRC_ERR_3,Indicates eFuse CRC error on chain 3" "0,1" newline bitfld.long 0x0 2. "CRC_ERR_2,Indicates eFuse CRC error on chain 2" "0,1" bitfld.long 0x0 1. "CRC_ERR_1,Indicates eFuse CRC error on chain 1" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xF008++0x7 line.long 0x0 "CTRLMMR_LOCK3_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_LOCK3_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers" group.long 0xF100++0x3 line.long 0x0 "CTRLMMR_P3_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0xF108++0xF line.long 0x0 "CTRLMMR_P3_CLAIM2" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_P3_CLAIM3" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_P3_CLAIM4" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_P3_CLAIM5" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0xF11C++0x3 line.long 0x0 "CTRLMMR_P3_CLAIM7" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x16000++0x3 line.long 0x0 "CTRLMMR_CHNG_DDR4_FSP_REQ" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "REQ,Initiate FSP frequency change" "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0.--1. "REQ_TYPE,Frequency request type." "0,1,2,3" rgroup.long 0x16004++0x3 line.long 0x0 "CTRLMMR_CHNG_DDR4_FSP_ACK" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 7. "ACK,Frequency change acknowledge." "0,1" hexmask.long.byte 0x0 1.--6. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ERROR,Frequency change error" "0,1" rgroup.long 0x16080++0x3 line.long 0x0 "CTRLMMR_DDR4_FSP_CLKCHNG_REQ" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 7. "REQ,DDR Controller FSP clock change request" "0,1" hexmask.long.byte 0x0 2.--6. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0.--1. "REQ_TYPE,Frequency request type" "0,1,2,3" group.long 0x160C0++0x3 line.long 0x0 "CTRLMMR_DDR4_FSP_CLKCHNG_ACK" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "ACK,DDR FSP clock change ackowledge" "0,1" group.long 0x17008++0x7 line.long 0x0 "CTRLMMR_LOCK5_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition5 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_LOCK5_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition5 registers" group.long 0x17100++0x7 line.long 0x0 "CTRLMMR_P5_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_P5_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x1E000++0x10B line.long 0x0 "CTRLMMR_PADCONFIG0" bitfld.long 0x0 31. "LOCK,Lock" "0,1" rbitfld.long 0x0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x0 29. "WKUP_EN,Wakeup enable" "0,1" newline rbitfld.long 0x0 27.--28. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" bitfld.long 0x0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" newline bitfld.long 0x0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x0 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x0 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x0 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0x0 19.--20. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 18. "RXACTIVE,Input enable for the Pad" "0,1" newline rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" newline bitfld.long 0x0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" rbitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" bitfld.long 0x0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x4 "CTRLMMR_PADCONFIG1" bitfld.long 0x4 31. "LOCK,Lock" "0,1" rbitfld.long 0x4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x4 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x8 "CTRLMMR_PADCONFIG2" bitfld.long 0x8 31. "LOCK,Lock" "0,1" rbitfld.long 0x8 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x8 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x8 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x8 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x8 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x8 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x8 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x8 6. "RESERVED,Reserved" "0,1" bitfld.long 0x8 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xC "CTRLMMR_PADCONFIG3" bitfld.long 0xC 31. "LOCK,Lock" "0,1" rbitfld.long 0xC 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xC 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xC 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xC 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xC 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xC 6. "RESERVED,Reserved" "0,1" bitfld.long 0xC 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x10 "CTRLMMR_PADCONFIG4" bitfld.long 0x10 31. "LOCK,Lock" "0,1" rbitfld.long 0x10 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x10 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x10 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x10 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x10 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x10 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x10 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x10 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x10 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x10 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x10 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x10 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x10 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x10 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x10 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x10 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x10 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x10 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x10 6. "RESERVED,Reserved" "0,1" bitfld.long 0x10 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x10 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x14 "CTRLMMR_PADCONFIG5" bitfld.long 0x14 31. "LOCK,Lock" "0,1" rbitfld.long 0x14 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x14 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x14 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x14 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x14 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x14 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x14 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x14 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x14 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x14 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x14 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x14 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x14 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x14 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x14 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x14 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x14 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x14 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x14 6. "RESERVED,Reserved" "0,1" bitfld.long 0x14 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x14 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x18 "CTRLMMR_PADCONFIG6" bitfld.long 0x18 31. "LOCK,Lock" "0,1" rbitfld.long 0x18 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x18 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x18 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x18 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x18 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x18 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x18 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x18 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x18 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x18 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x18 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x18 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x18 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x18 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x18 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x18 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x18 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x18 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x18 6. "RESERVED,Reserved" "0,1" bitfld.long 0x18 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x18 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x1C "CTRLMMR_PADCONFIG7" bitfld.long 0x1C 31. "LOCK,Lock" "0,1" rbitfld.long 0x1C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x1C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x1C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x1C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x1C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x1C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x1C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x1C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x1C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x1C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x1C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x1C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x1C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x1C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x1C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x1C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x1C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x1C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x1C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x20 "CTRLMMR_PADCONFIG8" bitfld.long 0x20 31. "LOCK,Lock" "0,1" rbitfld.long 0x20 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x20 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x20 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x20 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x20 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x20 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x20 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x20 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x20 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x20 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x20 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x20 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x20 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x20 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x20 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x20 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x20 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x20 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x20 6. "RESERVED,Reserved" "0,1" bitfld.long 0x20 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x20 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x24 "CTRLMMR_PADCONFIG9" bitfld.long 0x24 31. "LOCK,Lock" "0,1" rbitfld.long 0x24 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x24 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x24 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x24 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x24 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x24 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x24 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x24 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x24 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x24 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x24 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x24 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x24 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x24 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x24 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x24 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x24 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x24 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x24 6. "RESERVED,Reserved" "0,1" bitfld.long 0x24 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x24 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x28 "CTRLMMR_PADCONFIG10" bitfld.long 0x28 31. "LOCK,Lock" "0,1" rbitfld.long 0x28 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x28 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x28 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x28 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x28 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x28 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x28 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x28 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x28 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x28 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x28 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x28 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x28 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x28 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x28 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x28 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x28 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x28 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x28 6. "RESERVED,Reserved" "0,1" bitfld.long 0x28 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x28 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x2C "CTRLMMR_PADCONFIG11" bitfld.long 0x2C 31. "LOCK,Lock" "0,1" rbitfld.long 0x2C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x2C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x2C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x2C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x2C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x2C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x2C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x2C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x2C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x2C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x2C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x2C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x2C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x2C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x2C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x2C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x2C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x2C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x2C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x2C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x30 "CTRLMMR_PADCONFIG12" bitfld.long 0x30 31. "LOCK,Lock" "0,1" rbitfld.long 0x30 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x30 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x30 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x30 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x30 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x30 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x30 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x30 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x30 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x30 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x30 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x30 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x30 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x30 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x30 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x30 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x30 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x30 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x30 6. "RESERVED,Reserved" "0,1" bitfld.long 0x30 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x30 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x34 "CTRLMMR_PADCONFIG13" bitfld.long 0x34 31. "LOCK,Lock" "0,1" rbitfld.long 0x34 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x34 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x34 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x34 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x34 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x34 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x34 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x34 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x34 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x34 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x34 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x34 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x34 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x34 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x34 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x34 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x34 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x34 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x34 6. "RESERVED,Reserved" "0,1" bitfld.long 0x34 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x34 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x38 "CTRLMMR_PADCONFIG14" bitfld.long 0x38 31. "LOCK,Lock" "0,1" rbitfld.long 0x38 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x38 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x38 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x38 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x38 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x38 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x38 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x38 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x38 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x38 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x38 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x38 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x38 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x38 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x38 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x38 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x38 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x38 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x38 6. "RESERVED,Reserved" "0,1" bitfld.long 0x38 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x38 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x3C "CTRLMMR_PADCONFIG15" bitfld.long 0x3C 31. "LOCK,Lock" "0,1" rbitfld.long 0x3C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x3C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x3C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x3C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x3C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x3C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x3C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x3C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x3C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x3C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x3C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x3C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x3C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x3C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x3C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x3C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x3C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x3C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x3C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x3C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x3C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x40 "CTRLMMR_PADCONFIG16" bitfld.long 0x40 31. "LOCK,Lock" "0,1" rbitfld.long 0x40 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x40 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x40 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x40 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x40 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x40 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x40 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x40 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x40 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x40 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x40 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x40 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x40 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x40 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x40 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x40 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x40 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x40 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x40 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x40 6. "RESERVED,Reserved" "0,1" bitfld.long 0x40 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x40 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x44 "CTRLMMR_PADCONFIG17" bitfld.long 0x44 31. "LOCK,Lock" "0,1" rbitfld.long 0x44 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x44 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x44 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x44 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x44 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x44 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x44 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x44 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x44 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x44 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x44 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x44 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x44 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x44 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x44 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x44 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x44 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x44 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x44 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x44 6. "RESERVED,Reserved" "0,1" bitfld.long 0x44 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x44 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x48 "CTRLMMR_PADCONFIG18" bitfld.long 0x48 31. "LOCK,Lock" "0,1" rbitfld.long 0x48 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x48 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x48 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x48 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x48 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x48 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x48 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x48 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x48 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x48 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x48 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x48 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x48 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x48 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x48 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x48 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x48 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x48 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x48 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x48 6. "RESERVED,Reserved" "0,1" bitfld.long 0x48 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x48 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x4C "CTRLMMR_PADCONFIG19" bitfld.long 0x4C 31. "LOCK,Lock" "0,1" rbitfld.long 0x4C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x4C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x4C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x4C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x4C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x4C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x4C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x4C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x4C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x4C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x4C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x4C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x4C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x4C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x4C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x50 "CTRLMMR_PADCONFIG20" bitfld.long 0x50 31. "LOCK,Lock" "0,1" rbitfld.long 0x50 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x50 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x50 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x50 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x50 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x50 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x50 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x50 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x50 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x50 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x50 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x50 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x50 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x50 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x50 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x50 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x50 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x50 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x50 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x50 6. "RESERVED,Reserved" "0,1" bitfld.long 0x50 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x50 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x54 "CTRLMMR_PADCONFIG21" bitfld.long 0x54 31. "LOCK,Lock" "0,1" rbitfld.long 0x54 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x54 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x54 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x54 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x54 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x54 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x54 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x54 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x54 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x54 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x54 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x54 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x54 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x54 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x54 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x54 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x54 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x54 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x54 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x54 6. "RESERVED,Reserved" "0,1" bitfld.long 0x54 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x54 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x58 "CTRLMMR_PADCONFIG22" bitfld.long 0x58 31. "LOCK,Lock" "0,1" rbitfld.long 0x58 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x58 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x58 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x58 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x58 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x58 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x58 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x58 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x58 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x58 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x58 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x58 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x58 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x58 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x58 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x58 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x58 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x58 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x58 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x58 6. "RESERVED,Reserved" "0,1" bitfld.long 0x58 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x58 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x5C "CTRLMMR_PADCONFIG23" bitfld.long 0x5C 31. "LOCK,Lock" "0,1" rbitfld.long 0x5C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x5C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x5C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x5C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x5C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x5C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x5C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x5C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x5C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x5C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x5C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x5C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x5C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x5C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x5C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x5C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x5C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x5C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x5C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x5C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x5C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x5C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x60 "CTRLMMR_PADCONFIG24" bitfld.long 0x60 31. "LOCK,Lock" "0,1" rbitfld.long 0x60 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x60 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x60 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x60 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x60 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x60 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x60 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x60 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x60 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x60 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x60 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x60 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x60 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x60 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x60 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x60 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x60 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x60 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x60 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x60 6. "RESERVED,Reserved" "0,1" bitfld.long 0x60 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x60 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x64 "CTRLMMR_PADCONFIG25" bitfld.long 0x64 31. "LOCK,Lock" "0,1" rbitfld.long 0x64 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x64 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x64 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x64 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x64 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x64 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x64 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x64 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x64 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x64 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x64 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x64 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x64 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x64 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x64 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x64 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x64 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x64 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x64 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x64 6. "RESERVED,Reserved" "0,1" bitfld.long 0x64 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x64 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x68 "CTRLMMR_PADCONFIG26" bitfld.long 0x68 31. "LOCK,Lock" "0,1" rbitfld.long 0x68 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x68 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x68 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x68 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x68 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x68 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x68 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x68 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x68 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x68 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x68 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x68 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x68 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x68 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x68 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x68 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x68 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x68 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x68 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x68 6. "RESERVED,Reserved" "0,1" bitfld.long 0x68 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x68 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x6C "CTRLMMR_PADCONFIG27" bitfld.long 0x6C 31. "LOCK,Lock" "0,1" rbitfld.long 0x6C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x6C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x6C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x6C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x6C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x6C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x6C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x6C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x6C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x6C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x6C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x6C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x6C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x6C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x6C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x6C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x6C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x6C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x6C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x6C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x6C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x6C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x70 "CTRLMMR_PADCONFIG28" bitfld.long 0x70 31. "LOCK,Lock" "0,1" rbitfld.long 0x70 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x70 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x70 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x70 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x70 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x70 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x70 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x70 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x70 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x70 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x70 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x70 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x70 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x70 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x70 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x70 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x70 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x70 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x70 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x70 6. "RESERVED,Reserved" "0,1" bitfld.long 0x70 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x70 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x74 "CTRLMMR_PADCONFIG29" bitfld.long 0x74 31. "LOCK,Lock" "0,1" rbitfld.long 0x74 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x74 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x74 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x74 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x74 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x74 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x74 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x74 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x74 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x74 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x74 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x74 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x74 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x74 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x74 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x74 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x74 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x74 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x74 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x74 6. "RESERVED,Reserved" "0,1" bitfld.long 0x74 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x74 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x78 "CTRLMMR_PADCONFIG30" bitfld.long 0x78 31. "LOCK,Lock" "0,1" rbitfld.long 0x78 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x78 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x78 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x78 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x78 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x78 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x78 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x78 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x78 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x78 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x78 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x78 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x78 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x78 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x78 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x78 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x78 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x78 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x78 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x78 6. "RESERVED,Reserved" "0,1" bitfld.long 0x78 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x78 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x7C "CTRLMMR_PADCONFIG31" bitfld.long 0x7C 31. "LOCK,Lock" "0,1" rbitfld.long 0x7C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x7C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x7C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x7C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x7C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x7C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x7C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x7C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x7C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x7C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x7C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x7C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x7C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x7C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x7C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x7C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x7C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x7C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x7C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x7C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x7C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x7C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x80 "CTRLMMR_PADCONFIG32" bitfld.long 0x80 31. "LOCK,Lock" "0,1" rbitfld.long 0x80 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x80 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x80 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x80 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x80 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x80 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x80 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x80 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x80 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x80 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x80 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x80 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x80 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x80 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x80 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x80 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x80 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x80 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x80 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x80 6. "RESERVED,Reserved" "0,1" bitfld.long 0x80 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x80 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x84 "CTRLMMR_PADCONFIG33" bitfld.long 0x84 31. "LOCK,Lock" "0,1" rbitfld.long 0x84 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x84 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x84 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x84 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x84 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x84 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x84 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x84 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x84 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x84 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x84 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x84 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x84 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x84 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x84 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x84 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x84 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x84 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x84 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x84 6. "RESERVED,Reserved" "0,1" bitfld.long 0x84 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x84 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x88 "CTRLMMR_PADCONFIG34" bitfld.long 0x88 31. "LOCK,Lock" "0,1" rbitfld.long 0x88 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x88 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x88 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x88 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x88 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x88 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x88 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x88 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x88 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x88 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x88 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x88 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x88 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x88 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x88 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x88 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x88 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x88 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x88 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x88 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x88 6. "RESERVED,Reserved" "0,1" bitfld.long 0x88 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x88 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x8C "CTRLMMR_PADCONFIG35" bitfld.long 0x8C 31. "LOCK,Lock" "0,1" rbitfld.long 0x8C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x8C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x8C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x8C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x8C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x8C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x8C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x8C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x8C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x8C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x8C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x8C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x8C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x8C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x8C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x8C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x8C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x8C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x8C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x8C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x90 "CTRLMMR_PADCONFIG36" bitfld.long 0x90 31. "LOCK,Lock" "0,1" rbitfld.long 0x90 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x90 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x90 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x90 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x90 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x90 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x90 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x90 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x90 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x90 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x90 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x90 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x90 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x90 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x90 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x90 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x90 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x90 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x90 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x90 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x90 6. "RESERVED,Reserved" "0,1" bitfld.long 0x90 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x90 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x94 "CTRLMMR_PADCONFIG37" bitfld.long 0x94 31. "LOCK,Lock" "0,1" rbitfld.long 0x94 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x94 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x94 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x94 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x94 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x94 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x94 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x94 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x94 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x94 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x94 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x94 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x94 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x94 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x94 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x94 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x94 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x94 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x94 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x94 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x94 6. "RESERVED,Reserved" "0,1" bitfld.long 0x94 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x94 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x98 "CTRLMMR_PADCONFIG38" bitfld.long 0x98 31. "LOCK,Lock" "0,1" rbitfld.long 0x98 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x98 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x98 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x98 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x98 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x98 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x98 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x98 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x98 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x98 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x98 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x98 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x98 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x98 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x98 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x98 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x98 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x98 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x98 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x98 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x98 6. "RESERVED,Reserved" "0,1" bitfld.long 0x98 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x98 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x9C "CTRLMMR_PADCONFIG39" bitfld.long 0x9C 31. "LOCK,Lock" "0,1" rbitfld.long 0x9C 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x9C 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x9C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x9C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x9C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x9C 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x9C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x9C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x9C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x9C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x9C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x9C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x9C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x9C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x9C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x9C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x9C 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x9C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x9C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x9C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x9C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x9C 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x9C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xA0 "CTRLMMR_PADCONFIG40" bitfld.long 0xA0 31. "LOCK,Lock" "0,1" rbitfld.long 0xA0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xA0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xA0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xA0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xA0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xA0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xA0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xA0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xA0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xA0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xA0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xA0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xA0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xA0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xA0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xA0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xA0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xA0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xA0 6. "RESERVED,Reserved" "0,1" bitfld.long 0xA0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xA0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xA4 "CTRLMMR_PADCONFIG41" bitfld.long 0xA4 31. "LOCK,Lock" "0,1" rbitfld.long 0xA4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xA4 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xA4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xA4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xA4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xA4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xA4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xA4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xA4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xA4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xA4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xA4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xA4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xA4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xA4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xA4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xA4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xA4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xA4 6. "RESERVED,Reserved" "0,1" bitfld.long 0xA4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xA4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xA8 "CTRLMMR_PADCONFIG42" bitfld.long 0xA8 31. "LOCK,Lock" "0,1" rbitfld.long 0xA8 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xA8 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xA8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xA8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xA8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xA8 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xA8 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xA8 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xA8 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xA8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xA8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xA8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xA8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xA8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xA8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xA8 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xA8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xA8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xA8 6. "RESERVED,Reserved" "0,1" bitfld.long 0xA8 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xA8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xAC "CTRLMMR_PADCONFIG43" bitfld.long 0xAC 31. "LOCK,Lock" "0,1" rbitfld.long 0xAC 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xAC 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xAC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xAC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xAC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xAC 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xAC 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xAC 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xAC 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xAC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xAC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xAC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xAC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xAC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xAC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xAC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xAC 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xAC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xAC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xAC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xAC 6. "RESERVED,Reserved" "0,1" bitfld.long 0xAC 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xAC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xB0 "CTRLMMR_PADCONFIG44" bitfld.long 0xB0 31. "LOCK,Lock" "0,1" rbitfld.long 0xB0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xB0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xB0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xB0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xB0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xB0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xB0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xB0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xB0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xB0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xB0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xB0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xB0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xB0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xB0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xB0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xB0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xB0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xB0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xB0 6. "RESERVED,Reserved" "0,1" bitfld.long 0xB0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xB0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xB4 "CTRLMMR_PADCONFIG45" bitfld.long 0xB4 31. "LOCK,Lock" "0,1" rbitfld.long 0xB4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xB4 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xB4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xB4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xB4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xB4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xB4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xB4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xB4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xB4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xB4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xB4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xB4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xB4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xB4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xB4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xB4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xB4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xB4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xB4 6. "RESERVED,Reserved" "0,1" bitfld.long 0xB4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xB4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xB8 "CTRLMMR_PADCONFIG46" bitfld.long 0xB8 31. "LOCK,Lock" "0,1" rbitfld.long 0xB8 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xB8 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xB8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xB8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xB8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xB8 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xB8 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xB8 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xB8 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xB8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xB8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xB8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xB8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xB8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xB8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xB8 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xB8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xB8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xB8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xB8 6. "RESERVED,Reserved" "0,1" bitfld.long 0xB8 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xB8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xBC "CTRLMMR_PADCONFIG47" bitfld.long 0xBC 31. "LOCK,Lock" "0,1" rbitfld.long 0xBC 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xBC 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xBC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xBC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xBC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xBC 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xBC 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xBC 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xBC 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xBC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xBC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xBC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xBC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xBC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xBC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xBC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xBC 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xBC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xBC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xBC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xBC 6. "RESERVED,Reserved" "0,1" bitfld.long 0xBC 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xBC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xC0 "CTRLMMR_PADCONFIG48" bitfld.long 0xC0 31. "LOCK,Lock" "0,1" rbitfld.long 0xC0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xC0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xC0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xC0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xC0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xC0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xC0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xC0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xC0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xC0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xC0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xC0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xC0 6. "RESERVED,Reserved" "0,1" bitfld.long 0xC0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xC0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xC4 "CTRLMMR_PADCONFIG49" bitfld.long 0xC4 31. "LOCK,Lock" "0,1" rbitfld.long 0xC4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xC4 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xC4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xC4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xC4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xC4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xC4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xC4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xC4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xC4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xC4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xC4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xC4 6. "RESERVED,Reserved" "0,1" bitfld.long 0xC4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xC4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xC8 "CTRLMMR_PADCONFIG50" bitfld.long 0xC8 31. "LOCK,Lock" "0,1" rbitfld.long 0xC8 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xC8 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xC8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xC8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC8 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xC8 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xC8 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xC8 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xC8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xC8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xC8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xC8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC8 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xC8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xC8 6. "RESERVED,Reserved" "0,1" bitfld.long 0xC8 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xC8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xCC "CTRLMMR_PADCONFIG51" bitfld.long 0xCC 31. "LOCK,Lock" "0,1" rbitfld.long 0xCC 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xCC 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xCC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xCC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xCC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xCC 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xCC 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xCC 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xCC 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xCC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xCC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xCC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xCC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xCC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xCC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xCC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xCC 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xCC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xCC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xCC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xCC 6. "RESERVED,Reserved" "0,1" bitfld.long 0xCC 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xCC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xD0 "CTRLMMR_PADCONFIG52" bitfld.long 0xD0 31. "LOCK,Lock" "0,1" rbitfld.long 0xD0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xD0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xD0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xD0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xD0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xD0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xD0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xD0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xD0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xD0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xD0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xD0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xD0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xD0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xD0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xD0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xD0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xD0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xD0 6. "RESERVED,Reserved" "0,1" bitfld.long 0xD0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xD0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xD4 "CTRLMMR_PADCONFIG53" bitfld.long 0xD4 31. "LOCK,Lock" "0,1" rbitfld.long 0xD4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xD4 29. "WKUP_EN,Wakeup enable" "0,1" newline rbitfld.long 0xD4 27.--28. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" bitfld.long 0xD4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" newline bitfld.long 0xD4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xD4 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xD4 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xD4 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0xD4 19.--20. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD4 18. "RXACTIVE,Input enable for the Pad" "0,1" newline rbitfld.long 0xD4 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xD4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" newline bitfld.long 0xD4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" rbitfld.long 0xD4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xD4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xD4 6. "RESERVED,Reserved" "0,1" bitfld.long 0xD4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" newline hexmask.long.byte 0xD4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xD8 "CTRLMMR_PADCONFIG54" bitfld.long 0xD8 31. "LOCK,Lock" "0,1" rbitfld.long 0xD8 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xD8 29. "WKUP_EN,Wakeup enable" "0,1" newline rbitfld.long 0xD8 27.--28. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" bitfld.long 0xD8 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" newline bitfld.long 0xD8 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xD8 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xD8 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xD8 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0xD8 19.--20. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD8 18. "RXACTIVE,Input enable for the Pad" "0,1" newline rbitfld.long 0xD8 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xD8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" newline bitfld.long 0xD8 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" rbitfld.long 0xD8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xD8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xD8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xD8 6. "RESERVED,Reserved" "0,1" bitfld.long 0xD8 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" newline hexmask.long.byte 0xD8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xDC "CTRLMMR_PADCONFIG55" bitfld.long 0xDC 31. "LOCK,Lock" "0,1" rbitfld.long 0xDC 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xDC 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xDC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xDC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xDC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xDC 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xDC 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xDC 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xDC 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xDC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xDC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xDC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xDC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xDC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xDC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xDC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xDC 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xDC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xDC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xDC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xDC 6. "RESERVED,Reserved" "0,1" bitfld.long 0xDC 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xDC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xE0 "CTRLMMR_PADCONFIG56" bitfld.long 0xE0 31. "LOCK,Lock" "0,1" rbitfld.long 0xE0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xE0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xE0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xE0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xE0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xE0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xE0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xE0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xE0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xE0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xE0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xE0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xE0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xE0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xE0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xE0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xE0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xE0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xE0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xE0 6. "RESERVED,Reserved" "0,1" bitfld.long 0xE0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xE0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xE4 "CTRLMMR_PADCONFIG57" bitfld.long 0xE4 31. "LOCK,Lock" "0,1" rbitfld.long 0xE4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xE4 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xE4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xE4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xE4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xE4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xE4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xE4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xE4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xE4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xE4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xE4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xE4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xE4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xE4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xE4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xE4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xE4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xE4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xE4 6. "RESERVED,Reserved" "0,1" bitfld.long 0xE4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xE4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xE8 "CTRLMMR_PADCONFIG58" bitfld.long 0xE8 31. "LOCK,Lock" "0,1" rbitfld.long 0xE8 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xE8 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xE8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xE8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xE8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xE8 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xE8 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xE8 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xE8 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xE8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xE8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xE8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xE8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xE8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xE8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xE8 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xE8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xE8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xE8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xE8 6. "RESERVED,Reserved" "0,1" bitfld.long 0xE8 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xE8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xEC "CTRLMMR_PADCONFIG59" bitfld.long 0xEC 31. "LOCK,Lock" "0,1" rbitfld.long 0xEC 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xEC 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xEC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xEC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xEC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xEC 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xEC 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xEC 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xEC 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xEC 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0xEC 19.--20. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xEC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xEC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xEC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xEC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xEC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xEC 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xEC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xEC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xEC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xEC 6. "RESERVED,Reserved" "0,1" bitfld.long 0xEC 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xEC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xF0 "CTRLMMR_PADCONFIG60" bitfld.long 0xF0 31. "LOCK,Lock" "0,1" rbitfld.long 0xF0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xF0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xF0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xF0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xF0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xF0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xF0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xF0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xF0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xF0 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0xF0 19.--20. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xF0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xF0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xF0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xF0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xF0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xF0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xF0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xF0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xF0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xF0 6. "RESERVED,Reserved" "0,1" bitfld.long 0xF0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xF0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xF4 "CTRLMMR_PADCONFIG61" bitfld.long 0xF4 31. "LOCK,Lock" "0,1" rbitfld.long 0xF4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xF4 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xF4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xF4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xF4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xF4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xF4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xF4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xF4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xF4 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0xF4 19.--20. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xF4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xF4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xF4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xF4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xF4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xF4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xF4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xF4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xF4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xF4 6. "RESERVED,Reserved" "0,1" bitfld.long 0xF4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xF4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xF8 "CTRLMMR_PADCONFIG62" bitfld.long 0xF8 31. "LOCK,Lock" "0,1" rbitfld.long 0xF8 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xF8 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xF8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xF8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xF8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xF8 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xF8 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xF8 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xF8 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xF8 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0xF8 19.--20. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xF8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xF8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xF8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xF8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xF8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xF8 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xF8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xF8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xF8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xF8 6. "RESERVED,Reserved" "0,1" bitfld.long 0xF8 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xF8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0xFC "CTRLMMR_PADCONFIG63" bitfld.long 0xFC 31. "LOCK,Lock" "0,1" rbitfld.long 0xFC 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0xFC 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0xFC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0xFC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xFC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xFC 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0xFC 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xFC 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xFC 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xFC 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0xFC 19.--20. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xFC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xFC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0xFC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0xFC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0xFC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xFC 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xFC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xFC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0xFC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0xFC 6. "RESERVED,Reserved" "0,1" bitfld.long 0xFC 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0xFC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x100 "CTRLMMR_PADCONFIG64" bitfld.long 0x100 31. "LOCK,Lock" "0,1" rbitfld.long 0x100 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x100 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x100 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x100 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x100 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x100 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x100 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x100 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x100 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x100 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0x100 19.--20. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x100 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x100 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x100 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x100 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x100 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x100 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x100 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x100 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x100 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x100 6. "RESERVED,Reserved" "0,1" bitfld.long 0x100 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x100 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x104 "CTRLMMR_PADCONFIG65" bitfld.long 0x104 31. "LOCK,Lock" "0,1" rbitfld.long 0x104 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x104 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x104 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x104 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x104 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x104 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x104 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x104 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x104 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x104 21. "TX_DIS,Driver Disable" "0,1" rbitfld.long 0x104 19.--20. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x104 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x104 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x104 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x104 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x104 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x104 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x104 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x104 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x104 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x104 6. "RESERVED,Reserved" "0,1" bitfld.long 0x104 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x104 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x108 "CTRLMMR_PADCONFIG66" bitfld.long 0x108 31. "LOCK,Lock" "0,1" rbitfld.long 0x108 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x108 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x108 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x108 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x108 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x108 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x108 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x108 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x108 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x108 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x108 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x108 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x108 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x108 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x108 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x108 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x108 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x108 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x108 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x108 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x108 6. "RESERVED,Reserved" "0,1" bitfld.long 0x108 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x108 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." group.long 0x1E110++0x3 line.long 0x0 "CTRLMMR_PADCONFIG68" bitfld.long 0x0 31. "LOCK,Lock" "0,1" rbitfld.long 0x0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" bitfld.long 0x0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." group.long 0x1E11C++0xB line.long 0x0 "CTRLMMR_PADCONFIG71" bitfld.long 0x0 31. "LOCK,Lock" "0,1" rbitfld.long 0x0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" bitfld.long 0x0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x4 "CTRLMMR_PADCONFIG72" bitfld.long 0x4 31. "LOCK,Lock" "0,1" rbitfld.long 0x4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x4 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x8 "CTRLMMR_PADCONFIG73" bitfld.long 0x8 31. "LOCK,Lock" "0,1" rbitfld.long 0x8 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x8 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x8 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x8 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x8 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x8 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x8 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x8 6. "RESERVED,Reserved" "0,1" bitfld.long 0x8 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." group.long 0x1E164++0x7 line.long 0x0 "CTRLMMR_PADCONFIG89" bitfld.long 0x0 31. "LOCK,Lock" "0,1" rbitfld.long 0x0 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x0 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x0 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x0 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" bitfld.long 0x0 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." line.long 0x4 "CTRLMMR_PADCONFIG90" bitfld.long 0x4 31. "LOCK,Lock" "0,1" rbitfld.long 0x4 30. "WKUP_EVT,Wakeup event status" "0,1" bitfld.long 0x4 29. "WKUP_EN,Wakeup enable" "0,1" newline bitfld.long 0x4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" bitfld.long 0x4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4 25. "DSOUT_DIS,Deep Sleep output disable" "0,1" bitfld.long 0x4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" bitfld.long 0x4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" newline bitfld.long 0x4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" bitfld.long 0x4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" bitfld.long 0x4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" newline rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select. 0h - Implement GPIO in GPIO0 instance 1h - Implement GPIO in GPIO2 instance 2h - Implement GPIO in GPIO4 instance 3h - Implement GPIO in GPIO6 instance" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12.." group.long 0x1F008++0x7 line.long 0x0 "CTRLMMR_LOCK7_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_LOCK7_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers" group.long 0x1F100++0xB line.long 0x0 "CTRLMMR_P7_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_P7_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_P7_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" tree.end tree "DCC" base ad:0x0 tree "DCC0" base ad:0x800000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree "DCC1" base ad:0x804000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree "DCC2" base ad:0x808000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree "DCC3" base ad:0x80C000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree "DCC4" base ad:0x810000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree "DCC5" base ad:0x814000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree "DCC6" base ad:0x818000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree.end tree "ECAP" base ad:0x0 tree "ECAP0_CTL_STS" base ad:0x3100000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCNT,Time Stamp Counter register" hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32-bit counter register which is used as the capture time-base." line.long 0x4 "ECAP_CNTPHS,Counter Phase Control register" hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter phase value register that can be programmed for phase Lag/Lead." line.long 0x8 "ECAP_CAP1,Capture-1 register" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:" line.long 0xC "ECAP_CAP2,Capture-2 register" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:" line.long 0x10 "ECAP_CAP3,Capture-3 register" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APMW mode this is the period shadow (APER) register." line.long 0x14 "ECAP_CAP4,Capture-4 register" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APMW mode this is the compare shadow (ACMP) register." group.long 0x28++0xB line.long 0x0 "ECAP_ECCTL,ECAP Control register" hexmask.long.byte 0x0 27.--31. 1. "FILTER" bitfld.long 0x0 26. "APWMPOL,APWM Output Polarity Select:" "0,1" bitfld.long 0x0 25. "CAP_APWM,CAP/APWM Operating Mode Select:" "0,1" bitfld.long 0x0 24. "SWSYNC,Software Forced Counter (" "0,1" bitfld.long 0x0 22.--23. "SYNCO_SEL,SyncOut Select:" "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (" "0,1" bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control:" "0,1" newline bitfld.long 0x0 19. "REARM_RESET,One-Shot 'Re-arming' Control Write 0h = Has no effect." "0,1" bitfld.long 0x0 17.--18. "STOPVALUE,Stop Value for One-Shot Mode:" "0,1,2,3" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or One-shot Mode Control (applicable only in Capture mode):" "0,1" bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter Prescale Select:" bitfld.long 0x0 8. "CAPLDEN,Enable Loading of the" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4:" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity Select:" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3:" "0,1" bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity Select:" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2:" "0,1" bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity Select:" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1:" "0,1" bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity Select:" "0,1" line.long 0x4 "ECAP_ECINT_EN_FLG,ECAP Interrupt Enable and Flag register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag:" "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag:" "0,1" rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag:" "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag:" "0,1" rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag:" "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag:" "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag:" "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag:" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable:" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable:" "0,1" bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable:" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable:" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable:" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable:" "0,1" bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable:" "0,1" rbitfld.long 0x4 0. "RESERVED,Reserved" "0,1" line.long 0x8 "ECAP_ECINT_CLR_FRC,ECAP Interrupt Clear and Forcing register" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal:" "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal:" "0,1" bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow:" "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4:" "0,1" bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3:" "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2:" "0,1" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1:" "0,1" hexmask.long.word 0x8 8.--16. 1. "RESERVED,Reserved" eventfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag:" "0,1" eventfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag:" "0,1" eventfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag:" "0,1" eventfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag:" "0,1" eventfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag:" "0,1" newline eventfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag:" "0,1" eventfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag:" "0,1" eventfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag:" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "ECAP_PID,Peripheral ID register" hexmask.long 0x0 0.--31. 1. "REVISION,TI internal data. Identifies revision of peripheral." tree.end tree "ECAP1_CTL_STS" base ad:0x3110000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCNT,Time Stamp Counter register" hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32-bit counter register which is used as the capture time-base." line.long 0x4 "ECAP_CNTPHS,Counter Phase Control register" hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter phase value register that can be programmed for phase Lag/Lead." line.long 0x8 "ECAP_CAP1,Capture-1 register" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:" line.long 0xC "ECAP_CAP2,Capture-2 register" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:" line.long 0x10 "ECAP_CAP3,Capture-3 register" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APMW mode this is the period shadow (APER) register." line.long 0x14 "ECAP_CAP4,Capture-4 register" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APMW mode this is the compare shadow (ACMP) register." group.long 0x28++0xB line.long 0x0 "ECAP_ECCTL,ECAP Control register" hexmask.long.byte 0x0 27.--31. 1. "FILTER" bitfld.long 0x0 26. "APWMPOL,APWM Output Polarity Select:" "0,1" bitfld.long 0x0 25. "CAP_APWM,CAP/APWM Operating Mode Select:" "0,1" bitfld.long 0x0 24. "SWSYNC,Software Forced Counter (" "0,1" bitfld.long 0x0 22.--23. "SYNCO_SEL,SyncOut Select:" "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (" "0,1" bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control:" "0,1" newline bitfld.long 0x0 19. "REARM_RESET,One-Shot 'Re-arming' Control Write 0h = Has no effect." "0,1" bitfld.long 0x0 17.--18. "STOPVALUE,Stop Value for One-Shot Mode:" "0,1,2,3" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or One-shot Mode Control (applicable only in Capture mode):" "0,1" bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter Prescale Select:" bitfld.long 0x0 8. "CAPLDEN,Enable Loading of the" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4:" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity Select:" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3:" "0,1" bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity Select:" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2:" "0,1" bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity Select:" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1:" "0,1" bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity Select:" "0,1" line.long 0x4 "ECAP_ECINT_EN_FLG,ECAP Interrupt Enable and Flag register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag:" "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag:" "0,1" rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag:" "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag:" "0,1" rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag:" "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag:" "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag:" "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag:" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable:" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable:" "0,1" bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable:" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable:" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable:" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable:" "0,1" bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable:" "0,1" rbitfld.long 0x4 0. "RESERVED,Reserved" "0,1" line.long 0x8 "ECAP_ECINT_CLR_FRC,ECAP Interrupt Clear and Forcing register" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal:" "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal:" "0,1" bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow:" "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4:" "0,1" bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3:" "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2:" "0,1" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1:" "0,1" hexmask.long.word 0x8 8.--16. 1. "RESERVED,Reserved" eventfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag:" "0,1" eventfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag:" "0,1" eventfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag:" "0,1" eventfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag:" "0,1" eventfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag:" "0,1" newline eventfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag:" "0,1" eventfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag:" "0,1" eventfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag:" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "ECAP_PID,Peripheral ID register" hexmask.long 0x0 0.--31. 1. "REVISION,TI internal data. Identifies revision of peripheral." tree.end tree "ECAP2_CTL_STS" base ad:0x3120000 group.long 0x0++0x17 line.long 0x0 "ECAP_TSCNT,Time Stamp Counter register" hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32-bit counter register which is used as the capture time-base." line.long 0x4 "ECAP_CNTPHS,Counter Phase Control register" hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter phase value register that can be programmed for phase Lag/Lead." line.long 0x8 "ECAP_CAP1,Capture-1 register" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by:" line.long 0xC "ECAP_CAP2,Capture-2 register" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by:" line.long 0x10 "ECAP_CAP3,Capture-3 register" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APMW mode this is the period shadow (APER) register." line.long 0x14 "ECAP_CAP4,Capture-4 register" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APMW mode this is the compare shadow (ACMP) register." group.long 0x28++0xB line.long 0x0 "ECAP_ECCTL,ECAP Control register" hexmask.long.byte 0x0 27.--31. 1. "FILTER" bitfld.long 0x0 26. "APWMPOL,APWM Output Polarity Select:" "0,1" bitfld.long 0x0 25. "CAP_APWM,CAP/APWM Operating Mode Select:" "0,1" bitfld.long 0x0 24. "SWSYNC,Software Forced Counter (" "0,1" bitfld.long 0x0 22.--23. "SYNCO_SEL,SyncOut Select:" "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (" "0,1" bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control:" "0,1" newline bitfld.long 0x0 19. "REARM_RESET,One-Shot 'Re-arming' Control Write 0h = Has no effect." "0,1" bitfld.long 0x0 17.--18. "STOPVALUE,Stop Value for One-Shot Mode:" "0,1,2,3" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or One-shot Mode Control (applicable only in Capture mode):" "0,1" bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter Prescale Select:" bitfld.long 0x0 8. "CAPLDEN,Enable Loading of the" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4:" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity Select:" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3:" "0,1" bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity Select:" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2:" "0,1" bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity Select:" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1:" "0,1" bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity Select:" "0,1" line.long 0x4 "ECAP_ECINT_EN_FLG,ECAP Interrupt Enable and Flag register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag:" "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag:" "0,1" rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag:" "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag:" "0,1" rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag:" "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag:" "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag:" "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag:" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable:" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable:" "0,1" bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable:" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable:" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable:" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable:" "0,1" bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable:" "0,1" rbitfld.long 0x4 0. "RESERVED,Reserved" "0,1" line.long 0x8 "ECAP_ECINT_CLR_FRC,ECAP Interrupt Clear and Forcing register" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal:" "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal:" "0,1" bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow:" "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4:" "0,1" bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3:" "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2:" "0,1" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1:" "0,1" hexmask.long.word 0x8 8.--16. 1. "RESERVED,Reserved" eventfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag:" "0,1" eventfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag:" "0,1" eventfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag:" "0,1" eventfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag:" "0,1" eventfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag:" "0,1" newline eventfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag:" "0,1" eventfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag:" "0,1" eventfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag:" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "ECAP_PID,Peripheral ID register" hexmask.long 0x0 0.--31. 1. "REVISION,TI internal data. Identifies revision of peripheral." tree.end tree.end tree "EHRPWM" base ad:0x0 tree "EHRPWM0_EHRPWM" base ad:0x3008000 group.word 0x40++0x1 line.word 0x0 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension. Otherwise. this location is reserved." hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "PULSESEL,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. The user should select this event to match the selection of the CMPA load mode 0h: Load on CTR = 0. Time-base counter equal to zero (EPWM_TBCNT =.." "0,1" bitfld.word 0x0 2. "DELBUSSEL,Control Mode Bits Selects the register (CMP or TBPHS) that controls the MEP. 0h = Select CMPAHR(8) register controls the edge position. This is duty control mode (default on reset). 1h = Select TBPHSHR(8) register controls the edge position.." "0,1" bitfld.word 0x0 0.--1. "DELMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic. 0h = HRPWM capability is disabled (default on reset) 1h = MEP control of rising edge 2h = MEP control of falling edge 3h = MEP control of both.." "0,1,2,3" tree.end tree "EHRPWM0_EPWM" base ad:0x3000000 group.word 0x0++0xB line.word 0x0 "EPWM_TBCTL" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the EPWM time-base counter during emulation events. 0h: Stop after the next time-base counter increment or decrement 1h: Stop when counter completes a whole cycle 2h: Free run 3h: Free run" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0h: Count down after the synchronization event 1h: Count up after the.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) 0h: /1 (default on reset) 1h: /2 2h: /4 3h: /8 4h: /16 5h: /32 6h: /64 7h: /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV). 0h: /1 1h: /2 (default on reset) 2h: /4 3h: /6 4h: /8 5h: /10 6h: /12 7h: /14" "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse 0h: Writing a 0h has no effect and reads always return a 0h. 1h: Writing a 1h forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the EPWM module. SWFSYNC.." "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal. 0h: EPWMxSYNC 1h: TBCNT = 0: Time-base counter equal to zero ( 2h: TBCNT = CMPB: Time-base counter equal to counter-compare B ( 3h: Disable EPWMxSYNCO signal" "0: Time-base counter equal to zero,?,?,?" newline bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select 0h: The period register ( 1h: Load the" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable 0h: Do not load the time-base counter ( 1h: Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0,1,2,3" line.word 0x2 "EPWM_TBSTS" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0h = Reading a 0h indicates the time-base counter never reached its maximum value. Writing a 0h will have no effect. 1h = Reading a 1h on this bit indicates that the time-base counter reached the max value.." "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit 0h = Writing a 0h will have no effect. Reading a 0h indicates no external synchronization event has occurred. 1h = Reading a 1h on this bit indicates that an external synchronization event has occurred.." "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via the 0h = Time-Base Counter is currently counting down 1h =.." "0,1" line.word 0x4 "HRPWM_TBPHSHR" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" hexmask.word.byte 0x4 0.--7. 1. "RESERVED,Reserved" line.word 0x6 "EPWM_TBPHS,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal: [a] If [b] If These bits set time-base counter phase of the selected EPWM relative to the time-base that is.." line.word 0x8 "EPWM_TBCNT" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the.." line.word 0xA "EPWM_TBPRD" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.word 0xE++0x17 line.word 0x0 "EPWM_CMPCTL" hexmask.word.byte 0x0 10.--15. 1. "RESERVED,Reserved" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B ( This bit self clears once a load-strobe occurs. 0h = CMPB shadow FIFO not full yet 1h = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A ( 0h = CMPA shadow FIFO not full yet 1h = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" rbitfld.word 0x0 7. "RESERVED,Reserved" "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for.." "0,1" rbitfld.word 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B ( This bit has no effect in immediate mode ( 0h = Load on 1h = Load on 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A ( This bit has no effect in immediate mode ( 0h = Load on TBCNT = 0h: Time-base counter equal to zero ( 1h = Load on TBCNT = TBPRD: Time-base counter equal to period ( 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" line.word 0x2 "HRPWM_CMPAHR,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation: 1h to 255h." hexmask.word.byte 0x2 0.--7. 1. "RESERVED,Reserved" line.word 0x4 "EPWM_CMPA" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the activeWhen the values are equal the counter-compare module generates a 'Time-Base counter equal to counter compare A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x6 "EPWM_CMPB" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the activeWhen the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x8 "EPWM_AQCTLA" hexmask.word.byte 0x8 12.--15. 1. "RESERVED,Reserved" bitfld.word 0x8 10.--11. "CBD,Action when the Time-Base counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be.." "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output.." "0,1,2,3" line.word 0xA "EPWM_AQCTLB" hexmask.word.byte 0xA 12.--15. 1. "RESERVED,Reserved" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output.." "0,1,2,3" line.word 0xC "EPWM_AQSFRC" hexmask.word.byte 0xC 8.--15. 1. "RESERVED,Reserved" bitfld.word 0xC 6.--7. "RLDCSF" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B 0h = Writing a 0h (zero) has no effect. Always reads back a 0h. This bit is auto cleared once a write to this register is complete that is a forced event is initiated. This is a one-shot forced event. It.." "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked 0h = Does nothing (action disabled) 1h = Clear (low) 2h = Set (high) 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A 0h = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1h = Initiates a single software.." "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 0h = Does nothing (action disabled). 1h = Clear (low). 2h = Set (high). 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" line.word 0xE "EPWM_AQCSFRC" hexmask.word 0xE 4.--15. 1. "RESERVED,Reserved" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0h = Forcing.." "0,1,2,3" line.word 0x10 "EPWM_DBCTL" hexmask.word 0x10 6.--15. 1. "RESERVED,Reserved" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0h = Dead-band generation is.." "0,1,2,3" line.word 0x12 "EPWM_DBRED" hexmask.word.byte 0x12 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count. 10-bit counter." line.word 0x14 "EPWM_DBFED" hexmask.word.byte 0x14 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count. 10-bit counter" line.word 0x16 "EPWM_TZSEL" rbitfld.word 0x16 14.--15. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 13. "OSHT6,Trip-zone 5 (TZ5) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a one-shot trip source.." "0,1" bitfld.word 0x16 12. "OSHT5,Trip-zone 4 (TZ4) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a one-shot trip source.." "0,1" bitfld.word 0x16 11. "OSHT4,Trip-zone 3 (TZ3) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a one-shot trip source.." "0,1" bitfld.word 0x16 10. "OSHT3,Trip-zone 2 (TZ2) Select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a one-shot trip source.." "0,1" bitfld.word 0x16 9. "OSHT2,Trip-zone 1 (TZ1) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a one-shot trip source.." "0,1" newline bitfld.word 0x16 8. "OSHT1,Trip-zone 0 (TZ0) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a one-shot trip source.." "0,1" rbitfld.word 0x16 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 5. "CBC5,Trip-zone 5 (TZ5) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a CBC trip.." "0,1" bitfld.word 0x16 4. "CBC4,Trip-zone 4 (TZ4) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a CBC trip.." "0,1" bitfld.word 0x16 3. "CBC3,Trip-zone 3 (TZ3) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a CBC trip.." "0,1" bitfld.word 0x16 2. "CBC2,Trip-zone 2 (TZ2) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a CBC trip.." "0,1" newline bitfld.word 0x16 1. "CBC1,Trip-zone 1 (TZ1) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a CBC trip.." "0,1" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a CBC trip.." "0,1" group.word 0x28++0x3 line.word 0x0 "EPWM_TZCTL" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxB = High-impedance state) 1h = Force EPWMxB to a high state 2h = Force EPWMxB to a low state.." "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxA = High-impedance state) 1h = Force EPWMxA to a high state 2h = Force EPWMxA to a low state.." "0,1,2,3" line.word 0x2 "EPWM_TZEINT" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation 1h = Enable interrupt generation" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_TZFLG" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0h = No one-shot trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0h = No cycle-by-cycle trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0h = Indicates no interrupt has been generated 1h = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the.." "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_TZCLR" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip (OST) Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0h = Has no effect. Always reads back a 0h 1h = Clears the trip-interrupt flag for this EPWM module ( Note: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the" "0,1" line.word 0x2 "EPWM_TZFRC" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a one-shot trip event and sets the" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a cycle-by-cycle trip event and sets the" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" line.word 0x4 "EPWM_ETSEL" bitfld.word 0x4 15. "SOCB,Enable SOCB pulse when set to 1h." "0,1" bitfld.word 0x4 12.--14. "SOCBSEL,EPWMxSOCB Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" bitfld.word 0x4 11. "SOCA,Enable SOCA pulse when set to 1h." "0,1" bitfld.word 0x4 8.--10. "SOCASEL,EPWMxSOCA Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.word 0x4 3. "INTEN,Enable EPWM Interrupt (EPWMx_INT) Generation 0h: Disable EPWMx_INT generation 1h: Enable EPWMx_INT generation" "0,1" newline bitfld.word 0x4 0.--2. "INTSEL,EPWM Interrupt (EPWMx_INT) Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero. ( 2h: Enable event time-base counter equal to period ( 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is.." "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_ETPS" rbitfld.word 0x6 14.--15. "SOCBCNT,EPWMxSOCB Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 12.--13. "SOCBPRD,EPWMxSOCB Period Select These bits select how many selected event need to occur before an SOCB pulse is generated." "0,1,2,3" rbitfld.word 0x6 10.--11. "SOCACNT,EPWMxSOCA Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 8.--9. "SOCAPRD,EPWMxSOCA Period Select These bits select how many selected event need to occur before an SOCA pulse is generated." "0,1,2,3" hexmask.word.byte 0x6 4.--7. 1. "RESERVED,Reserved" rbitfld.word 0x6 2.--3. "INTCNT,EPWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected 0h: No events have occurred 1h: 1 event has occurred 2h: 2 events have occurred 3h: 3 events have occurred" "0,1,2,3" newline bitfld.word 0x6 0.--1. "INTPRD,EPWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected 0h: Disable the interrupt event counter. No interrupt will be generated and the 1h: Generate an interrupt on the first event INTCNT = 0b01 (first event) 2h: Generate.." "0,1,2,3" rgroup.word 0x36++0x3 line.word 0x0 "EPWM_ETFLG" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,Latched SOCB Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB Note: Unlike the INT flag bit the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 2. "SOCA,Latched SOCA Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA Note: Unlike the INT flag bit the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,Latched EPWM Interrupt (EPWMx_INT) Status Flag 0h: Indicates no event occurred. 1h: Indicates that an EPWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0,1" line.word 0x2 "EPWM_ETCLR" hexmask.word 0x2 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" group.word 0x3A++0x3 line.word 0x0 "EPWM_ETFRC" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,SOCB Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[3] SOCB flag bit" "0,1" bitfld.word 0x0 2. "SOCA,SOCA Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[2] SOCA flag bit" "0,1" rbitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,EPWM Interrupt (EPWMx_INT) Flag Clear Bit 0h: Writing a 0 has no effect. Always reads back a 0h. 1h: Writing 1 clears the" "0,1" line.word 0x2 "EPWM_PCCTL" hexmask.word.byte 0x2 11.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0h = Duty = 1/8 (12.5%) 1h = Duty = 2/8 (25.0%) 2h = Duty = 3/8 (37.5%) 3h = Duty = 4/8 (50.0%) 4h = Duty = 5/8 (62.5%) 5h = Duty = 6/8 (75.0%) 6h = Duty = 7/8 (87.5%) 7h = Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 5.--7. "CHPFREQ,Chopping Clock Frequency 0h = Divide by 1 (no prescale) 1h = Divide by 2 2h = Divide by 3 3h = Divide by 4 4h = Divide by 5 5h = Divide by 6 6h = Divide by 7 7h = Divide by 8" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0h = 1 - SYSCLKOUT/8 wide 1h = 2 - SYSCLKOUT/8 wide 2h = 3 - SYSCLKOUT/8 wide 3h = 4 - SYSCLKOUT/8 wide Fh = 16 - SYSCLKOUT/8 wide" bitfld.word 0x2 0. "CHPEN,PWM-chopping Enable 0h = Disable (bypass) PWM chopping function 1h = Enable chopping function" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_PID,The revision register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data Identifies revision of peripheral." tree.end tree "EHRPWM1_EHRPWM" base ad:0x3018000 group.word 0x40++0x1 line.word 0x0 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension. Otherwise. this location is reserved." hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "PULSESEL,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. The user should select this event to match the selection of the CMPA load mode 0h: Load on CTR = 0. Time-base counter equal to zero (EPWM_TBCNT =.." "0,1" bitfld.word 0x0 2. "DELBUSSEL,Control Mode Bits Selects the register (CMP or TBPHS) that controls the MEP. 0h = Select CMPAHR(8) register controls the edge position. This is duty control mode (default on reset). 1h = Select TBPHSHR(8) register controls the edge position.." "0,1" bitfld.word 0x0 0.--1. "DELMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic. 0h = HRPWM capability is disabled (default on reset) 1h = MEP control of rising edge 2h = MEP control of falling edge 3h = MEP control of both.." "0,1,2,3" tree.end tree "EHRPWM1_EPWM" base ad:0x3010000 group.word 0x0++0xB line.word 0x0 "EPWM_TBCTL" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the EPWM time-base counter during emulation events. 0h: Stop after the next time-base counter increment or decrement 1h: Stop when counter completes a whole cycle 2h: Free run 3h: Free run" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0h: Count down after the synchronization event 1h: Count up after the.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) 0h: /1 (default on reset) 1h: /2 2h: /4 3h: /8 4h: /16 5h: /32 6h: /64 7h: /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV). 0h: /1 1h: /2 (default on reset) 2h: /4 3h: /6 4h: /8 5h: /10 6h: /12 7h: /14" "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse 0h: Writing a 0h has no effect and reads always return a 0h. 1h: Writing a 1h forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the EPWM module. SWFSYNC.." "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal. 0h: EPWMxSYNC 1h: TBCNT = 0: Time-base counter equal to zero ( 2h: TBCNT = CMPB: Time-base counter equal to counter-compare B ( 3h: Disable EPWMxSYNCO signal" "0: Time-base counter equal to zero,?,?,?" newline bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select 0h: The period register ( 1h: Load the" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable 0h: Do not load the time-base counter ( 1h: Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0,1,2,3" line.word 0x2 "EPWM_TBSTS" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0h = Reading a 0h indicates the time-base counter never reached its maximum value. Writing a 0h will have no effect. 1h = Reading a 1h on this bit indicates that the time-base counter reached the max value.." "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit 0h = Writing a 0h will have no effect. Reading a 0h indicates no external synchronization event has occurred. 1h = Reading a 1h on this bit indicates that an external synchronization event has occurred.." "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via the 0h = Time-Base Counter is currently counting down 1h =.." "0,1" line.word 0x4 "HRPWM_TBPHSHR" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" hexmask.word.byte 0x4 0.--7. 1. "RESERVED,Reserved" line.word 0x6 "EPWM_TBPHS,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal: [a] If [b] If These bits set time-base counter phase of the selected EPWM relative to the time-base that is.." line.word 0x8 "EPWM_TBCNT" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the.." line.word 0xA "EPWM_TBPRD" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.word 0xE++0x17 line.word 0x0 "EPWM_CMPCTL" hexmask.word.byte 0x0 10.--15. 1. "RESERVED,Reserved" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B ( This bit self clears once a load-strobe occurs. 0h = CMPB shadow FIFO not full yet 1h = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A ( 0h = CMPA shadow FIFO not full yet 1h = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" rbitfld.word 0x0 7. "RESERVED,Reserved" "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for.." "0,1" rbitfld.word 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B ( This bit has no effect in immediate mode ( 0h = Load on 1h = Load on 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A ( This bit has no effect in immediate mode ( 0h = Load on TBCNT = 0h: Time-base counter equal to zero ( 1h = Load on TBCNT = TBPRD: Time-base counter equal to period ( 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" line.word 0x2 "HRPWM_CMPAHR,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation: 1h to 255h." hexmask.word.byte 0x2 0.--7. 1. "RESERVED,Reserved" line.word 0x4 "EPWM_CMPA" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the activeWhen the values are equal the counter-compare module generates a 'Time-Base counter equal to counter compare A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x6 "EPWM_CMPB" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the activeWhen the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x8 "EPWM_AQCTLA" hexmask.word.byte 0x8 12.--15. 1. "RESERVED,Reserved" bitfld.word 0x8 10.--11. "CBD,Action when the Time-Base counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be.." "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output.." "0,1,2,3" line.word 0xA "EPWM_AQCTLB" hexmask.word.byte 0xA 12.--15. 1. "RESERVED,Reserved" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output.." "0,1,2,3" line.word 0xC "EPWM_AQSFRC" hexmask.word.byte 0xC 8.--15. 1. "RESERVED,Reserved" bitfld.word 0xC 6.--7. "RLDCSF" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B 0h = Writing a 0h (zero) has no effect. Always reads back a 0h. This bit is auto cleared once a write to this register is complete that is a forced event is initiated. This is a one-shot forced event. It.." "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked 0h = Does nothing (action disabled) 1h = Clear (low) 2h = Set (high) 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A 0h = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1h = Initiates a single software.." "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 0h = Does nothing (action disabled). 1h = Clear (low). 2h = Set (high). 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" line.word 0xE "EPWM_AQCSFRC" hexmask.word 0xE 4.--15. 1. "RESERVED,Reserved" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0h = Forcing.." "0,1,2,3" line.word 0x10 "EPWM_DBCTL" hexmask.word 0x10 6.--15. 1. "RESERVED,Reserved" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0h = Dead-band generation is.." "0,1,2,3" line.word 0x12 "EPWM_DBRED" hexmask.word.byte 0x12 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count. 10-bit counter." line.word 0x14 "EPWM_DBFED" hexmask.word.byte 0x14 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count. 10-bit counter" line.word 0x16 "EPWM_TZSEL" rbitfld.word 0x16 14.--15. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 13. "OSHT6,Trip-zone 5 (TZ5) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a one-shot trip source.." "0,1" bitfld.word 0x16 12. "OSHT5,Trip-zone 4 (TZ4) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a one-shot trip source.." "0,1" bitfld.word 0x16 11. "OSHT4,Trip-zone 3 (TZ3) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a one-shot trip source.." "0,1" bitfld.word 0x16 10. "OSHT3,Trip-zone 2 (TZ2) Select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a one-shot trip source.." "0,1" bitfld.word 0x16 9. "OSHT2,Trip-zone 1 (TZ1) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a one-shot trip source.." "0,1" newline bitfld.word 0x16 8. "OSHT1,Trip-zone 0 (TZ0) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a one-shot trip source.." "0,1" rbitfld.word 0x16 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 5. "CBC5,Trip-zone 5 (TZ5) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a CBC trip.." "0,1" bitfld.word 0x16 4. "CBC4,Trip-zone 4 (TZ4) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a CBC trip.." "0,1" bitfld.word 0x16 3. "CBC3,Trip-zone 3 (TZ3) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a CBC trip.." "0,1" bitfld.word 0x16 2. "CBC2,Trip-zone 2 (TZ2) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a CBC trip.." "0,1" newline bitfld.word 0x16 1. "CBC1,Trip-zone 1 (TZ1) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a CBC trip.." "0,1" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a CBC trip.." "0,1" group.word 0x28++0x3 line.word 0x0 "EPWM_TZCTL" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxB = High-impedance state) 1h = Force EPWMxB to a high state 2h = Force EPWMxB to a low state.." "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxA = High-impedance state) 1h = Force EPWMxA to a high state 2h = Force EPWMxA to a low state.." "0,1,2,3" line.word 0x2 "EPWM_TZEINT" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation 1h = Enable interrupt generation" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_TZFLG" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0h = No one-shot trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0h = No cycle-by-cycle trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0h = Indicates no interrupt has been generated 1h = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the.." "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_TZCLR" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip (OST) Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0h = Has no effect. Always reads back a 0h 1h = Clears the trip-interrupt flag for this EPWM module ( Note: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the" "0,1" line.word 0x2 "EPWM_TZFRC" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a one-shot trip event and sets the" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a cycle-by-cycle trip event and sets the" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" line.word 0x4 "EPWM_ETSEL" bitfld.word 0x4 15. "SOCB,Enable SOCB pulse when set to 1h." "0,1" bitfld.word 0x4 12.--14. "SOCBSEL,EPWMxSOCB Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" bitfld.word 0x4 11. "SOCA,Enable SOCA pulse when set to 1h." "0,1" bitfld.word 0x4 8.--10. "SOCASEL,EPWMxSOCA Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.word 0x4 3. "INTEN,Enable EPWM Interrupt (EPWMx_INT) Generation 0h: Disable EPWMx_INT generation 1h: Enable EPWMx_INT generation" "0,1" newline bitfld.word 0x4 0.--2. "INTSEL,EPWM Interrupt (EPWMx_INT) Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero. ( 2h: Enable event time-base counter equal to period ( 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is.." "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_ETPS" rbitfld.word 0x6 14.--15. "SOCBCNT,EPWMxSOCB Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 12.--13. "SOCBPRD,EPWMxSOCB Period Select These bits select how many selected event need to occur before an SOCB pulse is generated." "0,1,2,3" rbitfld.word 0x6 10.--11. "SOCACNT,EPWMxSOCA Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 8.--9. "SOCAPRD,EPWMxSOCA Period Select These bits select how many selected event need to occur before an SOCA pulse is generated." "0,1,2,3" hexmask.word.byte 0x6 4.--7. 1. "RESERVED,Reserved" rbitfld.word 0x6 2.--3. "INTCNT,EPWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected 0h: No events have occurred 1h: 1 event has occurred 2h: 2 events have occurred 3h: 3 events have occurred" "0,1,2,3" newline bitfld.word 0x6 0.--1. "INTPRD,EPWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected 0h: Disable the interrupt event counter. No interrupt will be generated and the 1h: Generate an interrupt on the first event INTCNT = 0b01 (first event) 2h: Generate.." "0,1,2,3" rgroup.word 0x36++0x3 line.word 0x0 "EPWM_ETFLG" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,Latched SOCB Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB Note: Unlike the INT flag bit the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 2. "SOCA,Latched SOCA Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA Note: Unlike the INT flag bit the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,Latched EPWM Interrupt (EPWMx_INT) Status Flag 0h: Indicates no event occurred. 1h: Indicates that an EPWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0,1" line.word 0x2 "EPWM_ETCLR" hexmask.word 0x2 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" group.word 0x3A++0x3 line.word 0x0 "EPWM_ETFRC" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,SOCB Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[3] SOCB flag bit" "0,1" bitfld.word 0x0 2. "SOCA,SOCA Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[2] SOCA flag bit" "0,1" rbitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,EPWM Interrupt (EPWMx_INT) Flag Clear Bit 0h: Writing a 0 has no effect. Always reads back a 0h. 1h: Writing 1 clears the" "0,1" line.word 0x2 "EPWM_PCCTL" hexmask.word.byte 0x2 11.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0h = Duty = 1/8 (12.5%) 1h = Duty = 2/8 (25.0%) 2h = Duty = 3/8 (37.5%) 3h = Duty = 4/8 (50.0%) 4h = Duty = 5/8 (62.5%) 5h = Duty = 6/8 (75.0%) 6h = Duty = 7/8 (87.5%) 7h = Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 5.--7. "CHPFREQ,Chopping Clock Frequency 0h = Divide by 1 (no prescale) 1h = Divide by 2 2h = Divide by 3 3h = Divide by 4 4h = Divide by 5 5h = Divide by 6 6h = Divide by 7 7h = Divide by 8" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0h = 1 - SYSCLKOUT/8 wide 1h = 2 - SYSCLKOUT/8 wide 2h = 3 - SYSCLKOUT/8 wide 3h = 4 - SYSCLKOUT/8 wide Fh = 16 - SYSCLKOUT/8 wide" bitfld.word 0x2 0. "CHPEN,PWM-chopping Enable 0h = Disable (bypass) PWM chopping function 1h = Enable chopping function" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_PID,The revision register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data Identifies revision of peripheral." tree.end tree "EHRPWM2_EHRPWM" base ad:0x3028000 group.word 0x40++0x1 line.word 0x0 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension. Otherwise. this location is reserved." hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "PULSESEL,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. The user should select this event to match the selection of the CMPA load mode 0h: Load on CTR = 0. Time-base counter equal to zero (EPWM_TBCNT =.." "0,1" bitfld.word 0x0 2. "DELBUSSEL,Control Mode Bits Selects the register (CMP or TBPHS) that controls the MEP. 0h = Select CMPAHR(8) register controls the edge position. This is duty control mode (default on reset). 1h = Select TBPHSHR(8) register controls the edge position.." "0,1" bitfld.word 0x0 0.--1. "DELMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic. 0h = HRPWM capability is disabled (default on reset) 1h = MEP control of rising edge 2h = MEP control of falling edge 3h = MEP control of both.." "0,1,2,3" tree.end tree "EHRPWM2_EPWM" base ad:0x3020000 group.word 0x0++0xB line.word 0x0 "EPWM_TBCTL" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the EPWM time-base counter during emulation events. 0h: Stop after the next time-base counter increment or decrement 1h: Stop when counter completes a whole cycle 2h: Free run 3h: Free run" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0h: Count down after the synchronization event 1h: Count up after the.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) 0h: /1 (default on reset) 1h: /2 2h: /4 3h: /8 4h: /16 5h: /32 6h: /64 7h: /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV). 0h: /1 1h: /2 (default on reset) 2h: /4 3h: /6 4h: /8 5h: /10 6h: /12 7h: /14" "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse 0h: Writing a 0h has no effect and reads always return a 0h. 1h: Writing a 1h forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the EPWM module. SWFSYNC.." "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal. 0h: EPWMxSYNC 1h: TBCNT = 0: Time-base counter equal to zero ( 2h: TBCNT = CMPB: Time-base counter equal to counter-compare B ( 3h: Disable EPWMxSYNCO signal" "0: Time-base counter equal to zero,?,?,?" newline bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select 0h: The period register ( 1h: Load the" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable 0h: Do not load the time-base counter ( 1h: Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0,1,2,3" line.word 0x2 "EPWM_TBSTS" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0h = Reading a 0h indicates the time-base counter never reached its maximum value. Writing a 0h will have no effect. 1h = Reading a 1h on this bit indicates that the time-base counter reached the max value.." "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit 0h = Writing a 0h will have no effect. Reading a 0h indicates no external synchronization event has occurred. 1h = Reading a 1h on this bit indicates that an external synchronization event has occurred.." "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via the 0h = Time-Base Counter is currently counting down 1h =.." "0,1" line.word 0x4 "HRPWM_TBPHSHR" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" hexmask.word.byte 0x4 0.--7. 1. "RESERVED,Reserved" line.word 0x6 "EPWM_TBPHS,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal: [a] If [b] If These bits set time-base counter phase of the selected EPWM relative to the time-base that is.." line.word 0x8 "EPWM_TBCNT" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the.." line.word 0xA "EPWM_TBPRD" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.word 0xE++0x17 line.word 0x0 "EPWM_CMPCTL" hexmask.word.byte 0x0 10.--15. 1. "RESERVED,Reserved" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B ( This bit self clears once a load-strobe occurs. 0h = CMPB shadow FIFO not full yet 1h = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A ( 0h = CMPA shadow FIFO not full yet 1h = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" rbitfld.word 0x0 7. "RESERVED,Reserved" "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for.." "0,1" rbitfld.word 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B ( This bit has no effect in immediate mode ( 0h = Load on 1h = Load on 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A ( This bit has no effect in immediate mode ( 0h = Load on TBCNT = 0h: Time-base counter equal to zero ( 1h = Load on TBCNT = TBPRD: Time-base counter equal to period ( 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" line.word 0x2 "HRPWM_CMPAHR,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation: 1h to 255h." hexmask.word.byte 0x2 0.--7. 1. "RESERVED,Reserved" line.word 0x4 "EPWM_CMPA" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the activeWhen the values are equal the counter-compare module generates a 'Time-Base counter equal to counter compare A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x6 "EPWM_CMPB" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the activeWhen the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x8 "EPWM_AQCTLA" hexmask.word.byte 0x8 12.--15. 1. "RESERVED,Reserved" bitfld.word 0x8 10.--11. "CBD,Action when the Time-Base counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be.." "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output.." "0,1,2,3" line.word 0xA "EPWM_AQCTLB" hexmask.word.byte 0xA 12.--15. 1. "RESERVED,Reserved" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output.." "0,1,2,3" line.word 0xC "EPWM_AQSFRC" hexmask.word.byte 0xC 8.--15. 1. "RESERVED,Reserved" bitfld.word 0xC 6.--7. "RLDCSF" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B 0h = Writing a 0h (zero) has no effect. Always reads back a 0h. This bit is auto cleared once a write to this register is complete that is a forced event is initiated. This is a one-shot forced event. It.." "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked 0h = Does nothing (action disabled) 1h = Clear (low) 2h = Set (high) 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A 0h = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1h = Initiates a single software.." "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 0h = Does nothing (action disabled). 1h = Clear (low). 2h = Set (high). 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" line.word 0xE "EPWM_AQCSFRC" hexmask.word 0xE 4.--15. 1. "RESERVED,Reserved" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0h = Forcing.." "0,1,2,3" line.word 0x10 "EPWM_DBCTL" hexmask.word 0x10 6.--15. 1. "RESERVED,Reserved" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0h = Dead-band generation is.." "0,1,2,3" line.word 0x12 "EPWM_DBRED" hexmask.word.byte 0x12 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count. 10-bit counter." line.word 0x14 "EPWM_DBFED" hexmask.word.byte 0x14 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count. 10-bit counter" line.word 0x16 "EPWM_TZSEL" rbitfld.word 0x16 14.--15. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 13. "OSHT6,Trip-zone 5 (TZ5) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a one-shot trip source.." "0,1" bitfld.word 0x16 12. "OSHT5,Trip-zone 4 (TZ4) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a one-shot trip source.." "0,1" bitfld.word 0x16 11. "OSHT4,Trip-zone 3 (TZ3) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a one-shot trip source.." "0,1" bitfld.word 0x16 10. "OSHT3,Trip-zone 2 (TZ2) Select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a one-shot trip source.." "0,1" bitfld.word 0x16 9. "OSHT2,Trip-zone 1 (TZ1) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a one-shot trip source.." "0,1" newline bitfld.word 0x16 8. "OSHT1,Trip-zone 0 (TZ0) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a one-shot trip source.." "0,1" rbitfld.word 0x16 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 5. "CBC5,Trip-zone 5 (TZ5) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a CBC trip.." "0,1" bitfld.word 0x16 4. "CBC4,Trip-zone 4 (TZ4) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a CBC trip.." "0,1" bitfld.word 0x16 3. "CBC3,Trip-zone 3 (TZ3) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a CBC trip.." "0,1" bitfld.word 0x16 2. "CBC2,Trip-zone 2 (TZ2) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a CBC trip.." "0,1" newline bitfld.word 0x16 1. "CBC1,Trip-zone 1 (TZ1) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a CBC trip.." "0,1" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a CBC trip.." "0,1" group.word 0x28++0x3 line.word 0x0 "EPWM_TZCTL" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxB = High-impedance state) 1h = Force EPWMxB to a high state 2h = Force EPWMxB to a low state.." "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxA = High-impedance state) 1h = Force EPWMxA to a high state 2h = Force EPWMxA to a low state.." "0,1,2,3" line.word 0x2 "EPWM_TZEINT" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation 1h = Enable interrupt generation" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_TZFLG" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0h = No one-shot trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0h = No cycle-by-cycle trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0h = Indicates no interrupt has been generated 1h = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the.." "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_TZCLR" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip (OST) Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0h = Has no effect. Always reads back a 0h 1h = Clears the trip-interrupt flag for this EPWM module ( Note: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the" "0,1" line.word 0x2 "EPWM_TZFRC" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a one-shot trip event and sets the" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a cycle-by-cycle trip event and sets the" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" line.word 0x4 "EPWM_ETSEL" bitfld.word 0x4 15. "SOCB,Enable SOCB pulse when set to 1h." "0,1" bitfld.word 0x4 12.--14. "SOCBSEL,EPWMxSOCB Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" bitfld.word 0x4 11. "SOCA,Enable SOCA pulse when set to 1h." "0,1" bitfld.word 0x4 8.--10. "SOCASEL,EPWMxSOCA Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.word 0x4 3. "INTEN,Enable EPWM Interrupt (EPWMx_INT) Generation 0h: Disable EPWMx_INT generation 1h: Enable EPWMx_INT generation" "0,1" newline bitfld.word 0x4 0.--2. "INTSEL,EPWM Interrupt (EPWMx_INT) Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero. ( 2h: Enable event time-base counter equal to period ( 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is.." "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_ETPS" rbitfld.word 0x6 14.--15. "SOCBCNT,EPWMxSOCB Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 12.--13. "SOCBPRD,EPWMxSOCB Period Select These bits select how many selected event need to occur before an SOCB pulse is generated." "0,1,2,3" rbitfld.word 0x6 10.--11. "SOCACNT,EPWMxSOCA Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 8.--9. "SOCAPRD,EPWMxSOCA Period Select These bits select how many selected event need to occur before an SOCA pulse is generated." "0,1,2,3" hexmask.word.byte 0x6 4.--7. 1. "RESERVED,Reserved" rbitfld.word 0x6 2.--3. "INTCNT,EPWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected 0h: No events have occurred 1h: 1 event has occurred 2h: 2 events have occurred 3h: 3 events have occurred" "0,1,2,3" newline bitfld.word 0x6 0.--1. "INTPRD,EPWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected 0h: Disable the interrupt event counter. No interrupt will be generated and the 1h: Generate an interrupt on the first event INTCNT = 0b01 (first event) 2h: Generate.." "0,1,2,3" rgroup.word 0x36++0x3 line.word 0x0 "EPWM_ETFLG" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,Latched SOCB Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB Note: Unlike the INT flag bit the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 2. "SOCA,Latched SOCA Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA Note: Unlike the INT flag bit the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,Latched EPWM Interrupt (EPWMx_INT) Status Flag 0h: Indicates no event occurred. 1h: Indicates that an EPWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0,1" line.word 0x2 "EPWM_ETCLR" hexmask.word 0x2 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" group.word 0x3A++0x3 line.word 0x0 "EPWM_ETFRC" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,SOCB Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[3] SOCB flag bit" "0,1" bitfld.word 0x0 2. "SOCA,SOCA Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[2] SOCA flag bit" "0,1" rbitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,EPWM Interrupt (EPWMx_INT) Flag Clear Bit 0h: Writing a 0 has no effect. Always reads back a 0h. 1h: Writing 1 clears the" "0,1" line.word 0x2 "EPWM_PCCTL" hexmask.word.byte 0x2 11.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0h = Duty = 1/8 (12.5%) 1h = Duty = 2/8 (25.0%) 2h = Duty = 3/8 (37.5%) 3h = Duty = 4/8 (50.0%) 4h = Duty = 5/8 (62.5%) 5h = Duty = 6/8 (75.0%) 6h = Duty = 7/8 (87.5%) 7h = Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 5.--7. "CHPFREQ,Chopping Clock Frequency 0h = Divide by 1 (no prescale) 1h = Divide by 2 2h = Divide by 3 3h = Divide by 4 4h = Divide by 5 5h = Divide by 6 6h = Divide by 7 7h = Divide by 8" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0h = 1 - SYSCLKOUT/8 wide 1h = 2 - SYSCLKOUT/8 wide 2h = 3 - SYSCLKOUT/8 wide 3h = 4 - SYSCLKOUT/8 wide Fh = 16 - SYSCLKOUT/8 wide" bitfld.word 0x2 0. "CHPEN,PWM-chopping Enable 0h = Disable (bypass) PWM chopping function 1h = Enable chopping function" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_PID,The revision register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data Identifies revision of peripheral." tree.end tree "EHRPWM3_EHRPWM" base ad:0x3038000 group.word 0x40++0x1 line.word 0x0 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension. Otherwise. this location is reserved." hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "PULSESEL,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. The user should select this event to match the selection of the CMPA load mode 0h: Load on CTR = 0. Time-base counter equal to zero (EPWM_TBCNT =.." "0,1" bitfld.word 0x0 2. "DELBUSSEL,Control Mode Bits Selects the register (CMP or TBPHS) that controls the MEP. 0h = Select CMPAHR(8) register controls the edge position. This is duty control mode (default on reset). 1h = Select TBPHSHR(8) register controls the edge position.." "0,1" bitfld.word 0x0 0.--1. "DELMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic. 0h = HRPWM capability is disabled (default on reset) 1h = MEP control of rising edge 2h = MEP control of falling edge 3h = MEP control of both.." "0,1,2,3" tree.end tree "EHRPWM3_EPWM" base ad:0x3030000 group.word 0x0++0xB line.word 0x0 "EPWM_TBCTL" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the EPWM time-base counter during emulation events. 0h: Stop after the next time-base counter increment or decrement 1h: Stop when counter completes a whole cycle 2h: Free run 3h: Free run" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0h: Count down after the synchronization event 1h: Count up after the.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) 0h: /1 (default on reset) 1h: /2 2h: /4 3h: /8 4h: /16 5h: /32 6h: /64 7h: /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV). 0h: /1 1h: /2 (default on reset) 2h: /4 3h: /6 4h: /8 5h: /10 6h: /12 7h: /14" "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse 0h: Writing a 0h has no effect and reads always return a 0h. 1h: Writing a 1h forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the EPWM module. SWFSYNC.." "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal. 0h: EPWMxSYNC 1h: TBCNT = 0: Time-base counter equal to zero ( 2h: TBCNT = CMPB: Time-base counter equal to counter-compare B ( 3h: Disable EPWMxSYNCO signal" "0: Time-base counter equal to zero,?,?,?" newline bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select 0h: The period register ( 1h: Load the" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable 0h: Do not load the time-base counter ( 1h: Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0,1,2,3" line.word 0x2 "EPWM_TBSTS" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0h = Reading a 0h indicates the time-base counter never reached its maximum value. Writing a 0h will have no effect. 1h = Reading a 1h on this bit indicates that the time-base counter reached the max value.." "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit 0h = Writing a 0h will have no effect. Reading a 0h indicates no external synchronization event has occurred. 1h = Reading a 1h on this bit indicates that an external synchronization event has occurred.." "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via the 0h = Time-Base Counter is currently counting down 1h =.." "0,1" line.word 0x4 "HRPWM_TBPHSHR" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" hexmask.word.byte 0x4 0.--7. 1. "RESERVED,Reserved" line.word 0x6 "EPWM_TBPHS,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal: [a] If [b] If These bits set time-base counter phase of the selected EPWM relative to the time-base that is.." line.word 0x8 "EPWM_TBCNT" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the.." line.word 0xA "EPWM_TBPRD" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.word 0xE++0x17 line.word 0x0 "EPWM_CMPCTL" hexmask.word.byte 0x0 10.--15. 1. "RESERVED,Reserved" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B ( This bit self clears once a load-strobe occurs. 0h = CMPB shadow FIFO not full yet 1h = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A ( 0h = CMPA shadow FIFO not full yet 1h = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" rbitfld.word 0x0 7. "RESERVED,Reserved" "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for.." "0,1" rbitfld.word 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B ( This bit has no effect in immediate mode ( 0h = Load on 1h = Load on 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A ( This bit has no effect in immediate mode ( 0h = Load on TBCNT = 0h: Time-base counter equal to zero ( 1h = Load on TBCNT = TBPRD: Time-base counter equal to period ( 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" line.word 0x2 "HRPWM_CMPAHR,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation: 1h to 255h." hexmask.word.byte 0x2 0.--7. 1. "RESERVED,Reserved" line.word 0x4 "EPWM_CMPA" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the activeWhen the values are equal the counter-compare module generates a 'Time-Base counter equal to counter compare A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x6 "EPWM_CMPB" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the activeWhen the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x8 "EPWM_AQCTLA" hexmask.word.byte 0x8 12.--15. 1. "RESERVED,Reserved" bitfld.word 0x8 10.--11. "CBD,Action when the Time-Base counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be.." "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output.." "0,1,2,3" line.word 0xA "EPWM_AQCTLB" hexmask.word.byte 0xA 12.--15. 1. "RESERVED,Reserved" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output.." "0,1,2,3" line.word 0xC "EPWM_AQSFRC" hexmask.word.byte 0xC 8.--15. 1. "RESERVED,Reserved" bitfld.word 0xC 6.--7. "RLDCSF" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B 0h = Writing a 0h (zero) has no effect. Always reads back a 0h. This bit is auto cleared once a write to this register is complete that is a forced event is initiated. This is a one-shot forced event. It.." "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked 0h = Does nothing (action disabled) 1h = Clear (low) 2h = Set (high) 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A 0h = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1h = Initiates a single software.." "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 0h = Does nothing (action disabled). 1h = Clear (low). 2h = Set (high). 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" line.word 0xE "EPWM_AQCSFRC" hexmask.word 0xE 4.--15. 1. "RESERVED,Reserved" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0h = Forcing.." "0,1,2,3" line.word 0x10 "EPWM_DBCTL" hexmask.word 0x10 6.--15. 1. "RESERVED,Reserved" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0h = Dead-band generation is.." "0,1,2,3" line.word 0x12 "EPWM_DBRED" hexmask.word.byte 0x12 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count. 10-bit counter." line.word 0x14 "EPWM_DBFED" hexmask.word.byte 0x14 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count. 10-bit counter" line.word 0x16 "EPWM_TZSEL" rbitfld.word 0x16 14.--15. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 13. "OSHT6,Trip-zone 5 (TZ5) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a one-shot trip source.." "0,1" bitfld.word 0x16 12. "OSHT5,Trip-zone 4 (TZ4) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a one-shot trip source.." "0,1" bitfld.word 0x16 11. "OSHT4,Trip-zone 3 (TZ3) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a one-shot trip source.." "0,1" bitfld.word 0x16 10. "OSHT3,Trip-zone 2 (TZ2) Select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a one-shot trip source.." "0,1" bitfld.word 0x16 9. "OSHT2,Trip-zone 1 (TZ1) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a one-shot trip source.." "0,1" newline bitfld.word 0x16 8. "OSHT1,Trip-zone 0 (TZ0) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a one-shot trip source.." "0,1" rbitfld.word 0x16 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 5. "CBC5,Trip-zone 5 (TZ5) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a CBC trip.." "0,1" bitfld.word 0x16 4. "CBC4,Trip-zone 4 (TZ4) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a CBC trip.." "0,1" bitfld.word 0x16 3. "CBC3,Trip-zone 3 (TZ3) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a CBC trip.." "0,1" bitfld.word 0x16 2. "CBC2,Trip-zone 2 (TZ2) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a CBC trip.." "0,1" newline bitfld.word 0x16 1. "CBC1,Trip-zone 1 (TZ1) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a CBC trip.." "0,1" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a CBC trip.." "0,1" group.word 0x28++0x3 line.word 0x0 "EPWM_TZCTL" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxB = High-impedance state) 1h = Force EPWMxB to a high state 2h = Force EPWMxB to a low state.." "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxA = High-impedance state) 1h = Force EPWMxA to a high state 2h = Force EPWMxA to a low state.." "0,1,2,3" line.word 0x2 "EPWM_TZEINT" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation 1h = Enable interrupt generation" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_TZFLG" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0h = No one-shot trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0h = No cycle-by-cycle trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0h = Indicates no interrupt has been generated 1h = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the.." "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_TZCLR" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip (OST) Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0h = Has no effect. Always reads back a 0h 1h = Clears the trip-interrupt flag for this EPWM module ( Note: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the" "0,1" line.word 0x2 "EPWM_TZFRC" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a one-shot trip event and sets the" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a cycle-by-cycle trip event and sets the" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" line.word 0x4 "EPWM_ETSEL" bitfld.word 0x4 15. "SOCB,Enable SOCB pulse when set to 1h." "0,1" bitfld.word 0x4 12.--14. "SOCBSEL,EPWMxSOCB Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" bitfld.word 0x4 11. "SOCA,Enable SOCA pulse when set to 1h." "0,1" bitfld.word 0x4 8.--10. "SOCASEL,EPWMxSOCA Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.word 0x4 3. "INTEN,Enable EPWM Interrupt (EPWMx_INT) Generation 0h: Disable EPWMx_INT generation 1h: Enable EPWMx_INT generation" "0,1" newline bitfld.word 0x4 0.--2. "INTSEL,EPWM Interrupt (EPWMx_INT) Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero. ( 2h: Enable event time-base counter equal to period ( 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is.." "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_ETPS" rbitfld.word 0x6 14.--15. "SOCBCNT,EPWMxSOCB Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 12.--13. "SOCBPRD,EPWMxSOCB Period Select These bits select how many selected event need to occur before an SOCB pulse is generated." "0,1,2,3" rbitfld.word 0x6 10.--11. "SOCACNT,EPWMxSOCA Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 8.--9. "SOCAPRD,EPWMxSOCA Period Select These bits select how many selected event need to occur before an SOCA pulse is generated." "0,1,2,3" hexmask.word.byte 0x6 4.--7. 1. "RESERVED,Reserved" rbitfld.word 0x6 2.--3. "INTCNT,EPWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected 0h: No events have occurred 1h: 1 event has occurred 2h: 2 events have occurred 3h: 3 events have occurred" "0,1,2,3" newline bitfld.word 0x6 0.--1. "INTPRD,EPWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected 0h: Disable the interrupt event counter. No interrupt will be generated and the 1h: Generate an interrupt on the first event INTCNT = 0b01 (first event) 2h: Generate.." "0,1,2,3" rgroup.word 0x36++0x3 line.word 0x0 "EPWM_ETFLG" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,Latched SOCB Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB Note: Unlike the INT flag bit the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 2. "SOCA,Latched SOCA Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA Note: Unlike the INT flag bit the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,Latched EPWM Interrupt (EPWMx_INT) Status Flag 0h: Indicates no event occurred. 1h: Indicates that an EPWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0,1" line.word 0x2 "EPWM_ETCLR" hexmask.word 0x2 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" group.word 0x3A++0x3 line.word 0x0 "EPWM_ETFRC" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,SOCB Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[3] SOCB flag bit" "0,1" bitfld.word 0x0 2. "SOCA,SOCA Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[2] SOCA flag bit" "0,1" rbitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,EPWM Interrupt (EPWMx_INT) Flag Clear Bit 0h: Writing a 0 has no effect. Always reads back a 0h. 1h: Writing 1 clears the" "0,1" line.word 0x2 "EPWM_PCCTL" hexmask.word.byte 0x2 11.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0h = Duty = 1/8 (12.5%) 1h = Duty = 2/8 (25.0%) 2h = Duty = 3/8 (37.5%) 3h = Duty = 4/8 (50.0%) 4h = Duty = 5/8 (62.5%) 5h = Duty = 6/8 (75.0%) 6h = Duty = 7/8 (87.5%) 7h = Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 5.--7. "CHPFREQ,Chopping Clock Frequency 0h = Divide by 1 (no prescale) 1h = Divide by 2 2h = Divide by 3 3h = Divide by 4 4h = Divide by 5 5h = Divide by 6 6h = Divide by 7 7h = Divide by 8" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0h = 1 - SYSCLKOUT/8 wide 1h = 2 - SYSCLKOUT/8 wide 2h = 3 - SYSCLKOUT/8 wide 3h = 4 - SYSCLKOUT/8 wide Fh = 16 - SYSCLKOUT/8 wide" bitfld.word 0x2 0. "CHPEN,PWM-chopping Enable 0h = Disable (bypass) PWM chopping function 1h = Enable chopping function" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_PID,The revision register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data Identifies revision of peripheral." tree.end tree "EHRPWM4_EHRPWM" base ad:0x3048000 group.word 0x40++0x1 line.word 0x0 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension. Otherwise. this location is reserved." hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "PULSESEL,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. The user should select this event to match the selection of the CMPA load mode 0h: Load on CTR = 0. Time-base counter equal to zero (EPWM_TBCNT =.." "0,1" bitfld.word 0x0 2. "DELBUSSEL,Control Mode Bits Selects the register (CMP or TBPHS) that controls the MEP. 0h = Select CMPAHR(8) register controls the edge position. This is duty control mode (default on reset). 1h = Select TBPHSHR(8) register controls the edge position.." "0,1" bitfld.word 0x0 0.--1. "DELMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic. 0h = HRPWM capability is disabled (default on reset) 1h = MEP control of rising edge 2h = MEP control of falling edge 3h = MEP control of both.." "0,1,2,3" tree.end tree "EHRPWM4_EPWM" base ad:0x3040000 group.word 0x0++0xB line.word 0x0 "EPWM_TBCTL" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the EPWM time-base counter during emulation events. 0h: Stop after the next time-base counter increment or decrement 1h: Stop when counter completes a whole cycle 2h: Free run 3h: Free run" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0h: Count down after the synchronization event 1h: Count up after the.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) 0h: /1 (default on reset) 1h: /2 2h: /4 3h: /8 4h: /16 5h: /32 6h: /64 7h: /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV). 0h: /1 1h: /2 (default on reset) 2h: /4 3h: /6 4h: /8 5h: /10 6h: /12 7h: /14" "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse 0h: Writing a 0h has no effect and reads always return a 0h. 1h: Writing a 1h forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the EPWM module. SWFSYNC.." "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal. 0h: EPWMxSYNC 1h: TBCNT = 0: Time-base counter equal to zero ( 2h: TBCNT = CMPB: Time-base counter equal to counter-compare B ( 3h: Disable EPWMxSYNCO signal" "0: Time-base counter equal to zero,?,?,?" newline bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select 0h: The period register ( 1h: Load the" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable 0h: Do not load the time-base counter ( 1h: Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0,1,2,3" line.word 0x2 "EPWM_TBSTS" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0h = Reading a 0h indicates the time-base counter never reached its maximum value. Writing a 0h will have no effect. 1h = Reading a 1h on this bit indicates that the time-base counter reached the max value.." "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit 0h = Writing a 0h will have no effect. Reading a 0h indicates no external synchronization event has occurred. 1h = Reading a 1h on this bit indicates that an external synchronization event has occurred.." "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via the 0h = Time-Base Counter is currently counting down 1h =.." "0,1" line.word 0x4 "HRPWM_TBPHSHR" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" hexmask.word.byte 0x4 0.--7. 1. "RESERVED,Reserved" line.word 0x6 "EPWM_TBPHS,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal: [a] If [b] If These bits set time-base counter phase of the selected EPWM relative to the time-base that is.." line.word 0x8 "EPWM_TBCNT" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the.." line.word 0xA "EPWM_TBPRD" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.word 0xE++0x17 line.word 0x0 "EPWM_CMPCTL" hexmask.word.byte 0x0 10.--15. 1. "RESERVED,Reserved" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B ( This bit self clears once a load-strobe occurs. 0h = CMPB shadow FIFO not full yet 1h = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A ( 0h = CMPA shadow FIFO not full yet 1h = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" rbitfld.word 0x0 7. "RESERVED,Reserved" "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for.." "0,1" rbitfld.word 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B ( This bit has no effect in immediate mode ( 0h = Load on 1h = Load on 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A ( This bit has no effect in immediate mode ( 0h = Load on TBCNT = 0h: Time-base counter equal to zero ( 1h = Load on TBCNT = TBPRD: Time-base counter equal to period ( 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" line.word 0x2 "HRPWM_CMPAHR,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation: 1h to 255h." hexmask.word.byte 0x2 0.--7. 1. "RESERVED,Reserved" line.word 0x4 "EPWM_CMPA" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the activeWhen the values are equal the counter-compare module generates a 'Time-Base counter equal to counter compare A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x6 "EPWM_CMPB" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the activeWhen the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x8 "EPWM_AQCTLA" hexmask.word.byte 0x8 12.--15. 1. "RESERVED,Reserved" bitfld.word 0x8 10.--11. "CBD,Action when the Time-Base counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be.." "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output.." "0,1,2,3" line.word 0xA "EPWM_AQCTLB" hexmask.word.byte 0xA 12.--15. 1. "RESERVED,Reserved" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output.." "0,1,2,3" line.word 0xC "EPWM_AQSFRC" hexmask.word.byte 0xC 8.--15. 1. "RESERVED,Reserved" bitfld.word 0xC 6.--7. "RLDCSF" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B 0h = Writing a 0h (zero) has no effect. Always reads back a 0h. This bit is auto cleared once a write to this register is complete that is a forced event is initiated. This is a one-shot forced event. It.." "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked 0h = Does nothing (action disabled) 1h = Clear (low) 2h = Set (high) 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A 0h = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1h = Initiates a single software.." "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 0h = Does nothing (action disabled). 1h = Clear (low). 2h = Set (high). 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" line.word 0xE "EPWM_AQCSFRC" hexmask.word 0xE 4.--15. 1. "RESERVED,Reserved" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0h = Forcing.." "0,1,2,3" line.word 0x10 "EPWM_DBCTL" hexmask.word 0x10 6.--15. 1. "RESERVED,Reserved" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0h = Dead-band generation is.." "0,1,2,3" line.word 0x12 "EPWM_DBRED" hexmask.word.byte 0x12 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count. 10-bit counter." line.word 0x14 "EPWM_DBFED" hexmask.word.byte 0x14 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count. 10-bit counter" line.word 0x16 "EPWM_TZSEL" rbitfld.word 0x16 14.--15. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 13. "OSHT6,Trip-zone 5 (TZ5) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a one-shot trip source.." "0,1" bitfld.word 0x16 12. "OSHT5,Trip-zone 4 (TZ4) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a one-shot trip source.." "0,1" bitfld.word 0x16 11. "OSHT4,Trip-zone 3 (TZ3) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a one-shot trip source.." "0,1" bitfld.word 0x16 10. "OSHT3,Trip-zone 2 (TZ2) Select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a one-shot trip source.." "0,1" bitfld.word 0x16 9. "OSHT2,Trip-zone 1 (TZ1) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a one-shot trip source.." "0,1" newline bitfld.word 0x16 8. "OSHT1,Trip-zone 0 (TZ0) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a one-shot trip source.." "0,1" rbitfld.word 0x16 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 5. "CBC5,Trip-zone 5 (TZ5) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a CBC trip.." "0,1" bitfld.word 0x16 4. "CBC4,Trip-zone 4 (TZ4) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a CBC trip.." "0,1" bitfld.word 0x16 3. "CBC3,Trip-zone 3 (TZ3) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a CBC trip.." "0,1" bitfld.word 0x16 2. "CBC2,Trip-zone 2 (TZ2) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a CBC trip.." "0,1" newline bitfld.word 0x16 1. "CBC1,Trip-zone 1 (TZ1) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a CBC trip.." "0,1" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a CBC trip.." "0,1" group.word 0x28++0x3 line.word 0x0 "EPWM_TZCTL" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxB = High-impedance state) 1h = Force EPWMxB to a high state 2h = Force EPWMxB to a low state.." "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxA = High-impedance state) 1h = Force EPWMxA to a high state 2h = Force EPWMxA to a low state.." "0,1,2,3" line.word 0x2 "EPWM_TZEINT" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation 1h = Enable interrupt generation" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_TZFLG" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0h = No one-shot trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0h = No cycle-by-cycle trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0h = Indicates no interrupt has been generated 1h = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the.." "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_TZCLR" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip (OST) Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0h = Has no effect. Always reads back a 0h 1h = Clears the trip-interrupt flag for this EPWM module ( Note: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the" "0,1" line.word 0x2 "EPWM_TZFRC" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a one-shot trip event and sets the" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a cycle-by-cycle trip event and sets the" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" line.word 0x4 "EPWM_ETSEL" bitfld.word 0x4 15. "SOCB,Enable SOCB pulse when set to 1h." "0,1" bitfld.word 0x4 12.--14. "SOCBSEL,EPWMxSOCB Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" bitfld.word 0x4 11. "SOCA,Enable SOCA pulse when set to 1h." "0,1" bitfld.word 0x4 8.--10. "SOCASEL,EPWMxSOCA Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.word 0x4 3. "INTEN,Enable EPWM Interrupt (EPWMx_INT) Generation 0h: Disable EPWMx_INT generation 1h: Enable EPWMx_INT generation" "0,1" newline bitfld.word 0x4 0.--2. "INTSEL,EPWM Interrupt (EPWMx_INT) Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero. ( 2h: Enable event time-base counter equal to period ( 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is.." "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_ETPS" rbitfld.word 0x6 14.--15. "SOCBCNT,EPWMxSOCB Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 12.--13. "SOCBPRD,EPWMxSOCB Period Select These bits select how many selected event need to occur before an SOCB pulse is generated." "0,1,2,3" rbitfld.word 0x6 10.--11. "SOCACNT,EPWMxSOCA Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 8.--9. "SOCAPRD,EPWMxSOCA Period Select These bits select how many selected event need to occur before an SOCA pulse is generated." "0,1,2,3" hexmask.word.byte 0x6 4.--7. 1. "RESERVED,Reserved" rbitfld.word 0x6 2.--3. "INTCNT,EPWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected 0h: No events have occurred 1h: 1 event has occurred 2h: 2 events have occurred 3h: 3 events have occurred" "0,1,2,3" newline bitfld.word 0x6 0.--1. "INTPRD,EPWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected 0h: Disable the interrupt event counter. No interrupt will be generated and the 1h: Generate an interrupt on the first event INTCNT = 0b01 (first event) 2h: Generate.." "0,1,2,3" rgroup.word 0x36++0x3 line.word 0x0 "EPWM_ETFLG" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,Latched SOCB Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB Note: Unlike the INT flag bit the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 2. "SOCA,Latched SOCA Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA Note: Unlike the INT flag bit the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,Latched EPWM Interrupt (EPWMx_INT) Status Flag 0h: Indicates no event occurred. 1h: Indicates that an EPWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0,1" line.word 0x2 "EPWM_ETCLR" hexmask.word 0x2 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" group.word 0x3A++0x3 line.word 0x0 "EPWM_ETFRC" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,SOCB Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[3] SOCB flag bit" "0,1" bitfld.word 0x0 2. "SOCA,SOCA Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[2] SOCA flag bit" "0,1" rbitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,EPWM Interrupt (EPWMx_INT) Flag Clear Bit 0h: Writing a 0 has no effect. Always reads back a 0h. 1h: Writing 1 clears the" "0,1" line.word 0x2 "EPWM_PCCTL" hexmask.word.byte 0x2 11.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0h = Duty = 1/8 (12.5%) 1h = Duty = 2/8 (25.0%) 2h = Duty = 3/8 (37.5%) 3h = Duty = 4/8 (50.0%) 4h = Duty = 5/8 (62.5%) 5h = Duty = 6/8 (75.0%) 6h = Duty = 7/8 (87.5%) 7h = Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 5.--7. "CHPFREQ,Chopping Clock Frequency 0h = Divide by 1 (no prescale) 1h = Divide by 2 2h = Divide by 3 3h = Divide by 4 4h = Divide by 5 5h = Divide by 6 6h = Divide by 7 7h = Divide by 8" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0h = 1 - SYSCLKOUT/8 wide 1h = 2 - SYSCLKOUT/8 wide 2h = 3 - SYSCLKOUT/8 wide 3h = 4 - SYSCLKOUT/8 wide Fh = 16 - SYSCLKOUT/8 wide" bitfld.word 0x2 0. "CHPEN,PWM-chopping Enable 0h = Disable (bypass) PWM chopping function 1h = Enable chopping function" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_PID,The revision register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data Identifies revision of peripheral." tree.end tree "EHRPWM5_EHRPWM" base ad:0x3058000 group.word 0x40++0x1 line.word 0x0 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension. Otherwise. this location is reserved." hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "PULSESEL,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. The user should select this event to match the selection of the CMPA load mode 0h: Load on CTR = 0. Time-base counter equal to zero (EPWM_TBCNT =.." "0,1" bitfld.word 0x0 2. "DELBUSSEL,Control Mode Bits Selects the register (CMP or TBPHS) that controls the MEP. 0h = Select CMPAHR(8) register controls the edge position. This is duty control mode (default on reset). 1h = Select TBPHSHR(8) register controls the edge position.." "0,1" bitfld.word 0x0 0.--1. "DELMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic. 0h = HRPWM capability is disabled (default on reset) 1h = MEP control of rising edge 2h = MEP control of falling edge 3h = MEP control of both.." "0,1,2,3" tree.end tree "EHRPWM5_EPWM" base ad:0x3050000 group.word 0x0++0xB line.word 0x0 "EPWM_TBCTL" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the EPWM time-base counter during emulation events. 0h: Stop after the next time-base counter increment or decrement 1h: Stop when counter completes a whole cycle 2h: Free run 3h: Free run" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0h: Count down after the synchronization event 1h: Count up after the.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) 0h: /1 (default on reset) 1h: /2 2h: /4 3h: /8 4h: /16 5h: /32 6h: /64 7h: /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV). 0h: /1 1h: /2 (default on reset) 2h: /4 3h: /6 4h: /8 5h: /10 6h: /12 7h: /14" "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse 0h: Writing a 0h has no effect and reads always return a 0h. 1h: Writing a 1h forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the EPWM module. SWFSYNC.." "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal. 0h: EPWMxSYNC 1h: TBCNT = 0: Time-base counter equal to zero ( 2h: TBCNT = CMPB: Time-base counter equal to counter-compare B ( 3h: Disable EPWMxSYNCO signal" "0: Time-base counter equal to zero,?,?,?" newline bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select 0h: The period register ( 1h: Load the" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable 0h: Do not load the time-base counter ( 1h: Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0,1,2,3" line.word 0x2 "EPWM_TBSTS" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0h = Reading a 0h indicates the time-base counter never reached its maximum value. Writing a 0h will have no effect. 1h = Reading a 1h on this bit indicates that the time-base counter reached the max value.." "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit 0h = Writing a 0h will have no effect. Reading a 0h indicates no external synchronization event has occurred. 1h = Reading a 1h on this bit indicates that an external synchronization event has occurred.." "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via the 0h = Time-Base Counter is currently counting down 1h =.." "0,1" line.word 0x4 "HRPWM_TBPHSHR" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" hexmask.word.byte 0x4 0.--7. 1. "RESERVED,Reserved" line.word 0x6 "EPWM_TBPHS,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal: [a] If [b] If These bits set time-base counter phase of the selected EPWM relative to the time-base that is.." line.word 0x8 "EPWM_TBCNT" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the.." line.word 0xA "EPWM_TBPRD" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.word 0xE++0x17 line.word 0x0 "EPWM_CMPCTL" hexmask.word.byte 0x0 10.--15. 1. "RESERVED,Reserved" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B ( This bit self clears once a load-strobe occurs. 0h = CMPB shadow FIFO not full yet 1h = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A ( 0h = CMPA shadow FIFO not full yet 1h = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" rbitfld.word 0x0 7. "RESERVED,Reserved" "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for.." "0,1" rbitfld.word 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A ( 0h = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1h = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B ( This bit has no effect in immediate mode ( 0h = Load on 1h = Load on 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A ( This bit has no effect in immediate mode ( 0h = Load on TBCNT = 0h: Time-base counter equal to zero ( 1h = Load on TBCNT = TBPRD: Time-base counter equal to period ( 2h = Load on either 3h = Freeze (no loads possible)" "0,1,2,3" line.word 0x2 "HRPWM_CMPAHR,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation: 1h to 255h." hexmask.word.byte 0x2 0.--7. 1. "RESERVED,Reserved" line.word 0x4 "EPWM_CMPA" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the activeWhen the values are equal the counter-compare module generates a 'Time-Base counter equal to counter compare A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x6 "EPWM_CMPB" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the activeWhen the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more.." line.word 0x8 "EPWM_AQCTLA" hexmask.word.byte 0x8 12.--15. 1. "RESERVED,Reserved" bitfld.word 0x8 10.--11. "CBD,Action when the Time-Base counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be.." "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output high 3h = Toggle EPWMxA output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxA output low 2h = Set: force EPWMxA output.." "0,1,2,3" line.word 0xA "EPWM_AQCTLB" hexmask.word.byte 0xA 12.--15. 1. "RESERVED,Reserved" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output high 3h = Toggle EPWMxB output: low output signal will be forced high and a high signal will be forced low" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force.." "0,1,2,3" newline bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0h = Do nothing (action disabled) 1h = Clear: force EPWMxB output low 2h = Set: force EPWMxB output.." "0,1,2,3" line.word 0xC "EPWM_AQSFRC" hexmask.word.byte 0xC 8.--15. 1. "RESERVED,Reserved" bitfld.word 0xC 6.--7. "RLDCSF" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B 0h = Writing a 0h (zero) has no effect. Always reads back a 0h. This bit is auto cleared once a write to this register is complete that is a forced event is initiated. This is a one-shot forced event. It.." "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked 0h = Does nothing (action disabled) 1h = Clear (low) 2h = Set (high) 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A 0h = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1h = Initiates a single software.." "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 0h = Does nothing (action disabled). 1h = Clear (low). 2h = Set (high). 3h = Toggle (Low -&gt; High High -&gt; Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" line.word 0xE "EPWM_AQCSFRC" hexmask.word 0xE 4.--15. 1. "RESERVED,Reserved" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0h = Forcing.." "0,1,2,3" line.word 0x10 "EPWM_DBCTL" hexmask.word 0x10 6.--15. 1. "RESERVED,Reserved" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0h = Dead-band generation is.." "0,1,2,3" line.word 0x12 "EPWM_DBRED" hexmask.word.byte 0x12 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count. 10-bit counter." line.word 0x14 "EPWM_DBFED" hexmask.word.byte 0x14 10.--15. 1. "RESERVED,Reserved" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count. 10-bit counter" line.word 0x16 "EPWM_TZSEL" rbitfld.word 0x16 14.--15. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 13. "OSHT6,Trip-zone 5 (TZ5) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a one-shot trip source.." "0,1" bitfld.word 0x16 12. "OSHT5,Trip-zone 4 (TZ4) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a one-shot trip source.." "0,1" bitfld.word 0x16 11. "OSHT4,Trip-zone 3 (TZ3) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a one-shot trip source.." "0,1" bitfld.word 0x16 10. "OSHT3,Trip-zone 2 (TZ2) Select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a one-shot trip source.." "0,1" bitfld.word 0x16 9. "OSHT2,Trip-zone 1 (TZ1) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a one-shot trip source.." "0,1" newline bitfld.word 0x16 8. "OSHT1,Trip-zone 0 (TZ0) select One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low a one-shot trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a one-shot trip source.." "0,1" rbitfld.word 0x16 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x16 5. "CBC5,Trip-zone 5 (TZ5) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ5 as a CBC trip.." "0,1" bitfld.word 0x16 4. "CBC4,Trip-zone 4 (TZ4) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ4 as a CBC trip.." "0,1" bitfld.word 0x16 3. "CBC3,Trip-zone 3 (TZ3) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ3 as a CBC trip.." "0,1" bitfld.word 0x16 2. "CBC2,Trip-zone 2 (TZ2) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ2 as a CBC trip.." "0,1" newline bitfld.word 0x16 1. "CBC1,Trip-zone 1 (TZ1) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ1 as a CBC trip.." "0,1" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low a cycle-by-cycle trip event occurs for this EPWM module. When the event occurs the action defined in the 0h: Disable TZ0 as a CBC trip.." "0,1" group.word 0x28++0x3 line.word 0x0 "EPWM_TZCTL" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxB = High-impedance state) 1h = Force EPWMxB to a high state 2h = Force EPWMxB to a low state.." "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0h = High impedance (EPWMxA = High-impedance state) 1h = Force EPWMxA to a high state 2h = Force EPWMxA to a low state.." "0,1,2,3" line.word 0x2 "EPWM_TZEINT" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable 0h = Disable one-shot interrupt generation 1h = Enable Interrupt generation" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0h = Disable cycle-by-cycle interrupt generation 1h = Enable interrupt generation" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_TZFLG" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0h = No one-shot trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0h = No cycle-by-cycle trip event has occurred 1h = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0h = Indicates no interrupt has been generated 1h = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the.." "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_TZCLR" hexmask.word 0x0 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip (OST) Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0h = Has no effect. Always reads back a 0h 1h = Clears this Trip (set) condition" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0h = Has no effect. Always reads back a 0h 1h = Clears the trip-interrupt flag for this EPWM module ( Note: No further EPWMxTZINT interrupts will be generated until the flag is cleared. If the" "0,1" line.word 0x2 "EPWM_TZFRC" hexmask.word 0x2 3.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a one-shot trip event and sets the" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0h = Writing of 0h is ignored. Always reads back a 0h. 1h = Forces a cycle-by-cycle trip event and sets the" "0,1" rbitfld.word 0x2 0. "RESERVED,Reserved" "0,1" line.word 0x4 "EPWM_ETSEL" bitfld.word 0x4 15. "SOCB,Enable SOCB pulse when set to 1h." "0,1" bitfld.word 0x4 12.--14. "SOCBSEL,EPWMxSOCB Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" bitfld.word 0x4 11. "SOCA,Enable SOCA pulse when set to 1h." "0,1" bitfld.word 0x4 8.--10. "SOCASEL,EPWMxSOCA Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero (CNT_zero event) 2h: Enable event time-base counter equal to period (PRD_eq event) 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.word 0x4 3. "INTEN,Enable EPWM Interrupt (EPWMx_INT) Generation 0h: Disable EPWMx_INT generation 1h: Enable EPWMx_INT generation" "0,1" newline bitfld.word 0x4 0.--2. "INTSEL,EPWM Interrupt (EPWMx_INT) Selection Options 0h: Reserved 1h: Enable event time-base counter equal to zero. ( 2h: Enable event time-base counter equal to period ( 3h: Reserved 4h: Enable event time-base counter equal to CMPA when the timer is.." "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_ETPS" rbitfld.word 0x6 14.--15. "SOCBCNT,EPWMxSOCB Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 12.--13. "SOCBPRD,EPWMxSOCB Period Select These bits select how many selected event need to occur before an SOCB pulse is generated." "0,1,2,3" rbitfld.word 0x6 10.--11. "SOCACNT,EPWMxSOCA Counter Register These bits indicate how many selected events have occurred." "0,1,2,3" bitfld.word 0x6 8.--9. "SOCAPRD,EPWMxSOCA Period Select These bits select how many selected event need to occur before an SOCA pulse is generated." "0,1,2,3" hexmask.word.byte 0x6 4.--7. 1. "RESERVED,Reserved" rbitfld.word 0x6 2.--3. "INTCNT,EPWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected 0h: No events have occurred 1h: 1 event has occurred 2h: 2 events have occurred 3h: 3 events have occurred" "0,1,2,3" newline bitfld.word 0x6 0.--1. "INTPRD,EPWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected 0h: Disable the interrupt event counter. No interrupt will be generated and the 1h: Generate an interrupt on the first event INTCNT = 0b01 (first event) 2h: Generate.." "0,1,2,3" rgroup.word 0x36++0x3 line.word 0x0 "EPWM_ETFLG" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,Latched SOCB Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCB Note: Unlike the INT flag bit the EPWMxSOCB output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 2. "SOCA,Latched SOCA Flag Bit Status 0h: Indicates no event occurred 1h: Indicates that a start of conversion pulse was generated on EPWMxSOCA Note: Unlike the INT flag bit the EPWMxSOCA output will continue to pulse even if the flag bit is set." "0,1" bitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,Latched EPWM Interrupt (EPWMx_INT) Status Flag 0h: Indicates no event occurred. 1h: Indicates that an EPWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0,1" line.word 0x2 "EPWM_ETCLR" hexmask.word 0x2 1.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" group.word 0x3A++0x3 line.word 0x0 "EPWM_ETFRC" hexmask.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 3. "SOCB,SOCB Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[3] SOCB flag bit" "0,1" bitfld.word 0x0 2. "SOCA,SOCA Flag Clear Bit 0h: Writing a 0h has no effect. Always reads back a 0h. 1h: Writing a 1h clears the EPWM_ETFLG[2] SOCA flag bit" "0,1" rbitfld.word 0x0 1. "RESERVED,Reserved" "0,1" bitfld.word 0x0 0. "INT,EPWM Interrupt (EPWMx_INT) Flag Clear Bit 0h: Writing a 0 has no effect. Always reads back a 0h. 1h: Writing 1 clears the" "0,1" line.word 0x2 "EPWM_PCCTL" hexmask.word.byte 0x2 11.--15. 1. "RESERVED,Reserved" bitfld.word 0x2 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0h = Duty = 1/8 (12.5%) 1h = Duty = 2/8 (25.0%) 2h = Duty = 3/8 (37.5%) 3h = Duty = 4/8 (50.0%) 4h = Duty = 5/8 (62.5%) 5h = Duty = 6/8 (75.0%) 6h = Duty = 7/8 (87.5%) 7h = Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 5.--7. "CHPFREQ,Chopping Clock Frequency 0h = Divide by 1 (no prescale) 1h = Divide by 2 2h = Divide by 3 3h = Divide by 4 4h = Divide by 5 5h = Divide by 6 6h = Divide by 7 7h = Divide by 8" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0h = 1 - SYSCLKOUT/8 wide 1h = 2 - SYSCLKOUT/8 wide 2h = 3 - SYSCLKOUT/8 wide 3h = 4 - SYSCLKOUT/8 wide Fh = 16 - SYSCLKOUT/8 wide" bitfld.word 0x2 0. "CHPEN,PWM-chopping Enable 0h = Disable (bypass) PWM chopping function 1h = Enable chopping function" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_PID,The revision register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data Identifies revision of peripheral." tree.end tree.end tree "ELM0" base ad:0x0 rgroup.long 0x5380000++0x3 line.long 0x0 "ELM_REVISION,This register contains the IP revision code. (A write to or reset of this register has no effect.)" hexmask.long 0x0 0.--31. 1. "REVISION,TI internal data. Identifies revision of peripheral." group.long 0x5380010++0x3 line.long 0x0 "ELM_SYSCONFIG,This register controls ELM local power management and software reset. Some of the ELM features described in this section may not be supported on this family of devices. For more information. see . ELM Not Supported Features." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "CLOCKACTIVITYOCP,ELM_FICLK activity when module is in IDLE mode 0h (R/W) = ELM_FICLK can be switched off. 1h (R/W) = ELM_FICLK is maintained." "0,1" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Slave interface power management (clock stop req/ack control) 0h (R/W) = Force-idle. A clock stop request is acknowledged unconditionally and immediately 1h (R/W) = No-idle. A clock stop request is never acknowledged. 2h (R/W) = Smart-idle. The.." "0,1,2,3" newline rbitfld.long 0x0 2. "RESERVED,Reserved" "0,1" bitfld.long 0x0 1. "SOFTRESET,Module software reset 0h (R/W) = Normal mode 1h (R/W) = Start soft reset sequence." "0,1" bitfld.long 0x0 0. "AUTOGATING,Internal ELM_FICLK gating strategy 0h (R/W) = ELM_FICLK is free-running. 1h (R/W) = Automatic internal ELM_FICLK gating strategy is applied based on the Interconnect interface activity." "0,1" rgroup.long 0x5380014++0x3 line.long 0x0 "ELM_SYSSTATUS,Internal reset monitoring Undefined since: From hardware perspective. the reset state is 0. From software user perspective. when the accessible module is 1." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Reset is ongoing. 1h (R) = Reset is done (completed)." "0,1" group.long 0x5380018++0xB line.long 0x0 "ELM_IRQSTATUS,Interrupt status. This register doubles as a status register for the error-location processes." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "PAGE_VALID,Error-location status for a full page based on the mask definition" "0,1" bitfld.long 0x0 7. "LOC_VALID_7,Error-location status for syndrome polynomial 7" "0,1" bitfld.long 0x0 6. "LOC_VALID_6,Error-location status for syndrome polynomial 6" "0,1" newline bitfld.long 0x0 5. "LOC_VALID_5,Error-location status for syndrome polynomial 5" "0,1" bitfld.long 0x0 4. "LOC_VALID_4,Error-location status for syndrome polynomial 4" "0,1" bitfld.long 0x0 3. "LOC_VALID_3,Error-location status for syndrome polynomial 3" "0,1" bitfld.long 0x0 2. "LOC_VALID_2,Error-location status for syndrome polynomial 2" "0,1" newline bitfld.long 0x0 1. "LOC_VALID_1,Error-location status for syndrome polynomial 1" "0,1" bitfld.long 0x0 0. "LOC_VALID_0,Error-location status for syndrome polynomial 0" "0,1" line.long 0x4 "ELM_IRQENABLE,Interrupt enable." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "PAGE_MASK,Page interrupt mask bit" "0,1" bitfld.long 0x4 7. "LOCATION_MASK_7,Error-location interrupt mask bit for syndrome polynomial 7" "0,1" bitfld.long 0x4 6. "LOCATION_MASK_6,Error-location interrupt mask bit for syndrome polynomial 6" "0,1" newline bitfld.long 0x4 5. "LOCATION_MASK_5,Error-location interrupt mask bit for syndrome polynomial 5" "0,1" bitfld.long 0x4 4. "LOCATION_MASK_4,Error-location interrupt mask bit for syndrome polynomial 4" "0,1" bitfld.long 0x4 3. "LOCATION_MASK_3,Error-location interrupt mask bit for syndrome polynomial 3" "0,1" bitfld.long 0x4 2. "LOCATION_MASK_2,Error-location interrupt mask bit for syndrome polynomial 2" "0,1" newline bitfld.long 0x4 1. "LOCATION_MASK_1,Error-location interrupt mask bit for syndrome polynomial 1" "0,1" bitfld.long 0x4 0. "LOCATION_MASK_0,Error-location interrupt mask bit for syndrome polynomial 0" "0,1" line.long 0x8 "ELM_LOCATION_CONFIG,ECC algorithm parameters." hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error-location engine is used in number of nibbles (4-bit entities)" hexmask.long.word 0x8 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--1. "ECC_BCH_LEVEL,Error correction level" "0,1,2,3" group.long 0x5380080++0x3 line.long 0x0 "ELM_PAGE_CTRL,Page definition." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode. Must be 0 in continuous mode." "0,1" newline bitfld.long 0x0 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode. Must be 0 in continuous mode." "0,1" newline bitfld.long 0x0 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode. Must be 0 in continuous mode." "0,1" group.long 0x5380400++0x1B line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i,Input syndrome polynomial bits 0 to 31. Offset = 400h + (i * 40h). where: i = 0 to 7" hexmask.long 0x0 0.--31. 1. "SYNDROME_0,Syndrome bits 0 to 31" line.long 0x4 "ELM_SYNDROME_FRAGMENT_1_i,Input syndrome polynomial bits 32 to 63. Offset = 404h + (i * 40h). where: i = 0 to 7" hexmask.long 0x4 0.--31. 1. "SYNDROME_1,Syndrome bits 32 to 63" line.long 0x8 "ELM_SYNDROME_FRAGMENT_2_i,Input syndrome polynomial bits 64 to 95. Offset = 408h + (i * 40h). where: i = 0 to 7" hexmask.long 0x8 0.--31. 1. "SYNDROME_2,Syndrome bits 64 to 95" line.long 0xC "ELM_SYNDROME_FRAGMENT_3_i,Input syndrome polynomial bits 96 to 127. Offset = 40Ch + (i * 40h). where: i = 0 to 7" hexmask.long 0xC 0.--31. 1. "SYNDROME_3,Syndrome bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i,Input syndrome polynomial bits 128 to 159. Offset = 410h + (i * 40h). where: i = 0 to 7" hexmask.long 0x10 0.--31. 1. "SYNDROME_4,Syndrome bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i,Input syndrome polynomial bits 160 to 191. Offset = 414h + (i * 40h). where: i = 0 to 7" hexmask.long 0x14 0.--31. 1. "SYNDROME_5,Syndrome bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i,Input syndrome polynomial bits 192 to 207. Offset = 418h + (i * 40h). where: i = 0 to 7" hexmask.long.word 0x18 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "0,1" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" rgroup.long 0x5380800++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i,Exit status for the syndrome polynomial processing. Offset = 800h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "ECC_CORRECTABLE,Error-location process exit status" "0,1" bitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "ECC_NB_ERRORS,Number of errors detected and located" rgroup.long 0x5380880++0x3F line.long 0x0 "ELM_ERROR_LOCATION_0_i,Error-location register 0. Offset = 880h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x4 "ELM_ERROR_LOCATION_1_i,Error-location register 1. Offset = 884h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x8 "ELM_ERROR_LOCATION_2_i,Error-location register 2. Offset = 888h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x8 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0xC "ELM_ERROR_LOCATION_3_i,Error-location register 3. Offset = 88Ch + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_i,Error-location register 4. Offset = 890h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x10 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_i,Error-location register 5. Offset = 894h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x14 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_i,Error-location register 6. Offset = 898h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_7_i,Error-location register 7. Offset = 89Ch + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_i,Error-location register 8. Offset = 8A0h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x20 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_i,Error-location register 9. Offset = 8A4h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_i,Error-location register 10. Offset = 8A8h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x2C "ELM_ERROR_LOCATION_11_i,Error-location register 11. Offset = 8ACh + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_i,Error-location register 12. Offset = 8B0h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_i,Error-location register 13. Offset = 8B4h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x34 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_i,Error-location register 14. Offset = 8B8h + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x38 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x38 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x3C "ELM_ERROR_LOCATION_15_i,Error-location register 15. Offset = 8BCh + (i * 100h). where: i = 0 to 7" hexmask.long.tbyte 0x3C 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x3C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" tree.end tree "EQEP" base ad:0x0 tree "EQEP0_REG" base ad:0x3200000 group.long 0x0++0xF line.long 0x0 "EQEP_QPOSCNT,QEP Position Counter register" hexmask.long 0x0 0.--31. 1. "POSCNT,This 32-bit Position Counter register counts up/down on every QEP pulse based on direction input." line.long 0x4 "EQEP_QPOSINIT,Position Counter Initialization register" hexmask.long 0x4 0.--31. 1. "INITPOS,This register contains the position value to be used to initialize the Position Counter based on external strobe or Index event." line.long 0x8 "EQEP_QPOSMAX,Maximum Position Count register" hexmask.long 0x8 0.--31. 1. "MAXPOS,This register contains the maximum Position Counter value for error checking in index reset mode or to reset the Position Counter based on the maximum count value." line.long 0xC "EQEP_QPOSCMP,Position Compare register" hexmask.long 0xC 0.--31. 1. "POSCMP,Position compare value in this register is compared with the Position Counter (" rgroup.long 0x10++0xB line.long 0x0 "EQEP_QPOSILAT,Index Position Latch register" hexmask.long 0x0 0.--31. 1. "IPOSLAT,Position Counter value can be latched into this register on index event as defined by the" line.long 0x4 "EQEP_QPOSSLAT,Strobe Position Latch register" hexmask.long 0x4 0.--31. 1. "SPOSLAT,Position Counter value can be latched into this register on strobe event as defined by the" line.long 0x8 "EQEP_QPOSLAT,QEP Position Counter Latch register" hexmask.long 0x8 0.--31. 1. "POSLAT,Position Counter value can be latched into this register on unit time out event." group.long 0x1C++0x23 line.long 0x0 "EQEP_QUTMR,QEP Unit Timer register" hexmask.long 0x0 0.--31. 1. "UNITTMR,This register acts as time base for unit time event generation." line.long 0x4 "EQEP_QUPRD,QEP Unit Period register" hexmask.long 0x4 0.--31. 1. "UNITPRD,This register contains the period count for unit timer to generate periodic unit time events to latch the EQEP position information at periodic interval and optionally to generate interrupt." line.long 0x8 "EQEP_QWD_TMR_PRD,QEP Watchdog Timer and Period register" hexmask.long.word 0x8 16.--31. 1. "QWDPRD,This field contains the time-out count for the QEP peripheral watch dog timer." hexmask.long.word 0x8 0.--15. 1. "QWDTMR,This field acts as time base for watch dog to detect stalls." line.long 0xC "EQEP_QDEC_QEP_CTL,Quadrature Decoder and QEP Control register" bitfld.long 0xC 30.--31. "FREE_SOFT,POSCNT Behavior:" "0,1,2,3" bitfld.long 0xC 28.--29. "PCRM,Position Counter Reset Mode:" "0,1,2,3" bitfld.long 0xC 26.--27. "SEI,Strobe Event Initialization of Position Counter:" "0,1,2,3" bitfld.long 0xC 24.--25. "IEI,Index Event Initialization of Position Counter:" "0,1,2,3" bitfld.long 0xC 23. "SWI,Software Initialization of Position Counter:" "0,1" bitfld.long 0xC 22. "SEL,Strobe Event Latch of Position Counter:" "0,1" bitfld.long 0xC 20.--21. "IEL,Index Event Latch of Position Counter (Software Index Marker):" "0,1,2,3" newline bitfld.long 0xC 19. "QPEN,Quadrature Position Counter Enable/Software Reset:" "0,1" bitfld.long 0xC 18. "QCLM,EQEP Capture Latch Mode:" "0,1" bitfld.long 0xC 17. "UTE,QEP Unit Timer Enable:" "0,1" bitfld.long 0xC 16. "WDE,QEP Watchdog Enable:" "0,1" bitfld.long 0xC 14.--15. "QSRC,Position Counter Source selection:" "0,1,2,3" bitfld.long 0xC 13. "SOEN,Enable Position Compare Sync Output:" "0,1" bitfld.long 0xC 12. "SPSEL,Sync Output Pin Selection:" "0,1" newline bitfld.long 0xC 11. "XCR,External Clock Rate:" "0,1" bitfld.long 0xC 10. "SWAP,CLK/DIR Signal Source for Position Counter:" "0,1" bitfld.long 0xC 9. "IGATE,Index Pulse Gating Option:" "0,1" bitfld.long 0xC 8. "QAP,QEPA Input Polarity:" "0,1" bitfld.long 0xC 7. "QBP,QEPB Input Polarity:" "0,1" bitfld.long 0xC 6. "QIP,QEPI Input Polarity:" "0,1" bitfld.long 0xC 5. "QSP,QEPS Input Polarity:" "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "RESERVED,Reserved" line.long 0x10 "EQEP_QCAP_QPOS_CTL,QEP Capture and Position Compare Control register" bitfld.long 0x10 31. "PCSHDW,Position-Compare Shadow Enable:" "0,1" bitfld.long 0x10 30. "PCLOAD,Position Compare Shadow Load Mode:" "0,1" bitfld.long 0x10 29. "PCPOL,Polarity of Sync Output:" "0,1" bitfld.long 0x10 28. "PCE,Position Compare Enable/Disable:" "0,1" hexmask.long.word 0x10 16.--27. 1. "PCSPW,Select Pulse Width Period in EQEP_FICLK Cycles:" bitfld.long 0x10 15. "CEN,Enable EQEP Capture:" "0,1" hexmask.long.byte 0x10 7.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x10 4.--6. "CCPS,EQEP Capture Timer Clock Prescalar:" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--3. 1. "UPPS,Unit Position Event Prescalar:" line.long 0x14 "EQEP_QINT_EN_FLG,QEP Interrupt Control and Flag register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 27. "UTOI_FLG,Unit Time Out Interrupt Flag:" "0,1" rbitfld.long 0x14 26. "IELI_FLG,Index Event Latch Interrupt Flag:" "0,1" rbitfld.long 0x14 25. "SELI_FLG,Strobe Event Latch Interrupt Flag:" "0,1" rbitfld.long 0x14 24. "PCMI_FLG,EQEP Compare Match Event Interrupt Flag:" "0,1" rbitfld.long 0x14 23. "PCRI_FLG,Position Compare Ready Interrupt Flag:" "0,1" rbitfld.long 0x14 22. "PCOI_FLG,Position Counter Overflow Interrupt Flag:" "0,1" newline rbitfld.long 0x14 21. "PCUI_FLG,Position Counter Underflow Interrupt Flag:" "0,1" rbitfld.long 0x14 20. "WTOI_FLG,Watchdog Timeout Interrupt Flag:" "0,1" rbitfld.long 0x14 19. "QDCI_FLG,Quadrature Direction Change Interrupt Flag:" "0,1" rbitfld.long 0x14 18. "QPEI_FLG,Quadrature Phase Error Interrupt Flag:" "0,1" rbitfld.long 0x14 17. "PCEI_FLG,Position Counter Error Interrupt Flag:" "0,1" rbitfld.long 0x14 16. "INT_FLG,Global Interrupt Status Flag:" "0,1" hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x14 11. "UTOI_EN,Unit Time Out Interrupt Enable:" "0,1" bitfld.long 0x14 10. "IELI_EN,Index Event Latch Interrupt Enable:" "0,1" bitfld.long 0x14 9. "SELI_EN,Strobe Event Latch Interrupt Enable:" "0,1" bitfld.long 0x14 8. "PCMI_EN,Position Compare Match Interrupt Enable:" "0,1" bitfld.long 0x14 7. "PCRI_EN,Position Compare Ready Interrupt Enable:" "0,1" bitfld.long 0x14 6. "PCOI_EN,Position Counter Overflow Interrupt Enable:" "0,1" bitfld.long 0x14 5. "PCUI_EN,Position Counter Underflow Interrupt Enable:" "0,1" newline bitfld.long 0x14 4. "WTOI_EN,Watchdog Time Out Interrupt Enable:" "0,1" bitfld.long 0x14 3. "QDCI_EN,Quadrature Direction Change Interrupt Enable:" "0,1" bitfld.long 0x14 2. "QPEI_EN,Quadrature Phase Error Interrupt Enable:" "0,1" bitfld.long 0x14 1. "PCEI_EN,Position Counter Error Interrupt Enable:" "0,1" rbitfld.long 0x14 0. "RESERVED,Reserved" "0,1" line.long 0x18 "EQEP_QINT_CLR_FRC,QEP Interrupt Clear and Forcing register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 27. "UTOI_FRC,Unit Time Out Interrupt Force:" "0,1" bitfld.long 0x18 26. "IELI_FRC,Index Event Latch Interrupt Force:" "0,1" bitfld.long 0x18 25. "SELI_FRC,Strobe Event Latch Interrupt Force:" "0,1" bitfld.long 0x18 24. "PCMI_FRC,Position Compare Match Interrupt Force:" "0,1" bitfld.long 0x18 23. "PCRI_FRC,Position Compare Ready Interrupt Force:" "0,1" bitfld.long 0x18 22. "PCOI_FRC,Position Counter Overflow Interrupt Force:" "0,1" newline bitfld.long 0x18 21. "PCUI_FRC,Position Counter Underflow Interrupt Force:" "0,1" bitfld.long 0x18 20. "WTOI_FRC,Watchdog Time Out Interrupt Force:" "0,1" bitfld.long 0x18 19. "QDCI_FRC,Quadrature Direction Change Interrupt Force:" "0,1" bitfld.long 0x18 18. "QPEI_FRC,Quadrature Phase Error Interrupt Force:" "0,1" bitfld.long 0x18 17. "PCEI_FRC,Position Counter Error Interrupt Force:" "0,1" hexmask.long.byte 0x18 12.--16. 1. "RESERVED,Reserved" eventfld.long 0x18 11. "UTOI_CLR,Clear Unit Time Out Interrupt Flag:" "0,1" newline eventfld.long 0x18 10. "IELI_CLR,Clear Index Event Latch Interrupt Flag:" "0,1" eventfld.long 0x18 9. "SELI_CLR,Clear Strobe Event Latch Interrupt Flag:" "0,1" eventfld.long 0x18 8. "PCMI_CLR,Clear QEP Compare Match Event Interrupt Flag:" "0,1" eventfld.long 0x18 7. "PCRI_CLR,Clear Position Compare Ready Interrupt Flag:" "0,1" eventfld.long 0x18 6. "PCOI_CLR,Clear Position Counter Overflow Interrupt Flag:" "0,1" eventfld.long 0x18 5. "PCUI_CLR,Clear Position Counter Underflow Interrupt Flag:" "0,1" eventfld.long 0x18 4. "WTOI_CLR,Clear Watchdog Timeout Interrupt Flag:" "0,1" newline eventfld.long 0x18 3. "QDCI_CLR,Clear Quadrature Direction Change Interrupt Flag:" "0,1" eventfld.long 0x18 2. "QPEI_CLR,Clear Quadrature Phase Error Interrupt Flag:" "0,1" eventfld.long 0x18 1. "PCEI_CLR,Clear Position Counter Error Interrupt Flag:" "0,1" eventfld.long 0x18 0. "INT_CLR,Global Interrupt Clear Flag:" "0,1" line.long 0x1C "EQEP_QEP_STS_CT,QEP Status and Capture Timer register" hexmask.long.word 0x1C 16.--31. 1. "QCTMR,This field provides time base for edge capture unit." hexmask.long.word 0x1C 7.--15. 1. "RESERVED,Reserved" rbitfld.long 0x1C 6. "FIDF,Direction on First Index Marker" "0,1" rbitfld.long 0x1C 5. "QDF,Quadrature Direction Flag" "0,1" rbitfld.long 0x1C 4. "QDLF,EQEP Direction Latch Flag" "0,1" bitfld.long 0x1C 3. "COEF,Capture Overflow Error Flag" "0,1" bitfld.long 0x1C 2. "CDEF,Capture Direction Error Flag 1h = Direction change occurred between the capture position event" "0,1" newline bitfld.long 0x1C 1. "FIMF,First Index Marker Flag" "0,1" rbitfld.long 0x1C 0. "PCEF,Position Counter Error Flag" "0,1" line.long 0x20 "EQEP_QC_PRD_TLAT,QEP Capture Period and Timer Latch register" hexmask.long.word 0x20 16.--31. 1. "QCTMRLAT,EQEP Capture Timer value can be latched into this register on two events:" hexmask.long.word 0x20 0.--15. 1. "QCPRD,This field holds the period count value between the last successive EQEP position events." rgroup.long 0x40++0x3 line.long 0x0 "EQEP_QCPRDLAT,QEP Capture Period Latch register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "QCPRDLAT,EQEP capture period value can be latched into this register on two events:" rgroup.long 0x5C++0x3 line.long 0x0 "EQEP_PID,Peripheral ID register" hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data" tree.end tree "EQEP1_REG" base ad:0x3210000 group.long 0x0++0xF line.long 0x0 "EQEP_QPOSCNT,QEP Position Counter register" hexmask.long 0x0 0.--31. 1. "POSCNT,This 32-bit Position Counter register counts up/down on every QEP pulse based on direction input." line.long 0x4 "EQEP_QPOSINIT,Position Counter Initialization register" hexmask.long 0x4 0.--31. 1. "INITPOS,This register contains the position value to be used to initialize the Position Counter based on external strobe or Index event." line.long 0x8 "EQEP_QPOSMAX,Maximum Position Count register" hexmask.long 0x8 0.--31. 1. "MAXPOS,This register contains the maximum Position Counter value for error checking in index reset mode or to reset the Position Counter based on the maximum count value." line.long 0xC "EQEP_QPOSCMP,Position Compare register" hexmask.long 0xC 0.--31. 1. "POSCMP,Position compare value in this register is compared with the Position Counter (" rgroup.long 0x10++0xB line.long 0x0 "EQEP_QPOSILAT,Index Position Latch register" hexmask.long 0x0 0.--31. 1. "IPOSLAT,Position Counter value can be latched into this register on index event as defined by the" line.long 0x4 "EQEP_QPOSSLAT,Strobe Position Latch register" hexmask.long 0x4 0.--31. 1. "SPOSLAT,Position Counter value can be latched into this register on strobe event as defined by the" line.long 0x8 "EQEP_QPOSLAT,QEP Position Counter Latch register" hexmask.long 0x8 0.--31. 1. "POSLAT,Position Counter value can be latched into this register on unit time out event." group.long 0x1C++0x23 line.long 0x0 "EQEP_QUTMR,QEP Unit Timer register" hexmask.long 0x0 0.--31. 1. "UNITTMR,This register acts as time base for unit time event generation." line.long 0x4 "EQEP_QUPRD,QEP Unit Period register" hexmask.long 0x4 0.--31. 1. "UNITPRD,This register contains the period count for unit timer to generate periodic unit time events to latch the EQEP position information at periodic interval and optionally to generate interrupt." line.long 0x8 "EQEP_QWD_TMR_PRD,QEP Watchdog Timer and Period register" hexmask.long.word 0x8 16.--31. 1. "QWDPRD,This field contains the time-out count for the QEP peripheral watch dog timer." hexmask.long.word 0x8 0.--15. 1. "QWDTMR,This field acts as time base for watch dog to detect stalls." line.long 0xC "EQEP_QDEC_QEP_CTL,Quadrature Decoder and QEP Control register" bitfld.long 0xC 30.--31. "FREE_SOFT,POSCNT Behavior:" "0,1,2,3" bitfld.long 0xC 28.--29. "PCRM,Position Counter Reset Mode:" "0,1,2,3" bitfld.long 0xC 26.--27. "SEI,Strobe Event Initialization of Position Counter:" "0,1,2,3" bitfld.long 0xC 24.--25. "IEI,Index Event Initialization of Position Counter:" "0,1,2,3" bitfld.long 0xC 23. "SWI,Software Initialization of Position Counter:" "0,1" bitfld.long 0xC 22. "SEL,Strobe Event Latch of Position Counter:" "0,1" bitfld.long 0xC 20.--21. "IEL,Index Event Latch of Position Counter (Software Index Marker):" "0,1,2,3" newline bitfld.long 0xC 19. "QPEN,Quadrature Position Counter Enable/Software Reset:" "0,1" bitfld.long 0xC 18. "QCLM,EQEP Capture Latch Mode:" "0,1" bitfld.long 0xC 17. "UTE,QEP Unit Timer Enable:" "0,1" bitfld.long 0xC 16. "WDE,QEP Watchdog Enable:" "0,1" bitfld.long 0xC 14.--15. "QSRC,Position Counter Source selection:" "0,1,2,3" bitfld.long 0xC 13. "SOEN,Enable Position Compare Sync Output:" "0,1" bitfld.long 0xC 12. "SPSEL,Sync Output Pin Selection:" "0,1" newline bitfld.long 0xC 11. "XCR,External Clock Rate:" "0,1" bitfld.long 0xC 10. "SWAP,CLK/DIR Signal Source for Position Counter:" "0,1" bitfld.long 0xC 9. "IGATE,Index Pulse Gating Option:" "0,1" bitfld.long 0xC 8. "QAP,QEPA Input Polarity:" "0,1" bitfld.long 0xC 7. "QBP,QEPB Input Polarity:" "0,1" bitfld.long 0xC 6. "QIP,QEPI Input Polarity:" "0,1" bitfld.long 0xC 5. "QSP,QEPS Input Polarity:" "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "RESERVED,Reserved" line.long 0x10 "EQEP_QCAP_QPOS_CTL,QEP Capture and Position Compare Control register" bitfld.long 0x10 31. "PCSHDW,Position-Compare Shadow Enable:" "0,1" bitfld.long 0x10 30. "PCLOAD,Position Compare Shadow Load Mode:" "0,1" bitfld.long 0x10 29. "PCPOL,Polarity of Sync Output:" "0,1" bitfld.long 0x10 28. "PCE,Position Compare Enable/Disable:" "0,1" hexmask.long.word 0x10 16.--27. 1. "PCSPW,Select Pulse Width Period in EQEP_FICLK Cycles:" bitfld.long 0x10 15. "CEN,Enable EQEP Capture:" "0,1" hexmask.long.byte 0x10 7.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x10 4.--6. "CCPS,EQEP Capture Timer Clock Prescalar:" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--3. 1. "UPPS,Unit Position Event Prescalar:" line.long 0x14 "EQEP_QINT_EN_FLG,QEP Interrupt Control and Flag register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 27. "UTOI_FLG,Unit Time Out Interrupt Flag:" "0,1" rbitfld.long 0x14 26. "IELI_FLG,Index Event Latch Interrupt Flag:" "0,1" rbitfld.long 0x14 25. "SELI_FLG,Strobe Event Latch Interrupt Flag:" "0,1" rbitfld.long 0x14 24. "PCMI_FLG,EQEP Compare Match Event Interrupt Flag:" "0,1" rbitfld.long 0x14 23. "PCRI_FLG,Position Compare Ready Interrupt Flag:" "0,1" rbitfld.long 0x14 22. "PCOI_FLG,Position Counter Overflow Interrupt Flag:" "0,1" newline rbitfld.long 0x14 21. "PCUI_FLG,Position Counter Underflow Interrupt Flag:" "0,1" rbitfld.long 0x14 20. "WTOI_FLG,Watchdog Timeout Interrupt Flag:" "0,1" rbitfld.long 0x14 19. "QDCI_FLG,Quadrature Direction Change Interrupt Flag:" "0,1" rbitfld.long 0x14 18. "QPEI_FLG,Quadrature Phase Error Interrupt Flag:" "0,1" rbitfld.long 0x14 17. "PCEI_FLG,Position Counter Error Interrupt Flag:" "0,1" rbitfld.long 0x14 16. "INT_FLG,Global Interrupt Status Flag:" "0,1" hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x14 11. "UTOI_EN,Unit Time Out Interrupt Enable:" "0,1" bitfld.long 0x14 10. "IELI_EN,Index Event Latch Interrupt Enable:" "0,1" bitfld.long 0x14 9. "SELI_EN,Strobe Event Latch Interrupt Enable:" "0,1" bitfld.long 0x14 8. "PCMI_EN,Position Compare Match Interrupt Enable:" "0,1" bitfld.long 0x14 7. "PCRI_EN,Position Compare Ready Interrupt Enable:" "0,1" bitfld.long 0x14 6. "PCOI_EN,Position Counter Overflow Interrupt Enable:" "0,1" bitfld.long 0x14 5. "PCUI_EN,Position Counter Underflow Interrupt Enable:" "0,1" newline bitfld.long 0x14 4. "WTOI_EN,Watchdog Time Out Interrupt Enable:" "0,1" bitfld.long 0x14 3. "QDCI_EN,Quadrature Direction Change Interrupt Enable:" "0,1" bitfld.long 0x14 2. "QPEI_EN,Quadrature Phase Error Interrupt Enable:" "0,1" bitfld.long 0x14 1. "PCEI_EN,Position Counter Error Interrupt Enable:" "0,1" rbitfld.long 0x14 0. "RESERVED,Reserved" "0,1" line.long 0x18 "EQEP_QINT_CLR_FRC,QEP Interrupt Clear and Forcing register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 27. "UTOI_FRC,Unit Time Out Interrupt Force:" "0,1" bitfld.long 0x18 26. "IELI_FRC,Index Event Latch Interrupt Force:" "0,1" bitfld.long 0x18 25. "SELI_FRC,Strobe Event Latch Interrupt Force:" "0,1" bitfld.long 0x18 24. "PCMI_FRC,Position Compare Match Interrupt Force:" "0,1" bitfld.long 0x18 23. "PCRI_FRC,Position Compare Ready Interrupt Force:" "0,1" bitfld.long 0x18 22. "PCOI_FRC,Position Counter Overflow Interrupt Force:" "0,1" newline bitfld.long 0x18 21. "PCUI_FRC,Position Counter Underflow Interrupt Force:" "0,1" bitfld.long 0x18 20. "WTOI_FRC,Watchdog Time Out Interrupt Force:" "0,1" bitfld.long 0x18 19. "QDCI_FRC,Quadrature Direction Change Interrupt Force:" "0,1" bitfld.long 0x18 18. "QPEI_FRC,Quadrature Phase Error Interrupt Force:" "0,1" bitfld.long 0x18 17. "PCEI_FRC,Position Counter Error Interrupt Force:" "0,1" hexmask.long.byte 0x18 12.--16. 1. "RESERVED,Reserved" eventfld.long 0x18 11. "UTOI_CLR,Clear Unit Time Out Interrupt Flag:" "0,1" newline eventfld.long 0x18 10. "IELI_CLR,Clear Index Event Latch Interrupt Flag:" "0,1" eventfld.long 0x18 9. "SELI_CLR,Clear Strobe Event Latch Interrupt Flag:" "0,1" eventfld.long 0x18 8. "PCMI_CLR,Clear QEP Compare Match Event Interrupt Flag:" "0,1" eventfld.long 0x18 7. "PCRI_CLR,Clear Position Compare Ready Interrupt Flag:" "0,1" eventfld.long 0x18 6. "PCOI_CLR,Clear Position Counter Overflow Interrupt Flag:" "0,1" eventfld.long 0x18 5. "PCUI_CLR,Clear Position Counter Underflow Interrupt Flag:" "0,1" eventfld.long 0x18 4. "WTOI_CLR,Clear Watchdog Timeout Interrupt Flag:" "0,1" newline eventfld.long 0x18 3. "QDCI_CLR,Clear Quadrature Direction Change Interrupt Flag:" "0,1" eventfld.long 0x18 2. "QPEI_CLR,Clear Quadrature Phase Error Interrupt Flag:" "0,1" eventfld.long 0x18 1. "PCEI_CLR,Clear Position Counter Error Interrupt Flag:" "0,1" eventfld.long 0x18 0. "INT_CLR,Global Interrupt Clear Flag:" "0,1" line.long 0x1C "EQEP_QEP_STS_CT,QEP Status and Capture Timer register" hexmask.long.word 0x1C 16.--31. 1. "QCTMR,This field provides time base for edge capture unit." hexmask.long.word 0x1C 7.--15. 1. "RESERVED,Reserved" rbitfld.long 0x1C 6. "FIDF,Direction on First Index Marker" "0,1" rbitfld.long 0x1C 5. "QDF,Quadrature Direction Flag" "0,1" rbitfld.long 0x1C 4. "QDLF,EQEP Direction Latch Flag" "0,1" bitfld.long 0x1C 3. "COEF,Capture Overflow Error Flag" "0,1" bitfld.long 0x1C 2. "CDEF,Capture Direction Error Flag 1h = Direction change occurred between the capture position event" "0,1" newline bitfld.long 0x1C 1. "FIMF,First Index Marker Flag" "0,1" rbitfld.long 0x1C 0. "PCEF,Position Counter Error Flag" "0,1" line.long 0x20 "EQEP_QC_PRD_TLAT,QEP Capture Period and Timer Latch register" hexmask.long.word 0x20 16.--31. 1. "QCTMRLAT,EQEP Capture Timer value can be latched into this register on two events:" hexmask.long.word 0x20 0.--15. 1. "QCPRD,This field holds the period count value between the last successive EQEP position events." rgroup.long 0x40++0x3 line.long 0x0 "EQEP_QCPRDLAT,QEP Capture Period Latch register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "QCPRDLAT,EQEP capture period value can be latched into this register on two events:" rgroup.long 0x5C++0x3 line.long 0x0 "EQEP_PID,Peripheral ID register" hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data" tree.end tree "EQEP2_REG" base ad:0x3220000 group.long 0x0++0xF line.long 0x0 "EQEP_QPOSCNT,QEP Position Counter register" hexmask.long 0x0 0.--31. 1. "POSCNT,This 32-bit Position Counter register counts up/down on every QEP pulse based on direction input." line.long 0x4 "EQEP_QPOSINIT,Position Counter Initialization register" hexmask.long 0x4 0.--31. 1. "INITPOS,This register contains the position value to be used to initialize the Position Counter based on external strobe or Index event." line.long 0x8 "EQEP_QPOSMAX,Maximum Position Count register" hexmask.long 0x8 0.--31. 1. "MAXPOS,This register contains the maximum Position Counter value for error checking in index reset mode or to reset the Position Counter based on the maximum count value." line.long 0xC "EQEP_QPOSCMP,Position Compare register" hexmask.long 0xC 0.--31. 1. "POSCMP,Position compare value in this register is compared with the Position Counter (" rgroup.long 0x10++0xB line.long 0x0 "EQEP_QPOSILAT,Index Position Latch register" hexmask.long 0x0 0.--31. 1. "IPOSLAT,Position Counter value can be latched into this register on index event as defined by the" line.long 0x4 "EQEP_QPOSSLAT,Strobe Position Latch register" hexmask.long 0x4 0.--31. 1. "SPOSLAT,Position Counter value can be latched into this register on strobe event as defined by the" line.long 0x8 "EQEP_QPOSLAT,QEP Position Counter Latch register" hexmask.long 0x8 0.--31. 1. "POSLAT,Position Counter value can be latched into this register on unit time out event." group.long 0x1C++0x23 line.long 0x0 "EQEP_QUTMR,QEP Unit Timer register" hexmask.long 0x0 0.--31. 1. "UNITTMR,This register acts as time base for unit time event generation." line.long 0x4 "EQEP_QUPRD,QEP Unit Period register" hexmask.long 0x4 0.--31. 1. "UNITPRD,This register contains the period count for unit timer to generate periodic unit time events to latch the EQEP position information at periodic interval and optionally to generate interrupt." line.long 0x8 "EQEP_QWD_TMR_PRD,QEP Watchdog Timer and Period register" hexmask.long.word 0x8 16.--31. 1. "QWDPRD,This field contains the time-out count for the QEP peripheral watch dog timer." hexmask.long.word 0x8 0.--15. 1. "QWDTMR,This field acts as time base for watch dog to detect stalls." line.long 0xC "EQEP_QDEC_QEP_CTL,Quadrature Decoder and QEP Control register" bitfld.long 0xC 30.--31. "FREE_SOFT,POSCNT Behavior:" "0,1,2,3" bitfld.long 0xC 28.--29. "PCRM,Position Counter Reset Mode:" "0,1,2,3" bitfld.long 0xC 26.--27. "SEI,Strobe Event Initialization of Position Counter:" "0,1,2,3" bitfld.long 0xC 24.--25. "IEI,Index Event Initialization of Position Counter:" "0,1,2,3" bitfld.long 0xC 23. "SWI,Software Initialization of Position Counter:" "0,1" bitfld.long 0xC 22. "SEL,Strobe Event Latch of Position Counter:" "0,1" bitfld.long 0xC 20.--21. "IEL,Index Event Latch of Position Counter (Software Index Marker):" "0,1,2,3" newline bitfld.long 0xC 19. "QPEN,Quadrature Position Counter Enable/Software Reset:" "0,1" bitfld.long 0xC 18. "QCLM,EQEP Capture Latch Mode:" "0,1" bitfld.long 0xC 17. "UTE,QEP Unit Timer Enable:" "0,1" bitfld.long 0xC 16. "WDE,QEP Watchdog Enable:" "0,1" bitfld.long 0xC 14.--15. "QSRC,Position Counter Source selection:" "0,1,2,3" bitfld.long 0xC 13. "SOEN,Enable Position Compare Sync Output:" "0,1" bitfld.long 0xC 12. "SPSEL,Sync Output Pin Selection:" "0,1" newline bitfld.long 0xC 11. "XCR,External Clock Rate:" "0,1" bitfld.long 0xC 10. "SWAP,CLK/DIR Signal Source for Position Counter:" "0,1" bitfld.long 0xC 9. "IGATE,Index Pulse Gating Option:" "0,1" bitfld.long 0xC 8. "QAP,QEPA Input Polarity:" "0,1" bitfld.long 0xC 7. "QBP,QEPB Input Polarity:" "0,1" bitfld.long 0xC 6. "QIP,QEPI Input Polarity:" "0,1" bitfld.long 0xC 5. "QSP,QEPS Input Polarity:" "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "RESERVED,Reserved" line.long 0x10 "EQEP_QCAP_QPOS_CTL,QEP Capture and Position Compare Control register" bitfld.long 0x10 31. "PCSHDW,Position-Compare Shadow Enable:" "0,1" bitfld.long 0x10 30. "PCLOAD,Position Compare Shadow Load Mode:" "0,1" bitfld.long 0x10 29. "PCPOL,Polarity of Sync Output:" "0,1" bitfld.long 0x10 28. "PCE,Position Compare Enable/Disable:" "0,1" hexmask.long.word 0x10 16.--27. 1. "PCSPW,Select Pulse Width Period in EQEP_FICLK Cycles:" bitfld.long 0x10 15. "CEN,Enable EQEP Capture:" "0,1" hexmask.long.byte 0x10 7.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x10 4.--6. "CCPS,EQEP Capture Timer Clock Prescalar:" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--3. 1. "UPPS,Unit Position Event Prescalar:" line.long 0x14 "EQEP_QINT_EN_FLG,QEP Interrupt Control and Flag register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 27. "UTOI_FLG,Unit Time Out Interrupt Flag:" "0,1" rbitfld.long 0x14 26. "IELI_FLG,Index Event Latch Interrupt Flag:" "0,1" rbitfld.long 0x14 25. "SELI_FLG,Strobe Event Latch Interrupt Flag:" "0,1" rbitfld.long 0x14 24. "PCMI_FLG,EQEP Compare Match Event Interrupt Flag:" "0,1" rbitfld.long 0x14 23. "PCRI_FLG,Position Compare Ready Interrupt Flag:" "0,1" rbitfld.long 0x14 22. "PCOI_FLG,Position Counter Overflow Interrupt Flag:" "0,1" newline rbitfld.long 0x14 21. "PCUI_FLG,Position Counter Underflow Interrupt Flag:" "0,1" rbitfld.long 0x14 20. "WTOI_FLG,Watchdog Timeout Interrupt Flag:" "0,1" rbitfld.long 0x14 19. "QDCI_FLG,Quadrature Direction Change Interrupt Flag:" "0,1" rbitfld.long 0x14 18. "QPEI_FLG,Quadrature Phase Error Interrupt Flag:" "0,1" rbitfld.long 0x14 17. "PCEI_FLG,Position Counter Error Interrupt Flag:" "0,1" rbitfld.long 0x14 16. "INT_FLG,Global Interrupt Status Flag:" "0,1" hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x14 11. "UTOI_EN,Unit Time Out Interrupt Enable:" "0,1" bitfld.long 0x14 10. "IELI_EN,Index Event Latch Interrupt Enable:" "0,1" bitfld.long 0x14 9. "SELI_EN,Strobe Event Latch Interrupt Enable:" "0,1" bitfld.long 0x14 8. "PCMI_EN,Position Compare Match Interrupt Enable:" "0,1" bitfld.long 0x14 7. "PCRI_EN,Position Compare Ready Interrupt Enable:" "0,1" bitfld.long 0x14 6. "PCOI_EN,Position Counter Overflow Interrupt Enable:" "0,1" bitfld.long 0x14 5. "PCUI_EN,Position Counter Underflow Interrupt Enable:" "0,1" newline bitfld.long 0x14 4. "WTOI_EN,Watchdog Time Out Interrupt Enable:" "0,1" bitfld.long 0x14 3. "QDCI_EN,Quadrature Direction Change Interrupt Enable:" "0,1" bitfld.long 0x14 2. "QPEI_EN,Quadrature Phase Error Interrupt Enable:" "0,1" bitfld.long 0x14 1. "PCEI_EN,Position Counter Error Interrupt Enable:" "0,1" rbitfld.long 0x14 0. "RESERVED,Reserved" "0,1" line.long 0x18 "EQEP_QINT_CLR_FRC,QEP Interrupt Clear and Forcing register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 27. "UTOI_FRC,Unit Time Out Interrupt Force:" "0,1" bitfld.long 0x18 26. "IELI_FRC,Index Event Latch Interrupt Force:" "0,1" bitfld.long 0x18 25. "SELI_FRC,Strobe Event Latch Interrupt Force:" "0,1" bitfld.long 0x18 24. "PCMI_FRC,Position Compare Match Interrupt Force:" "0,1" bitfld.long 0x18 23. "PCRI_FRC,Position Compare Ready Interrupt Force:" "0,1" bitfld.long 0x18 22. "PCOI_FRC,Position Counter Overflow Interrupt Force:" "0,1" newline bitfld.long 0x18 21. "PCUI_FRC,Position Counter Underflow Interrupt Force:" "0,1" bitfld.long 0x18 20. "WTOI_FRC,Watchdog Time Out Interrupt Force:" "0,1" bitfld.long 0x18 19. "QDCI_FRC,Quadrature Direction Change Interrupt Force:" "0,1" bitfld.long 0x18 18. "QPEI_FRC,Quadrature Phase Error Interrupt Force:" "0,1" bitfld.long 0x18 17. "PCEI_FRC,Position Counter Error Interrupt Force:" "0,1" hexmask.long.byte 0x18 12.--16. 1. "RESERVED,Reserved" eventfld.long 0x18 11. "UTOI_CLR,Clear Unit Time Out Interrupt Flag:" "0,1" newline eventfld.long 0x18 10. "IELI_CLR,Clear Index Event Latch Interrupt Flag:" "0,1" eventfld.long 0x18 9. "SELI_CLR,Clear Strobe Event Latch Interrupt Flag:" "0,1" eventfld.long 0x18 8. "PCMI_CLR,Clear QEP Compare Match Event Interrupt Flag:" "0,1" eventfld.long 0x18 7. "PCRI_CLR,Clear Position Compare Ready Interrupt Flag:" "0,1" eventfld.long 0x18 6. "PCOI_CLR,Clear Position Counter Overflow Interrupt Flag:" "0,1" eventfld.long 0x18 5. "PCUI_CLR,Clear Position Counter Underflow Interrupt Flag:" "0,1" eventfld.long 0x18 4. "WTOI_CLR,Clear Watchdog Timeout Interrupt Flag:" "0,1" newline eventfld.long 0x18 3. "QDCI_CLR,Clear Quadrature Direction Change Interrupt Flag:" "0,1" eventfld.long 0x18 2. "QPEI_CLR,Clear Quadrature Phase Error Interrupt Flag:" "0,1" eventfld.long 0x18 1. "PCEI_CLR,Clear Position Counter Error Interrupt Flag:" "0,1" eventfld.long 0x18 0. "INT_CLR,Global Interrupt Clear Flag:" "0,1" line.long 0x1C "EQEP_QEP_STS_CT,QEP Status and Capture Timer register" hexmask.long.word 0x1C 16.--31. 1. "QCTMR,This field provides time base for edge capture unit." hexmask.long.word 0x1C 7.--15. 1. "RESERVED,Reserved" rbitfld.long 0x1C 6. "FIDF,Direction on First Index Marker" "0,1" rbitfld.long 0x1C 5. "QDF,Quadrature Direction Flag" "0,1" rbitfld.long 0x1C 4. "QDLF,EQEP Direction Latch Flag" "0,1" bitfld.long 0x1C 3. "COEF,Capture Overflow Error Flag" "0,1" bitfld.long 0x1C 2. "CDEF,Capture Direction Error Flag 1h = Direction change occurred between the capture position event" "0,1" newline bitfld.long 0x1C 1. "FIMF,First Index Marker Flag" "0,1" rbitfld.long 0x1C 0. "PCEF,Position Counter Error Flag" "0,1" line.long 0x20 "EQEP_QC_PRD_TLAT,QEP Capture Period and Timer Latch register" hexmask.long.word 0x20 16.--31. 1. "QCTMRLAT,EQEP Capture Timer value can be latched into this register on two events:" hexmask.long.word 0x20 0.--15. 1. "QCPRD,This field holds the period count value between the last successive EQEP position events." rgroup.long 0x40++0x3 line.long 0x0 "EQEP_QCPRDLAT,QEP Capture Period Latch register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "QCPRDLAT,EQEP capture period value can be latched into this register on two events:" rgroup.long 0x5C++0x3 line.long 0x0 "EQEP_PID,Peripheral ID register" hexmask.long 0x0 0.--31. 1. "REVISION,TI Internal Data" tree.end tree.end tree "ESM0_CFG" base ad:0x700000 rgroup.long 0x0++0x7 line.long 0x0 "ESM_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,Always reads as 1h. Writes have no affect." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit:2h = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID. Always read as the assigned functional ID. Writes have no affect." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom. Special version." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "ESM_INFO,The Info Register gives the configuration information of this ESM." bitfld.long 0x4 31. "LAST_RESET,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Indicates the number of event groups that are pulse (as opposed to level) driven." hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Indicates the total number of groups that exist in the ESM." group.long 0x8++0x3 line.long 0x0 "ESM_EN,The Global Enable Register has the master interrupt mask" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,This field is the global mask for all interrupts. It is reset by the warm reset. The purpose is to leave all of the raw status and per-interrupt enable bits alone so that after a warm reset software may observe the state of the ESM before the warm.." wgroup.long 0xC++0x3 line.long 0x0 "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset field. Writing to this field can cause all of the raw status and all enables to be cleared. This can be used to reset the ESM state after debugging because of a warm reset." group.long 0x10++0xF line.long 0x0 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--7. 1. "STS,This is the raw status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0h." line.long 0x4 "ESM_ERR_STS,Config Error Enable and Clear Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x4 0.--7. 1. "MSK,This is the masked status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0." line.long 0x8 "ESM_ERR_EN_SET,Config Error Enable Set Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x8 0.--7. 1. "MSK,This is the mask enable for errors in the configuration for Group N. If the corresponding bit and the" line.long 0xC "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0xC 0.--7. 1. "MSK,This is the mask clear for errors in the configuration for Group N. If the corresponding bit and the" rgroup.long 0x20++0xF line.long 0x0 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt" hexmask.long.word 0x0 16.--31. 1. "PLS,Indicates what the highest priority low priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." hexmask.long.word 0x0 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for High Priority while.." line.long 0x4 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt" hexmask.long.word 0x4 16.--31. 1. "PLS,Indicates what the highest priority high priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." hexmask.long.word 0x4 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." line.long 0x8 "ESM_LOW,Shows which groups have outstanding low priority interrupts" hexmask.long 0x8 0.--31. 1. "STS,Indicates which Event Groups have one or more low priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0 bit 1 is for Event Group 1 etc… (bit N is for Event Group N)." line.long 0xC "ESM_HI,Shows which groups have outstanding high priority interrupts" hexmask.long 0xC 0.--31. 1. "STS,Indicates which Event Groups have one or more high priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0 bit 1 is for Event Group 1 etc… (bit N is for Event Group N)." wgroup.long 0x30++0x3 line.long 0x0 "ESM_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced. Writing the corresponding vector to this field will cause a re-evaluation of interrupts. If when the vector is written there are still pending interrupts a new pulse will be generated. Reads always return 0." group.long 0x40++0x3 line.long 0x0 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin control key. This field controls behavior of the error pin. Note during reset the field is 0h but the error pin is asserted (active low). Immediately after reset the error pin de-asserts. This field is only reset by a Power-On-Reset (not warm.." rgroup.long 0x44++0x7 line.long 0x0 "ESM_PIN_STS,This register reflects the status of the error_pin_n output" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." bitfld.long 0x0 0. "VAL,This field indicates the status of the error pin as looped back from the I/O. This field reflects the state of the ERR_I pin. Since the ERR_O pin is only affected by Power-On-Reset then the value of this field may be 1h after the release of Warm.." "0,1" line.long 0x4 "ESM_PIN_CNTR,This register shows the current value of the error pin counter" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,This field indicates the current value of the time interval counter. See" group.long 0x4C++0x3 line.long 0x0 "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,This is the value that will be pre-loaded in to the counter field of the" group.long 0x400++0x1B line.long 0x0 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…)" line.long 0x4 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will.." line.long 0x8 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x8 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) If the corresponding bit and the global enable" line.long 0xC "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0xC 0.--31. 1. "MSK,This field is used to disable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) If the corresponding bit and the global enable" line.long 0x10 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x10 0.--31. 1. "MSK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset.." line.long 0x14 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x14 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft.." line.long 0x18 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x18 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft.." tree.end tree "GPIO" base ad:0x0 tree "GPIO0" base ad:0x600000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable" group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits " hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits " line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state" hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state" line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits" group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits" line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits" line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits" line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" line.long 0x14 "GPIO_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits " hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits " line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits" group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits" line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits" line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits" line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" line.long 0x14 "GPIO_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits " hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits " line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits" group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits" line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits" line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits" line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" line.long 0x14 "GPIO_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits " hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits " line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits" group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits" line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits" line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits" line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" line.long 0x14 "GPIO_DIR8,Direction Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits " line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits" group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits" line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits" line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits" line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" tree.end tree "GPIO2" base ad:0x610000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable" group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits " hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits " line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state" hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state" line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits" group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits" line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits" line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits" line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" line.long 0x14 "GPIO_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits " hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits " line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits" group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits" line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits" line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits" line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" line.long 0x14 "GPIO_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits " hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits " line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits" group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits" line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits" line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits" line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" line.long 0x14 "GPIO_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits " hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits " line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits" group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits" line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits" line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits" line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" line.long 0x14 "GPIO_DIR8,Direction Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits " line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits" group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits" line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits" line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits" line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" tree.end tree "GPIO4" base ad:0x620000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable" group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits " hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits " line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state" hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state" line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits" group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits" line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits" line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits" line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" line.long 0x14 "GPIO_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits " hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits " line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits" group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits" line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits" line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits" line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" line.long 0x14 "GPIO_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits " hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits " line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits" group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits" line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits" line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits" line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" line.long 0x14 "GPIO_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits " hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits " line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits" group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits" line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits" line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits" line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" line.long 0x14 "GPIO_DIR8,Direction Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits " line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits" group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits" line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits" line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits" line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" tree.end tree "GPIO6" base ad:0x630000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable" group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits " hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits " line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state" hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state" line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits" group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits" line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits" line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits" line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" line.long 0x14 "GPIO_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits " hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits " line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits" group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits" line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits" line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits" line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" line.long 0x14 "GPIO_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits " hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits " line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits" group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits" line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits" line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits" line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" line.long 0x14 "GPIO_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits " hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits " line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits" group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits" line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits" line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits" line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" line.long 0x14 "GPIO_DIR8,Direction Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits " line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits" group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits" line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits" line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits" line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" tree.end tree "GPIOMUX_INTRTR0_INTR_ROUTER_CFG" base ad:0xA00000 rgroup.long 0x0++0x3 line.long 0x0 "GPIOMUX_INTRTR0_PID,Peripheral identification register. Uniquely identifies the module and its specific revision." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "GPIOMUX_INTRTR0_MUXCNTL_n,Interrupt mux control register. Offset = 4h + (n * 4h); where n = 0h to 3Fh." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "INT_ENABLE,Enable for interrupt output N" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--8. 1. "ENABLE,Mux control for interrupt output N" tree.end tree.end tree "GPMC0_CFG" base ad:0x5390000 rgroup.long 0x0++0x3 line.long 0x0 "GPMC_REVISION,This register contains the IP revision code." hexmask.long 0x0 0.--31. 1. "REVISION,TI internal data. Identifies revision of peripheral." group.long 0x10++0x3 line.long 0x0 "GPMC_SYSCONFIG,Register related to module software reset and local power management." hexmask.long 0x0 5.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0." bitfld.long 0x0 3.--4. "IDLEMODE,0h = Force-idle. A clock stop request is acknowledged unconditionally. 1h (R/W) = No-idle. A clock stop request is never acknowledged. 2h (R/W) = Smart-idle. Acknowledgment to a clock stop request is given based on the internal activity of the.." "0,1,2,3" rbitfld.long 0x0 2. "RESERVED,Write 0 for future compatibility Read returns 0." "0,1" newline bitfld.long 0x0 1. "RESERVED,This bit must be kept 0 for normal functioning of the IP." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic Interface clock gating strategy is applied based on the interconnect activity." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0 (reserved for interconnect-socket status information)." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing. 1h (R) = Reset is complete." "0,1" group.long 0x18++0x7 line.long 0x0 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x0 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt Write: 0h = WAIT1EDGEDETECTIONSTATUS bit is unchanged. 1h = WAIT1EDGEDETECTIONSTATUS bit is reset. Read: 0h = A transition on WAIT1 input pin has not been detected. 1h = A transition.." "0,1" bitfld.long 0x0 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt Write: 0h = WAIT0EDGEDETECTIONSTATUS bit is unchanged. 1h = WAIT0EDGEDETECTIONSTATUS bit is reset. Read: 0h = A transition on WAIT0 input pin has not been detected. 1h = A transition.." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x0 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt Write: 0h = TERMINALCOUNTSTATUS bit is unchanged. 1h = TERMINALCOUNTSTATUS bit is reset. Read: 0h = Indicates that CountValue is greater than 0. 1h = Indicates that CountValue is equal to 0." "0,1" bitfld.long 0x0 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt Write: 0h = FIFOEVENTSTATUS bit is unchanged. 1h = FIFOEVENTSTATUS bit is reset. Read: 0h = Indicates that less than 1h = Indicates that at least" "0,1" line.long 0x4 "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x4 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt 0h (R/W) = Wait1EdgeDetection interrupt is masked. 1h (R/W) = Wait1EdgeDetection event generates an interrupt if occurs." "0,1" bitfld.long 0x4 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt 0h (R/W) = Wait0EdgeDetection interrupt is masked. 1h (R/W) = Wait0EdgeDetection event generates an interrupt if occurs." "0,1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x4 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode 0h (R/W) = TerminalCountEvent interrupt is masked. 1h (R/W) = TerminalCountEvent interrupt is not masked." "0,1" bitfld.long 0x4 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt 0h (R/W) = FIFOEvent interrupt is masked. 1h (R/W) = FIFOEvent interrupt is not masked." "0,1" group.long 0x40++0x3 line.long 0x0 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." hexmask.long.word 0x0 4.--12. 1. "TIMEOUTSTARTVALUE,Start value of the time-out counter" rbitfld.long 0x0 1.--3. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature 0h (R/W) = TimeOut feature is disabled. 1h (R/W) = TimeOut feature is enabled." "0,1" rgroup.long 0x44++0x3 line.long 0x0 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs." bitfld.long 0x0 31. "RESERVED,Write 0s for future compatibility. Read returns 0." "0,1" hexmask.long 0x0 0.--30. 1. "ILLEGALADD,Address of illegal access" group.long 0x48++0x3 line.long 0x0 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." rbitfld.long 0x0 8.--10. "ILLEGALMCMD,System command of the transaction that caused the error" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 5.--7. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 4. "ERRORNOTSUPPADD,Not supported address error 0h (R) = No error occurs. 1h (R) = The error is due to a nonsupported address." "0,1" rbitfld.long 0x0 3. "ERRORNOTSUPPMCMD,Not supported command error 0h (R) = No error occurs. 1h (R) = The error is due to a nonsupported command" "0,1" rbitfld.long 0x0 2. "ERRORTIMEOUT,Time-out error 0h (R) = No error occurs. 1h (R) = The error is due to a timeout." "0,1" newline rbitfld.long 0x0 1. "RESERVED,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 0. "ERRORVALID,Error validity status - Must be explicitly cleared with a write 1 transaction 0h (R/W) = All error fields no longer valid 1h (R/W) = Error detected and logged in the other error fields" "0,1" group.long 0x50++0x3 line.long 0x0 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x0 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1 0h (R/W) = WAIT1 active low 1h (R/W) = WAIT1 active high" "0,1" bitfld.long 0x0 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0 0h (R/W) = WAIT0 active low 1h (R/W) = WAIT0 active high" "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "WRITEPROTECT,Controls the WP output pin level 0h (R/W) = nWP output pin is low 1h (R/W) = nWP output pin is high" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location 0h (R/W) = Disables Force Posted Write 1h (R/W) = Enables Force Posted Write" "0,1" rgroup.long 0x54++0x3 line.long 0x0 "GPMC_STATUS,The status register provides global status bits of the GPMC." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x0 9. "WAIT1STATUS,Is a copy of input pin WAIT1. (Reset value is WAIT1 input pin sampled at device reset.) 0h (R) = WAIT1 asserted (inactive state) 1h (R) = WAIT1 deasserted" "0,1" bitfld.long 0x0 8. "WAIT0STATUS,Is a copy of input pin WAIT0. (Reset value is WAIT0 input pin sampled at device reset.) 0h (R) = WAIT0 asserted (inactive state) 1h (R) = WAIT0 deasserted" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Write 0s for future compatibility. Reads returns 0" bitfld.long 0x0 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer 0h (R) = Write buffer is not empty. 1h (R) = Write buffer is empty." "0,1" group.long 0x60++0x1B line.long 0x0 "GPMC_CONFIG1_i,The configuration register 1 sets signal control parameters per chip-select. Offset = 60h + (i * 30h). where: i = 0 to 3" bitfld.long 0x0 31. "WRAPBURST,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst 0h (R/W) = Synchronous wrapping burst not supported 1h (R/W) = Synchronous wrapping burst supported" "0,1" bitfld.long 0x0 30. "READMULTIPLE,Selects the read single or multiple access 0h (R/W) = Single access 1h (R/W) = Multiple access (burst if synchronous page if asynchronous)" "0,1" bitfld.long 0x0 29. "READTYPE,Selects the read mode operation 0h (R/W) = Read asynchronous 1h (R/W) = Read synchronous" "0,1" newline bitfld.long 0x0 28. "WRITEMULTIPLE,Selects the write single or multiple access 0h (R/W) = Single access 1h (R/W) = Multiple access (burst if synchronous considered as single if asynchronous)" "0,1" bitfld.long 0x0 27. "WRITETYPE,Selects the write mode operation 0h (R/W) = Write asynchronous 1h (R/W) = Write synchronous" "0,1" bitfld.long 0x0 25.--26. "CLKACTIVATIONTIME,Output GPMC CLK activation time 0h (R/W) = First rising edge of GPMC CLK at start access time 1h (R/W) = First rising edge of GPMC CLK one GPMC_FCLK cycle after start access time 2h (R/W) = First rising edge of GPMC CLK two GPMC_FCLK.." "0,1,2,3" newline bitfld.long 0x0 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length 0h (R/W) = 4 words 1h (R/W) = 8 words 2h (R/W) = 16 words 3h (R/W) = Reserved (1 word = interface size)" "0,1,2,3" bitfld.long 0x0 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses 0h (R/W) = WAIT pin is not monitored for read accesses. 1h (R/W) = WAIT pin is monitored for read accesses." "0,1" bitfld.long 0x0 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses 0h (R/W) = WAIT pin is not monitored for write accesses. 1h (R/W) = WAIT pin is monitored for write accesses." "0,1" newline rbitfld.long 0x0 20. "RESERVED,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time 0h (R/W) = WAIT pin is monitored with valid data. 1h (R/W) = WAIT pin is monitored one GPMC CLK cycle before valid data. 2h (R/W) = WAIT pin is monitored two GPMC CLK cycle before valid data. 3h.." "0,1,2,3" bitfld.long 0x0 16.--17. "WAITPINSELECT,Selects the input WAIT pin for this chip-select 0h (R/W) = Wait input pin is WAIT0. 1h (R/W) = Wait input pin is WAIT1. 2h (R/W) = Reserved 3h (R/W) = Reserved" "0,1,2,3" newline rbitfld.long 0x0 14.--15. "RESERVED,Write 0s for future compatibility." "0,1,2,3" bitfld.long 0x0 12.--13. "DEVICESIZE,Selects the device size attached 0h (R/W) = 8 bit 1h (R/W) = 16 bit 2h (R/W) = Reserved 3h (R/W) = Reserved" "0,1,2,3" bitfld.long 0x0 10.--11. "DEVICETYPE,Selects the attached device type 0h (R/W) = NOR flash-like asynchronous and synchronous devices 1h (R/W) = Reserved 2h (R/W) = NAND flash-like devices stream mode 3h (R/W) = Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol 0h (R/W) = Nonmultiplexed attached device 1h (R/W) = AAD-multiplexed protocol device 2h (R/W) = Address and data multiplexed attached device 3h (R/W) = Reserved" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND .." "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" bitfld.long 0x0 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock 0h (R/W) = GPMC CLK frequency = GPMC_FCLK frequency 1h (R/W) = GPMC CLK frequency = GPMC_FCLK frequency / 2 2h (R/W) = GPMC CLK frequency = GPMC_FCLK frequency / 3 3h (R/W) = GPMC CLK frequency = GPMC_FCLK.." "0,1,2,3" line.long 0x4 "GPMC_CONFIG2_i,CS signal timing parameter configuration Offset = 64h + (i * 30h). where: i = 0 to 3" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Write 0s for future compatibility." hexmask.long.byte 0x4 16.--20. 1. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" rbitfld.long 0x4 13.--15. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--12. 1. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" bitfld.long 0x4 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle 0h (R/W) = CS i Timing control signal is not delayed 1h (R/W) = CS i Timing control signal is delayed of half GPMC_FCLK clock cycle" "0,1" rbitfld.long 0x4 4.--6. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "CSONTIME,CS i assertion time from start cycle time" line.long 0x8 "GPMC_CONFIG3_i,nADV signal timing parameter configuration Offset = 68h + (i * 30h). where: i = 0 to 3" rbitfld.long 0x8 31. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x8 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" rbitfld.long 0x8 27. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1" newline bitfld.long 0x8 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" rbitfld.long 0x8 21.--23. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 16.--20. 1. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" newline rbitfld.long 0x8 13.--15. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" bitfld.long 0x8 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle 0h (R/W) = nADV timing control signal is not delayed 1h (R/W) = nADV timing control signal is delayed of half GPMC_FCLK clock cycle" "0,1" newline bitfld.long 0x8 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--3. 1. "ADVONTIME,nADV assertion time from start cycle time" line.long 0xC "GPMC_CONFIG4_i,nWE and nOE signals timing parameter configuration Offset = 6Ch + (i * 30h). where: i = 0 to 3" rbitfld.long 0xC 29.--31. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--28. 1. "WEOFFTIME,nWE deassertion time from start cycle time" bitfld.long 0xC 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle 0h (R/W) = nWE timing control signal is not delayed 1h (R/W) = nWE timing control signal is delayed of half-GPMC_FCLK clock cycle" "0,1" newline rbitfld.long 0xC 20.--22. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "WEONTIME,nWE assertion time from start cycle time" bitfld.long 0xC 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "OEOFFTIME,nOE deassertion time from start cycle time" bitfld.long 0xC 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle 0h (R/W) = nOE timing control signal is not delayed 1h (R/W) = nOE timing control signal is delayed of half-GPMC_FCLK clock cycle" "0,1" bitfld.long 0xC 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--3. 1. "OEONTIME,nOE assertion time from start cycle time" line.long 0x10 "GPMC_CONFIG5_i,RdAccessTime and CycleTime timing parameters configuration Offset = 70h + (i * 30h). where: i = 0 to 3" hexmask.long.byte 0x10 28.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." hexmask.long.byte 0x10 24.--27. 1. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" rbitfld.long 0x10 21.--23. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "RDACCESSTIME,Delay between start cycle time and first data valid" rbitfld.long 0x10 13.--15. "RESERVED,Write 0s for future compatibility." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--12. 1. "WRCYCLETIME,Total write cycle time" newline rbitfld.long 0x10 5.--7. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--4. 1. "RDCYCLETIME,Total read cycle time" line.long 0x14 "GPMC_CONFIG6_i,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration Offset = 74h + (i * 30h). where: i = 0 to 3" bitfld.long 0x14 31. "RESERVED,TI Internal use - Do not modify." "0,1" rbitfld.long 0x14 29.--30. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" hexmask.long.byte 0x14 24.--28. 1. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC CLK rising edge used by the attached memory for the first data capture" newline hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." hexmask.long.byte 0x14 16.--19. 1. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." newline hexmask.long.byte 0x14 8.--11. 1. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type) 0h (R/W) = No delay between the two accesses 1h (R/W) = Add CYCLE2CYCLEDELAY" "0,1" bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type) 0h (R/W) = No delay between the two accesses 1h (R/W) = Add CYCLE2CYCLEDELAY" "0,1" newline rbitfld.long 0x14 4.--5. "RESERVED,Write 0s for future compatibility." "0,1,2,3" hexmask.long.byte 0x14 0.--3. 1. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" line.long 0x18 "GPMC_CONFIG7_i,CS address mapping configuration Offset = 78h + (i * 30h). where: i = 0 to 3" hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." hexmask.long.byte 0x18 8.--11. 1. "MASKADDRESS,CS mask address." rbitfld.long 0x18 7. "RESERVED,Write 0s for future compatibility. Read returns 0." "0,1" newline bitfld.long 0x18 6. "CSVALID,CS enable 0h (R/W) = CS disabled 1h (R/W) = CS enabled" "0,1" hexmask.long.byte 0x18 0.--5. 1. "BASEADDRESS,CSi base address where i = 0 to 3 (16-MB minimum granularity) bits [5-0] corresponds to A29 A28 A27 A26 A25 and A24. See" wgroup.long 0x7C++0x7 line.long 0x0 "GPMC_NAND_COMMAND_i,This register is not a true register. only an address location. Offset = 7Ch + (i * 30h). where: i = 0 to 3" hexmask.long 0x0 0.--31. 1. "GPMC_NAND_COMMAND,This register is not a true register only an address location. Writing data at the" line.long 0x4 "GPMC_NAND_ADDRESS_i,This register is not a true register. only an address location. Offset = 80h + (i * 30h). where: i = 0 to 3" hexmask.long 0x4 0.--31. 1. "GPMC_NAND_ADDRESS,This register is not a true register only an address location. Writing data at the" group.long 0x84++0x3 line.long 0x0 "GPMC_NAND_DATA_i,This register is not a true register. only an address location. Offset = 84h + (i * 30h). where: i = 0 to 3" hexmask.long 0x0 0.--31. 1. "GPMC_NAND_DATA,This register is not a true register only an address location. Reading data from the" group.long 0x1E0++0x7 line.long 0x0 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1 Some of the GPMC features described in this section may not be supported on this family of devices. For more information. see . GPMC Not Supported Features." rbitfld.long 0x0 31. "RESERVED,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME WRCYCLETIME RDACCESSTIME CSRDOFFTIME CSWROFFTIME ADVRDOFFTIME ADVWROFFTIME OEOFFTIME WEOFFTIME" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization 0h (R/W) = Access cycle optimization is disabled. 1h (R/W) = Access cycle optimization is enabled." "0,1" newline bitfld.long 0x0 24.--26. "ENGINECSSELECTOR,Selects the chip-select where Prefetch Postwrite engine is active" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration 0h (R/W) = Prefetch Postwrite engine round robin arbitration is disabled. 1h (R/W) = Prefetch Postwrite engine round robin arbitration is enabled." "0,1" rbitfld.long 0x0 20.--22. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a DMA and a PFPW engine access the DMA is always serviced. If the PFPWEnRoundRobin is enabled " rbitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility. Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request" newline bitfld.long 0x0 7. "ENABLEENGINE,Enables the Prefetch Postwite engine 0h (R/W) = Prefetch Postwrite engine is disabled. 1h (R/W) = Prefetch Postwrite engine is enabled." "0,1" rbitfld.long 0x0 6. "RESERVED,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode 0h (R/W) = Selects Wait0 EdgeDetection 1h (R/W) = Selects Wait1 EdgeDetection2h (R/W) = Reserved 3h (R/W) = Reserved" "0,1,2,3" newline bitfld.long 0x0 3. "SYNCHROMODE,Selects when the engine starts the access to chip-select 0h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set 1h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set AND wait to nonwait.." "0,1" bitfld.long 0x0 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization 0h (R/W) = Interrupt synchronization is enabled. Only interrupt line is activated on FIFO threshold crossing. 1h (R/W) = DMA request synchronization is enabled. A DMA request.." "0,1" bitfld.long 0x0 1. "ENDIANISMTYPE,Selects endianism for prefetch data0h = Little endian 1h = Bit endian" "0,1" newline bitfld.long 0x0 0. "ACCESSMODE,Selects prefetch read or write-posting accesses 0h (R/W) = Prefetch read mode 1h (R/W) = Write-posting mode" "0,1" line.long 0x4 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." hexmask.long.word 0x4 0.--13. 1. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected chip-select" group.long 0x1EC++0x3 line.long 0x0 "GPMC_PREFETCH_CONTROL,Prefetch engine control" hexmask.long 0x0 1.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x0 0. "STARTENGINE,Resets the FIFO pointer and starts the engine Write: 0h = Stops the engine. 1h = Resets the FIFO pointer to 0h in prefetch mode and 40h in postwrite mode and starts the engine. Read: 0h = Engine is stopped. 1h = Engine is running." "0,1" rgroup.long 0x1F0++0x3 line.long 0x0 "GPMC_PREFETCH_STATUS,Prefetch engine status" bitfld.long 0x0 31. "RESERVED,Write 0s for future compatibility. Read returns 0." "0,1" hexmask.long.byte 0x0 24.--30. 1. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written" hexmask.long.byte 0x0 17.--23. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." newline bitfld.long 0x0 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value 0h (R) = FIFOPointer smaller or equal to FIFOThreshold. Writing to this bit has no effect. 1h (R) = FIFOPointer greater than FIFOThreshold. Writing to this bit has no effect." "0,1" bitfld.long 0x0 14.--15. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" hexmask.long.word 0x0 0.--13. 1. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value" group.long 0x1F4++0xB line.long 0x0 "GPMC_ECC_CONFIG,ECC configuration" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x0 16. "ECCALGORITHM,ECC algorithm used 0h (R/W) = Hamming code 1h (R/W) = BCH code" "0,1" rbitfld.long 0x0 14.--15. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" newline bitfld.long 0x0 12.--13. "ECCBCHTSEL,Error correction capability used for BCH 0h (R/W) = Up to 4 bits error correction (t = 4) 1h (R/W) = Up to 8 bits error correction (t = 8) 2h (R/W) = Up to 16 bits error correction (t = 16) 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details" bitfld.long 0x0 7. "ECC16B,Selects an ECC calculated on 16 columns 0h (R/W) = ECC calculated on 8 columns 1h (R/W) = ECC calculated on 16 columns" "0,1" newline bitfld.long 0x0 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm 1h = 2 sectors" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "ECCCS,Selects the CS where ECC is computed 0h (R/W) = CS0 1h (R/W) = CS1 2h (R/W) = CS2 3h (R/W) = CS3 Other: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "ECCENABLE,Enables the ECC feature 0h (R/W) = ECC disabled 1h (R/W) = ECC enabled" "0,1" line.long 0x4 "GPMC_ECC_CONTROL,ECC control" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x4 8. "ECCCLEAR,Clear all ECC result registers" "0,1" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." newline hexmask.long.byte 0x4 0.--3. 1. "ECCPOINTER,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Writing other values disables the ECC engine.." line.long 0x8 "GPMC_ECC_SIZE_CONFIG,ECC size" hexmask.long.word 0x8 22.--31. 1. "ECCSIZE1,Defines ECC size 1." hexmask.long.word 0x8 12.--21. 1. "ECCSIZE0,Defines ECC size 0." rbitfld.long 0x8 9.--11. "RESERVED,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" bitfld.long 0x8 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" bitfld.long 0x8 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" newline bitfld.long 0x8 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" bitfld.long 0x8 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" bitfld.long 0x8 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" newline bitfld.long 0x8 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" bitfld.long 0x8 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" bitfld.long 0x8 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "0,1" rgroup.long 0x200++0x3 line.long 0x0 "GPMC_ECCj_RESULT,ECC result register Offset = 200h + (j * 4h). where: j = 0 to 8" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x0 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x0 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x0 24. "P256O,Odd row parity bit 256" "0,1" bitfld.long 0x0 23. "P128O,Odd row parity bit 128" "0,1" newline bitfld.long 0x0 22. "P64O,Odd row parity bit 64" "0,1" bitfld.long 0x0 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x0 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x0 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x0 18. "P4O,Odd Column Parity bit 4" "0,1" bitfld.long 0x0 17. "P2O,Odd Column Parity bit 2" "0,1" newline bitfld.long 0x0 16. "P1O,Odd Column Parity bit 1" "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." bitfld.long 0x0 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" newline bitfld.long 0x0 10. "P1024E,Even row parity bit 1024" "0,1" bitfld.long 0x0 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x0 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x0 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x0 6. "P64E,Even row parity bit 64" "0,1" bitfld.long 0x0 5. "P32E,Even row parity bit 32" "0,1" newline bitfld.long 0x0 4. "P16E,Even row parity bit 16" "0,1" bitfld.long 0x0 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x0 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x0 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x0 0. "P1E,Even column parity bit 1" "0,1" rgroup.long 0x240++0xF line.long 0x0 "GPMC_BCH_RESULT0_i,BCH ECC result (bits 0 to 31) Offset = 240h + (i * 10h). where: i = 0 to 3" hexmask.long 0x0 0.--31. 1. "BCH_RESULT_0,BCH ECC result (bits 0 to 31)" line.long 0x4 "GPMC_BCH_RESULT1_i,BCH ECC result (bits 32 to 63) Offset = 244h + (i * 10h). where: i = 0 to 3" hexmask.long 0x4 0.--31. 1. "BCH_RESULT_1,BCH ECC result (bits 32 to 63)" line.long 0x8 "GPMC_BCH_RESULT2_i,BCH ECC result (bits 64 to 95) Offset = 248h + (i * 10h). where: i = 0 to 3" hexmask.long 0x8 0.--31. 1. "BCH_RESULT_2,BCH ECC result (bits 64 to 95)" line.long 0xC "GPMC_BCH_RESULT3_i,BCH ECC result (bits 96 to 127) Offset = 24Ch + (i * 10h). where: i = 0 to 3" hexmask.long 0xC 0.--31. 1. "BCH_RESULT_3,BCH ECC result (bits 96 to 127)" group.long 0x2D0++0x3 line.long 0x0 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." hexmask.long.word 0x0 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation" rgroup.long 0x300++0xB line.long 0x0 "GPMC_BCH_RESULT4_i,BCH ECC result (bits 128 to 159) Offset = 300h + (i * 10h). where: i = 0 to 3" hexmask.long 0x0 0.--31. 1. "BCH_RESULT_4,BCH ECC result (bits 128 to 159)" line.long 0x4 "GPMC_BCH_RESULT5_i,BCH ECC result (bits 160 to 191) Offset = 304h + (i * 10h). where: i = 0 to 3" hexmask.long 0x4 0.--31. 1. "BCH_RESULT_5,BCH ECC result (bits 160 to 191)" line.long 0x8 "GPMC_BCH_RESULT6_i,BCH ECC result (bits 192 to 207) Offset = 308h + (i * 10h). where: i = 0 to 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Write 0s for future compatibility. Read returns 0s." hexmask.long.word 0x8 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" tree.end tree "GTC" base ad:0x0 tree "GTC0_GTC_CFG0" base ad:0xA80000 rgroup.long 0x0++0x7 line.long 0x0 "GTC_PID,This is the standard platform IP revision register which contains the ID and revision information of the MMR generator." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." line.long 0x4 "GTC_GTC_PID,This is the standard platform IP revision register which contains the ID and revision information of the GTC peripheral." hexmask.long 0x4 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "GTC_PUSHEVT,Selects which bit of the count value to output as a push event for global timesync." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved. Always read as 0." hexmask.long.byte 0x0 0.--5. 1. "EXPBIT_SEL,This field controls the mux that selects which bit [63:0] of the system counter value is exported on the0h = Select CNTR[0]1h = Select CNTR[1]...3Fh = Select CNTR]63]" tree.end tree "GTC0_GTC_CFG1" base ad:0xA90000 group.long 0x0++0x3 line.long 0x0 "GTC_CNTCR,This register enables the system counter and controls counter operation during debug." hexmask.long.tbyte 0x0 8.--31. 1. "FCREQ,Frequency change request. Indicates the number of the entry in the frequency table to select. For this device this field is implemented as read-only pointing to the base frequency table entry (000000h)." hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Always read as 0." bitfld.long 0x0 1. "HDBG,Halt on debug0 = System counter ignores debug halt1 = System counter is halted when debug halt is asserted" "0,1" bitfld.long 0x0 0. "EN,Enable system counter0 = System counter is disabled1 = System counter is enabled" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "GTC_CNTSR,This register provides system counter frequency status information." hexmask.long.tbyte 0x0 8.--31. 1. "FCACK,Frequency change ackowledge. Indicates the currently selected entry in the frequency table. For this device this field is tied to 0." hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Always read as 0." bitfld.long 0x0 1. "DBGH,Debug halt. Indicates if the system counter is halted due to debug.0 = System counter is not halted by a debug halt1 = System counter is halted by a debug halt" "0: System counter is not halted by a debug halt1 =..,?" bitfld.long 0x0 0. "RESERVED,Reserved. Always read as 0." "0,1" group.long 0x8++0x7 line.long 0x0 "GTC_CNTCV_LO,Indicates the current system counter count value and can be used to set the system counter count value." hexmask.long 0x0 0.--31. 1. "COUNTVALUE,Indicates bits [31:0] of the system counter value. This field is only writable when the system counter is disabled. The read value is the current value of system counter count [31:0]." line.long 0x4 "GTC_CNTCV_HI,Indicates the current system counter count value and can be used to set the system counter count value." hexmask.long 0x4 0.--31. 1. "COUNTVALUE,Indicates bits [63:32] of the system counter value. This field is only writable when the system counter is disabled. The read value is the current value of system counter count [63:32]." group.long 0x20++0x3 line.long 0x0 "GTC_CNTFID0,Indicates base frequency of the system counter. Device bootcode/firmware should write this register with the frequency of the selected GTC clock source before enabling the system counter." hexmask.long 0x0 0.--31. 1. "FREQVALUE,Indicates the base update frequency of the system counter in Hz." rgroup.long 0x24++0x3 line.long 0x0 "GTC_CNTFID1,Indicates the system counter increment frequency." hexmask.long 0x0 0.--31. 1. "FREQVALUE,Frequency table end indicator. All 0s value marks the end of the frequency table." tree.end tree "GTC0_GTC_CFG2" base ad:0xAA0000 rgroup.long 0x0++0x7 line.long 0x0 "GTC_CNTCVS_LO,Indicates the current system counter count value. It reflects the same value as the CNTCV_LO register." hexmask.long 0x0 0.--31. 1. "COUNTVALUE,Indicates bits [31:0] of the system counter value." line.long 0x4 "GTC_CNTCVS_HI,Indicates the current system counter count value. It reflects the same value as the CNTCV_HI register." hexmask.long 0x4 0.--31. 1. "COUNTVALUE,Indicates bits [63:32] of the system counter value." tree.end tree "GTC0_GTC_CFG3" base ad:0xAB0000 rgroup.long 0x0++0x3 line.long 0x0 "GTC_CNTTIDR,Indicates the implemented timers in the memory map and their features. Because the platform does not implement memory-mapped timers. this register is set to all 0s." hexmask.long.byte 0x0 28.--31. 1. "FRAME7,Indicates the features of timer frame 7" hexmask.long.byte 0x0 24.--27. 1. "FRAME6,Indicates the features of timer frame 6" hexmask.long.byte 0x0 20.--23. 1. "FRAME5,Indicates the features of timer frame 5" hexmask.long.byte 0x0 16.--19. 1. "FRAME4,Indicates the features of timer frame 4" hexmask.long.byte 0x0 12.--15. 1. "FRAME3,Indicates the features of timer frame 3" hexmask.long.byte 0x0 8.--11. 1. "FRAME2,Indicates the features of timer frame 2" hexmask.long.byte 0x0 4.--7. 1. "FRAME1,Indicates the features of timer frame 1" hexmask.long.byte 0x0 0.--3. 1. "FRAME0,Indicates the features of timer frame 0" tree.end tree.end tree "I2C" base ad:0x0 tree "I2C0_CFG" base ad:0x2000000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C1_CFG" base ad:0x2010000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C2_CFG" base ad:0x2020000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C3_CFG" base ad:0x2030000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C4_CFG" base ad:0x2040000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C5_CFG" base ad:0x2050000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C6_CFG" base ad:0x2060000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree.end tree "I3C" base ad:0x0 tree "I3C0_MMR_MMRVBP" base ad:0x20A0000 rgroup.long 0x0++0x3 line.long 0x0 "I3C_PID,Return to the . The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit:" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end tree "I3C0_P_ECC_AGGR_CFG" base ad:0x2A74000 rgroup.long 0x0++0x3 line.long 0x0 "I3C_P_REV,Return to the . Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "I3C_P_VECTOR,Return to the . ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "I3C_P_STAT,Return to the . Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "I3C_P_RESERVED_SVBUS_y,Return to the . Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "I3C_P_SEC_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "I3C_P_SEC_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "I3C_P_SEC_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "I3C_P_SEC_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "I3C_P_DED_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "I3C_P_DED_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "I3C_P_DED_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "I3C_P_DED_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" group.long 0x200++0xF line.long 0x0 "I3C_P_AGGR_ENABLE_SET,Return to the . AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "I3C_P_AGGR_ENABLE_CLR,Return to the . AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "I3C_P_AGGR_STATUS_SET,Return to the . AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "I3C_P_AGGR_STATUS_CLR,Return to the . AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "I3C0_S_ECC_AGGR_CFG" base ad:0x2A75000 rgroup.long 0x0++0x3 line.long 0x0 "I3C_S_REV,Return to the . Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "I3C_S_VECTOR,Return to the . ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "I3C_S_STAT,Return to the . Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "I3C_S_RESERVED_SVBUS_y,Return to the . Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "I3C_S_SEC_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "I3C_S_SEC_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1" bitfld.long 0x4 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1" bitfld.long 0x4 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1" newline bitfld.long 0x4 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1" bitfld.long 0x4 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1" bitfld.long 0x4 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1" bitfld.long 0x4 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1" newline bitfld.long 0x4 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1" bitfld.long 0x4 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "I3C_S_SEC_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1" bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1" newline bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "I3C_S_SEC_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1" bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1" newline bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "I3C_S_DED_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "I3C_S_DED_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1" bitfld.long 0x4 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1" bitfld.long 0x4 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1" newline bitfld.long 0x4 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1" bitfld.long 0x4 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1" bitfld.long 0x4 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1" bitfld.long 0x4 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1" newline bitfld.long 0x4 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1" bitfld.long 0x4 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "I3C_S_DED_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1" bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1" newline bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "I3C_S_DED_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1" bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1" newline bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1" group.long 0x200++0xF line.long 0x0 "I3C_S_AGGR_ENABLE_SET,Return to the . AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "I3C_S_AGGR_ENABLE_CLR,Return to the . AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "I3C_S_AGGR_STATUS_SET,Return to the . AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "I3C_S_AGGR_STATUS_CLR,Return to the . AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST" base ad:0x20A8000 rgroup.long 0x0++0xF line.long 0x0 "I3C_DEV_ID,Return to the . This register holds the IP identifier." hexmask.long.word 0x0 16.--31. 1. "RSVD0,Reserved." hexmask.long.word 0x0 0.--15. 1. "DEV_ID,Unique IP identifier within IP portfolio" line.long 0x4 "I3C_CONF_STATUS0,Return to the . The read-only Configuration Status Register 0 indicates the hardware configuration options chosen for implementation of the I3C-Master." bitfld.long 0x4 29.--31. "CMDR_MEM_DEPTH,CMD Resp MEM depth coded into 3 bits." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "ASF,Indicates supported ASF checks." newline hexmask.long.byte 0x4 16.--23. 1. "GPO_NUM,Returns the value of User GPO" hexmask.long.byte 0x4 8.--15. 1. "GPI_NUM,Returns the value of User GPI" newline bitfld.long 0x4 6.--7. "IBIR_MEM_DEPTH,IBI Resp MEM depth coded into 2 bits." "0,1,2,3" bitfld.long 0x4 5. "DDR,Indicates if DDR is supported." "0,1" newline bitfld.long 0x4 4. "DEV_ROLE,Returns status of Device Role [Main/Secondary Master]." "0,1" hexmask.long.byte 0x4 0.--3. 1. "DEVS_NUM,Returns the number of retaining registers for I3C Slave devices [Addresses and Characteristics] the max value is 11." line.long 0x8 "I3C_CONF_STATUS1,Return to the . The read-only Configuration Status Register 1 indicates the hardware configuration options chosen for implementation of the I3C-Master." hexmask.long.byte 0x8 28.--31. 1. "IBI_HW_RES,IBI resources" bitfld.long 0x8 26.--27. "CMD_MEM_DEPTH,CMD FIFO depth coded into 3 bits." "0,1,2,3" newline hexmask.long.byte 0x8 21.--25. 1. "SLV_DDR_RX_MEM_DEPTH,SLV DDR RX FIFO depth coded into 5 bits." hexmask.long.byte 0x8 16.--20. 1. "SLV_DDR_TX_MEM_DEPTH,SLV DDR TX FIFO depth coded into 5 bits." newline bitfld.long 0x8 13.--15. "RSVD0,Reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x8 10.--12. "IBI_MEM_DEPTH,IBI FIFO depth coded into 3 bits." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 5.--9. 1. "RX_MEM_DEPTH,RX FIFO depth coded into 5 bits." hexmask.long.byte 0x8 0.--4. 1. "TX_MEM_DEPTH,TX FIFO depth coded into 5 bits." line.long 0xC "I3C_REV_ID,Return to the . This register gives an information about particular version of the IP." hexmask.long.word 0xC 20.--31. 1. "VID,VENDOR_ID: IP vendor ID affected to IP [reset = 0xCAD]." hexmask.long.word 0xC 8.--19. 1. "PID,PRODUCT_ID: unique IP identifier within CDNS IP portfolio [reset = 0x13C]." newline bitfld.long 0xC 5.--7. "REV_MAJOR,X: Major revision value." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--4. 1. "REV_MINOR,Y: Minor revision value." group.long 0x10++0xB line.long 0x0 "I3C_CTRL,Return to the . Control Register for I3C Master IP - register that provides main control and configuration options for the controller." bitfld.long 0x0 31. "DEV_EN,When set HIGH the I3C-Master is enabled and it can initiates the I3C/I2C transactions." "0,1" bitfld.long 0x0 30. "HALT_EN,Enable halt on abort behavior." "0,1" newline bitfld.long 0x0 29. "MCS,Manual Command Start writing 1 starts execution of the commands currently in CMD Memories." "0,1" bitfld.long 0x0 28. "MCS_EN,Manual Command Start Enable if set 1 the IP will wait with starting of command execution until MCS but [" "0,1" newline rbitfld.long 0x0 27. "RSVD2,Reserved." "0,1" bitfld.long 0x0 26. "I3C_11_SUPP,Enables support for timing parameter that has been changed in v1.1 i.e." "0,1" newline bitfld.long 0x0 24.--25. "THD_DEL,Field that provides option to add data hold delay with respect to the SCL clock on which data on SDA is launched [applied only during actual Data transfer]" "0,1,2,3" hexmask.long.word 0x0 9.--23. 1. "RSVD1,Reserved." newline bitfld.long 0x0 8. "HJ_DISEC,This bit controls the HW response for ACK'ed HJ request." "0,1" bitfld.long 0x0 7. "MST_ACK,Specifies ACK response type for GETACCMST CCC it can be either ACK response type [mst_ack = 1] or NACK response type [mst_ack = 0]." "0,1" newline bitfld.long 0x0 6. "HJ_ACK,Specifies ACK response type for HJ request it can be either ACK response type [hj_ack = 1] or NACK response type [hj_ack = 0]." "0,1" bitfld.long 0x0 5. "HJ_INIT,Initiate HJ request - applicable only for Secondary master in slave mode." "0,1" newline bitfld.long 0x0 4. "MST_INIT,Initiate Mastership request - applicable only in slave mode." "0,1" bitfld.long 0x0 3. "AHDR_OPT,Enable[1]/Disable[0] the Address Header optimization." "0,1" newline rbitfld.long 0x0 2. "RSVD0,Reserved" "0,1" bitfld.long 0x0 0.--1. "BUS_MODE,Bus Mode" "0,1,2,3" line.long 0x4 "I3C_PRESCL_CTRL0,Return to the . Prescale settings for SDR/I2C modes" hexmask.long.word 0x4 16.--31. 1. "I2C,Prescaler value for I2C SCL clock generation." hexmask.long.byte 0x4 10.--15. 1. "RSVD0,Reserved" newline hexmask.long.word 0x4 0.--9. 1. "I3C,Prescaler value for I3C Push-Pull SDR Mode SCL clock generation." line.long 0x8 "I3C_PRESCL_CTRL1,Return to the . Prescale settings related to Open Drain / Push Pull I3C timings" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "PP_LOW,Counter for low period of SCL clock for Push Pull in I3C." newline hexmask.long.byte 0x8 0.--7. 1. "OD_LOW,Counter for low period of SCL clock for Open Drain in I3C." group.long 0x20++0x7 line.long 0x0 "I3C_MST_IER,Return to the . The write only Interrupt Enable Register is used to enable interrupts by setting bits in the read only Interrupt Mask Register - Master Mode (). See Interrupt Status Register - Master Mode () description for details on.." hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x0 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Enable." "0,1" bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Enable" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Enable." "0,1" bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Enable" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Enable." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Enable." "0,1" bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Enable" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Enable" "0,1" bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Enable." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Enable." "0,1" bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Enable." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Enable." "0,1" bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Enable." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Enable." "0,1" bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Enable." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Enable." "0,1" bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Enable." "0,1" line.long 0x4 "I3C_MST_IDR,Return to the . The write only Interrupt Disable Register is used to disable interrupts by clearing the bits in the read only Interrupt Mask Register - Master Mode (). See Interrupt Status Register - Master Mode () description for details on.." hexmask.long.word 0x4 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x4 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x4 17. "MR_DONE,Mastership handoff done Disable." "0,1" bitfld.long 0x4 16. "IMM_COMP,Immediate Commmand Completed Disable" "0,1" newline bitfld.long 0x4 15. "TX_THR,Tx Data Threshold Disable." "0,1" bitfld.long 0x4 14. "TX_OVF,Tx Data MEM Underflow Disable" "0,1" newline bitfld.long 0x4 13. "RSVD0,Reserved." "0,1" bitfld.long 0x4 12. "IBID_THR,IBI Data MEM threshold Disable." "0,1" newline bitfld.long 0x4 11. "IBID_UNF,IBI Data MEM underflow Disable." "0,1" bitfld.long 0x4 10. "IBIR_THR,IBI Response Queue threshold Disable" "0,1" newline bitfld.long 0x4 9. "IBIR_UNF,IBI Response Queue underflow Disable" "0,1" bitfld.long 0x4 8. "IBIR_OVF,IBI Response Queue onverflow Disable." "0,1" newline bitfld.long 0x4 7. "RX_THR,Rx Data MEM threshold Disable." "0,1" bitfld.long 0x4 6. "RX_UNF,Rx Data MEM underflow Disable." "0,1" newline bitfld.long 0x4 5. "CMDD_EMP,Command Request Queue Empty Disable." "0,1" bitfld.long 0x4 4. "CMDD_THR,Command Request Queue Threshold Disable." "0,1" newline bitfld.long 0x4 3. "CMDD_OVF,Command Request Queue Overflow Disable." "0,1" bitfld.long 0x4 2. "CMDR_THR,Command Response Queue Threshold Disable." "0,1" newline bitfld.long 0x4 1. "CMDR_UNF,Command Response Queue Underflow Disable." "0,1" bitfld.long 0x4 0. "CMDR_OVF,Command Response Queue Overflow Disable." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "I3C_MST_IMR,Return to the . This read only register. indicates the current state of the interrupts mask. See Interrupt Status Register - Master Mode () description for details on specific interrupt conditions. A high value indicates the interrupt is.." hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x0 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Mask." "0,1" bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Mask." "0,1" bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Mask." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Mask." "0,1" bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1" bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Mask." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Mask." "0,1" bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Mask." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Mask." "0,1" bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Mask." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Mask." "0,1" bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Mask." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Mask." "0,1" bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Mask." "0,1" group.long 0x2C++0x3 line.long 0x0 "I3C_MST_ICR,Return to the . Interrupt Clear Register for Master Mode of the cdnsi3c_master controller. Write 1 to clear (change from 1 to 0) corresponding bit in . Writing 0 has no effect" hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x0 18. "HALTED,Controller is in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Mask." "0,1" bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Mask." "0,1" bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Mask." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Mask." "0,1" bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1" bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Mask." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Mask." "0,1" bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Mask." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Mask." "0,1" bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Mask." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Mask." "0,1" bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Mask." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Mask." "0,1" bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Mask." "0,1" rgroup.long 0x30++0x3 line.long 0x0 "I3C_MST_ISR,Return to the . Interrupt Status Register for Master Mode of the cdnsi3c_master controller" hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x0 18. "HALTED,Controller in Halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done." "0,1" bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold." "0,1" bitfld.long 0x0 14. "TX_OVF,Tx Data MEM overflow" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow." "0,1" bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow" "0,1" bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold." "0,1" bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty." "0,1" bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow." "0,1" bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow." "0,1" bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow." "0,1" group.long 0x34++0x3 line.long 0x0 "I3C_MST_STATUS0,Return to the . Status Register for I3C Master IP. meaningful only when controller operates in Master mode." hexmask.long.word 0x0 19.--31. 1. "RSVD2,Reserved" rbitfld.long 0x0 18. "IDLE,Indicates when the core is IDLE and ready to accept new commands." "0,1" newline bitfld.long 0x0 17. "HALTED,Core Halted." "0,1" rbitfld.long 0x0 16. "OP_MODE,Indicates current mode of the controller:" "0,1" newline rbitfld.long 0x0 14.--15. "RSVD1,Reserved." "0,1,2,3" rbitfld.long 0x0 13. "TX_FULL,TX Full." "0,1" newline rbitfld.long 0x0 12. "IBID_FULL,IBID Full." "0,1" rbitfld.long 0x0 11. "IBIR_FULL" "0,1" newline rbitfld.long 0x0 10. "RX_FULL,RX Full." "0,1" rbitfld.long 0x0 9. "CMDD_FULL,CMDD Full." "0,1" newline rbitfld.long 0x0 8. "CMDR_FULL" "0,1" rbitfld.long 0x0 6.--7. "RSVD0,Reserved." "0,1,2,3" newline rbitfld.long 0x0 5. "TX_EMP,TX Empty." "0,1" rbitfld.long 0x0 4. "IBID_EMP,IBID Empty." "0,1" newline rbitfld.long 0x0 3. "IBIR_EMP" "0,1" rbitfld.long 0x0 2. "RX_EMP,RX Empty." "0,1" newline rbitfld.long 0x0 1. "CMDD_EMP,CMDD Empty." "0,1" rbitfld.long 0x0 0. "CMDR_EMP" "0,1" rgroup.long 0x38++0x7 line.long 0x0 "I3C_CMDR,Return to the . Stores status on completion of each command. works on FIFO-basis." hexmask.long.byte 0x0 28.--31. 1. "RSVD1,Reserved." hexmask.long.byte 0x0 24.--27. 1. "ERROR,This field contains the code of an error that has occured during the last transaction." newline hexmask.long.byte 0x0 20.--23. 1. "RSVD0,Reserved." hexmask.long.word 0x0 8.--19. 1. "XFER_BYTES,The number of transferred bytes [SDR] or transferred words [DDR] during the last command." newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ID,CMD_ID - command identifier." line.long 0x4 "I3C_IBIR,Return to the . Stores status of SIR on its completion. works on FIFO-basis." hexmask.long.tbyte 0x4 13.--31. 1. "RSVD0,Reserved" bitfld.long 0x4 12. "RESP,If HIGH IBI has been ACKed NACK response otherwise" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "SLV_ID,ID of a Slave that has issued an IBI request" bitfld.long 0x4 7. "ERROR,Set to 1 if IBI Data FIFO overflow has occured during the transaction." "0,1" newline hexmask.long.byte 0x4 2.--6. 1. "XFER_BYTES,Number of received DATA bytes." bitfld.long 0x4 0.--1. "IBI_TYPE,This field contains the type of an IBI." "0,1,2,3" wgroup.long 0x40++0x7 line.long 0x0 "I3C_SLV_IER,Return to the . The write only Interrupt Enable Register is used to enable interrupts by setting bits in the read only Interrupt Mask Register - Slave Mode (). See Interrupt Status Register - Slave Mode () description for details on specific.." hexmask.long.word 0x0 22.--31. 1. "RESERVED" bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Enable." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Enable." "0,1" bitfld.long 0x0 19. "ERROR,ERROR interrupt Enable." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Enable." "0,1" bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Enable." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Enable." "0,1" bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Enable" "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Enable" "0,1" bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Enable" "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Enable." "0,1" bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Enable." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Enable." "0,1" bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Enable." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SLV_SDR_TX_THR interrupt Enable." "0,1" bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Enable." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Enable." "0,1" bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Enable." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Enable." "0,1" bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Enable." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Enable." "0,1" bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Enable." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Enable." "0,1" line.long 0x4 "I3C_SLV_IDR,Return to the . The write only Interrupt Disable Register is used to disable interrupts by clearing the bits in the read only Interrupt Mask Register - Slave Mode (). See Interrupt Status Register - Slave Mode () description for details on.." hexmask.long.word 0x4 22.--31. 1. "RESERVED" bitfld.long 0x4 21. "DEFSLVS,DEFSLVS interrupt Disable." "0,1" newline bitfld.long 0x4 20. "TM,TM interrupt Disable." "0,1" bitfld.long 0x4 19. "ERROR,ERROR interrupt Disable." "0,1" newline bitfld.long 0x4 18. "EVENT_UP,EVENT_UP interrupt Disable." "0,1" bitfld.long 0x4 17. "HJ_DONE,HJ_DONE interrupt Disable." "0,1" newline bitfld.long 0x4 16. "MR_DONE,MR_DONE interrupt Disable." "0,1" bitfld.long 0x4 15. "DA_UPDATE,DA_UPDATE interrupt Disable." "0,1" newline bitfld.long 0x4 14. "SDR_FAIL,SDR_FAIL interrupt Disable" "0,1" bitfld.long 0x4 13. "DDR_FAIL,DDR_FAIL interrupt Disable" "0,1" newline bitfld.long 0x4 12. "M_RD_ABORT,M_RD_ABORT interrupt Disable." "0,1" bitfld.long 0x4 11. "DDR_RX_THR,DDR_RX_THR interrupt Disable." "0,1" newline bitfld.long 0x4 10. "DDR_TX_THR,DDR_TX_THR interrupt Disable." "0,1" bitfld.long 0x4 9. "SDR_RX_THR,SDR_RX_THR interrupt Disable." "0,1" newline bitfld.long 0x4 8. "SDR_TX_THR,SDR_TX_THR interrupt Disable." "0,1" bitfld.long 0x4 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Disable." "0,1" newline bitfld.long 0x4 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Disable." "0,1" bitfld.long 0x4 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Disable." "0,1" newline bitfld.long 0x4 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Disable." "0,1" bitfld.long 0x4 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Disable." "0,1" newline bitfld.long 0x4 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Disable." "0,1" bitfld.long 0x4 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Disable." "0,1" newline bitfld.long 0x4 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Disable." "0,1" rgroup.long 0x48++0x3 line.long 0x0 "I3C_SLV_IMR,Return to the . This read only register. indicates the current state of the interrupts mask. See Interrupt Status Register - Slave Mode () description for details on specific interrupt conditions. A high value indicates the interrupt is.." hexmask.long.word 0x0 22.--31. 1. "RESERVED" bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Mask." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Mask." "0,1" bitfld.long 0x0 19. "ERROR,ERROR interrupt Mask." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Mask." "0,1" bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Mask." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Mask." "0,1" bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Mask." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Mask" "0,1" bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Mask" "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Mask." "0,1" bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Mask." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Mask." "0,1" bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Mask." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SDR_TX_THR interrupt Mask." "0,1" bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Mask." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Mask." "0,1" bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Mask." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Mask." "0,1" bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Mask." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Mask." "0,1" bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Mask." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Mask." "0,1" wgroup.long 0x4C++0x3 line.long 0x0 "I3C_SLV_ICR,Return to the . Interrupt Clear Register for Slave Mode of the cdnsi3c_master controller. Write 1 to clear (change from 1 to 0) corresponding bit in . Writing 0 has no effect" hexmask.long.word 0x0 22.--31. 1. "RESERVED" bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Clear." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Clear." "0,1" bitfld.long 0x0 19. "ERROR,ERROR interrupt Clear." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Clear." "0,1" bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Clear." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Clear." "0,1" bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Clear." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Clear." "0,1" bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Clear." "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Clear." "0,1" bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Clear." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Clear." "0,1" bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Clear." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SDR_TX_THR interrupt Clear." "0,1" bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Clear." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Clear." "0,1" bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Clear." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Clear." "0,1" bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Clear." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Clear." "0,1" bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Clear." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Clear." "0,1" rgroup.long 0x50++0xB line.long 0x0 "I3C_SLV_ISR,Return to the . Interrupt Status Register for Slave Mode of the cdnsi3c_master controller" hexmask.long.word 0x0 22.--31. 1. "RESERVED" bitfld.long 0x0 21. "DEFSLVS,This interrupt is triggered whenever I3C-Slave DEFSLVS CCC command is received." "0,1" newline bitfld.long 0x0 20. "TM,This interrupt is triggered whenever I3C-Slave is not in Test Mode and ENTTM CCC command with byte value of 0x01 [general Test Mode] is received." "0,1" bitfld.long 0x0 19. "ERROR,This event is triggered whenever SDR Error is detected - applicable for S0 S1 S2 S4 and S5 Errors from MIPI spec." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,This event is triggered whenever DISEC CCC or ENEC CCC is received." "0,1" bitfld.long 0x0 17. "HJ_DONE,This event is triggered whenever Hot-Join request is completed." "0,1" newline bitfld.long 0x0 16. "MR_DONE,This event is triggered whenever Mastership Request is completed." "0,1" bitfld.long 0x0 15. "DA_UPDATE,This event is triggered whenever Dynamic Address of the device has been updated." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,This event is triggered whenever fail event during SDR transfer is detected [applicable for Private Write transfers only]." "0,1" bitfld.long 0x0 13. "DDR_FAIL,This event is triggered whenever fail event during DDR transfer is detected." "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,Read Transfer Aborted by Master." "0,1" bitfld.long 0x0 11. "DDR_RX_THR,This event is triggered whenever threshold level for DDR Rx DATA Buffer is reached." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,This event is triggered whenever threshold level for DDR Tx DATA Buffer is reached." "0,1" bitfld.long 0x0 9. "SDR_RX_THR,Rx DATA Buffer Threshold." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,Tx DATA Buffer Threshold." "0,1" bitfld.long 0x0 7. "DDR_RX_UNF,Set if the host attempts to read from the DDR_RX_FIFO register when there is no more data." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,Set if the host attempts to write to DDR_TX_FIFO register more times than the FIFO depth." "0,1" bitfld.long 0x0 5. "SDR_RX_UNF,Rx DATA Buffer Underflow." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,Tx DATA Buffer Overflow." "0,1" bitfld.long 0x0 3. "DDR_RD_COMP,This bit is set whenever the Slave terminates the DDR Read transfer." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,This bit is set whenever the Master terminates the DDR Write transfer." "0,1" bitfld.long 0x0 1. "SDR_RD_COMP,This bit is set whenever the Slave terminates the SDR Private Read transfer." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,This bit is set whenever the Master terminates the SDR Private Write transfer." "0,1" line.long 0x4 "I3C_SLV_STATUS0,Return to the . The read only Status 0 register () is provided to enable the continuous monitoring of the raw unmasked status information of the I3C-Master operating in Slave mode." hexmask.long.byte 0x4 24.--31. 1. "RSVD0,Reserved" hexmask.long.byte 0x4 16.--23. 1. "REG_ADDR,Private Read/Write Address." newline hexmask.long.word 0x4 0.--15. 1. "XFERRED_BYTES,Number of transferred bytes in SDR transactions." line.long 0x8 "I3C_SLV_STATUS1,Return to the . The read only Status 1 register () is provided to enable the continuous monitoring of the raw unmasked status information of the I3C-Master operating in Slave mode." hexmask.long.word 0x8 22.--31. 1. "RSVD1,Reserved" bitfld.long 0x8 20.--21. "ENTAS,Bits that indicate current Activity State." "0,1,2,3" newline bitfld.long 0x8 19. "VEN_TM,Vendor Test Mode." "0,1" bitfld.long 0x8 18. "HJ_DIS,Hot-Join Disabled." "0,1" newline bitfld.long 0x8 17. "MR_DIS,This bit is set whenever MR request is disabled by Current I3C-Master using DISEC CCC." "0,1" bitfld.long 0x8 16. "PROT_ERROR,Protocol Error Condition Indicator." "0,1" newline hexmask.long.byte 0x8 9.--15. 1. "DA,Slave Dynamic Address." bitfld.long 0x8 8. "HAS_DA,This bit is set whenever Slave has Dynamic Address assigned." "0,1" newline bitfld.long 0x8 7. "DDRRX_FULL,This bit is set whenever" "0,1" bitfld.long 0x8 6. "DDRTX_FULL,This bit is set whenever" "0,1" newline bitfld.long 0x8 5. "DDRRX_EMPTY,This bit is set whenever" "0,1" bitfld.long 0x8 4. "DDRTX_EMPTY,This bit is set whenever" "0,1" newline bitfld.long 0x8 3. "SDRRX_FULL,This bit is set whenever SDR_RX_FIFO is full." "0,1" bitfld.long 0x8 2. "SDRTX_FULL,This bit is set whenever SDR_TX_FIFO is full." "0,1" newline bitfld.long 0x8 1. "SDRRX_EMPTY,This bit is set whenever SDR_RX_FIFO is empty." "0,1" bitfld.long 0x8 0. "SDRTX_EMPTY,This bit is set whenever SDR_TX_FIFO is empty." "0,1" wgroup.long 0x60++0x3 line.long 0x0 "I3C_CMD0_FIFO,Return to the . Command0 FIFO. When implemented. the commands will be executed sequentially in order of arrival from the FW." bitfld.long 0x0 31. "IS_DDR,IS_DDR - DDR command." "0,1" bitfld.long 0x0 30. "IS_CCC,IsCCC." "0,1" newline bitfld.long 0x0 29. "BCH,BCH - Broadcast Header." "0,1" bitfld.long 0x0 27.--28. "XMIT_MODE,Defines transfer modes for I3C private read/write commands [not CCC] the following options are available:" "0,1,2,3" newline bitfld.long 0x0 26. "SBCA,SBCA - Sixteen Bits CSR Addressing." "0,1" bitfld.long 0x0 25. "RSBC,RSBC - Repeated Start Between Commands." "0,1" newline bitfld.long 0x0 24. "IS10B,Is10B - Normal/Extended Address." "0,1" hexmask.long.word 0x0 12.--23. 1. "PL_LEN,PL_LEN - Payload Length." newline bitfld.long 0x0 11. "RESERVED" "0,1" bitfld.long 0x0 8.--10. "DEV_ADDR_MSB,DEV_ADDR_MSB - legacy I2C Extended Address." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address." bitfld.long 0x0 0. "RNW,RnW - Read no Write." "0,1" group.long 0x64++0x3 line.long 0x0 "I3C_CMD1_FIFO,Return to the . Command 1 FIFO. When implemented. the commands will be executed sequentially in order of arrival from the FW." hexmask.long.byte 0x0 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]." hexmask.long.byte 0x0 16.--23. 1. "RSVD0,Reserved" newline hexmask.long.byte 0x0 8.--15. 1. "CSRADDR1,CSR ADDR" hexmask.long.byte 0x0 0.--7. 1. "CCC_CSRADDR0,CCC/CSR ADDR" wgroup.long 0x68++0x3 line.long 0x0 "I3C_TX_FIFO,Return to the . Tx Data FIFO which stores number of bytes to be sent with particular command. APB->I3C direction" hexmask.long 0x0 0.--31. 1. "DATA,Tx Data FIFO which stores number of bytes to be sent with particular command" wgroup.long 0x70++0x3 line.long 0x0 "I3C_IMD_CMD0,Return to the . High priority command register. When the core currently is executing a particular command from the CMD FIFO and new immediate command is sent. the core finish the standard command and then will execute the immediate command..." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED" bitfld.long 0x0 12.--14. "PL_LEN,PL_LEN - Payload Length." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address." newline bitfld.long 0x0 0. "RNW,RnW - Read no Write." "0,1" group.long 0x74++0x7 line.long 0x0 "I3C_IMD_CMD1,Return to the . High priority command register. When the core currently is executing a particular command from the CMD FIFO and new immediate command is sent. the core finish the standard command and then will execute the immediate command..." hexmask.long.byte 0x0 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]." hexmask.long.word 0x0 8.--23. 1. "RSVD0,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "CCC,CCC code" line.long 0x4 "I3C_IMD_DATA,Return to the . Payload/Data for a particular immediate command." hexmask.long 0x4 0.--31. 1. "DATA,Payload/Data for a particular immediate command." rgroup.long 0x80++0x7 line.long 0x0 "I3C_RX_FIFO,Return to the . Rx Data FIFO which stores number of bytes to be received with particular command. I3C->APB direction" hexmask.long 0x0 0.--31. 1. "DATA,Rx Data FIFO which stores number of bytes to be received with particular command." line.long 0x4 "I3C_IBI_DATA_FIFO,Return to the . IBI Data FIFO which stores number of bytes to be received for particular IBI request when BCR[2]=1 I3C->APB direction" hexmask.long 0x4 0.--31. 1. "DATA,IBI Data FIFO which stores number of bytes to be received for particular IBI request." wgroup.long 0x88++0x3 line.long 0x0 "I3C_SLV_DDR_TX_FIFO,Return to the . DDR Tx Data FIFO stores number of words to be sent with particular DDR command in slave mode. APB->I3C direction" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "DDR_SLAVE_TX_DATA_FIFO,DDR Tx Data FIFO stores number of words to be sent with particular DDR command in slave mode" rgroup.long 0x8C++0x3 line.long 0x0 "I3C_SLV_DDR_RX_FIFO,Return to the . DDR Rx Data FIFO stores number of words to be received with particular DDR command in slave mode. APB->I3C direction" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "DDR_SLAVE_RX_DATA_FIFO,DDR Rx Data FIFO stores number of words to be received with particular DDR command in slave mode" group.long 0x90++0xB line.long 0x0 "I3C_CMD_IBI_THR_CTRL,Return to the . Configuration register for Command and In-Band Interrupt data buffer thresholds." rbitfld.long 0x0 30.--31. "RSVD3,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "IBIR_THR,Threshold configuration value for IBI RESP memory block" newline rbitfld.long 0x0 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "CMDR_THR,Threshold configuration value for Command RESP memory block" newline rbitfld.long 0x0 14.--15. "RSVD1,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "IBID_THR,Threshold configuration value for IBI DATA memory block" newline rbitfld.long 0x0 5.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "CMDD_THR,Threshold configuration value for Command REQ memory block" line.long 0x4 "I3C_TX_RX_THR_CTRL,Return to the . Configuration register for Tx and Rx data buffer thresholds." hexmask.long.word 0x4 16.--31. 1. "RX_THR,Threshold configuration value for Rx Data memory block" hexmask.long.word 0x4 0.--15. 1. "TX_THR,Threshold configuration value for Tx Data memory block" line.long 0x8 "I3C_SLV_DDR_TX_RX_THR_CTRL,Return to the . Configuration register for Tx and Rx thresholds associated with Slave Mode DDR Data memory blocks." hexmask.long.word 0x8 16.--31. 1. "SLV_DDR_RX_THR,Threshold configuration value for Slave Mode DDR Rx Data memory block" hexmask.long.word 0x8 0.--15. 1. "SLV_DDR_TX_THR,Threshold configuration value for Slave Mode DDR Tx Data memory block" wgroup.long 0x9C++0x3 line.long 0x0 "I3C_FLUSH_CTRL,Return to the . Control register for FIFO soft flush control" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "IBI_RESP_FLUSH,When asserted while controller is disabled the IBI Response Queue read/write pointers will be set to 0 effectively make the FIFO empty." "0,1" newline bitfld.long 0x0 23. "CMD_RESP_FLUSH,When asserted while controller is disabled the Command Response Queue read/write pointers will be set to 0 effectively make the FIFO empty." "0,1" bitfld.long 0x0 22. "SLV_DDR_RX_FLUSH,When asserted while controller is disabled the SLV DDR Rx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty." "0,1" newline bitfld.long 0x0 21. "SLV_DDR_TX_FLUSH,When asserted while controller is disabled the SLV DDR Tx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty." "0,1" bitfld.long 0x0 20. "IMM_CMD_FLUSH,When asserted while controller is disabled the immediate command/data register will be cleared." "0,1" newline bitfld.long 0x0 19. "IBI_FLUSH,When asserted while controller is disabled the IBI data memory block read/write pointers will be set to 0." "0,1" bitfld.long 0x0 18. "RX_FLUSH,When asserted while controller is disabled the Rx Data memory block read/write pointers will be set to 0." "0,1" newline bitfld.long 0x0 17. "TX_FLUSH,When asserted while controller is disabled the Tx Data memory block read/write pointers will be set to 0." "0,1" bitfld.long 0x0 16. "CMD_FLUSH,When asserted while controller is disabled the command Command memory block read/write pointers will be set to 0." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED" group.long 0xB0++0xB line.long 0x0 "I3C_TTO_PRESCL_CTRL0,Return to the . Prescale settings for First SCL high timeout detection" hexmask.long.byte 0x0 26.--31. 1. "RSVD1,Reserved" hexmask.long.word 0x0 16.--25. 1. "DIV_B,Divider B" newline hexmask.long.byte 0x0 11.--15. 1. "RSVD0,Reserved" hexmask.long.word 0x0 0.--10. 1. "DIV_A,Divider A" line.long 0x4 "I3C_TTO_PRESCL_CTRL1,Return to the . Prescale settings for SCL high and low timeout detection" hexmask.long.byte 0x4 26.--31. 1. "RSVD1,Reserved" hexmask.long.word 0x4 16.--25. 1. "DIV_B,Divider B" newline hexmask.long.byte 0x4 8.--15. 1. "RSVD0,Reserved" hexmask.long.byte 0x4 0.--7. 1. "DIV_A,Divider A" line.long 0x8 "I3C_DEVS_CTRL,Return to the . Device control register" hexmask.long.byte 0x8 28.--31. 1. "RSVD1,Reserved." bitfld.long 0x8 27. "DEV11_CLR,Clear DevID11 retaining registers set." "0,1" newline bitfld.long 0x8 26. "DEV10_CLR,Clear DevID10 retaining registers set." "0,1" bitfld.long 0x8 25. "DEV9_CLR,Clear DevID9 retaining registers set." "0,1" newline bitfld.long 0x8 24. "DEV8_CLR,Clear DevID8 retaining registers set." "0,1" bitfld.long 0x8 23. "DEV7_CLR,Clear DevID7 retaining registers set." "0,1" newline bitfld.long 0x8 22. "DEV6_CLR,Clear DevID6 retaining registers set." "0,1" bitfld.long 0x8 21. "DEV5_CLR,Clear DevID5 retaining registers set." "0,1" newline bitfld.long 0x8 20. "DEV4_CLR,Clear DevID4 retaining registers set." "0,1" bitfld.long 0x8 19. "DEV3_CLR,Clear DevID3 retaining registers set." "0,1" newline bitfld.long 0x8 18. "DEV2_CLR,Clear DevID2 retaining registers set." "0,1" bitfld.long 0x8 17. "DEV1_CLR,Clear DevID1 retaining registers set." "0,1" newline hexmask.long.byte 0x8 12.--16. 1. "RSVD0,Reserved." bitfld.long 0x8 11. "DEV11_ACTIVE,DevID11 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 10. "DEV10_ACTIVE,DevID10 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 9. "DEV9_ACTIVE,DevID9 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 8. "DEV8_ACTIVE,DevID8 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 7. "DEV7_ACTIVE,DevID7 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 6. "DEV6_ACTIVE,DevID6 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 5. "DEV5_ACTIVE,DevID5 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 4. "DEV4_ACTIVE,DevID4 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 3. "DEV3_ACTIVE,DevID3 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 2. "DEV2_ACTIVE,DevID2 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 1. "DEV1_ACTIVE,DevID1 is active - has either valid DA or SA." "0,1" newline rbitfld.long 0x8 0. "DEV0_ACTIVE,DevID0 is active - has either valid DA or SA." "0,1" group.long 0xC0++0xB line.long 0x0 "I3C_DEV_ID0_RR0,Return to the . Device ID 0 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 0 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" rbitfld.long 0x0 9. "IS_I3C,Device 0 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 0 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID0_RR1,Return to the . Device ID 0 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 0 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID0_RR2,Return to the . Device ID 0 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 0 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 0 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 0 DCR [if I3C device] or LVR [if I2C device] register" group.long 0xD0++0xB line.long 0x0 "I3C_DEV_ID1_RR0,Return to the . Device ID 1 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 1 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 1 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 1 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID1_RR1,Return to the . Device ID 1 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 1 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID1_RR2,Return to the . Device ID 1 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 1 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 1 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 1 DCR [if I3C device] or LVR [if I2C device] register" group.long 0xE0++0xB line.long 0x0 "I3C_DEV_ID2_RR0,Return to the . Device ID 2 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 2 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 2 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 2 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID2_RR1,Return to the . Device ID 2 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 2 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID2_RR2,Return to the . Device ID 2 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 2 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 2 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 2 DCR [if I3C device] or LVR [if I2C device] register" group.long 0xF0++0xB line.long 0x0 "I3C_DEV_ID3_RR0,Return to the . Device ID 3 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 3 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 3 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 3 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID3_RR1,Return to the . Device ID 3 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 3 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID3_RR2,Return to the . Device ID 3 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 3 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 3 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 3 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x100++0xB line.long 0x0 "I3C_DEV_ID4_RR0,Return to the . Device ID 4 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 4 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 4 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 4 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID4_RR1,Return to the . Device ID 4 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 4 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID4_RR2,Return to the . Device ID 4 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 4 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 4 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 4 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x110++0xB line.long 0x0 "I3C_DEV_ID5_RR0,Return to the . Device ID 5 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 5 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 5 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 5 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID5_RR1,Return to the . Device ID 5 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 5 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID5_RR2,Return to the . Device ID 5 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 5 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 5 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 5 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x120++0xB line.long 0x0 "I3C_DEV_ID6_RR0,Return to the . Device ID 6 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 6 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 6 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 6 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID6_RR1,Return to the . Device ID 6 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 6 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID6_RR2,Return to the . Device ID 6 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 6 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 6 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 6 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x130++0xB line.long 0x0 "I3C_DEV_ID7_RR0,Return to the . Device ID 7 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 7 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 7 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 7 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID7_RR1,Return to the . Device ID 7 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 7 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID7_RR2,Return to the . Device ID 7 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 7 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 7 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 7 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x140++0xB line.long 0x0 "I3C_DEV_ID8_RR0,Return to the . Device ID 8 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 8 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 8 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 8 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID8_RR1,Return to the . Device ID 8 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 8 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID8_RR2,Return to the . Device ID 8 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 8 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 8 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 8 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x150++0xB line.long 0x0 "I3C_DEV_ID9_RR0,Return to the . Device ID 9 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 9 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 9 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 9 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID9_RR1,Return to the . Device ID 9 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 9 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID9_RR2,Return to the . Device ID 9 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 9 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 9 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 9 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x160++0xB line.long 0x0 "I3C_DEV_ID10_RR0,Return to the . Device ID 10 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 10 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 10 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 10 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID10_RR1,Return to the . Device ID 10 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 10 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID10_RR2,Return to the . Device ID 10 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 10 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 10 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 10 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x170++0xB line.long 0x0 "I3C_DEV_ID11_RR0,Return to the . Device ID 11 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 11 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 11 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 11 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID11_RR1,Return to the . Device ID 11 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 11 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID11_RR2,Return to the . Device ID 11 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 11 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 11 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 11 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x180++0x17 line.long 0x0 "I3C_SIR_MAP0,Return to the . Slave-initiated request Device ID Detection register0" bitfld.long 0x0 30.--31. "DEVID1_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3" bitfld.long 0x0 29. "DEVID1_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "DEVID1_PL,Slave-initiated request Device ID0 payload length" hexmask.long.byte 0x0 17.--23. 1. "DEVID1_DA,Slave-initiated request Device ID0 DA" newline bitfld.long 0x0 16. "DEVID1_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1" bitfld.long 0x0 14.--15. "DEVID0_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3" newline bitfld.long 0x0 13. "DEVID0_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x0 8.--12. 1. "DEVID0_PL,Slave-initiated request Device ID0 payload length" newline hexmask.long.byte 0x0 1.--7. 1. "DEVID0_DA,Slave-initiated request Device ID0 DA" bitfld.long 0x0 0. "DEVID0_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1" line.long 0x4 "I3C_SIR_MAP1,Return to the . Slave-initiated request Device ID Detection register1" bitfld.long 0x4 30.--31. "DEVID3_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3" bitfld.long 0x4 29. "DEVID3_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0x4 24.--28. 1. "DEVID3_PL,Slave-initiated request Device ID2 payload length" hexmask.long.byte 0x4 17.--23. 1. "DEVID3_DA,Slave-initiated request Device ID2 DA" newline bitfld.long 0x4 16. "DEVID3_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1" bitfld.long 0x4 14.--15. "DEVID2_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3" newline bitfld.long 0x4 13. "DEVID2_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x4 8.--12. 1. "DEVID2_PL,Slave-initiated request Device ID2 payload length" newline hexmask.long.byte 0x4 1.--7. 1. "DEVID2_DA,Slave-initiated request Device ID2 DA" bitfld.long 0x4 0. "DEVID2_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1" line.long 0x8 "I3C_SIR_MAP2,Return to the . Slave-initiated request Device ID Detection register2" bitfld.long 0x8 30.--31. "DEVID5_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3" bitfld.long 0x8 29. "DEVID5_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "DEVID5_PL,Slave-initiated request Device ID4 payload length" hexmask.long.byte 0x8 17.--23. 1. "DEVID5_DA,Slave-initiated request Device ID4 DA" newline bitfld.long 0x8 16. "DEVID5_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1" bitfld.long 0x8 14.--15. "DEVID4_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3" newline bitfld.long 0x8 13. "DEVID4_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x8 8.--12. 1. "DEVID4_PL,Slave-initiated request Device ID4 payload length" newline hexmask.long.byte 0x8 1.--7. 1. "DEVID4_DA,Slave-initiated request Device ID4 DA" bitfld.long 0x8 0. "DEVID4_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1" line.long 0xC "I3C_SIR_MAP3,Return to the . Slave-initiated request Device ID Detection register3" bitfld.long 0xC 30.--31. "DEVID7_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3" bitfld.long 0xC 29. "DEVID7_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0xC 24.--28. 1. "DEVID7_PL,Slave-initiated request Device ID6 payload length" hexmask.long.byte 0xC 17.--23. 1. "DEVID7_DA,Slave-initiated request Device ID6 DA" newline bitfld.long 0xC 16. "DEVID7_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1" bitfld.long 0xC 14.--15. "DEVID6_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3" newline bitfld.long 0xC 13. "DEVID6_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1" hexmask.long.byte 0xC 8.--12. 1. "DEVID6_PL,Slave-initiated request Device ID6 payload length" newline hexmask.long.byte 0xC 1.--7. 1. "DEVID6_DA,Slave-initiated request Device ID6 DA" bitfld.long 0xC 0. "DEVID6_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1" line.long 0x10 "I3C_SIR_MAP4,Return to the . Slave-initiated request Device ID Detection register4" bitfld.long 0x10 30.--31. "DEVID9_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3" bitfld.long 0x10 29. "DEVID9_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0x10 24.--28. 1. "DEVID9_PL,Slave-initiated request Device ID8 payload length" hexmask.long.byte 0x10 17.--23. 1. "DEVID9_DA,Slave-initiated request Device ID8 DA" newline bitfld.long 0x10 16. "DEVID9_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1" bitfld.long 0x10 14.--15. "DEVID8_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3" newline bitfld.long 0x10 13. "DEVID8_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x10 8.--12. 1. "DEVID8_PL,Slave-initiated request Device ID8 payload length" newline hexmask.long.byte 0x10 1.--7. 1. "DEVID8_DA,Slave-initiated request Device ID8 DA" bitfld.long 0x10 0. "DEVID8_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1" line.long 0x14 "I3C_SIR_MAP5,Return to the . Slave-initiated request Device ID Detection register5" hexmask.long.word 0x14 16.--31. 1. "RESERVED" bitfld.long 0x14 14.--15. "DEVID10_ROLE,Slave-initiated request Device ID10 BCR role" "0,1,2,3" newline bitfld.long 0x14 13. "DEVID10_SLOW,Slave-initiated request Device ID10 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x14 8.--12. 1. "DEVID10_PL,Slave-initiated request Device ID10 payload length" newline hexmask.long.byte 0x14 1.--7. 1. "DEVID10_DA,Slave-initiated request Device ID10 DA" bitfld.long 0x14 0. "DEVID10_RESP,Slave-initiated request Device ID10 Ack/Nack response" "0,1" rgroup.long 0x1A0++0x3 line.long 0x0 "I3C_GPIR_WORD0,Return to the . User Defined GPI Word 0: four 8-bits GPI Registers" hexmask.long.byte 0x0 24.--31. 1. "RSVD2,Reserved" hexmask.long.byte 0x0 16.--23. 1. "RSVD1,Reserved" newline hexmask.long.byte 0x0 8.--15. 1. "RSVD0,Reserved" hexmask.long.byte 0x0 0.--7. 1. "GPI0,User Defined GPI Register 0" rgroup.long 0x220++0x3 line.long 0x0 "I3C_GPOR_WORD0,Return to the . User Defined GPO Word 0: four 8-bits GPO Registers" hexmask.long.byte 0x0 24.--31. 1. "RSVD2,Reserved" hexmask.long.byte 0x0 16.--23. 1. "RSVD1,Reserved" newline hexmask.long.byte 0x0 8.--15. 1. "RSVD0,Reserved" hexmask.long.byte 0x0 0.--7. 1. "GPO0,User Defined GPO Register 0" group.long 0x300++0x13 line.long 0x0 "I3C_ASF_INT_STATUS,Return to the . ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the asf_fatal or.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "I3C_ASF_INT_RAW_STATUS,Return to the . ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both registers. For test.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "I3C_ASF_INT_MASK,Return to the . The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "I3C_ASF_INT_TEST,Return to the . The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "I3C_ASF_FATAL_NONFATAL_SELECT,Return to the . The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then fatal interrupt.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x320++0x7 line.long 0x0 "I3C_ASF_SRAM_CORR_FAULT_STATUS,Return to the . Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "I3C_ASF_SRAM_UNCORR_FAULT_STATUS,Return to the . Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." group.long 0x328++0x3 line.long 0x0 "I3C_ASF_SRAM_FAULT_STATS,Return to the . Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented." hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented." group.long 0x330++0xB line.long 0x0 "I3C_ASF_TRANS_TO_CTRL,Return to the . Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "I3C_ASF_TRANS_TO_FAULT_MASK,Return to the . Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The width.." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x4 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask bit for apb transaction timeout fault." "0,1" newline bitfld.long 0x4 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask bit for I3C transaction SCL low timeout fault." "0,1" bitfld.long 0x4 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask bit for I3C transaction SCL high timeout fault." "0,1" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask bit for I3C transaction first SCL high timeout fault." "0,1" line.long 0x8 "I3C_ASF_TRANS_TO_FAULT_STATUS,Return to the . Status register for transaction timeouts fault. If a fault occurs the relevant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x8 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for apb transaction timeout fault." "0,1" newline bitfld.long 0x8 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for I3C transaction SCL low timeout fault." "0,1" bitfld.long 0x8 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for I3C transaction SCL high timeout fault." "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for I3C transaction first SCL high timeout fault." "0,1" group.long 0x340++0x7 line.long 0x0 "I3C_ASF_PROTOCOL_FAULT_MASK,Return to the . Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The width of this.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x0 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_MASK,Mask bit for slv_sdr_rd_abort protocol fault source." "0,1" newline bitfld.long 0x0 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_MASK,Mask bit for slv_ddr_fail protocol fault source." "0,1" bitfld.long 0x0 10. "ASF_PROTOCOL_FAULT_S5_MASK,Mask bit for s5 protocol fault source." "0,1" newline bitfld.long 0x0 9. "ASF_PROTOCOL_FAULT_S4_MASK,Mask bit for s4 protocol fault source." "0,1" bitfld.long 0x0 8. "ASF_PROTOCOL_FAULT_S3_MASK,Mask bit for s3 protocol fault source." "0,1" newline bitfld.long 0x0 7. "ASF_PROTOCOL_FAULT_S2_MASK,Mask bit for s2 protocol fault source." "0,1" bitfld.long 0x0 6. "ASF_PROTOCOL_FAULT_S1_MASK,Mask bit for s1 protocol fault source." "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_FAULT_S0_MASK,Mask bit for s0 protocol fault source." "0,1" bitfld.long 0x0 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_MASK,Mask bit for mst_sdr_rd_abort protocol fault source." "0,1" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_MASK,Mask bit for mst_ddr_fail protocol fault source." "0,1" bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_M2_MASK,Mask bit for m2 protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_M1_MASK,Mask bit for m1 protocol fault source." "0,1" bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_M0_MASK,Mask bit for m0 protocol fault source." "0,1" line.long 0x4 "I3C_ASF_PROTOCOL_FAULT_STATUS,Return to the . Status register for protocol faults. If a fault occurs the relevant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x4 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_STATUS,Status bit for slv_sdr_rd_abort protocol fault." "0,1" newline bitfld.long 0x4 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_STATUS,Status bit for slv_ddr_fail protocol fault." "0,1" bitfld.long 0x4 10. "ASF_PROTOCOL_FAULT_S5_STATUS,Status bit for s5 protocol fault." "0,1" newline bitfld.long 0x4 9. "ASF_PROTOCOL_FAULT_S4_STATUS,Status bit for s4 protocol fault." "0,1" bitfld.long 0x4 8. "ASF_PROTOCOL_FAULT_S3_STATUS,Status bit for s3 protocol fault." "0,1" newline bitfld.long 0x4 7. "ASF_PROTOCOL_FAULT_S2_STATUS,Status bit for s2 protocol fault." "0,1" bitfld.long 0x4 6. "ASF_PROTOCOL_FAULT_S1_STATUS,Status bit for s1 protocol fault." "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_FAULT_S0_STATUS,Status bit for s0 protocol fault." "0,1" bitfld.long 0x4 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_STATUS,Status bit for mst_sdr_rd_abort protocol fault." "0,1" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_STATUS,Status bit for mst_ddr_fail protocol fault." "0,1" bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_M2_STATUS,Status bit for m2 protocol fault." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_M1_STATUS,Status bit for m1 protocol fault." "0,1" bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_M0_STATUS,Status bit for m0 protocol fault." "0,1" tree.end tree.end tree "MAIN2MCU" base ad:0x0 tree "MAIN2MCU_LVL_INTRTR0_CFG" base ad:0xA10000 rgroup.long 0x0++0x3 line.long 0x0 "MAIN2MCU_LVL_INTRTR0_PID,Peripheral identification register. Uniquely identifies the module and its specific revision." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "MAIN2MCU_LVL_INTRTR0_MUXCNTL_n,Interrupt mux control register. Offset = 4h + (n * 4h); where n = 0h to 3Fh." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "INT_ENABLE,Enable for interrupt output N" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--8. 1. "ENABLE,Mux control for interrupt output N" tree.end tree "MAIN2MCU_PLS_INTRTR0_CFG" base ad:0xA20000 rgroup.long 0x0++0x3 line.long 0x0 "MAIN2MCU_PLS_INTRTR0_PID,Peripheral identification register. Uniquely identifies the module and its specific revision." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "MAIN2MCU_PLS_INTRTR0_MUXCNTL_n,Interrupt mux control register. Offset = 4h + (n * 4h); where n = 0h to 2Fh." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "INT_ENABLE,Enable for interrupt output N" "0,1" hexmask.long.word 0x0 7.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--6. 1. "ENABLE,Mux control for interrupt output N" tree.end tree.end tree "MCAN" base ad:0x0 tree "MCAN0" tree "MCAN0_CFG" base ad:0x1000 rgroup.long 0x2700000++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0x270000C++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x2700040++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x2700048++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x2700050++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x2700080++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x2700090++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x2700094++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x2700098++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0x27000A4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0x27000A8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0x27000B4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0x27000B8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0x27000C4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0x27000C8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0x27000CC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0x27000D0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0x27000D8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0x27000E0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0x27000F0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0x27000F4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0x27000F8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN0_ECC_AGGR" base ad:0x8000 rgroup.long 0x2A70000++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x2A70008++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0x2A7000C++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x2A7003C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x2A70080++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x2A700C0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x2A7013C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x2A70180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x2A701C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x2A70200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end base ad:0x0 tree "MCAN0_SS" rgroup.long 0x2700000++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x2700004++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x2700008++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0x270000C++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x270001C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x2700020++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x2700028++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN1" tree "MCAN1_CFG" base ad:0x1000 rgroup.long 0x2710000++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0x271000C++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x2710040++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x2710048++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x2710050++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x2710080++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x2710090++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x2710094++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x2710098++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0x27100A4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0x27100A8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0x27100B4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0x27100B8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0x27100C4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0x27100C8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0x27100CC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0x27100D0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0x27100D8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0x27100E0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0x27100F0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0x27100F4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0x27100F8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN1_ECC_AGGR" base ad:0x9000 rgroup.long 0x2A70000++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x2A70008++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0x2A7000C++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x2A7003C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x2A70080++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x2A700C0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x2A7013C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x2A70180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x2A701C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x2A70200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end base ad:0x0 tree "MCAN1_SS" rgroup.long 0x2710000++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x2710004++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x2710008++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0x271000C++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x271001C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x2710020++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x2710028++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCAN10_CFG" base ad:0x27A1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN10_ECC_AGGR" base ad:0x2A42000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN10_SS" base ad:0x27A0000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCAN11_CFG" base ad:0x27B1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN11_ECC_AGGR" base ad:0x2A43000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN11_SS" base ad:0x27B0000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCAN12_CFG" base ad:0x27C1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN12_ECC_AGGR" base ad:0x2A44000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN12_SS" base ad:0x27C0000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCAN13_CFG" base ad:0x27D1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN13_ECC_AGGR" base ad:0x2A45000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN13_SS" base ad:0x27D0000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCAN14_CFG" base ad:0x2681000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN14_ECC_AGGR" base ad:0x2A46000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN14_SS" base ad:0x2680000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCAN15_CFG" base ad:0x2691000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN15_ECC_AGGR" base ad:0x2A47000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN15_SS" base ad:0x2690000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCAN16_CFG" base ad:0x26A1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN16_ECC_AGGR" base ad:0x2A48000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN16_SS" base ad:0x26A0000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCAN17_CFG" base ad:0x26B1000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN17_ECC_AGGR" base ad:0x2A49000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN17_SS" base ad:0x26B0000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN2" tree "MCAN2_CFG" base ad:0x2721000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN2_ECC_AGGR" base ad:0x2A7A000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN2_SS" base ad:0x2720000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN3" tree "MCAN3_CFG" base ad:0x2731000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN3_ECC_AGGR" base ad:0x2A7B000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN3_SS" base ad:0x2730000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN4" tree "MCAN4_CFG" base ad:0x2741000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN4_ECC_AGGR" base ad:0x2A7C000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN4_SS" base ad:0x2740000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN5" tree "MCAN5_CFG" base ad:0x2751000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN5_ECC_AGGR" base ad:0x2A7D000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN5_SS" base ad:0x2750000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN6" tree "MCAN6_CFG" base ad:0x2761000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN6_ECC_AGGR" base ad:0x2A7E000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN6_SS" base ad:0x2760000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN7" tree "MCAN7_CFG" base ad:0x2771000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN7_ECC_AGGR" base ad:0x2A7F000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN7_SS" base ad:0x2770000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN8" tree "MCAN8_CFG" base ad:0x2781000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN8_ECC_AGGR" base ad:0x2A40000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN8_SS" base ad:0x2780000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCAN9" tree "MCAN9_CFG" base ad:0x2791000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCAN9_ECC_AGGR" base ad:0x2A41000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCAN9_SS" base ad:0x2790000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree.end tree "MCASP" base ad:0x0 tree "MCASP0_CFG" base ad:0x2B00000 rgroup.long 0x0++0x3 line.long 0x0 "MCASP_PID" bitfld.long 0x0 30.--31. "SCHEME,Distinguishes between old scheme and current." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Indicates a software-compatible module family." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version." bitfld.long 0x0 8.--10. "REVMAJOR,Major revision number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a given device." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMINOR,Minor revision number." group.long 0x4++0x3 line.long 0x0 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG register." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLE_MODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state. 0h = Force-idle mode: local target's idle state follows (acknowledges) the.." "0,1,2,3" group.long 0x10++0xB line.long 0x0 "MCASP_PFUNC" bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Determines if AXR15 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 14. "AXR14,Determines if AXR14 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 13. "AXR13,Determines if AXR13 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 12. "AXR12,Determines if AXR12 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 11. "AXR11,Determines if AXR11 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 10. "AXR10,Determines if AXR10 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 9. "AXR9,Determines if AXR9 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 8. "AXR8,Determines if AXR8 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 7. "AXR7,Determines if AXR7 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 6. "AXR6,Determines if AXR6 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 5. "AXR5,Determines if AXR5 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 4. "AXR4,Determines if AXR4 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 3. "AXR3,Determines if AXR3 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 2. "AXR2,Determines if AXR2 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 1. "AXR1,Determines if AXR1 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 0. "AXR0,Determines if AXR0 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" line.long 0x4 "MCASP_PDIR" bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" hexmask.long.word 0x4 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "AXR15,Determines if AXR15 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 14. "AXR14,Determines if AXR14 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 13. "AXR13,Determines if AXR13 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 12. "AXR12,Determines if AXR12 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 11. "AXR11,Determines if AXR11 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 10. "AXR10,Determines if AXR10 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 9. "AXR9,Determines if AXR9 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 8. "AXR8,Determines if AXR8 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 7. "AXR7,Determines if AXR7 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 6. "AXR6,Determines if AXR6 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 5. "AXR5,Determines if AXR5 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 4. "AXR4,Determines if AXR4 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 3. "AXR3,Determines if AXR3 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 2. "AXR2,Determines if AXR2 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 1. "AXR1,Determines if AXR1 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 0. "AXR0,Determines if AXR0 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" line.long 0x8 "MCASP_PDOUT" bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the correspondingMCASP_PFUNC[25] and MCASP_PDIR[25] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" hexmask.long.word 0x8 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCASP_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR." bitfld.long 0x0 31. "AFSR,Logic level on AFSR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 30. "AHCLKR,Logic level on AHCLKR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 29. "ACLKR,Logic level on ACLKR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 28. "AFSX,Logic level on AFSX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 27. "AHCLKX,Logic level on AHCLKX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 26. "ACLKX,Logic level on ACLKX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 25. "AMUTE,Logic level on AMUTE pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Logic level on AXR15 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 14. "AXR14,Logic level on AXR14 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 13. "AXR13,Logic level on AXR13 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 12. "AXR12,Logic level on AXR12 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 11. "AXR11,Logic level on AXR11 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 10. "AXR10,Logic level on AXR10 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 9. "AXR9,Logic level on AXR9 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 8. "AXR8,Logic level on AXR8 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 7. "AXR7,Logic level on AXR7 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 6. "AXR6,Logic level on AXR6 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 5. "AXR5,Logic level on AXR5 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 4. "AXR4,Logic level on AXR4 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 3. "AXR3,Logic level on AXR3 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 2. "AXR2,Logic level on AXR2 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 1. "AXR1,Logic level on AXR1 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 0. "AXR0,Logic level on AXR0 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" group.long 0x1C++0x7 line.long 0x0 "MCASP_PDSET,The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x0 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 30. "AHCLKR,Allows the corresponding AHCLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 25. "AMUTE,Allows the corresponding AMUTE bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Allows the corresponding AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 14. "AXR14,Allows the corresponding AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 13. "AXR13,Allows the corresponding AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 12. "AXR12,Allows the corresponding AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 11. "AXR11,Allows the corresponding AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 10. "AXR10,Allows the corresponding AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 9. "AXR9,Allows the corresponding AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 8. "AXR8,Allows the corresponding AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 7. "AXR7,Allows the corresponding AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 6. "AXR6,Allows the corresponding AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 5. "AXR5,Allows the corresponding AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 4. "AXR4,Allows the corresponding AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 3. "AXR3,Allows the corresponding AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 2. "AXR2,Allows the corresponding AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 1. "AXR1,Allows the corresponding AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 0. "AXR0,Allows the corresponding AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" line.long 0x4 "MCASP_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a.." bitfld.long 0x4 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 30. "AHCLKR,Allows the corresponding AHCLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 25. "AMUTE,Allows the corresponding AMUTE bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" hexmask.long.word 0x4 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "AXR15,Allows the corresponding AXR[15] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 14. "AXR14,Allows the corresponding AXR[14] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 13. "AXR13,Allows the corresponding AXR[13] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 12. "AXR12,Allows the corresponding AXR[12] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 11. "AXR11,Allows the corresponding AXR[11] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 10. "AXR10,Allows the corresponding AXR[10] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 9. "AXR9,Allows the corresponding AXR[9] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 8. "AXR8,Allows the corresponding AXR[8] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 7. "AXR7,Allows the corresponding AXR[7] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 6. "AXR6,Allows the corresponding AXR[6] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 5. "AXR5,Allows the corresponding AXR[5] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 4. "AXR4,Allows the corresponding AXR[4] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 3. "AXR3,Allows the corresponding AXR[3] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 2. "AXR2,Allows the corresponding AXR[2] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 1. "AXR1,Allows the corresponding AXR[1] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 0. "AXR0,Allows the corresponding AXR[0] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" group.long 0x30++0xB line.long 0x0 "MCASP_TLGC,for IODFT" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 14.--15. "MT,MISR on/off trigger command. These monitor trigger codes only are affective for the MISR signature capture when MC = 3h. MT Code effect on MISR: 0h = MISR capture start on the first active cycle decode of the IP bus activity and continues to update.." "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "MMS,Chooses the source of the MISR input: 0h = output register 1h = input capture" "0,1" bitfld.long 0x0 7. "ESEL,Output enable select: 0h = test mode and the functional OEN is gated off 1h = normal functional mode" "0,1" newline bitfld.long 0x0 6. "TOEN,Test output enable control. This signal is paired with ESEL. TOEN is never 1 when ESEL is 1. When ESEL is 0 (test mode) TOEN is: 0h = output enabled 1h = output disabled Note: In boundary scan mode this signal is not selected and the BSR controls.." "0,1" bitfld.long 0x0 4.--5. "MC,This defines the states of the MISR: 0h = download results 1h = hold current value 2h = load initial value (from PC bits) 3h = MISR enable to capture signature" "0,1,2,3" bitfld.long 0x0 1.--3. "PC,Pattern code defines the type of pattern that is selected for the artificial pattern generation logic in the IODFT. Modes: 0h = functional (default) 1h = random XOR 2h = random XNOR 3h = shift register 4h = hold current value Note: McASP does not have.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "TM,At reset the value is 1 for normal functional mode. This bit is tied high and should not be written to." "0,1" line.long 0x4 "MCASP_TLMR,for IODFT" hexmask.long 0x4 0.--31. 1. "TLMR,This contains the result signature of a given test after the download function is executed." line.long 0x8 "MCASP_TLEC,for IODFT" hexmask.long 0x8 0.--31. 1. "TLEC,Contains the number of cycles during which the MISR signature will be accumulated." group.long 0x44++0xF line.long 0x0 "MCASP_GBLCTL" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit.0h = Transmit frame sync generator is reset. 1h = Transmit frame sync generator is active. When released from reset the transmit frame sync generator begins counting serial clocks and generating frame.." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit.0h = Transmit state machine is held in reset. AXRn pin state: If 1h = Transmit state machine is released from reset. When released from reset the transmit state machine immediately transfers data from.." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit.0h = Transmit high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Transmit high-frequency clock divider is running." "0,1" newline bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit.0h = Transmit clock divider is held in reset. When the clock divider is in reset it passes through a divide-by-1 of its input. 1h = Transmit clock divider is running." "0,1" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit.0h = Receive frame sync generator is reset. 1h = Receive frame sync generator is active. When released from reset the receive frame sync generator begins counting serial clocks and generating frame.." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit.0h = Receive state machine is held in reset. 1h = Receive state machine is released from reset. When released from reset the receive state machine immediately begins detecting frame sync and is ready to.." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed. 0h = Receive serializers are cleared. 1h = Receive serializers are active." "0,1" newline bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit.0h = Receive high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Receive high-frequency clock divider is running." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit.0h = Receive clock divider is held in reset. When the clock divider is in reset it passes through a divide-by-1 of its input. 1h = Receive clock divider is running." "0,1" line.long 0x4 "MCASP_AMUTE" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit DMA error is ignored by 1h = Drive is enabled (active). Upon detection of transmit DMA error " "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receive DMA error is ignored by 1h = Drive is enabled (active). Upon detection of receive DMA error " "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit clock failure is ignored by 1h = Drive is enabled (active). Upon detection of transmit clock failure " "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receive clock failure is ignored by 1h = Drive is enabled (active). Upon detection of receive clock failure " "0,1" newline bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of unexpected transmit frame sync error is ignored by 1h = Drive is enabled (active). Upon detection of unexpected transmit.." "0,1" bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of unexpected receive frame sync error is ignored by 1h = Drive is enabled (active). Upon detection of unexpected receive.." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit underrun error is ignored by 1h = Drive is enabled (active). Upon detection of transmit underrun error " "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receiver overrun error is ignored by 1h = Drive is enabled (active). Upon detection of receiver overrun error " "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin whenMCASP_PFUNC[n] and MCASP_PDIR[n] bits are set to 1. 0h = AMUTEIN pin is inactive. 1h = AMUTEIN pin is active. Audio mute in error is detected." "0,1" newline bitfld.long 0x4 3. "INEN,DriveMCASP_AMUTE active when AMUTEIN error is active [INSTAT = 1]. 0h = Drive is disabled. AMUTEIN is ignored by 1h = Drive is enabled (active). INSTAT = 1 drives" "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit.0h = Polarity is active high. A high on AMUTEIN sets INSTAT to 1. 1h = Polarity is active low. A low on AM UTEIN sets INSTAT to 1." "0,1" bitfld.long 0x4 0.--1. "MUTEN,MCASP_AMUTE pin enable bit [unless overridden by GPIO registers]. 0h = 1h = 2h = 3h = Reserved" "0,1,2,3" line.long 0x8 "MCASP_LBCTL" hexmask.long 0x8 5.--31. 1. "RESERVED" bitfld.long 0x8 4. "IOLBEN,I/O loopback enable. Chip-level loopback; looped back through I/O buffers. 0h = I/O loopback disabled 1h = I/O loopback enabled Note: These are only valid if LBEN = 1. If LBEN = 0 neither internal nor I/O loopback will be selected." "0,1" bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]. 0h = Default and reserved on loopback mode (DLBEN = 1). When in non-loopback mode (DLBEN = 0) MODE should be left at default (00). When in loopback mode (DLBEN =.." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1].0h = Odd serializers N + 1 transmit to even serializers N that receive. The corresponding serializers must be programmed properly. 1h = Even serializers N transmit to odd serializers N + 1.." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit.0h = Loopback mode is disabled. 1h = Loopback mode is enabled." "0,1" line.long 0xC "MCASP_TXDITCTL" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe].0h = V bit is 0 during odd DIT subframes. 1h = V bit is 1 during odd DIT subframes." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe].0h = V bit is 0 during even DIT subframes. 1h = V bit is 1 during even DIT subframes." "0,1" bitfld.long 0xC 1. "RESERVED,Reserved" "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in MCASP_GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in MCASP_GBLCTL to change DITEN. 0h = DIT.." "0,1" group.long 0x60++0x23 line.long 0x0 "MCASP_GBLCTLR" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" bitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of MCASP_GBLCTL. 0h = Receive frame sync generator is reset. 1h = Receive frame sync generator is active." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of MCASP_GBLCTL. 0h = Receive state machine is held in reset. 1h = Receive state machine is released from reset." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of MCASP_GBLCTL. 0h = Receive serializers are cleared. 1h = Receive serializers are active." "0,1" newline bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of MCASP_GBLCTL. 0h = Receive high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Receive.." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of MCASP_GBLCTL. 0h = Receive clock divider is held in reset. 1h = Receive clock divider is running." "0,1" line.long 0x4 "MCASP_RXMASK" bitfld.long 0x4 31. "RMASK31,Receive data mask 31 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 30. "RMASK30,Receive data mask 30 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 29. "RMASK29,Receive data mask 29 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 28. "RMASK28,Receive data mask 28 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 27. "RMASK27,Receive data mask 27 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 26. "RMASK26,Receive data mask 26 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 25. "RMASK25,Receive data mask 25 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 24. "RMASK24,Receive data mask 24 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 23. "RMASK23,Receive data mask 23 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 22. "RMASK22,Receive data mask 22 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 21. "RMASK21,Receive data mask 21 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 20. "RMASK20,Receive data mask 20 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 19. "RMASK19,Receive data mask 19 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 18. "RMASK18,Receive data mask 18 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 17. "RMASK17,Receive data mask 17 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 16. "RMASK16,Receive data mask 16 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 15. "RMASK15,Receive data mask 15 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 14. "RMASK14,Receive data mask 14 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 13. "RMASK13,Receive data mask 13 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 12. "RMASK12,Receive data mask 12 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 11. "RMASK11,Receive data mask 11 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 10. "RMASK10,Receive data mask 10 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 9. "RMASK9,Receive data mask 9 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 8. "RMASK8,Receive data mask 8 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 7. "RMASK7,Receive data mask 7 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 6. "RMASK6,Receive data mask 6 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 5. "RMASK5,Receive data mask 5 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 4. "RMASK4,Receive data mask 4 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 3. "RMASK3,Receive data mask 3 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 2. "RMASK2,Receive data mask 2 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 1. "RMASK1,Receive data mask 1 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 0. "RMASK0,Receive data mask 0 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" line.long 0x8 "MCASP_RXFMT" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay.0h = 0-bit delay. The first receive data bit AXRn occurs in same ACLKR cycle as the receive frame sync (AFSR). 1h = 1-bit delay. The first receive data bit AXRn occurs one ACLKR cycle after the receive frame sync (AFSR). 2h.." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order.0h = Bitstream is LSB first. No bit reversal is performed in receive format bit reverse unit. 1h = Bitstream is MSB first. Bit reversal is performed in receive format bit reverse unit." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when MCASP_RMASK[n] = 0. 0h = Pad extra bits with 0. 1h = Pad extra bits with 1. 2h = Pad extra bits with one of the bits from the word as specified by RPBIT.." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h. 0h = Pad with bit 0 value. 1h = Pad with bit 1 to bit 31 value from 1h to 1Fh." newline hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size.0h = Reseved. 1h = Reserved. 2h = Reserved. 3h = Slot size is 8 bits. 4h = Reserved 5h = Slot size is 12 bits. 6h = Reserved 7h = Slot size is 16 bits. 8h = Reserved 9h = Slot size is 20 bits. Ah = Reserved Bh = Slot size is 24.." bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port.0h = Reads from XRBUF[n] originate on data port. Reads from XRBUF[n] on configuration bus are ignored. 1h = Reads from XRBUF[n].." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit.0h = Rotate right by 0 (no rotation). 1h = Rotate right by 4 bit positions. 2h = Rotate right by 8 bit positions. 3h = Rotate right by 12 bit positions. 4h = Rotate right by 16 bit positions." "0,1,2,3,4,5,6,7" line.long 0xC "MCASP_RXFMCTL" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh. 0h = Burst mode. 1h = Reserved. 2h = 2-slot TDM (I2S mode) to 32-slot TDM from 2h to 20h. 21h = Reserved from 21h to 17Fh. 180h = 384-slot TDM (external DIR IC inputting.." bitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period.0h = Single bit. 1h = Single word." "0,1" bitfld.long 0xC 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit.0h = Externally-generated receive frame sync. 1h = Internally-generated receive frame sync." "0,1" bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit.0h = A rising edge on receive frame sync (AFSR) indicates the beginning of a frame. 1h = A falling edge on receive frame sync (AFSR) indicates the beginning of a frame." "0,1" line.long 0x10 "MCASP_ACLKRCTL" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Тhe OR of bits 18 and 19 indicating that some clk change is in progress when high." "0,1" bitfld.long 0x10 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x10 18. "ADJBUSY,One-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment contro.l If CLKRDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock no adjustment 1h = (m-1) input clocks per output clock 2h =.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "CLKRP,Bitstream clock polarity for receive section: 0h = Falling Edge. Receiver captures sample data on the falling edge of the serial clock so the EXTERNAL transmitter driving this receiver must shift data out on the rising edge of the serial clock. 1h.." "0,1" bitfld.long 0x10 6. "RESERVED,Reserved" "0,1" bitfld.long 0x10 5. "CLKRM,Receive clock source: 0h = External Transmit Clock From ACLKR pin 1h = Internal (output of divider) output clock on ACLKR pin." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive clock divide ratio from high frequency transmit clock: 00000b = /1 00001b = /2 . . . 11111b = /32 All values between /1 and /32 are supported." line.long 0x14 "MCASP_AHCLKRCTL" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,The OR of bits 18 and 19 indicating that some clk change is in progress when high." "0,1" bitfld.long 0x14 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x14 18. "ADJBUSY,One-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)." "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment control If HCLKRDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline bitfld.long 0x14 15. "HCLKRM,High frequency receive clock source: 0h = External Clock on AHCLKR pin passes through divider (typically set to /1). 1h = Internal CPU Clock passed through divider. Divider output on AHCLKR pin." "0,1" bitfld.long 0x14 14. "HCLKRP,high frequency clock polarity: 0h = AHCLKR not inverted before divider. Rising Edge of AHCLKR causes edges on ACLKR when internally generated. 1h = AHCLKR inverted before divider. Falling Edge of AHCLK causes edges on ACLKR when internally.." "0,1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive clock divide ratio from CPU master clock or external high frequency clock: 0000 0000 0000b = /1 0000 0000 0001b = /2 . . . 1111 1111 1111b = /4096 All values between /1 and /4096 are supported." line.long 0x18 "MCASP_RXTDM" bitfld.long 0x18 31. "RTDMS31,Receiver mode during TDM time slot 31.0h = Receive TDM time slot 31 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 31 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 30. "RTDMS30,Receiver mode during TDM time slot 30.0h = Receive TDM time slot 30 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 30 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 29. "RTDMS29,Receiver mode during TDM time slot 29.0h = Receive TDM time slot 29 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 29 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 28. "RTDMS28,Receiver mode during TDM time slot 28.0h = Receive TDM time slot 28 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 28 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 27. "RTDMS27,Receiver mode during TDM time slot 27.0h = Receive TDM time slot 27 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 27 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 26. "RTDMS26,Receiver mode during TDM time slot 26.0h = Receive TDM time slot 26 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 26 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 25. "RTDMS25,Receiver mode during TDM time slot 25.0h = Receive TDM time slot 25 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 25 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 24. "RTDMS24,Receiver mode during TDM time slot 24.0h = Receive TDM time slot 24 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 24 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 23. "RTDMS23,Receiver mode during TDM time slot 23.0h = Receive TDM time slot 23 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 23 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 22. "RTDMS22,Receiver mode during TDM time slot 22.0h = Receive TDM time slot 22 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 22 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 21. "RTDMS21,Receiver mode during TDM time slot 21.0h = Receive TDM time slot 21 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 21 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 20. "RTDMS20,Receiver mode during TDM time slot 20.0h = Receive TDM time slot 20 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 20 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 19. "RTDMS19,Receiver mode during TDM time slot 19.0h = Receive TDM time slot 19 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 19 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 18. "RTDMS18,Receiver mode during TDM time slot 18.0h = Receive TDM time slot 18 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 18 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 17. "RTDMS17,Receiver mode during TDM time slot 17.0h = Receive TDM time slot 17 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 17 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 16. "RTDMS16,Receiver mode during TDM time slot 16.0h = Receive TDM time slot 16 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 16 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 15. "RTDMS15,Receiver mode during TDM time slot 15.0h = Receive TDM time slot 15 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 15 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 14. "RTDMS14,Receiver mode during TDM time slot 14.0h = Receive TDM time slot 14 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 14 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 13. "RTDMS13,Receiver mode during TDM time slot 13.0h = Receive TDM time slot 13 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 13 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 12. "RTDMS12,Receiver mode during TDM time slot 12.0h = Receive TDM time slot 12 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 12 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 11. "RTDMS11,Receiver mode during TDM time slot 11.0h = Receive TDM time slot 11 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 11 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 10. "RTDMS10,Receiver mode during TDM time slot 10.0h = Receive TDM time slot 10 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 10 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 9. "RTDMS9,Receiver mode during TDM time slot 9.0h = Receive TDM time slot 9 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 9 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 8. "RTDMS8,Receiver mode during TDM time slot 8.0h = Receive TDM time slot 8 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 8 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 7. "RTDMS7,Receiver mode during TDM time slot 7.0h = Receive TDM time slot 7 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 7 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 6. "RTDMS6,Receiver mode during TDM time slot 6.0h = Receive TDM time slot 6 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 6 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 5. "RTDMS5,Receiver mode during TDM time slot 5.0h = Receive TDM time slot 5 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 5 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 4. "RTDMS4,Receiver mode during TDM time slot 4.0h = Receive TDM time slot 4 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 4 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 3. "RTDMS3,Receiver mode during TDM time slot 3.0h = Receive TDM time slot 3 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 3 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 2. "RTDMS2,Receiver mode during TDM time slot 2.0h = Receive TDM time slot 2 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 2 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 1. "RTDMS1,Receiver mode during TDM time slot 1.0h = Receive TDM time slot 1 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 1 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 0. "RTDMS0,Receiver mode during TDM time slot 0.0h = Receive TDM time slot 0 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 0 is active. The receive serializer shifts in data during this slot." "0,1" line.long 0x1C "MCASP_EVTCTLR" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit.0h = Interrupt is disabled. A receive start of frame interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive start of frame interrupt generates a MCASP receive.." "0,1" bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit.0h = Interrupt is disabled. A receive data ready interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive data ready interrupt generates a MCASP receive interrupt.." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit.0h = Interrupt is disabled. A receive last slot interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive last slot interrupt generates a MCASP receive interrupt (RINT)." "0,1" newline bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit.0h = Interrupt is disabled. A receive DMA error interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive DMA error interrupt generates a MCASP receive interrupt.." "0,1" bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit.0h = Interrupt is disabled. A receive clock failure interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive clock failure interrupt generates a MCASP receive.." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit.0h = Interrupt is disabled. An unexpected receive frame sync interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. An unexpected receive frame sync interrupt.." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit.0h = Interrupt is disabled. A receiver overrun interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receiver overrun interrupt generates a MCASP receive interrupt (RINT)." "0,1" line.long 0x20 "MCASP_RXSTAT" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred. 0h = No errors have occurred. 1h = An error has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in MCASP_RINTCTL is.." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect. 0h = No new receive frame sync (AFSR).." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect. 0h = No new data in RBUF. 1h = Data is.." "0,1" newline bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing.." "0,1" bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of MCASP_RSLOT. Allows a single read of MCASP_RSTAT to determine whether the current TDM time slot is even or odd. 0h = Current TDM time slot is odd. 1h = Current TDM time slot is even." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this.." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in MCASP_RINTCTL is set. This bit is cleared by writing a 1.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for &gt; 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." group.long 0x88++0x7 line.long 0x0 "MCASP_RXCLKCHK" hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value.0h = MCASP system clock divided by 1. 1h = MCASP system clock divided by 2. 2h = MCASP system clock divided by 4. 3h = MCASP system clock divided by 8. 4h = MCASP system clock divided by 16. 5h = MCASP system clock.." line.long 0x4 "MCASP_REVTCTL" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0. 0h = Receive data DMA request is enabled. 1h = Reserved" "0,1" group.long 0xA0++0x23 line.long 0x0 "MCASP_GBLCTLX" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of MCASP_GBLCTL. 0h = Transmit frame sync generator is reset. 1h = Transmit frame sync generator is active." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of MCASP_GBLCTL. 0h = Transmit state machine is held in reset. 1h = Transmit state machine is released from reset." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of MCASP_GBLCTL. 0h = Transmit serializers are cleared. 1h = Transmit serializers are active." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of MCASP_GBLCTL. 0h = Transmit high-frequency clock divider is held in reset. 1h = Transmit high-frequency clock divider is running." "0,1" newline bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of MCASP_GBLCTL. 0h = Transmit clock divider is held in reset. 1h = Transmit clock divider is running." "0,1" bitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLKR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of MCASP_GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" line.long 0x4 "MCASP_TXMASK" bitfld.long 0x4 31. "XMASK31,Transmit data mask 31 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 30. "XMASK30,Transmit data mask 30 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 29. "XMASK29,Transmit data mask 29 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 28. "XMASK28,Transmit data mask 28 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 27. "XMASK27,Transmit data mask 27 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 26. "XMASK26,Transmit data mask 26 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 25. "XMASK25,Transmit data mask 25 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 24. "XMASK24,Transmit data mask 24 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 23. "XMASK23,Transmit data mask 23 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 22. "XMASK22,Transmit data mask 22 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 21. "XMASK21,Transmit data mask 21 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 20. "XMASK20,Transmit data mask 20 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 19. "XMASK19,Transmit data mask 19 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 18. "XMASK18,Transmit data mask 18 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 17. "XMASK17,Transmit data mask 17 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 16. "XMASK16,Transmit data mask 16 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 15. "XMASK15,Transmit data mask 15 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 14. "XMASK14,Transmit data mask 14 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 13. "XMASK13,Transmit data mask 13 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 12. "XMASK12,Transmit data mask 12 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 11. "XMASK11,Transmit data mask 11 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 10. "XMASK10,Transmit data mask 10 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 9. "XMASK9,Transmit data mask 9 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 8. "XMASK8,Transmit data mask 8 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 7. "XMASK7,Transmit data mask 7 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 6. "XMASK6,Transmit data mask 6 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 5. "XMASK5,Transmit data mask 5 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 4. "XMASK4,Transmit data mask 4 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 3. "XMASK3,Transmit data mask 3 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 2. "XMASK2,Transmit data mask 2 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 1. "XMASK1,Transmit data mask 1 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 0. "XMASK0,Transmit data mask 0 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" line.long 0x8 "MCASP_TXFMT" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay.0h = 0-bit delay. The first transmit data bit AXRn occurs in same ACLKX cycle as the transmit frame sync (AFSX). 1h = 1-bit delay. The first transmit data bit AXRn occurs one ACLKX cycle after the transmit frame sync.." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order.0h = Bitstream is LSB first. No bit reversal is performed in transmit format bit reverse unit. 1h = Bitstream is MSB first. Bit reversal is performed in transmit format bit reverse unit." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by MCASP_XMASK. This field only applies to bits when MCASP_XMASK[n] = 0. 0h = Pad extra bits with 0. 1h = Pad extra bits with 1. 2h = Pad extra bits with one of the bits from the word as.." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h. 0h = Pad with bit 0 value. 1h = Pad with bit 1 to bit 31 value from 1h to 1Fh." newline hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size.0h = Reserved. 1h = Reserved. 2h = Reserved. 3h = Slot size is 8 bits. 4h = Reserved. 5h = Slot size is 12 bits. 6h = Reserved. 7h = Slot size is 16 bits. 8h = Reserved. 9h = Slot size is 20 bits. Ah = Reserved. Bh = Slot size is.." bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port.0h = Writes to XRBUF[n] originate from the data port. Writes to XRBUF[n] from the configuration bus are ignored with no effect.." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit.0h = Rotate right by 0 (no rotation). 1h = Rotate right by 4 bit positions. 2h = Rotate right by 8 bit positions. 3h = Rotate right by 12 bit positions. 4h = Rotate right by 16 bit.." "0,1,2,3,4,5,6,7" line.long 0xC "MCASP_TXFMCTL" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh. 0h = Burst mode. 1h = Reserved. 2h = 2-slot TDM (I2S mode) to 32-slot TDM from 2h to 20h. 21h = Reserved from 21h to 17Fh. 180h = 384-slot DIT mode. 181h = Reserved from 181h.." bitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period.0h = Single bit. 1h = Single word." "0,1" bitfld.long 0xC 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit.0h = Externally-generated transmit frame sync. 1h = Internally-generated transmit frame sync." "0,1" bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit.0h = A rising edge on transmit frame sync (AFSX) indicates the beginning of a frame. 1h = A falling edge on transmit frame sync (AFSX) indicates the beginning of a frame." "0,1" line.long 0x10 "MCASP_ACLKXCTL" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,The logic OR of bits 18 and 19 indicating that some clk change is in progress when high" "0,1" bitfld.long 0x10 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x10 18. "ADJBUSY,one-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment control. If CLKXDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit.0h = Rising edge. External receiver samples data on the falling edge of the serial clock so the transmitter must shift data out on the rising edge of the serial clock. 1h = Falling edge. External.." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit.0h = Synchronous. Transmit clock and frame sync provides the source for both the transmit and receive sections. 1h = Asynchronous. Separate clock and frame sync used by transmit and receive sections." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit.0h = External transmit clock source from ACLKX pin. 1h = Internal transmit clock source from output of programmable bit clock divider." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX.0h = Divide-by-1. 1h = Divide-by-2. 2h = Divide-by-3 to divide-by-32 from 2h to 1Fh." line.long 0x14 "MCASP_AHCLKXCTL" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,The logic OR of bits 18 and 19 indicating that some clk change is in progress when high" "0,1" bitfld.long 0x14 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x14 18. "ADJBUSY,one-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,CLKXDIV one-shot adjustment control. If CLKXDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit.0h = External transmit high-frequency clock source from AHCLKX pin. 1h = Internal transmit high-frequency clock source from output of programmable high clock divider." "0,1" bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit.0h = AHCLKX is not inverted before programmable bit clock divider. In the special case where the transmit bit clock (ACLKX) is internally generated and the programmable bit clock divider.." "0,1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX.0h = Divide-by-1. 1h = Divide-by-2. 2h = Divide-by-3 to divide-by-4096 from 2h to FFFh." line.long 0x18 "MCASP_TXTDM" bitfld.long 0x18 31. "XTDMS31,Transmitter mode during TDM time slot 31.0h = Transmit TDM time slot 31 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 31 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 30. "XTDMS30,Transmitter mode during TDM time slot 30.0h = Transmit TDM time slot 30 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 30 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 29. "XTDMS29,Transmitter mode during TDM time slot 29.0h = Transmit TDM time slot 29 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 29 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 28. "XTDMS28,Transmitter mode during TDM time slot 28.0h = Transmit TDM time slot 28 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 28 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 27. "XTDMS27,Transmitter mode during TDM time slot 27.0h = Transmit TDM time slot 27 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 27 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 26. "XTDMS26,Transmitter mode during TDM time slot 26.0h = Transmit TDM time slot 26 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 26 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 25. "XTDMS25,Transmitter mode during TDM time slot 25.0h = Transmit TDM time slot 25 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 25 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 24. "XTDMS24,Transmitter mode during TDM time slot 24.0h = Transmit TDM time slot 24 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 24 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 23. "XTDMS23,Transmitter mode during TDM time slot 23.0h = Transmit TDM time slot 23 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 23 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 22. "XTDMS22,Transmitter mode during TDM time slot 22.0h = Transmit TDM time slot 22 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 22 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 21. "XTDMS21,Transmitter mode during TDM time slot 21.0h = Transmit TDM time slot 21 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 21 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 20. "XTDMS20,Transmitter mode during TDM time slot 20.0h = Transmit TDM time slot 20 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 20 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 19. "XTDMS19,Transmitter mode during TDM time slot 19.0h = Transmit TDM time slot 19 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 19 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 18. "XTDMS18,Transmitter mode during TDM time slot 18.0h = Transmit TDM time slot 18 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 18 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 17. "XTDMS17,Transmitter mode during TDM time slot 17.0h = Transmit TDM time slot 17 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 17 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 16. "XTDMS16,Transmitter mode during TDM time slot 16.0h = Transmit TDM time slot 16 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 16 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 15. "XTDMS15,Transmitter mode during TDM time slot 15.0h = Transmit TDM time slot 15 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 15 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 14. "XTDMS14,Transmitter mode during TDM time slot 14.0h = Transmit TDM time slot 14 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 14 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 13. "XTDMS13,Transmitter mode during TDM time slot 13.0h = Transmit TDM time slot 13 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 13 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 12. "XTDMS12,Transmitter mode during TDM time slot 12.0h = Transmit TDM time slot 12 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 12 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 11. "XTDMS11,Transmitter mode during TDM time slot 11.0h = Transmit TDM time slot 11 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 11 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 10. "XTDMS10,Transmitter mode during TDM time slot 10.0h = Transmit TDM time slot 10 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 10 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 9. "XTDMS9,Transmitter mode during TDM time slot 9.0h = Transmit TDM time slot 9 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 9 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 8. "XTDMS8,Transmitter mode during TDM time slot 8.0h = Transmit TDM time slot 8 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 8 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 7. "XTDMS7,Transmitter mode during TDM time slot 7.0h = Transmit TDM time slot 7 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 7 is active. The transmit serializer shifts out data during this slot.." "0,1" newline bitfld.long 0x18 6. "XTDMS6,Transmitter mode during TDM time slot 6.0h = Transmit TDM time slot 6 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 6 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 5. "XTDMS5,Transmitter mode during TDM time slot 5.0h = Transmit TDM time slot 5 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 5 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 4. "XTDMS4,Transmitter mode during TDM time slot 4.0h = Transmit TDM time slot 4 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 4 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 3. "XTDMS3,Transmitter mode during TDM time slot 3.0h = Transmit TDM time slot 3 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 3 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 2. "XTDMS2,Transmitter mode during TDM time slot 2.0h = Transmit TDM time slot 2 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 2 is active. The transmit serializer shifts out data during this slot.." "0,1" newline bitfld.long 0x18 1. "XTDMS1,Transmitter mode during TDM time slot 1.0h = Transmit TDM time slot 1 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 1 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 0. "XTDMS0,Transmitter mode during TDM time slot 0.0h = Transmit TDM time slot 0 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 0 is active. The transmit serializer shifts out data during this slot.." "0,1" line.long 0x1C "MCASP_EVTCTLX" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit.0h = Interrupt is disabled. A transmit start of frame interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit start of frame interrupt generates a McASP.." "0,1" bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit.0h = Interrupt is disabled. A transmit data ready interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit data ready interrupt generates a McASP transmit.." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit.0h = Interrupt is disabled. A transmit last slot interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit last slot interrupt generates a McASP transmit interrupt.." "0,1" newline bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit.0h = Interrupt is disabled. A transmit DMA error interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit DMA error interrupt generates a McASP transmit interrupt.." "0,1" bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit.0h = Interrupt is disabled. A transmit clock failure interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit clock failure interrupt generates a McASP.." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit.0h = Interrupt is disabled. An unexpected transmit frame sync interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. An unexpected transmit frame sync.." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit.0h = Interrupt is disabled. A transmitter underrun interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmitter underrun interrupt generates a McASP transmit.." "0,1" line.long 0x20 "MCASP_TXSTAT" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred. 0h = No errors have occurred. 1h = An error has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect. 0h = No new transmit frame sync (AFSX) is.." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect. 0h = XBUF is written and is full. 1h = Data is copied.." "0,1" newline bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of MCASP_XSLOT. Allows a single read of MCASP_XSTAT to determine whether the current TDM time slot is even or odd. 0h = Current TDM time slot is odd. 1h = Current TDM time slot is even." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this.." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in MCASP_XINTCTL is set. This bit is cleared by writing.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." group.long 0xC8++0xB line.long 0x0 "MCASP_TXCLKCHK" hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh. 0h = MCASP system clock divided by 1. 1h = MCASP system clock divided by 2. 2h = MCASP system clock divided by 4. 3h = MCASP system clock divided by 8. 4h = MCASP system clock divided.." line.long 0x4 "MCASP_XEVTCTL" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0. 0h = Transmit data DMA request is enabled. 1h = Reserved" "0,1" line.long 0x8 "MCASP_CLKADJEN" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0. "ENABLE,One-shot clock adjustment enable. 0 = One-shot clock adjustment is DISABLED. Writes to bits 17:16 of 1 = One-shot clock adjustment is ENABLED. Writes to bits 17:16 of" "0: One-shot clock adjustment is DISABLED,1: One-shot clock adjustment is ENABLED" group.long 0x100++0x5F line.long 0x0 "MCASP_DITCSRA0" hexmask.long 0x0 0.--31. 1. "DITCSRA0,DIT left channel status registers." line.long 0x4 "MCASP_DITCSRA1" hexmask.long 0x4 0.--31. 1. "DITCSRA1,DIT left channel status registers." line.long 0x8 "MCASP_DITCSRA2" hexmask.long 0x8 0.--31. 1. "DITCSRA2,DIT left channel status registers." line.long 0xC "MCASP_DITCSRA3" hexmask.long 0xC 0.--31. 1. "DITCSRA3,DIT left channel status registers." line.long 0x10 "MCASP_DITCSRA4" hexmask.long 0x10 0.--31. 1. "DITCSRA4,DIT left channel status registers." line.long 0x14 "MCASP_DITCSRA5" hexmask.long 0x14 0.--31. 1. "DITCSRA5,DIT left channel status registers." line.long 0x18 "MCASP_DITCSRB0" hexmask.long 0x18 0.--31. 1. "DITCSRB0,DIT right channel status registers." line.long 0x1C "MCASP_DITCSRB1" hexmask.long 0x1C 0.--31. 1. "DITCSRB1,DIT right channel status registers." line.long 0x20 "MCASP_DITCSRB2" hexmask.long 0x20 0.--31. 1. "DITCSRB2,DIT right channel status registers." line.long 0x24 "MCASP_DITCSRB3" hexmask.long 0x24 0.--31. 1. "DITCSRB3,DIT right channel status registers." line.long 0x28 "MCASP_DITCSRB4" hexmask.long 0x28 0.--31. 1. "DITCSRB4,DIT right channel status registers." line.long 0x2C "MCASP_DITCSRB5" hexmask.long 0x2C 0.--31. 1. "DITCSRB5,DIT right channel status registers." line.long 0x30 "MCASP_DITUDRA0" hexmask.long 0x30 0.--31. 1. "DITUDRA0,DIT left channel user data registers." line.long 0x34 "MCASP_DITUDRA1" hexmask.long 0x34 0.--31. 1. "DITUDRA1,DIT left channel user data registers." line.long 0x38 "MCASP_DITUDRA2" hexmask.long 0x38 0.--31. 1. "DITUDRA2,DIT left channel user data registers." line.long 0x3C "MCASP_DITUDRA3" hexmask.long 0x3C 0.--31. 1. "DITUDRA3,DIT left channel user data registers." line.long 0x40 "MCASP_DITUDRA4" hexmask.long 0x40 0.--31. 1. "DITUDRA4,DIT left channel user data registers." line.long 0x44 "MCASP_DITUDRA5" hexmask.long 0x44 0.--31. 1. "DITUDRA5,DIT left channel user data registers." line.long 0x48 "MCASP_DITUDRB0" hexmask.long 0x48 0.--31. 1. "DITUDRB0,DIT right channel user data registers." line.long 0x4C "MCASP_DITUDRB1" hexmask.long 0x4C 0.--31. 1. "DITUDRB1,DIT right channel user data registers." line.long 0x50 "MCASP_DITUDRB2" hexmask.long 0x50 0.--31. 1. "DITUDRB2,DIT right channel user data registers." line.long 0x54 "MCASP_DITUDRB3" hexmask.long 0x54 0.--31. 1. "DITUDRB3,DIT right channel user data registers." line.long 0x58 "MCASP_DITUDRB4" hexmask.long 0x58 0.--31. 1. "DITUDRB4,DIT right channel user data registers." line.long 0x5C "MCASP_DITUDRB5" hexmask.long 0x5C 0.--31. 1. "DITUDRB5,DIT right channel user data registers." group.long 0x180++0x3F line.long 0x0 "MCASP_XRSRCTL0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x4 "MCASP_XRSRCTL1" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x8 "MCASP_XRSRCTL2" hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0xC "MCASP_XRSRCTL3" hexmask.long 0xC 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x10 "MCASP_XRSRCTL4" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x14 "MCASP_XRSRCTL5" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x18 "MCASP_XRSRCTL6" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x1C "MCASP_XRSRCTL7" hexmask.long 0x1C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x20 "MCASP_XRSRCTL8" hexmask.long 0x20 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x24 "MCASP_XRSRCTL9" hexmask.long 0x24 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x28 "MCASP_XRSRCTL10" hexmask.long 0x28 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x2C "MCASP_XRSRCTL11" hexmask.long 0x2C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x30 "MCASP_XRSRCTL12" hexmask.long 0x30 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x34 "MCASP_XRSRCTL13" hexmask.long 0x34 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x38 "MCASP_XRSRCTL14" hexmask.long 0x38 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x3C "MCASP_XRSRCTL15" hexmask.long 0x3C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" group.long 0x200++0x3F line.long 0x0 "MCASP_TXBUF0" hexmask.long 0x0 0.--31. 1. "XBUF0,Transmit buffers for serializers." line.long 0x4 "MCASP_TXBUF1" hexmask.long 0x4 0.--31. 1. "XBUF1,Transmit buffers for serializers." line.long 0x8 "MCASP_TXBUF2" hexmask.long 0x8 0.--31. 1. "XBUF2,Transmit buffers for serializers." line.long 0xC "MCASP_TXBUF3" hexmask.long 0xC 0.--31. 1. "XBUF3,Transmit buffers for serializers." line.long 0x10 "MCASP_TXBUF4" hexmask.long 0x10 0.--31. 1. "XBUF4,Transmit buffers for serializers." line.long 0x14 "MCASP_TXBUF5" hexmask.long 0x14 0.--31. 1. "XBUF5,Transmit buffers for serializers." line.long 0x18 "MCASP_TXBUF6" hexmask.long 0x18 0.--31. 1. "XBUF6,Transmit buffers for serializers." line.long 0x1C "MCASP_TXBUF7" hexmask.long 0x1C 0.--31. 1. "XBUF7,Transmit buffers for serializers." line.long 0x20 "MCASP_TXBUF8" hexmask.long 0x20 0.--31. 1. "XBUF8,Transmit buffers for serializers." line.long 0x24 "MCASP_TXBUF9" hexmask.long 0x24 0.--31. 1. "XBUF9,Transmit buffers for serializers." line.long 0x28 "MCASP_TXBUF10" hexmask.long 0x28 0.--31. 1. "XBUF10,Transmit buffers for serializers." line.long 0x2C "MCASP_TXBUF11" hexmask.long 0x2C 0.--31. 1. "XBUF11,Transmit buffers for serializers." line.long 0x30 "MCASP_TXBUF12" hexmask.long 0x30 0.--31. 1. "XBUF12,Transmit buffers for serializers." line.long 0x34 "MCASP_TXBUF13" hexmask.long 0x34 0.--31. 1. "XBUF13,Transmit buffers for serializers." line.long 0x38 "MCASP_TXBUF14" hexmask.long 0x38 0.--31. 1. "XBUF14,Transmit buffers for serializers." line.long 0x3C "MCASP_TXBUF15" hexmask.long 0x3C 0.--31. 1. "XBUF15,Transmit buffers for serializers." group.long 0x280++0x3F line.long 0x0 "MCASP_RXBUF0" hexmask.long 0x0 0.--31. 1. "RBUF0,Receive buffers for serializers." line.long 0x4 "MCASP_RXBUF1" hexmask.long 0x4 0.--31. 1. "RBUF1,Receive buffers for serializers." line.long 0x8 "MCASP_RXBUF2" hexmask.long 0x8 0.--31. 1. "RBUF2,Receive buffers for serializers." line.long 0xC "MCASP_RXBUF3" hexmask.long 0xC 0.--31. 1. "RBUF3,Receive buffers for serializers." line.long 0x10 "MCASP_RXBUF4" hexmask.long 0x10 0.--31. 1. "RBUF4,Receive buffers for serializers." line.long 0x14 "MCASP_RXBUF5" hexmask.long 0x14 0.--31. 1. "RBUF5,Receive buffers for serializers." line.long 0x18 "MCASP_RXBUF6" hexmask.long 0x18 0.--31. 1. "RBUF6,Receive buffers for serializers." line.long 0x1C "MCASP_RXBUF7" hexmask.long 0x1C 0.--31. 1. "RBUF7,Receive buffers for serializers." line.long 0x20 "MCASP_RXBUF8" hexmask.long 0x20 0.--31. 1. "RBUF8,Receive buffers for serializers." line.long 0x24 "MCASP_RXBUF9" hexmask.long 0x24 0.--31. 1. "RBUF9,Receive buffers for serializers." line.long 0x28 "MCASP_RXBUF10" hexmask.long 0x28 0.--31. 1. "RBUF10,Receive buffers for serializers." line.long 0x2C "MCASP_RXBUF11" hexmask.long 0x2C 0.--31. 1. "RBUF11,Receive buffers for serializers." line.long 0x30 "MCASP_RXBUF12" hexmask.long 0x30 0.--31. 1. "RBUF12,Receive buffers for serializers." line.long 0x34 "MCASP_RXBUF13" hexmask.long 0x34 0.--31. 1. "RBUF13,Receive buffers for serializers." line.long 0x38 "MCASP_RXBUF14" hexmask.long 0x38 0.--31. 1. "RBUF14,Receive buffers for serializers." line.long 0x3C "MCASP_RXBUF15" hexmask.long 0x3C 0.--31. 1. "RBUF15,Receive buffers for serializers." tree.end tree "MCASP0_DMA" base ad:0x2B08000 rgroup.long 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers. For receive operations through the DATA port. the Host should read from the same.." hexmask.long 0x0 0.--31. 1. "RXBUF,Rx buffer data." wgroup.long 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port. the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port. the Host should write to the same DATA.." hexmask.long 0x0 0.--31. 1. "TXBUF,Tx buffer data." tree.end tree "MCASP1_CFG" base ad:0x2B10000 rgroup.long 0x0++0x3 line.long 0x0 "MCASP_PID" bitfld.long 0x0 30.--31. "SCHEME,Distinguishes between old scheme and current." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Indicates a software-compatible module family." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version." bitfld.long 0x0 8.--10. "REVMAJOR,Major revision number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a given device." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMINOR,Minor revision number." group.long 0x4++0x3 line.long 0x0 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG register." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLE_MODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state. 0h = Force-idle mode: local target's idle state follows (acknowledges) the.." "0,1,2,3" group.long 0x10++0xB line.long 0x0 "MCASP_PFUNC" bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Determines if AXR15 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 14. "AXR14,Determines if AXR14 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 13. "AXR13,Determines if AXR13 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 12. "AXR12,Determines if AXR12 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 11. "AXR11,Determines if AXR11 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 10. "AXR10,Determines if AXR10 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 9. "AXR9,Determines if AXR9 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 8. "AXR8,Determines if AXR8 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 7. "AXR7,Determines if AXR7 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 6. "AXR6,Determines if AXR6 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 5. "AXR5,Determines if AXR5 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 4. "AXR4,Determines if AXR4 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 3. "AXR3,Determines if AXR3 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 2. "AXR2,Determines if AXR2 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 1. "AXR1,Determines if AXR1 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 0. "AXR0,Determines if AXR0 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" line.long 0x4 "MCASP_PDIR" bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" hexmask.long.word 0x4 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "AXR15,Determines if AXR15 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 14. "AXR14,Determines if AXR14 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 13. "AXR13,Determines if AXR13 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 12. "AXR12,Determines if AXR12 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 11. "AXR11,Determines if AXR11 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 10. "AXR10,Determines if AXR10 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 9. "AXR9,Determines if AXR9 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 8. "AXR8,Determines if AXR8 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 7. "AXR7,Determines if AXR7 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 6. "AXR6,Determines if AXR6 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 5. "AXR5,Determines if AXR5 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 4. "AXR4,Determines if AXR4 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 3. "AXR3,Determines if AXR3 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 2. "AXR2,Determines if AXR2 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 1. "AXR1,Determines if AXR1 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 0. "AXR0,Determines if AXR0 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" line.long 0x8 "MCASP_PDOUT" bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the correspondingMCASP_PFUNC[25] and MCASP_PDIR[25] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" hexmask.long.word 0x8 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCASP_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR." bitfld.long 0x0 31. "AFSR,Logic level on AFSR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 30. "AHCLKR,Logic level on AHCLKR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 29. "ACLKR,Logic level on ACLKR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 28. "AFSX,Logic level on AFSX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 27. "AHCLKX,Logic level on AHCLKX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 26. "ACLKX,Logic level on ACLKX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 25. "AMUTE,Logic level on AMUTE pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Logic level on AXR15 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 14. "AXR14,Logic level on AXR14 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 13. "AXR13,Logic level on AXR13 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 12. "AXR12,Logic level on AXR12 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 11. "AXR11,Logic level on AXR11 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 10. "AXR10,Logic level on AXR10 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 9. "AXR9,Logic level on AXR9 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 8. "AXR8,Logic level on AXR8 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 7. "AXR7,Logic level on AXR7 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 6. "AXR6,Logic level on AXR6 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 5. "AXR5,Logic level on AXR5 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 4. "AXR4,Logic level on AXR4 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 3. "AXR3,Logic level on AXR3 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 2. "AXR2,Logic level on AXR2 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 1. "AXR1,Logic level on AXR1 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 0. "AXR0,Logic level on AXR0 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" group.long 0x1C++0x7 line.long 0x0 "MCASP_PDSET,The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x0 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 30. "AHCLKR,Allows the corresponding AHCLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 25. "AMUTE,Allows the corresponding AMUTE bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Allows the corresponding AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 14. "AXR14,Allows the corresponding AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 13. "AXR13,Allows the corresponding AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 12. "AXR12,Allows the corresponding AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 11. "AXR11,Allows the corresponding AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 10. "AXR10,Allows the corresponding AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 9. "AXR9,Allows the corresponding AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 8. "AXR8,Allows the corresponding AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 7. "AXR7,Allows the corresponding AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 6. "AXR6,Allows the corresponding AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 5. "AXR5,Allows the corresponding AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 4. "AXR4,Allows the corresponding AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 3. "AXR3,Allows the corresponding AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 2. "AXR2,Allows the corresponding AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 1. "AXR1,Allows the corresponding AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 0. "AXR0,Allows the corresponding AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" line.long 0x4 "MCASP_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a.." bitfld.long 0x4 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 30. "AHCLKR,Allows the corresponding AHCLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 25. "AMUTE,Allows the corresponding AMUTE bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" hexmask.long.word 0x4 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "AXR15,Allows the corresponding AXR[15] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 14. "AXR14,Allows the corresponding AXR[14] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 13. "AXR13,Allows the corresponding AXR[13] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 12. "AXR12,Allows the corresponding AXR[12] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 11. "AXR11,Allows the corresponding AXR[11] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 10. "AXR10,Allows the corresponding AXR[10] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 9. "AXR9,Allows the corresponding AXR[9] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 8. "AXR8,Allows the corresponding AXR[8] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 7. "AXR7,Allows the corresponding AXR[7] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 6. "AXR6,Allows the corresponding AXR[6] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 5. "AXR5,Allows the corresponding AXR[5] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 4. "AXR4,Allows the corresponding AXR[4] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 3. "AXR3,Allows the corresponding AXR[3] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 2. "AXR2,Allows the corresponding AXR[2] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 1. "AXR1,Allows the corresponding AXR[1] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 0. "AXR0,Allows the corresponding AXR[0] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" group.long 0x30++0xB line.long 0x0 "MCASP_TLGC,for IODFT" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 14.--15. "MT,MISR on/off trigger command. These monitor trigger codes only are affective for the MISR signature capture when MC = 3h. MT Code effect on MISR: 0h = MISR capture start on the first active cycle decode of the IP bus activity and continues to update.." "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "MMS,Chooses the source of the MISR input: 0h = output register 1h = input capture" "0,1" bitfld.long 0x0 7. "ESEL,Output enable select: 0h = test mode and the functional OEN is gated off 1h = normal functional mode" "0,1" newline bitfld.long 0x0 6. "TOEN,Test output enable control. This signal is paired with ESEL. TOEN is never 1 when ESEL is 1. When ESEL is 0 (test mode) TOEN is: 0h = output enabled 1h = output disabled Note: In boundary scan mode this signal is not selected and the BSR controls.." "0,1" bitfld.long 0x0 4.--5. "MC,This defines the states of the MISR: 0h = download results 1h = hold current value 2h = load initial value (from PC bits) 3h = MISR enable to capture signature" "0,1,2,3" bitfld.long 0x0 1.--3. "PC,Pattern code defines the type of pattern that is selected for the artificial pattern generation logic in the IODFT. Modes: 0h = functional (default) 1h = random XOR 2h = random XNOR 3h = shift register 4h = hold current value Note: McASP does not have.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "TM,At reset the value is 1 for normal functional mode. This bit is tied high and should not be written to." "0,1" line.long 0x4 "MCASP_TLMR,for IODFT" hexmask.long 0x4 0.--31. 1. "TLMR,This contains the result signature of a given test after the download function is executed." line.long 0x8 "MCASP_TLEC,for IODFT" hexmask.long 0x8 0.--31. 1. "TLEC,Contains the number of cycles during which the MISR signature will be accumulated." group.long 0x44++0xF line.long 0x0 "MCASP_GBLCTL" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit.0h = Transmit frame sync generator is reset. 1h = Transmit frame sync generator is active. When released from reset the transmit frame sync generator begins counting serial clocks and generating frame.." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit.0h = Transmit state machine is held in reset. AXRn pin state: If 1h = Transmit state machine is released from reset. When released from reset the transmit state machine immediately transfers data from.." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit.0h = Transmit high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Transmit high-frequency clock divider is running." "0,1" newline bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit.0h = Transmit clock divider is held in reset. When the clock divider is in reset it passes through a divide-by-1 of its input. 1h = Transmit clock divider is running." "0,1" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit.0h = Receive frame sync generator is reset. 1h = Receive frame sync generator is active. When released from reset the receive frame sync generator begins counting serial clocks and generating frame.." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit.0h = Receive state machine is held in reset. 1h = Receive state machine is released from reset. When released from reset the receive state machine immediately begins detecting frame sync and is ready to.." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed. 0h = Receive serializers are cleared. 1h = Receive serializers are active." "0,1" newline bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit.0h = Receive high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Receive high-frequency clock divider is running." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit.0h = Receive clock divider is held in reset. When the clock divider is in reset it passes through a divide-by-1 of its input. 1h = Receive clock divider is running." "0,1" line.long 0x4 "MCASP_AMUTE" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit DMA error is ignored by 1h = Drive is enabled (active). Upon detection of transmit DMA error " "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receive DMA error is ignored by 1h = Drive is enabled (active). Upon detection of receive DMA error " "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit clock failure is ignored by 1h = Drive is enabled (active). Upon detection of transmit clock failure " "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receive clock failure is ignored by 1h = Drive is enabled (active). Upon detection of receive clock failure " "0,1" newline bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of unexpected transmit frame sync error is ignored by 1h = Drive is enabled (active). Upon detection of unexpected transmit.." "0,1" bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of unexpected receive frame sync error is ignored by 1h = Drive is enabled (active). Upon detection of unexpected receive.." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit underrun error is ignored by 1h = Drive is enabled (active). Upon detection of transmit underrun error " "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receiver overrun error is ignored by 1h = Drive is enabled (active). Upon detection of receiver overrun error " "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin whenMCASP_PFUNC[n] and MCASP_PDIR[n] bits are set to 1. 0h = AMUTEIN pin is inactive. 1h = AMUTEIN pin is active. Audio mute in error is detected." "0,1" newline bitfld.long 0x4 3. "INEN,DriveMCASP_AMUTE active when AMUTEIN error is active [INSTAT = 1]. 0h = Drive is disabled. AMUTEIN is ignored by 1h = Drive is enabled (active). INSTAT = 1 drives" "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit.0h = Polarity is active high. A high on AMUTEIN sets INSTAT to 1. 1h = Polarity is active low. A low on AM UTEIN sets INSTAT to 1." "0,1" bitfld.long 0x4 0.--1. "MUTEN,MCASP_AMUTE pin enable bit [unless overridden by GPIO registers]. 0h = 1h = 2h = 3h = Reserved" "0,1,2,3" line.long 0x8 "MCASP_LBCTL" hexmask.long 0x8 5.--31. 1. "RESERVED" bitfld.long 0x8 4. "IOLBEN,I/O loopback enable. Chip-level loopback; looped back through I/O buffers. 0h = I/O loopback disabled 1h = I/O loopback enabled Note: These are only valid if LBEN = 1. If LBEN = 0 neither internal nor I/O loopback will be selected." "0,1" bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]. 0h = Default and reserved on loopback mode (DLBEN = 1). When in non-loopback mode (DLBEN = 0) MODE should be left at default (00). When in loopback mode (DLBEN =.." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1].0h = Odd serializers N + 1 transmit to even serializers N that receive. The corresponding serializers must be programmed properly. 1h = Even serializers N transmit to odd serializers N + 1.." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit.0h = Loopback mode is disabled. 1h = Loopback mode is enabled." "0,1" line.long 0xC "MCASP_TXDITCTL" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe].0h = V bit is 0 during odd DIT subframes. 1h = V bit is 1 during odd DIT subframes." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe].0h = V bit is 0 during even DIT subframes. 1h = V bit is 1 during even DIT subframes." "0,1" bitfld.long 0xC 1. "RESERVED,Reserved" "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in MCASP_GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in MCASP_GBLCTL to change DITEN. 0h = DIT.." "0,1" group.long 0x60++0x23 line.long 0x0 "MCASP_GBLCTLR" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" bitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of MCASP_GBLCTL. 0h = Receive frame sync generator is reset. 1h = Receive frame sync generator is active." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of MCASP_GBLCTL. 0h = Receive state machine is held in reset. 1h = Receive state machine is released from reset." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of MCASP_GBLCTL. 0h = Receive serializers are cleared. 1h = Receive serializers are active." "0,1" newline bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of MCASP_GBLCTL. 0h = Receive high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Receive.." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of MCASP_GBLCTL. 0h = Receive clock divider is held in reset. 1h = Receive clock divider is running." "0,1" line.long 0x4 "MCASP_RXMASK" bitfld.long 0x4 31. "RMASK31,Receive data mask 31 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 30. "RMASK30,Receive data mask 30 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 29. "RMASK29,Receive data mask 29 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 28. "RMASK28,Receive data mask 28 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 27. "RMASK27,Receive data mask 27 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 26. "RMASK26,Receive data mask 26 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 25. "RMASK25,Receive data mask 25 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 24. "RMASK24,Receive data mask 24 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 23. "RMASK23,Receive data mask 23 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 22. "RMASK22,Receive data mask 22 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 21. "RMASK21,Receive data mask 21 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 20. "RMASK20,Receive data mask 20 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 19. "RMASK19,Receive data mask 19 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 18. "RMASK18,Receive data mask 18 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 17. "RMASK17,Receive data mask 17 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 16. "RMASK16,Receive data mask 16 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 15. "RMASK15,Receive data mask 15 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 14. "RMASK14,Receive data mask 14 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 13. "RMASK13,Receive data mask 13 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 12. "RMASK12,Receive data mask 12 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 11. "RMASK11,Receive data mask 11 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 10. "RMASK10,Receive data mask 10 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 9. "RMASK9,Receive data mask 9 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 8. "RMASK8,Receive data mask 8 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 7. "RMASK7,Receive data mask 7 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 6. "RMASK6,Receive data mask 6 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 5. "RMASK5,Receive data mask 5 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 4. "RMASK4,Receive data mask 4 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 3. "RMASK3,Receive data mask 3 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 2. "RMASK2,Receive data mask 2 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 1. "RMASK1,Receive data mask 1 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 0. "RMASK0,Receive data mask 0 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" line.long 0x8 "MCASP_RXFMT" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay.0h = 0-bit delay. The first receive data bit AXRn occurs in same ACLKR cycle as the receive frame sync (AFSR). 1h = 1-bit delay. The first receive data bit AXRn occurs one ACLKR cycle after the receive frame sync (AFSR). 2h.." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order.0h = Bitstream is LSB first. No bit reversal is performed in receive format bit reverse unit. 1h = Bitstream is MSB first. Bit reversal is performed in receive format bit reverse unit." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when MCASP_RMASK[n] = 0. 0h = Pad extra bits with 0. 1h = Pad extra bits with 1. 2h = Pad extra bits with one of the bits from the word as specified by RPBIT.." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h. 0h = Pad with bit 0 value. 1h = Pad with bit 1 to bit 31 value from 1h to 1Fh." newline hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size.0h = Reseved. 1h = Reserved. 2h = Reserved. 3h = Slot size is 8 bits. 4h = Reserved 5h = Slot size is 12 bits. 6h = Reserved 7h = Slot size is 16 bits. 8h = Reserved 9h = Slot size is 20 bits. Ah = Reserved Bh = Slot size is 24.." bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port.0h = Reads from XRBUF[n] originate on data port. Reads from XRBUF[n] on configuration bus are ignored. 1h = Reads from XRBUF[n].." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit.0h = Rotate right by 0 (no rotation). 1h = Rotate right by 4 bit positions. 2h = Rotate right by 8 bit positions. 3h = Rotate right by 12 bit positions. 4h = Rotate right by 16 bit positions." "0,1,2,3,4,5,6,7" line.long 0xC "MCASP_RXFMCTL" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh. 0h = Burst mode. 1h = Reserved. 2h = 2-slot TDM (I2S mode) to 32-slot TDM from 2h to 20h. 21h = Reserved from 21h to 17Fh. 180h = 384-slot TDM (external DIR IC inputting.." bitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period.0h = Single bit. 1h = Single word." "0,1" bitfld.long 0xC 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit.0h = Externally-generated receive frame sync. 1h = Internally-generated receive frame sync." "0,1" bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit.0h = A rising edge on receive frame sync (AFSR) indicates the beginning of a frame. 1h = A falling edge on receive frame sync (AFSR) indicates the beginning of a frame." "0,1" line.long 0x10 "MCASP_ACLKRCTL" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Тhe OR of bits 18 and 19 indicating that some clk change is in progress when high." "0,1" bitfld.long 0x10 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x10 18. "ADJBUSY,One-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment contro.l If CLKRDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock no adjustment 1h = (m-1) input clocks per output clock 2h =.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "CLKRP,Bitstream clock polarity for receive section: 0h = Falling Edge. Receiver captures sample data on the falling edge of the serial clock so the EXTERNAL transmitter driving this receiver must shift data out on the rising edge of the serial clock. 1h.." "0,1" bitfld.long 0x10 6. "RESERVED,Reserved" "0,1" bitfld.long 0x10 5. "CLKRM,Receive clock source: 0h = External Transmit Clock From ACLKR pin 1h = Internal (output of divider) output clock on ACLKR pin." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive clock divide ratio from high frequency transmit clock: 00000b = /1 00001b = /2 . . . 11111b = /32 All values between /1 and /32 are supported." line.long 0x14 "MCASP_AHCLKRCTL" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,The OR of bits 18 and 19 indicating that some clk change is in progress when high." "0,1" bitfld.long 0x14 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x14 18. "ADJBUSY,One-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)." "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment control If HCLKRDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline bitfld.long 0x14 15. "HCLKRM,High frequency receive clock source: 0h = External Clock on AHCLKR pin passes through divider (typically set to /1). 1h = Internal CPU Clock passed through divider. Divider output on AHCLKR pin." "0,1" bitfld.long 0x14 14. "HCLKRP,high frequency clock polarity: 0h = AHCLKR not inverted before divider. Rising Edge of AHCLKR causes edges on ACLKR when internally generated. 1h = AHCLKR inverted before divider. Falling Edge of AHCLK causes edges on ACLKR when internally.." "0,1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive clock divide ratio from CPU master clock or external high frequency clock: 0000 0000 0000b = /1 0000 0000 0001b = /2 . . . 1111 1111 1111b = /4096 All values between /1 and /4096 are supported." line.long 0x18 "MCASP_RXTDM" bitfld.long 0x18 31. "RTDMS31,Receiver mode during TDM time slot 31.0h = Receive TDM time slot 31 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 31 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 30. "RTDMS30,Receiver mode during TDM time slot 30.0h = Receive TDM time slot 30 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 30 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 29. "RTDMS29,Receiver mode during TDM time slot 29.0h = Receive TDM time slot 29 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 29 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 28. "RTDMS28,Receiver mode during TDM time slot 28.0h = Receive TDM time slot 28 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 28 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 27. "RTDMS27,Receiver mode during TDM time slot 27.0h = Receive TDM time slot 27 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 27 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 26. "RTDMS26,Receiver mode during TDM time slot 26.0h = Receive TDM time slot 26 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 26 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 25. "RTDMS25,Receiver mode during TDM time slot 25.0h = Receive TDM time slot 25 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 25 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 24. "RTDMS24,Receiver mode during TDM time slot 24.0h = Receive TDM time slot 24 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 24 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 23. "RTDMS23,Receiver mode during TDM time slot 23.0h = Receive TDM time slot 23 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 23 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 22. "RTDMS22,Receiver mode during TDM time slot 22.0h = Receive TDM time slot 22 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 22 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 21. "RTDMS21,Receiver mode during TDM time slot 21.0h = Receive TDM time slot 21 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 21 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 20. "RTDMS20,Receiver mode during TDM time slot 20.0h = Receive TDM time slot 20 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 20 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 19. "RTDMS19,Receiver mode during TDM time slot 19.0h = Receive TDM time slot 19 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 19 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 18. "RTDMS18,Receiver mode during TDM time slot 18.0h = Receive TDM time slot 18 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 18 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 17. "RTDMS17,Receiver mode during TDM time slot 17.0h = Receive TDM time slot 17 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 17 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 16. "RTDMS16,Receiver mode during TDM time slot 16.0h = Receive TDM time slot 16 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 16 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 15. "RTDMS15,Receiver mode during TDM time slot 15.0h = Receive TDM time slot 15 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 15 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 14. "RTDMS14,Receiver mode during TDM time slot 14.0h = Receive TDM time slot 14 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 14 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 13. "RTDMS13,Receiver mode during TDM time slot 13.0h = Receive TDM time slot 13 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 13 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 12. "RTDMS12,Receiver mode during TDM time slot 12.0h = Receive TDM time slot 12 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 12 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 11. "RTDMS11,Receiver mode during TDM time slot 11.0h = Receive TDM time slot 11 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 11 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 10. "RTDMS10,Receiver mode during TDM time slot 10.0h = Receive TDM time slot 10 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 10 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 9. "RTDMS9,Receiver mode during TDM time slot 9.0h = Receive TDM time slot 9 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 9 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 8. "RTDMS8,Receiver mode during TDM time slot 8.0h = Receive TDM time slot 8 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 8 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 7. "RTDMS7,Receiver mode during TDM time slot 7.0h = Receive TDM time slot 7 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 7 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 6. "RTDMS6,Receiver mode during TDM time slot 6.0h = Receive TDM time slot 6 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 6 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 5. "RTDMS5,Receiver mode during TDM time slot 5.0h = Receive TDM time slot 5 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 5 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 4. "RTDMS4,Receiver mode during TDM time slot 4.0h = Receive TDM time slot 4 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 4 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 3. "RTDMS3,Receiver mode during TDM time slot 3.0h = Receive TDM time slot 3 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 3 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 2. "RTDMS2,Receiver mode during TDM time slot 2.0h = Receive TDM time slot 2 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 2 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 1. "RTDMS1,Receiver mode during TDM time slot 1.0h = Receive TDM time slot 1 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 1 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 0. "RTDMS0,Receiver mode during TDM time slot 0.0h = Receive TDM time slot 0 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 0 is active. The receive serializer shifts in data during this slot." "0,1" line.long 0x1C "MCASP_EVTCTLR" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit.0h = Interrupt is disabled. A receive start of frame interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive start of frame interrupt generates a MCASP receive.." "0,1" bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit.0h = Interrupt is disabled. A receive data ready interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive data ready interrupt generates a MCASP receive interrupt.." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit.0h = Interrupt is disabled. A receive last slot interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive last slot interrupt generates a MCASP receive interrupt (RINT)." "0,1" newline bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit.0h = Interrupt is disabled. A receive DMA error interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive DMA error interrupt generates a MCASP receive interrupt.." "0,1" bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit.0h = Interrupt is disabled. A receive clock failure interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive clock failure interrupt generates a MCASP receive.." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit.0h = Interrupt is disabled. An unexpected receive frame sync interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. An unexpected receive frame sync interrupt.." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit.0h = Interrupt is disabled. A receiver overrun interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receiver overrun interrupt generates a MCASP receive interrupt (RINT)." "0,1" line.long 0x20 "MCASP_RXSTAT" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred. 0h = No errors have occurred. 1h = An error has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in MCASP_RINTCTL is.." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect. 0h = No new receive frame sync (AFSR).." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect. 0h = No new data in RBUF. 1h = Data is.." "0,1" newline bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing.." "0,1" bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of MCASP_RSLOT. Allows a single read of MCASP_RSTAT to determine whether the current TDM time slot is even or odd. 0h = Current TDM time slot is odd. 1h = Current TDM time slot is even." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this.." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in MCASP_RINTCTL is set. This bit is cleared by writing a 1.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for &gt; 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." group.long 0x88++0x7 line.long 0x0 "MCASP_RXCLKCHK" hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value.0h = MCASP system clock divided by 1. 1h = MCASP system clock divided by 2. 2h = MCASP system clock divided by 4. 3h = MCASP system clock divided by 8. 4h = MCASP system clock divided by 16. 5h = MCASP system clock.." line.long 0x4 "MCASP_REVTCTL" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0. 0h = Receive data DMA request is enabled. 1h = Reserved" "0,1" group.long 0xA0++0x23 line.long 0x0 "MCASP_GBLCTLX" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of MCASP_GBLCTL. 0h = Transmit frame sync generator is reset. 1h = Transmit frame sync generator is active." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of MCASP_GBLCTL. 0h = Transmit state machine is held in reset. 1h = Transmit state machine is released from reset." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of MCASP_GBLCTL. 0h = Transmit serializers are cleared. 1h = Transmit serializers are active." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of MCASP_GBLCTL. 0h = Transmit high-frequency clock divider is held in reset. 1h = Transmit high-frequency clock divider is running." "0,1" newline bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of MCASP_GBLCTL. 0h = Transmit clock divider is held in reset. 1h = Transmit clock divider is running." "0,1" bitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLKR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of MCASP_GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" line.long 0x4 "MCASP_TXMASK" bitfld.long 0x4 31. "XMASK31,Transmit data mask 31 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 30. "XMASK30,Transmit data mask 30 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 29. "XMASK29,Transmit data mask 29 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 28. "XMASK28,Transmit data mask 28 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 27. "XMASK27,Transmit data mask 27 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 26. "XMASK26,Transmit data mask 26 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 25. "XMASK25,Transmit data mask 25 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 24. "XMASK24,Transmit data mask 24 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 23. "XMASK23,Transmit data mask 23 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 22. "XMASK22,Transmit data mask 22 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 21. "XMASK21,Transmit data mask 21 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 20. "XMASK20,Transmit data mask 20 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 19. "XMASK19,Transmit data mask 19 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 18. "XMASK18,Transmit data mask 18 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 17. "XMASK17,Transmit data mask 17 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 16. "XMASK16,Transmit data mask 16 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 15. "XMASK15,Transmit data mask 15 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 14. "XMASK14,Transmit data mask 14 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 13. "XMASK13,Transmit data mask 13 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 12. "XMASK12,Transmit data mask 12 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 11. "XMASK11,Transmit data mask 11 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 10. "XMASK10,Transmit data mask 10 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 9. "XMASK9,Transmit data mask 9 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 8. "XMASK8,Transmit data mask 8 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 7. "XMASK7,Transmit data mask 7 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 6. "XMASK6,Transmit data mask 6 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 5. "XMASK5,Transmit data mask 5 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 4. "XMASK4,Transmit data mask 4 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 3. "XMASK3,Transmit data mask 3 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 2. "XMASK2,Transmit data mask 2 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 1. "XMASK1,Transmit data mask 1 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 0. "XMASK0,Transmit data mask 0 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" line.long 0x8 "MCASP_TXFMT" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay.0h = 0-bit delay. The first transmit data bit AXRn occurs in same ACLKX cycle as the transmit frame sync (AFSX). 1h = 1-bit delay. The first transmit data bit AXRn occurs one ACLKX cycle after the transmit frame sync.." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order.0h = Bitstream is LSB first. No bit reversal is performed in transmit format bit reverse unit. 1h = Bitstream is MSB first. Bit reversal is performed in transmit format bit reverse unit." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by MCASP_XMASK. This field only applies to bits when MCASP_XMASK[n] = 0. 0h = Pad extra bits with 0. 1h = Pad extra bits with 1. 2h = Pad extra bits with one of the bits from the word as.." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h. 0h = Pad with bit 0 value. 1h = Pad with bit 1 to bit 31 value from 1h to 1Fh." newline hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size.0h = Reserved. 1h = Reserved. 2h = Reserved. 3h = Slot size is 8 bits. 4h = Reserved. 5h = Slot size is 12 bits. 6h = Reserved. 7h = Slot size is 16 bits. 8h = Reserved. 9h = Slot size is 20 bits. Ah = Reserved. Bh = Slot size is.." bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port.0h = Writes to XRBUF[n] originate from the data port. Writes to XRBUF[n] from the configuration bus are ignored with no effect.." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit.0h = Rotate right by 0 (no rotation). 1h = Rotate right by 4 bit positions. 2h = Rotate right by 8 bit positions. 3h = Rotate right by 12 bit positions. 4h = Rotate right by 16 bit.." "0,1,2,3,4,5,6,7" line.long 0xC "MCASP_TXFMCTL" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh. 0h = Burst mode. 1h = Reserved. 2h = 2-slot TDM (I2S mode) to 32-slot TDM from 2h to 20h. 21h = Reserved from 21h to 17Fh. 180h = 384-slot DIT mode. 181h = Reserved from 181h.." bitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period.0h = Single bit. 1h = Single word." "0,1" bitfld.long 0xC 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit.0h = Externally-generated transmit frame sync. 1h = Internally-generated transmit frame sync." "0,1" bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit.0h = A rising edge on transmit frame sync (AFSX) indicates the beginning of a frame. 1h = A falling edge on transmit frame sync (AFSX) indicates the beginning of a frame." "0,1" line.long 0x10 "MCASP_ACLKXCTL" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,The logic OR of bits 18 and 19 indicating that some clk change is in progress when high" "0,1" bitfld.long 0x10 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x10 18. "ADJBUSY,one-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment control. If CLKXDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit.0h = Rising edge. External receiver samples data on the falling edge of the serial clock so the transmitter must shift data out on the rising edge of the serial clock. 1h = Falling edge. External.." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit.0h = Synchronous. Transmit clock and frame sync provides the source for both the transmit and receive sections. 1h = Asynchronous. Separate clock and frame sync used by transmit and receive sections." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit.0h = External transmit clock source from ACLKX pin. 1h = Internal transmit clock source from output of programmable bit clock divider." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX.0h = Divide-by-1. 1h = Divide-by-2. 2h = Divide-by-3 to divide-by-32 from 2h to 1Fh." line.long 0x14 "MCASP_AHCLKXCTL" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,The logic OR of bits 18 and 19 indicating that some clk change is in progress when high" "0,1" bitfld.long 0x14 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x14 18. "ADJBUSY,one-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,CLKXDIV one-shot adjustment control. If CLKXDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit.0h = External transmit high-frequency clock source from AHCLKX pin. 1h = Internal transmit high-frequency clock source from output of programmable high clock divider." "0,1" bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit.0h = AHCLKX is not inverted before programmable bit clock divider. In the special case where the transmit bit clock (ACLKX) is internally generated and the programmable bit clock divider.." "0,1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX.0h = Divide-by-1. 1h = Divide-by-2. 2h = Divide-by-3 to divide-by-4096 from 2h to FFFh." line.long 0x18 "MCASP_TXTDM" bitfld.long 0x18 31. "XTDMS31,Transmitter mode during TDM time slot 31.0h = Transmit TDM time slot 31 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 31 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 30. "XTDMS30,Transmitter mode during TDM time slot 30.0h = Transmit TDM time slot 30 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 30 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 29. "XTDMS29,Transmitter mode during TDM time slot 29.0h = Transmit TDM time slot 29 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 29 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 28. "XTDMS28,Transmitter mode during TDM time slot 28.0h = Transmit TDM time slot 28 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 28 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 27. "XTDMS27,Transmitter mode during TDM time slot 27.0h = Transmit TDM time slot 27 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 27 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 26. "XTDMS26,Transmitter mode during TDM time slot 26.0h = Transmit TDM time slot 26 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 26 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 25. "XTDMS25,Transmitter mode during TDM time slot 25.0h = Transmit TDM time slot 25 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 25 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 24. "XTDMS24,Transmitter mode during TDM time slot 24.0h = Transmit TDM time slot 24 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 24 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 23. "XTDMS23,Transmitter mode during TDM time slot 23.0h = Transmit TDM time slot 23 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 23 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 22. "XTDMS22,Transmitter mode during TDM time slot 22.0h = Transmit TDM time slot 22 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 22 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 21. "XTDMS21,Transmitter mode during TDM time slot 21.0h = Transmit TDM time slot 21 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 21 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 20. "XTDMS20,Transmitter mode during TDM time slot 20.0h = Transmit TDM time slot 20 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 20 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 19. "XTDMS19,Transmitter mode during TDM time slot 19.0h = Transmit TDM time slot 19 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 19 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 18. "XTDMS18,Transmitter mode during TDM time slot 18.0h = Transmit TDM time slot 18 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 18 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 17. "XTDMS17,Transmitter mode during TDM time slot 17.0h = Transmit TDM time slot 17 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 17 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 16. "XTDMS16,Transmitter mode during TDM time slot 16.0h = Transmit TDM time slot 16 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 16 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 15. "XTDMS15,Transmitter mode during TDM time slot 15.0h = Transmit TDM time slot 15 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 15 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 14. "XTDMS14,Transmitter mode during TDM time slot 14.0h = Transmit TDM time slot 14 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 14 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 13. "XTDMS13,Transmitter mode during TDM time slot 13.0h = Transmit TDM time slot 13 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 13 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 12. "XTDMS12,Transmitter mode during TDM time slot 12.0h = Transmit TDM time slot 12 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 12 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 11. "XTDMS11,Transmitter mode during TDM time slot 11.0h = Transmit TDM time slot 11 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 11 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 10. "XTDMS10,Transmitter mode during TDM time slot 10.0h = Transmit TDM time slot 10 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 10 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 9. "XTDMS9,Transmitter mode during TDM time slot 9.0h = Transmit TDM time slot 9 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 9 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 8. "XTDMS8,Transmitter mode during TDM time slot 8.0h = Transmit TDM time slot 8 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 8 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 7. "XTDMS7,Transmitter mode during TDM time slot 7.0h = Transmit TDM time slot 7 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 7 is active. The transmit serializer shifts out data during this slot.." "0,1" newline bitfld.long 0x18 6. "XTDMS6,Transmitter mode during TDM time slot 6.0h = Transmit TDM time slot 6 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 6 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 5. "XTDMS5,Transmitter mode during TDM time slot 5.0h = Transmit TDM time slot 5 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 5 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 4. "XTDMS4,Transmitter mode during TDM time slot 4.0h = Transmit TDM time slot 4 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 4 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 3. "XTDMS3,Transmitter mode during TDM time slot 3.0h = Transmit TDM time slot 3 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 3 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 2. "XTDMS2,Transmitter mode during TDM time slot 2.0h = Transmit TDM time slot 2 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 2 is active. The transmit serializer shifts out data during this slot.." "0,1" newline bitfld.long 0x18 1. "XTDMS1,Transmitter mode during TDM time slot 1.0h = Transmit TDM time slot 1 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 1 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 0. "XTDMS0,Transmitter mode during TDM time slot 0.0h = Transmit TDM time slot 0 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 0 is active. The transmit serializer shifts out data during this slot.." "0,1" line.long 0x1C "MCASP_EVTCTLX" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit.0h = Interrupt is disabled. A transmit start of frame interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit start of frame interrupt generates a McASP.." "0,1" bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit.0h = Interrupt is disabled. A transmit data ready interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit data ready interrupt generates a McASP transmit.." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit.0h = Interrupt is disabled. A transmit last slot interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit last slot interrupt generates a McASP transmit interrupt.." "0,1" newline bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit.0h = Interrupt is disabled. A transmit DMA error interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit DMA error interrupt generates a McASP transmit interrupt.." "0,1" bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit.0h = Interrupt is disabled. A transmit clock failure interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit clock failure interrupt generates a McASP.." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit.0h = Interrupt is disabled. An unexpected transmit frame sync interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. An unexpected transmit frame sync.." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit.0h = Interrupt is disabled. A transmitter underrun interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmitter underrun interrupt generates a McASP transmit.." "0,1" line.long 0x20 "MCASP_TXSTAT" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred. 0h = No errors have occurred. 1h = An error has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect. 0h = No new transmit frame sync (AFSX) is.." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect. 0h = XBUF is written and is full. 1h = Data is copied.." "0,1" newline bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of MCASP_XSLOT. Allows a single read of MCASP_XSTAT to determine whether the current TDM time slot is even or odd. 0h = Current TDM time slot is odd. 1h = Current TDM time slot is even." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this.." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in MCASP_XINTCTL is set. This bit is cleared by writing.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." group.long 0xC8++0xB line.long 0x0 "MCASP_TXCLKCHK" hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh. 0h = MCASP system clock divided by 1. 1h = MCASP system clock divided by 2. 2h = MCASP system clock divided by 4. 3h = MCASP system clock divided by 8. 4h = MCASP system clock divided.." line.long 0x4 "MCASP_XEVTCTL" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0. 0h = Transmit data DMA request is enabled. 1h = Reserved" "0,1" line.long 0x8 "MCASP_CLKADJEN" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0. "ENABLE,One-shot clock adjustment enable. 0 = One-shot clock adjustment is DISABLED. Writes to bits 17:16 of 1 = One-shot clock adjustment is ENABLED. Writes to bits 17:16 of" "0: One-shot clock adjustment is DISABLED,1: One-shot clock adjustment is ENABLED" group.long 0x100++0x5F line.long 0x0 "MCASP_DITCSRA0" hexmask.long 0x0 0.--31. 1. "DITCSRA0,DIT left channel status registers." line.long 0x4 "MCASP_DITCSRA1" hexmask.long 0x4 0.--31. 1. "DITCSRA1,DIT left channel status registers." line.long 0x8 "MCASP_DITCSRA2" hexmask.long 0x8 0.--31. 1. "DITCSRA2,DIT left channel status registers." line.long 0xC "MCASP_DITCSRA3" hexmask.long 0xC 0.--31. 1. "DITCSRA3,DIT left channel status registers." line.long 0x10 "MCASP_DITCSRA4" hexmask.long 0x10 0.--31. 1. "DITCSRA4,DIT left channel status registers." line.long 0x14 "MCASP_DITCSRA5" hexmask.long 0x14 0.--31. 1. "DITCSRA5,DIT left channel status registers." line.long 0x18 "MCASP_DITCSRB0" hexmask.long 0x18 0.--31. 1. "DITCSRB0,DIT right channel status registers." line.long 0x1C "MCASP_DITCSRB1" hexmask.long 0x1C 0.--31. 1. "DITCSRB1,DIT right channel status registers." line.long 0x20 "MCASP_DITCSRB2" hexmask.long 0x20 0.--31. 1. "DITCSRB2,DIT right channel status registers." line.long 0x24 "MCASP_DITCSRB3" hexmask.long 0x24 0.--31. 1. "DITCSRB3,DIT right channel status registers." line.long 0x28 "MCASP_DITCSRB4" hexmask.long 0x28 0.--31. 1. "DITCSRB4,DIT right channel status registers." line.long 0x2C "MCASP_DITCSRB5" hexmask.long 0x2C 0.--31. 1. "DITCSRB5,DIT right channel status registers." line.long 0x30 "MCASP_DITUDRA0" hexmask.long 0x30 0.--31. 1. "DITUDRA0,DIT left channel user data registers." line.long 0x34 "MCASP_DITUDRA1" hexmask.long 0x34 0.--31. 1. "DITUDRA1,DIT left channel user data registers." line.long 0x38 "MCASP_DITUDRA2" hexmask.long 0x38 0.--31. 1. "DITUDRA2,DIT left channel user data registers." line.long 0x3C "MCASP_DITUDRA3" hexmask.long 0x3C 0.--31. 1. "DITUDRA3,DIT left channel user data registers." line.long 0x40 "MCASP_DITUDRA4" hexmask.long 0x40 0.--31. 1. "DITUDRA4,DIT left channel user data registers." line.long 0x44 "MCASP_DITUDRA5" hexmask.long 0x44 0.--31. 1. "DITUDRA5,DIT left channel user data registers." line.long 0x48 "MCASP_DITUDRB0" hexmask.long 0x48 0.--31. 1. "DITUDRB0,DIT right channel user data registers." line.long 0x4C "MCASP_DITUDRB1" hexmask.long 0x4C 0.--31. 1. "DITUDRB1,DIT right channel user data registers." line.long 0x50 "MCASP_DITUDRB2" hexmask.long 0x50 0.--31. 1. "DITUDRB2,DIT right channel user data registers." line.long 0x54 "MCASP_DITUDRB3" hexmask.long 0x54 0.--31. 1. "DITUDRB3,DIT right channel user data registers." line.long 0x58 "MCASP_DITUDRB4" hexmask.long 0x58 0.--31. 1. "DITUDRB4,DIT right channel user data registers." line.long 0x5C "MCASP_DITUDRB5" hexmask.long 0x5C 0.--31. 1. "DITUDRB5,DIT right channel user data registers." group.long 0x180++0x3F line.long 0x0 "MCASP_XRSRCTL0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x4 "MCASP_XRSRCTL1" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x8 "MCASP_XRSRCTL2" hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0xC "MCASP_XRSRCTL3" hexmask.long 0xC 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x10 "MCASP_XRSRCTL4" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x14 "MCASP_XRSRCTL5" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x18 "MCASP_XRSRCTL6" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x1C "MCASP_XRSRCTL7" hexmask.long 0x1C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x20 "MCASP_XRSRCTL8" hexmask.long 0x20 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x24 "MCASP_XRSRCTL9" hexmask.long 0x24 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x28 "MCASP_XRSRCTL10" hexmask.long 0x28 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x2C "MCASP_XRSRCTL11" hexmask.long 0x2C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x30 "MCASP_XRSRCTL12" hexmask.long 0x30 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x34 "MCASP_XRSRCTL13" hexmask.long 0x34 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x38 "MCASP_XRSRCTL14" hexmask.long 0x38 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x3C "MCASP_XRSRCTL15" hexmask.long 0x3C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" group.long 0x200++0x3F line.long 0x0 "MCASP_TXBUF0" hexmask.long 0x0 0.--31. 1. "XBUF0,Transmit buffers for serializers." line.long 0x4 "MCASP_TXBUF1" hexmask.long 0x4 0.--31. 1. "XBUF1,Transmit buffers for serializers." line.long 0x8 "MCASP_TXBUF2" hexmask.long 0x8 0.--31. 1. "XBUF2,Transmit buffers for serializers." line.long 0xC "MCASP_TXBUF3" hexmask.long 0xC 0.--31. 1. "XBUF3,Transmit buffers for serializers." line.long 0x10 "MCASP_TXBUF4" hexmask.long 0x10 0.--31. 1. "XBUF4,Transmit buffers for serializers." line.long 0x14 "MCASP_TXBUF5" hexmask.long 0x14 0.--31. 1. "XBUF5,Transmit buffers for serializers." line.long 0x18 "MCASP_TXBUF6" hexmask.long 0x18 0.--31. 1. "XBUF6,Transmit buffers for serializers." line.long 0x1C "MCASP_TXBUF7" hexmask.long 0x1C 0.--31. 1. "XBUF7,Transmit buffers for serializers." line.long 0x20 "MCASP_TXBUF8" hexmask.long 0x20 0.--31. 1. "XBUF8,Transmit buffers for serializers." line.long 0x24 "MCASP_TXBUF9" hexmask.long 0x24 0.--31. 1. "XBUF9,Transmit buffers for serializers." line.long 0x28 "MCASP_TXBUF10" hexmask.long 0x28 0.--31. 1. "XBUF10,Transmit buffers for serializers." line.long 0x2C "MCASP_TXBUF11" hexmask.long 0x2C 0.--31. 1. "XBUF11,Transmit buffers for serializers." line.long 0x30 "MCASP_TXBUF12" hexmask.long 0x30 0.--31. 1. "XBUF12,Transmit buffers for serializers." line.long 0x34 "MCASP_TXBUF13" hexmask.long 0x34 0.--31. 1. "XBUF13,Transmit buffers for serializers." line.long 0x38 "MCASP_TXBUF14" hexmask.long 0x38 0.--31. 1. "XBUF14,Transmit buffers for serializers." line.long 0x3C "MCASP_TXBUF15" hexmask.long 0x3C 0.--31. 1. "XBUF15,Transmit buffers for serializers." group.long 0x280++0x3F line.long 0x0 "MCASP_RXBUF0" hexmask.long 0x0 0.--31. 1. "RBUF0,Receive buffers for serializers." line.long 0x4 "MCASP_RXBUF1" hexmask.long 0x4 0.--31. 1. "RBUF1,Receive buffers for serializers." line.long 0x8 "MCASP_RXBUF2" hexmask.long 0x8 0.--31. 1. "RBUF2,Receive buffers for serializers." line.long 0xC "MCASP_RXBUF3" hexmask.long 0xC 0.--31. 1. "RBUF3,Receive buffers for serializers." line.long 0x10 "MCASP_RXBUF4" hexmask.long 0x10 0.--31. 1. "RBUF4,Receive buffers for serializers." line.long 0x14 "MCASP_RXBUF5" hexmask.long 0x14 0.--31. 1. "RBUF5,Receive buffers for serializers." line.long 0x18 "MCASP_RXBUF6" hexmask.long 0x18 0.--31. 1. "RBUF6,Receive buffers for serializers." line.long 0x1C "MCASP_RXBUF7" hexmask.long 0x1C 0.--31. 1. "RBUF7,Receive buffers for serializers." line.long 0x20 "MCASP_RXBUF8" hexmask.long 0x20 0.--31. 1. "RBUF8,Receive buffers for serializers." line.long 0x24 "MCASP_RXBUF9" hexmask.long 0x24 0.--31. 1. "RBUF9,Receive buffers for serializers." line.long 0x28 "MCASP_RXBUF10" hexmask.long 0x28 0.--31. 1. "RBUF10,Receive buffers for serializers." line.long 0x2C "MCASP_RXBUF11" hexmask.long 0x2C 0.--31. 1. "RBUF11,Receive buffers for serializers." line.long 0x30 "MCASP_RXBUF12" hexmask.long 0x30 0.--31. 1. "RBUF12,Receive buffers for serializers." line.long 0x34 "MCASP_RXBUF13" hexmask.long 0x34 0.--31. 1. "RBUF13,Receive buffers for serializers." line.long 0x38 "MCASP_RXBUF14" hexmask.long 0x38 0.--31. 1. "RBUF14,Receive buffers for serializers." line.long 0x3C "MCASP_RXBUF15" hexmask.long 0x3C 0.--31. 1. "RBUF15,Receive buffers for serializers." tree.end tree "MCASP1_DMA" base ad:0x2B18000 rgroup.long 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers. For receive operations through the DATA port. the Host should read from the same.." hexmask.long 0x0 0.--31. 1. "RXBUF,Rx buffer data." wgroup.long 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port. the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port. the Host should write to the same DATA.." hexmask.long 0x0 0.--31. 1. "TXBUF,Tx buffer data." tree.end tree "MCASP2_CFG" base ad:0x2B20000 rgroup.long 0x0++0x3 line.long 0x0 "MCASP_PID" bitfld.long 0x0 30.--31. "SCHEME,Distinguishes between old scheme and current." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Indicates a software-compatible module family." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version." bitfld.long 0x0 8.--10. "REVMAJOR,Major revision number." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a given device." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMINOR,Minor revision number." group.long 0x4++0x3 line.long 0x0 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG register." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLE_MODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state. 0h = Force-idle mode: local target's idle state follows (acknowledges) the.." "0,1,2,3" group.long 0x10++0xB line.long 0x0 "MCASP_PFUNC" bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Determines if AXR15 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 14. "AXR14,Determines if AXR14 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 13. "AXR13,Determines if AXR13 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 12. "AXR12,Determines if AXR12 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 11. "AXR11,Determines if AXR11 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 10. "AXR10,Determines if AXR10 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 9. "AXR9,Determines if AXR9 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 8. "AXR8,Determines if AXR8 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 7. "AXR7,Determines if AXR7 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 6. "AXR6,Determines if AXR6 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 5. "AXR5,Determines if AXR5 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 4. "AXR4,Determines if AXR4 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" newline bitfld.long 0x0 3. "AXR3,Determines if AXR3 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 2. "AXR2,Determines if AXR2 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 1. "AXR1,Determines if AXR1 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" bitfld.long 0x0 0. "AXR0,Determines if AXR0 pin functions as McASP or GPIO.0h = Pin functions as McASP pin. 1h = Pin functions as GPIO pin." "0,1" line.long 0x4 "MCASP_PDIR" bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" hexmask.long.word 0x4 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "AXR15,Determines if AXR15 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 14. "AXR14,Determines if AXR14 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 13. "AXR13,Determines if AXR13 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 12. "AXR12,Determines if AXR12 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 11. "AXR11,Determines if AXR11 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 10. "AXR10,Determines if AXR10 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 9. "AXR9,Determines if AXR9 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 8. "AXR8,Determines if AXR8 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 7. "AXR7,Determines if AXR7 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 6. "AXR6,Determines if AXR6 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 5. "AXR5,Determines if AXR5 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 4. "AXR4,Determines if AXR4 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" newline bitfld.long 0x4 3. "AXR3,Determines if AXR3 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 2. "AXR2,Determines if AXR2 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 1. "AXR1,Determines if AXR1 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" bitfld.long 0x4 0. "AXR0,Determines if AXR0 pin functions as an input or output.0h = Pin functions as input. 1h = Pin functions as output." "0,1" line.long 0x8 "MCASP_PDOUT" bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the correspondingMCASP_PFUNC[25] and MCASP_PDIR[25] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" hexmask.long.word 0x8 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" newline bitfld.long 0x8 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" bitfld.long 0x8 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1. 0h = Pin drives low. 1h = Pin drives high." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCASP_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR." bitfld.long 0x0 31. "AFSR,Logic level on AFSR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 30. "AHCLKR,Logic level on AHCLKR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 29. "ACLKR,Logic level on ACLKR pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 28. "AFSX,Logic level on AFSX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 27. "AHCLKX,Logic level on AHCLKX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 26. "ACLKX,Logic level on ACLKX pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 25. "AMUTE,Logic level on AMUTE pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Logic level on AXR15 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 14. "AXR14,Logic level on AXR14 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 13. "AXR13,Logic level on AXR13 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 12. "AXR12,Logic level on AXR12 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 11. "AXR11,Logic level on AXR11 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 10. "AXR10,Logic level on AXR10 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 9. "AXR9,Logic level on AXR9 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 8. "AXR8,Logic level on AXR8 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 7. "AXR7,Logic level on AXR7 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 6. "AXR6,Logic level on AXR6 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 5. "AXR5,Logic level on AXR5 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 4. "AXR4,Logic level on AXR4 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" newline bitfld.long 0x0 3. "AXR3,Logic level on AXR3 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 2. "AXR2,Logic level on AXR2 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 1. "AXR1,Logic level on AXR1 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" bitfld.long 0x0 0. "AXR0,Logic level on AXR0 pin.0h = Pin is logic low. 1h = Pin is logic high." "0,1" group.long 0x1C++0x7 line.long 0x0 "MCASP_PDSET,The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x0 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 30. "AHCLKR,Allows the corresponding AHCLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 25. "AMUTE,Allows the corresponding AMUTE bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" hexmask.long.word 0x0 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "AXR15,Allows the corresponding AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 14. "AXR14,Allows the corresponding AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 13. "AXR13,Allows the corresponding AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 12. "AXR12,Allows the corresponding AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 11. "AXR11,Allows the corresponding AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 10. "AXR10,Allows the corresponding AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 9. "AXR9,Allows the corresponding AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 8. "AXR8,Allows the corresponding AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 7. "AXR7,Allows the corresponding AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 6. "AXR6,Allows the corresponding AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 5. "AXR5,Allows the corresponding AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 4. "AXR4,Allows the corresponding AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x0 3. "AXR3,Allows the corresponding AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 2. "AXR2,Allows the corresponding AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 1. "AXR1,Allows the corresponding AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x0 0. "AXR0,Allows the corresponding AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" line.long 0x4 "MCASP_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a.." bitfld.long 0x4 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 30. "AHCLKR,Allows the corresponding AHCLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 25. "AMUTE,Allows the corresponding AMUTE bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" hexmask.long.word 0x4 16.--24. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "AXR15,Allows the corresponding AXR[15] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 14. "AXR14,Allows the corresponding AXR[14] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 13. "AXR13,Allows the corresponding AXR[13] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 12. "AXR12,Allows the corresponding AXR[12] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 11. "AXR11,Allows the corresponding AXR[11] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 10. "AXR10,Allows the corresponding AXR[10] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 9. "AXR9,Allows the corresponding AXR[9] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 8. "AXR8,Allows the corresponding AXR[8] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 7. "AXR7,Allows the corresponding AXR[7] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 6. "AXR6,Allows the corresponding AXR[6] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 5. "AXR5,Allows the corresponding AXR[5] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 4. "AXR4,Allows the corresponding AXR[4] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" newline bitfld.long 0x4 3. "AXR3,Allows the corresponding AXR[3] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 2. "AXR2,Allows the corresponding AXR[2] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 1. "AXR1,Allows the corresponding AXR[1] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" bitfld.long 0x4 0. "AXR0,Allows the corresponding AXR[0] bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. 0h = No effect. 1h =" "0,1" group.long 0x30++0xB line.long 0x0 "MCASP_TLGC,for IODFT" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 14.--15. "MT,MISR on/off trigger command. These monitor trigger codes only are affective for the MISR signature capture when MC = 3h. MT Code effect on MISR: 0h = MISR capture start on the first active cycle decode of the IP bus activity and continues to update.." "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "MMS,Chooses the source of the MISR input: 0h = output register 1h = input capture" "0,1" bitfld.long 0x0 7. "ESEL,Output enable select: 0h = test mode and the functional OEN is gated off 1h = normal functional mode" "0,1" newline bitfld.long 0x0 6. "TOEN,Test output enable control. This signal is paired with ESEL. TOEN is never 1 when ESEL is 1. When ESEL is 0 (test mode) TOEN is: 0h = output enabled 1h = output disabled Note: In boundary scan mode this signal is not selected and the BSR controls.." "0,1" bitfld.long 0x0 4.--5. "MC,This defines the states of the MISR: 0h = download results 1h = hold current value 2h = load initial value (from PC bits) 3h = MISR enable to capture signature" "0,1,2,3" bitfld.long 0x0 1.--3. "PC,Pattern code defines the type of pattern that is selected for the artificial pattern generation logic in the IODFT. Modes: 0h = functional (default) 1h = random XOR 2h = random XNOR 3h = shift register 4h = hold current value Note: McASP does not have.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "TM,At reset the value is 1 for normal functional mode. This bit is tied high and should not be written to." "0,1" line.long 0x4 "MCASP_TLMR,for IODFT" hexmask.long 0x4 0.--31. 1. "TLMR,This contains the result signature of a given test after the download function is executed." line.long 0x8 "MCASP_TLEC,for IODFT" hexmask.long 0x8 0.--31. 1. "TLEC,Contains the number of cycles during which the MISR signature will be accumulated." group.long 0x44++0xF line.long 0x0 "MCASP_GBLCTL" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit.0h = Transmit frame sync generator is reset. 1h = Transmit frame sync generator is active. When released from reset the transmit frame sync generator begins counting serial clocks and generating frame.." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit.0h = Transmit state machine is held in reset. AXRn pin state: If 1h = Transmit state machine is released from reset. When released from reset the transmit state machine immediately transfers data from.." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit.0h = Transmit high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Transmit high-frequency clock divider is running." "0,1" newline bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit.0h = Transmit clock divider is held in reset. When the clock divider is in reset it passes through a divide-by-1 of its input. 1h = Transmit clock divider is running." "0,1" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit.0h = Receive frame sync generator is reset. 1h = Receive frame sync generator is active. When released from reset the receive frame sync generator begins counting serial clocks and generating frame.." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit.0h = Receive state machine is held in reset. 1h = Receive state machine is released from reset. When released from reset the receive state machine immediately begins detecting frame sync and is ready to.." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed. 0h = Receive serializers are cleared. 1h = Receive serializers are active." "0,1" newline bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit.0h = Receive high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Receive high-frequency clock divider is running." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit.0h = Receive clock divider is held in reset. When the clock divider is in reset it passes through a divide-by-1 of its input. 1h = Receive clock divider is running." "0,1" line.long 0x4 "MCASP_AMUTE" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit DMA error is ignored by 1h = Drive is enabled (active). Upon detection of transmit DMA error " "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receive DMA error is ignored by 1h = Drive is enabled (active). Upon detection of receive DMA error " "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit clock failure is ignored by 1h = Drive is enabled (active). Upon detection of transmit clock failure " "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receive clock failure is ignored by 1h = Drive is enabled (active). Upon detection of receive clock failure " "0,1" newline bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of unexpected transmit frame sync error is ignored by 1h = Drive is enabled (active). Upon detection of unexpected transmit.." "0,1" bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of unexpected receive frame sync error is ignored by 1h = Drive is enabled (active). Upon detection of unexpected receive.." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of transmit underrun error is ignored by 1h = Drive is enabled (active). Upon detection of transmit underrun error " "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] driveMCASP_AMUTE active enable bit. 0h = Drive is disabled. Detection of receiver overrun error is ignored by 1h = Drive is enabled (active). Upon detection of receiver overrun error " "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin whenMCASP_PFUNC[n] and MCASP_PDIR[n] bits are set to 1. 0h = AMUTEIN pin is inactive. 1h = AMUTEIN pin is active. Audio mute in error is detected." "0,1" newline bitfld.long 0x4 3. "INEN,DriveMCASP_AMUTE active when AMUTEIN error is active [INSTAT = 1]. 0h = Drive is disabled. AMUTEIN is ignored by 1h = Drive is enabled (active). INSTAT = 1 drives" "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit.0h = Polarity is active high. A high on AMUTEIN sets INSTAT to 1. 1h = Polarity is active low. A low on AM UTEIN sets INSTAT to 1." "0,1" bitfld.long 0x4 0.--1. "MUTEN,MCASP_AMUTE pin enable bit [unless overridden by GPIO registers]. 0h = 1h = 2h = 3h = Reserved" "0,1,2,3" line.long 0x8 "MCASP_LBCTL" hexmask.long 0x8 5.--31. 1. "RESERVED" bitfld.long 0x8 4. "IOLBEN,I/O loopback enable. Chip-level loopback; looped back through I/O buffers. 0h = I/O loopback disabled 1h = I/O loopback enabled Note: These are only valid if LBEN = 1. If LBEN = 0 neither internal nor I/O loopback will be selected." "0,1" bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]. 0h = Default and reserved on loopback mode (DLBEN = 1). When in non-loopback mode (DLBEN = 0) MODE should be left at default (00). When in loopback mode (DLBEN =.." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1].0h = Odd serializers N + 1 transmit to even serializers N that receive. The corresponding serializers must be programmed properly. 1h = Even serializers N transmit to odd serializers N + 1.." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit.0h = Loopback mode is disabled. 1h = Loopback mode is enabled." "0,1" line.long 0xC "MCASP_TXDITCTL" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe].0h = V bit is 0 during odd DIT subframes. 1h = V bit is 1 during odd DIT subframes." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe].0h = V bit is 0 during even DIT subframes. 1h = V bit is 1 during even DIT subframes." "0,1" bitfld.long 0xC 1. "RESERVED,Reserved" "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in MCASP_GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in MCASP_GBLCTL to change DITEN. 0h = DIT.." "0,1" group.long 0x60++0x23 line.long 0x0 "MCASP_GBLCTLR" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" bitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of MCASP_GBLCTL. 0h = Receive frame sync generator is reset. 1h = Receive frame sync generator is active." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of MCASP_GBLCTL. 0h = Receive state machine is held in reset. 1h = Receive state machine is released from reset." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of MCASP_GBLCTL. 0h = Receive serializers are cleared. 1h = Receive serializers are active." "0,1" newline bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of MCASP_GBLCTL. 0h = Receive high-frequency clock divider is held in reset and passes through its input as divide-by-1. 1h = Receive.." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of MCASP_GBLCTL. 0h = Receive clock divider is held in reset. 1h = Receive clock divider is running." "0,1" line.long 0x4 "MCASP_RXMASK" bitfld.long 0x4 31. "RMASK31,Receive data mask 31 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 30. "RMASK30,Receive data mask 30 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 29. "RMASK29,Receive data mask 29 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 28. "RMASK28,Receive data mask 28 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 27. "RMASK27,Receive data mask 27 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 26. "RMASK26,Receive data mask 26 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 25. "RMASK25,Receive data mask 25 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 24. "RMASK24,Receive data mask 24 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 23. "RMASK23,Receive data mask 23 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 22. "RMASK22,Receive data mask 22 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 21. "RMASK21,Receive data mask 21 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 20. "RMASK20,Receive data mask 20 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 19. "RMASK19,Receive data mask 19 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 18. "RMASK18,Receive data mask 18 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 17. "RMASK17,Receive data mask 17 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 16. "RMASK16,Receive data mask 16 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 15. "RMASK15,Receive data mask 15 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 14. "RMASK14,Receive data mask 14 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 13. "RMASK13,Receive data mask 13 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 12. "RMASK12,Receive data mask 12 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 11. "RMASK11,Receive data mask 11 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 10. "RMASK10,Receive data mask 10 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 9. "RMASK9,Receive data mask 9 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 8. "RMASK8,Receive data mask 8 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 7. "RMASK7,Receive data mask 7 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 6. "RMASK6,Receive data mask 6 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 5. "RMASK5,Receive data mask 5 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 4. "RMASK4,Receive data mask 4 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 3. "RMASK3,Receive data mask 3 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 2. "RMASK2,Receive data mask 2 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" newline bitfld.long 0x4 1. "RMASK1,Receive data mask 1 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" bitfld.long 0x4 0. "RMASK0,Receive data mask 0 enable bit.0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in MCASP_RFMT). 1h = Corresponding bit of.." "0,1" line.long 0x8 "MCASP_RXFMT" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay.0h = 0-bit delay. The first receive data bit AXRn occurs in same ACLKR cycle as the receive frame sync (AFSR). 1h = 1-bit delay. The first receive data bit AXRn occurs one ACLKR cycle after the receive frame sync (AFSR). 2h.." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order.0h = Bitstream is LSB first. No bit reversal is performed in receive format bit reverse unit. 1h = Bitstream is MSB first. Bit reversal is performed in receive format bit reverse unit." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when MCASP_RMASK[n] = 0. 0h = Pad extra bits with 0. 1h = Pad extra bits with 1. 2h = Pad extra bits with one of the bits from the word as specified by RPBIT.." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h. 0h = Pad with bit 0 value. 1h = Pad with bit 1 to bit 31 value from 1h to 1Fh." newline hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size.0h = Reseved. 1h = Reserved. 2h = Reserved. 3h = Slot size is 8 bits. 4h = Reserved 5h = Slot size is 12 bits. 6h = Reserved 7h = Slot size is 16 bits. 8h = Reserved 9h = Slot size is 20 bits. Ah = Reserved Bh = Slot size is 24.." bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port.0h = Reads from XRBUF[n] originate on data port. Reads from XRBUF[n] on configuration bus are ignored. 1h = Reads from XRBUF[n].." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit.0h = Rotate right by 0 (no rotation). 1h = Rotate right by 4 bit positions. 2h = Rotate right by 8 bit positions. 3h = Rotate right by 12 bit positions. 4h = Rotate right by 16 bit positions." "0,1,2,3,4,5,6,7" line.long 0xC "MCASP_RXFMCTL" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh. 0h = Burst mode. 1h = Reserved. 2h = 2-slot TDM (I2S mode) to 32-slot TDM from 2h to 20h. 21h = Reserved from 21h to 17Fh. 180h = 384-slot TDM (external DIR IC inputting.." bitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period.0h = Single bit. 1h = Single word." "0,1" bitfld.long 0xC 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit.0h = Externally-generated receive frame sync. 1h = Internally-generated receive frame sync." "0,1" bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit.0h = A rising edge on receive frame sync (AFSR) indicates the beginning of a frame. 1h = A falling edge on receive frame sync (AFSR) indicates the beginning of a frame." "0,1" line.long 0x10 "MCASP_ACLKRCTL" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,Тhe OR of bits 18 and 19 indicating that some clk change is in progress when high." "0,1" bitfld.long 0x10 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x10 18. "ADJBUSY,One-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment contro.l If CLKRDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock no adjustment 1h = (m-1) input clocks per output clock 2h =.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "CLKRP,Bitstream clock polarity for receive section: 0h = Falling Edge. Receiver captures sample data on the falling edge of the serial clock so the EXTERNAL transmitter driving this receiver must shift data out on the rising edge of the serial clock. 1h.." "0,1" bitfld.long 0x10 6. "RESERVED,Reserved" "0,1" bitfld.long 0x10 5. "CLKRM,Receive clock source: 0h = External Transmit Clock From ACLKR pin 1h = Internal (output of divider) output clock on ACLKR pin." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive clock divide ratio from high frequency transmit clock: 00000b = /1 00001b = /2 . . . 11111b = /32 All values between /1 and /32 are supported." line.long 0x14 "MCASP_AHCLKRCTL" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,The OR of bits 18 and 19 indicating that some clk change is in progress when high." "0,1" bitfld.long 0x14 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x14 18. "ADJBUSY,One-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)." "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment control If HCLKRDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline bitfld.long 0x14 15. "HCLKRM,High frequency receive clock source: 0h = External Clock on AHCLKR pin passes through divider (typically set to /1). 1h = Internal CPU Clock passed through divider. Divider output on AHCLKR pin." "0,1" bitfld.long 0x14 14. "HCLKRP,high frequency clock polarity: 0h = AHCLKR not inverted before divider. Rising Edge of AHCLKR causes edges on ACLKR when internally generated. 1h = AHCLKR inverted before divider. Falling Edge of AHCLK causes edges on ACLKR when internally.." "0,1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive clock divide ratio from CPU master clock or external high frequency clock: 0000 0000 0000b = /1 0000 0000 0001b = /2 . . . 1111 1111 1111b = /4096 All values between /1 and /4096 are supported." line.long 0x18 "MCASP_RXTDM" bitfld.long 0x18 31. "RTDMS31,Receiver mode during TDM time slot 31.0h = Receive TDM time slot 31 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 31 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 30. "RTDMS30,Receiver mode during TDM time slot 30.0h = Receive TDM time slot 30 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 30 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 29. "RTDMS29,Receiver mode during TDM time slot 29.0h = Receive TDM time slot 29 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 29 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 28. "RTDMS28,Receiver mode during TDM time slot 28.0h = Receive TDM time slot 28 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 28 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 27. "RTDMS27,Receiver mode during TDM time slot 27.0h = Receive TDM time slot 27 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 27 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 26. "RTDMS26,Receiver mode during TDM time slot 26.0h = Receive TDM time slot 26 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 26 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 25. "RTDMS25,Receiver mode during TDM time slot 25.0h = Receive TDM time slot 25 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 25 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 24. "RTDMS24,Receiver mode during TDM time slot 24.0h = Receive TDM time slot 24 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 24 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 23. "RTDMS23,Receiver mode during TDM time slot 23.0h = Receive TDM time slot 23 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 23 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 22. "RTDMS22,Receiver mode during TDM time slot 22.0h = Receive TDM time slot 22 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 22 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 21. "RTDMS21,Receiver mode during TDM time slot 21.0h = Receive TDM time slot 21 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 21 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 20. "RTDMS20,Receiver mode during TDM time slot 20.0h = Receive TDM time slot 20 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 20 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 19. "RTDMS19,Receiver mode during TDM time slot 19.0h = Receive TDM time slot 19 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 19 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 18. "RTDMS18,Receiver mode during TDM time slot 18.0h = Receive TDM time slot 18 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 18 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 17. "RTDMS17,Receiver mode during TDM time slot 17.0h = Receive TDM time slot 17 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 17 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 16. "RTDMS16,Receiver mode during TDM time slot 16.0h = Receive TDM time slot 16 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 16 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 15. "RTDMS15,Receiver mode during TDM time slot 15.0h = Receive TDM time slot 15 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 15 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 14. "RTDMS14,Receiver mode during TDM time slot 14.0h = Receive TDM time slot 14 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 14 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 13. "RTDMS13,Receiver mode during TDM time slot 13.0h = Receive TDM time slot 13 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 13 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 12. "RTDMS12,Receiver mode during TDM time slot 12.0h = Receive TDM time slot 12 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 12 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 11. "RTDMS11,Receiver mode during TDM time slot 11.0h = Receive TDM time slot 11 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 11 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 10. "RTDMS10,Receiver mode during TDM time slot 10.0h = Receive TDM time slot 10 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 10 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 9. "RTDMS9,Receiver mode during TDM time slot 9.0h = Receive TDM time slot 9 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 9 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 8. "RTDMS8,Receiver mode during TDM time slot 8.0h = Receive TDM time slot 8 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 8 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 7. "RTDMS7,Receiver mode during TDM time slot 7.0h = Receive TDM time slot 7 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 7 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 6. "RTDMS6,Receiver mode during TDM time slot 6.0h = Receive TDM time slot 6 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 6 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 5. "RTDMS5,Receiver mode during TDM time slot 5.0h = Receive TDM time slot 5 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 5 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 4. "RTDMS4,Receiver mode during TDM time slot 4.0h = Receive TDM time slot 4 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 4 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 3. "RTDMS3,Receiver mode during TDM time slot 3.0h = Receive TDM time slot 3 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 3 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 2. "RTDMS2,Receiver mode during TDM time slot 2.0h = Receive TDM time slot 2 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 2 is active. The receive serializer shifts in data during this slot." "0,1" newline bitfld.long 0x18 1. "RTDMS1,Receiver mode during TDM time slot 1.0h = Receive TDM time slot 1 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 1 is active. The receive serializer shifts in data during this slot." "0,1" bitfld.long 0x18 0. "RTDMS0,Receiver mode during TDM time slot 0.0h = Receive TDM time slot 0 is inactive. The receive serializer does not shift in data during this slot. 1h = Receive TDM time slot 0 is active. The receive serializer shifts in data during this slot." "0,1" line.long 0x1C "MCASP_EVTCTLR" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit.0h = Interrupt is disabled. A receive start of frame interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive start of frame interrupt generates a MCASP receive.." "0,1" bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit.0h = Interrupt is disabled. A receive data ready interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive data ready interrupt generates a MCASP receive interrupt.." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit.0h = Interrupt is disabled. A receive last slot interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive last slot interrupt generates a MCASP receive interrupt (RINT)." "0,1" newline bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit.0h = Interrupt is disabled. A receive DMA error interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive DMA error interrupt generates a MCASP receive interrupt.." "0,1" bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit.0h = Interrupt is disabled. A receive clock failure interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive clock failure interrupt generates a MCASP receive.." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit.0h = Interrupt is disabled. An unexpected receive frame sync interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. An unexpected receive frame sync interrupt.." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit.0h = Interrupt is disabled. A receiver overrun interrupt does not generate a MCASP receive interrupt (RINT). 1h = Interrupt is enabled. A receiver overrun interrupt generates a MCASP receive interrupt (RINT)." "0,1" line.long 0x20 "MCASP_RXSTAT" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred. 0h = No errors have occurred. 1h = An error has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in MCASP_RINTCTL is.." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect. 0h = No new receive frame sync (AFSR).." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect. 0h = No new data in RBUF. 1h = Data is.." "0,1" newline bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing.." "0,1" bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of MCASP_RSLOT. Allows a single read of MCASP_RSTAT to determine whether the current TDM time slot is even or odd. 0h = Current TDM time slot is odd. 1h = Current TDM time slot is even." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in MCASP_RINTCTL is set. This bit is cleared by writing a 1 to this.." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in MCASP_RINTCTL is set. This bit is cleared by writing a 1.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for &gt; 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." group.long 0x88++0x7 line.long 0x0 "MCASP_RXCLKCHK" hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value.0h = MCASP system clock divided by 1. 1h = MCASP system clock divided by 2. 2h = MCASP system clock divided by 4. 3h = MCASP system clock divided by 8. 4h = MCASP system clock divided by 16. 5h = MCASP system clock.." line.long 0x4 "MCASP_REVTCTL" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0. 0h = Receive data DMA request is enabled. 1h = Reserved" "0,1" group.long 0xA0++0x23 line.long 0x0 "MCASP_GBLCTLX" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of MCASP_GBLCTL. 0h = Transmit frame sync generator is reset. 1h = Transmit frame sync generator is active." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of MCASP_GBLCTL. 0h = Transmit state machine is held in reset. 1h = Transmit state machine is released from reset." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of MCASP_GBLCTL. 0h = Transmit serializers are cleared. 1h = Transmit serializers are active." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of MCASP_GBLCTL. 0h = Transmit high-frequency clock divider is held in reset. 1h = Transmit high-frequency clock divider is running." "0,1" newline bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of MCASP_GBLCTL. 0h = Transmit clock divider is held in reset. 1h = Transmit clock divider is running." "0,1" bitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLKR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of MCASP_GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of MCASP_GBLCTL. Writes have no effect." "0,1" line.long 0x4 "MCASP_TXMASK" bitfld.long 0x4 31. "XMASK31,Transmit data mask 31 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 30. "XMASK30,Transmit data mask 30 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 29. "XMASK29,Transmit data mask 29 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 28. "XMASK28,Transmit data mask 28 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 27. "XMASK27,Transmit data mask 27 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 26. "XMASK26,Transmit data mask 26 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 25. "XMASK25,Transmit data mask 25 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 24. "XMASK24,Transmit data mask 24 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 23. "XMASK23,Transmit data mask 23 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 22. "XMASK22,Transmit data mask 22 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 21. "XMASK21,Transmit data mask 21 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 20. "XMASK20,Transmit data mask 20 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 19. "XMASK19,Transmit data mask 19 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 18. "XMASK18,Transmit data mask 18 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 17. "XMASK17,Transmit data mask 17 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 16. "XMASK16,Transmit data mask 16 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 15. "XMASK15,Transmit data mask 15 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 14. "XMASK14,Transmit data mask 14 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 13. "XMASK13,Transmit data mask 13 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 12. "XMASK12,Transmit data mask 12 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 11. "XMASK11,Transmit data mask 11 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 10. "XMASK10,Transmit data mask 10 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 9. "XMASK9,Transmit data mask 9 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 8. "XMASK8,Transmit data mask 8 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 7. "XMASK7,Transmit data mask 7 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 6. "XMASK6,Transmit data mask 6 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 5. "XMASK5,Transmit data mask 5 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 4. "XMASK4,Transmit data mask 4 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 3. "XMASK3,Transmit data mask 3 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 2. "XMASK2,Transmit data mask 2 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" newline bitfld.long 0x4 1. "XMASK1,Transmit data mask 1 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" bitfld.long 0x4 0. "XMASK0,Transmit data mask 0 enable bit.0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in MCASP_XFMT) which is transmitted out.." "0,1" line.long 0x8 "MCASP_TXFMT" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay.0h = 0-bit delay. The first transmit data bit AXRn occurs in same ACLKX cycle as the transmit frame sync (AFSX). 1h = 1-bit delay. The first transmit data bit AXRn occurs one ACLKX cycle after the transmit frame sync.." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order.0h = Bitstream is LSB first. No bit reversal is performed in transmit format bit reverse unit. 1h = Bitstream is MSB first. Bit reversal is performed in transmit format bit reverse unit." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by MCASP_XMASK. This field only applies to bits when MCASP_XMASK[n] = 0. 0h = Pad extra bits with 0. 1h = Pad extra bits with 1. 2h = Pad extra bits with one of the bits from the word as.." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h. 0h = Pad with bit 0 value. 1h = Pad with bit 1 to bit 31 value from 1h to 1Fh." newline hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size.0h = Reserved. 1h = Reserved. 2h = Reserved. 3h = Slot size is 8 bits. 4h = Reserved. 5h = Slot size is 12 bits. 6h = Reserved. 7h = Slot size is 16 bits. 8h = Reserved. 9h = Slot size is 20 bits. Ah = Reserved. Bh = Slot size is.." bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port.0h = Writes to XRBUF[n] originate from the data port. Writes to XRBUF[n] from the configuration bus are ignored with no effect.." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit.0h = Rotate right by 0 (no rotation). 1h = Rotate right by 4 bit positions. 2h = Rotate right by 8 bit positions. 3h = Rotate right by 12 bit positions. 4h = Rotate right by 16 bit.." "0,1,2,3,4,5,6,7" line.long 0xC "MCASP_TXFMCTL" hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh. 0h = Burst mode. 1h = Reserved. 2h = 2-slot TDM (I2S mode) to 32-slot TDM from 2h to 20h. 21h = Reserved from 21h to 17Fh. 180h = 384-slot DIT mode. 181h = Reserved from 181h.." bitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period.0h = Single bit. 1h = Single word." "0,1" bitfld.long 0xC 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit.0h = Externally-generated transmit frame sync. 1h = Internally-generated transmit frame sync." "0,1" bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit.0h = A rising edge on transmit frame sync (AFSX) indicates the beginning of a frame. 1h = A falling edge on transmit frame sync (AFSX) indicates the beginning of a frame." "0,1" line.long 0x10 "MCASP_ACLKXCTL" hexmask.long.word 0x10 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 20. "BUSY,The logic OR of bits 18 and 19 indicating that some clk change is in progress when high" "0,1" bitfld.long 0x10 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x10 18. "ADJBUSY,one-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment control. If CLKXDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit.0h = Rising edge. External receiver samples data on the falling edge of the serial clock so the transmitter must shift data out on the rising edge of the serial clock. 1h = Falling edge. External.." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit.0h = Synchronous. Transmit clock and frame sync provides the source for both the transmit and receive sections. 1h = Asynchronous. Separate clock and frame sync used by transmit and receive sections." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit.0h = External transmit clock source from ACLKX pin. 1h = Internal transmit clock source from output of programmable bit clock divider." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX.0h = Divide-by-1. 1h = Divide-by-2. 2h = Divide-by-3 to divide-by-32 from 2h to 1Fh." line.long 0x14 "MCASP_AHCLKXCTL" hexmask.long.word 0x14 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 20. "BUSY,The logic OR of bits 18 and 19 indicating that some clk change is in progress when high" "0,1" bitfld.long 0x14 19. "DIVBUSY,Divider change in progress (same behavior as bit 18)" "0,1" bitfld.long 0x14 18. "ADJBUSY,one-shot adj in progress (a BUSY bit that is set when an adj is in progress cleared when the adjustment has taken effect)" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,CLKXDIV one-shot adjustment control. If CLKXDIV is set such that there are “m” input clocks per one output clock then for one output cycle: 0h = (m+0) input clocks per output clock 1h = (m-1) input clocks per output clock 2h = (m+1) input.." "0,1,2,3" newline bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit.0h = External transmit high-frequency clock source from AHCLKX pin. 1h = Internal transmit high-frequency clock source from output of programmable high clock divider." "0,1" bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit.0h = AHCLKX is not inverted before programmable bit clock divider. In the special case where the transmit bit clock (ACLKX) is internally generated and the programmable bit clock divider.." "0,1" bitfld.long 0x14 12.--13. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX.0h = Divide-by-1. 1h = Divide-by-2. 2h = Divide-by-3 to divide-by-4096 from 2h to FFFh." line.long 0x18 "MCASP_TXTDM" bitfld.long 0x18 31. "XTDMS31,Transmitter mode during TDM time slot 31.0h = Transmit TDM time slot 31 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 31 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 30. "XTDMS30,Transmitter mode during TDM time slot 30.0h = Transmit TDM time slot 30 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 30 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 29. "XTDMS29,Transmitter mode during TDM time slot 29.0h = Transmit TDM time slot 29 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 29 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 28. "XTDMS28,Transmitter mode during TDM time slot 28.0h = Transmit TDM time slot 28 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 28 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 27. "XTDMS27,Transmitter mode during TDM time slot 27.0h = Transmit TDM time slot 27 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 27 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 26. "XTDMS26,Transmitter mode during TDM time slot 26.0h = Transmit TDM time slot 26 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 26 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 25. "XTDMS25,Transmitter mode during TDM time slot 25.0h = Transmit TDM time slot 25 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 25 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 24. "XTDMS24,Transmitter mode during TDM time slot 24.0h = Transmit TDM time slot 24 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 24 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 23. "XTDMS23,Transmitter mode during TDM time slot 23.0h = Transmit TDM time slot 23 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 23 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 22. "XTDMS22,Transmitter mode during TDM time slot 22.0h = Transmit TDM time slot 22 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 22 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 21. "XTDMS21,Transmitter mode during TDM time slot 21.0h = Transmit TDM time slot 21 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 21 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 20. "XTDMS20,Transmitter mode during TDM time slot 20.0h = Transmit TDM time slot 20 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 20 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 19. "XTDMS19,Transmitter mode during TDM time slot 19.0h = Transmit TDM time slot 19 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 19 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 18. "XTDMS18,Transmitter mode during TDM time slot 18.0h = Transmit TDM time slot 18 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 18 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 17. "XTDMS17,Transmitter mode during TDM time slot 17.0h = Transmit TDM time slot 17 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 17 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 16. "XTDMS16,Transmitter mode during TDM time slot 16.0h = Transmit TDM time slot 16 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 16 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 15. "XTDMS15,Transmitter mode during TDM time slot 15.0h = Transmit TDM time slot 15 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 15 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 14. "XTDMS14,Transmitter mode during TDM time slot 14.0h = Transmit TDM time slot 14 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 14 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 13. "XTDMS13,Transmitter mode during TDM time slot 13.0h = Transmit TDM time slot 13 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 13 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 12. "XTDMS12,Transmitter mode during TDM time slot 12.0h = Transmit TDM time slot 12 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 12 is active. The transmit serializer shifts out data during this.." "0,1" newline bitfld.long 0x18 11. "XTDMS11,Transmitter mode during TDM time slot 11.0h = Transmit TDM time slot 11 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 11 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 10. "XTDMS10,Transmitter mode during TDM time slot 10.0h = Transmit TDM time slot 10 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 10 is active. The transmit serializer shifts out data during this.." "0,1" bitfld.long 0x18 9. "XTDMS9,Transmitter mode during TDM time slot 9.0h = Transmit TDM time slot 9 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 9 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 8. "XTDMS8,Transmitter mode during TDM time slot 8.0h = Transmit TDM time slot 8 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 8 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 7. "XTDMS7,Transmitter mode during TDM time slot 7.0h = Transmit TDM time slot 7 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 7 is active. The transmit serializer shifts out data during this slot.." "0,1" newline bitfld.long 0x18 6. "XTDMS6,Transmitter mode during TDM time slot 6.0h = Transmit TDM time slot 6 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 6 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 5. "XTDMS5,Transmitter mode during TDM time slot 5.0h = Transmit TDM time slot 5 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 5 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 4. "XTDMS4,Transmitter mode during TDM time slot 4.0h = Transmit TDM time slot 4 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 4 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 3. "XTDMS3,Transmitter mode during TDM time slot 3.0h = Transmit TDM time slot 3 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 3 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 2. "XTDMS2,Transmitter mode during TDM time slot 2.0h = Transmit TDM time slot 2 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 2 is active. The transmit serializer shifts out data during this slot.." "0,1" newline bitfld.long 0x18 1. "XTDMS1,Transmitter mode during TDM time slot 1.0h = Transmit TDM time slot 1 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 1 is active. The transmit serializer shifts out data during this slot.." "0,1" bitfld.long 0x18 0. "XTDMS0,Transmitter mode during TDM time slot 0.0h = Transmit TDM time slot 0 is inactive. The transmit serializer does not shift out data during this slot. 1h = Transmit TDM time slot 0 is active. The transmit serializer shifts out data during this slot.." "0,1" line.long 0x1C "MCASP_EVTCTLX" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit.0h = Interrupt is disabled. A transmit start of frame interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit start of frame interrupt generates a McASP.." "0,1" bitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit.0h = Interrupt is disabled. A transmit data ready interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit data ready interrupt generates a McASP transmit.." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit.0h = Interrupt is disabled. A transmit last slot interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit last slot interrupt generates a McASP transmit interrupt.." "0,1" newline bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit.0h = Interrupt is disabled. A transmit DMA error interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit DMA error interrupt generates a McASP transmit interrupt.." "0,1" bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit.0h = Interrupt is disabled. A transmit clock failure interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmit clock failure interrupt generates a McASP.." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit.0h = Interrupt is disabled. An unexpected transmit frame sync interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. An unexpected transmit frame sync.." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit.0h = Interrupt is disabled. A transmitter underrun interrupt does not generate a McASP transmit interrupt (XINT). 1h = Interrupt is enabled. A transmitter underrun interrupt generates a McASP transmit.." "0,1" line.long 0x20 "MCASP_TXSTAT" hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred. 0h = No errors have occurred. 1h = An error has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect. 0h = No new transmit frame sync (AFSX) is.." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect. 0h = XBUF is written and is full. 1h = Data is copied.." "0,1" newline bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of MCASP_XSLOT. Allows a single read of MCASP_XSTAT to determine whether the current TDM time slot is even or odd. 0h = Current TDM time slot is odd. 1h = Current TDM time slot is even." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in MCASP_XINTCTL is set. This bit is cleared by writing a 1 to this.." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in MCASP_XINTCTL is set. This bit is cleared by writing.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." group.long 0xC8++0xB line.long 0x0 "MCASP_TXCLKCHK" hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh. 0h = MCASP system clock divided by 1. 1h = MCASP system clock divided by 2. 2h = MCASP system clock divided by 4. 3h = MCASP system clock divided by 8. 4h = MCASP system clock divided.." line.long 0x4 "MCASP_XEVTCTL" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0. 0h = Transmit data DMA request is enabled. 1h = Reserved" "0,1" line.long 0x8 "MCASP_CLKADJEN" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0. "ENABLE,One-shot clock adjustment enable. 0 = One-shot clock adjustment is DISABLED. Writes to bits 17:16 of 1 = One-shot clock adjustment is ENABLED. Writes to bits 17:16 of" "0: One-shot clock adjustment is DISABLED,1: One-shot clock adjustment is ENABLED" group.long 0x100++0x5F line.long 0x0 "MCASP_DITCSRA0" hexmask.long 0x0 0.--31. 1. "DITCSRA0,DIT left channel status registers." line.long 0x4 "MCASP_DITCSRA1" hexmask.long 0x4 0.--31. 1. "DITCSRA1,DIT left channel status registers." line.long 0x8 "MCASP_DITCSRA2" hexmask.long 0x8 0.--31. 1. "DITCSRA2,DIT left channel status registers." line.long 0xC "MCASP_DITCSRA3" hexmask.long 0xC 0.--31. 1. "DITCSRA3,DIT left channel status registers." line.long 0x10 "MCASP_DITCSRA4" hexmask.long 0x10 0.--31. 1. "DITCSRA4,DIT left channel status registers." line.long 0x14 "MCASP_DITCSRA5" hexmask.long 0x14 0.--31. 1. "DITCSRA5,DIT left channel status registers." line.long 0x18 "MCASP_DITCSRB0" hexmask.long 0x18 0.--31. 1. "DITCSRB0,DIT right channel status registers." line.long 0x1C "MCASP_DITCSRB1" hexmask.long 0x1C 0.--31. 1. "DITCSRB1,DIT right channel status registers." line.long 0x20 "MCASP_DITCSRB2" hexmask.long 0x20 0.--31. 1. "DITCSRB2,DIT right channel status registers." line.long 0x24 "MCASP_DITCSRB3" hexmask.long 0x24 0.--31. 1. "DITCSRB3,DIT right channel status registers." line.long 0x28 "MCASP_DITCSRB4" hexmask.long 0x28 0.--31. 1. "DITCSRB4,DIT right channel status registers." line.long 0x2C "MCASP_DITCSRB5" hexmask.long 0x2C 0.--31. 1. "DITCSRB5,DIT right channel status registers." line.long 0x30 "MCASP_DITUDRA0" hexmask.long 0x30 0.--31. 1. "DITUDRA0,DIT left channel user data registers." line.long 0x34 "MCASP_DITUDRA1" hexmask.long 0x34 0.--31. 1. "DITUDRA1,DIT left channel user data registers." line.long 0x38 "MCASP_DITUDRA2" hexmask.long 0x38 0.--31. 1. "DITUDRA2,DIT left channel user data registers." line.long 0x3C "MCASP_DITUDRA3" hexmask.long 0x3C 0.--31. 1. "DITUDRA3,DIT left channel user data registers." line.long 0x40 "MCASP_DITUDRA4" hexmask.long 0x40 0.--31. 1. "DITUDRA4,DIT left channel user data registers." line.long 0x44 "MCASP_DITUDRA5" hexmask.long 0x44 0.--31. 1. "DITUDRA5,DIT left channel user data registers." line.long 0x48 "MCASP_DITUDRB0" hexmask.long 0x48 0.--31. 1. "DITUDRB0,DIT right channel user data registers." line.long 0x4C "MCASP_DITUDRB1" hexmask.long 0x4C 0.--31. 1. "DITUDRB1,DIT right channel user data registers." line.long 0x50 "MCASP_DITUDRB2" hexmask.long 0x50 0.--31. 1. "DITUDRB2,DIT right channel user data registers." line.long 0x54 "MCASP_DITUDRB3" hexmask.long 0x54 0.--31. 1. "DITUDRB3,DIT right channel user data registers." line.long 0x58 "MCASP_DITUDRB4" hexmask.long 0x58 0.--31. 1. "DITUDRB4,DIT right channel user data registers." line.long 0x5C "MCASP_DITUDRB5" hexmask.long 0x5C 0.--31. 1. "DITUDRB5,DIT right channel user data registers." group.long 0x180++0x3F line.long 0x0 "MCASP_XRSRCTL0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x4 "MCASP_XRSRCTL1" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x8 "MCASP_XRSRCTL2" hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0xC "MCASP_XRSRCTL3" hexmask.long 0xC 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x10 "MCASP_XRSRCTL4" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x14 "MCASP_XRSRCTL5" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x18 "MCASP_XRSRCTL6" hexmask.long 0x18 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x1C "MCASP_XRSRCTL7" hexmask.long 0x1C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x20 "MCASP_XRSRCTL8" hexmask.long 0x20 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x24 "MCASP_XRSRCTL9" hexmask.long 0x24 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x28 "MCASP_XRSRCTL10" hexmask.long 0x28 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x2C "MCASP_XRSRCTL11" hexmask.long 0x2C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x30 "MCASP_XRSRCTL12" hexmask.long 0x30 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x34 "MCASP_XRSRCTL13" hexmask.long 0x34 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x38 "MCASP_XRSRCTL14" hexmask.long 0x38 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" line.long 0x3C "MCASP_XRSRCTL15" hexmask.long 0x3C 6.--31. 1. "RESERVED,Reserved" rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in MCASP_GBLCTL is switched from 0.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [MCASP_PFUNC = 0]. 0h = Drive on pin is 3-state. 1h = Reserved." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit.0h = Serializer is inactive. 1h = Serializer is transmitter. 2h = Serializer is receiver. 3h = Reserved." "0,1,2,3" group.long 0x200++0x3F line.long 0x0 "MCASP_TXBUF0" hexmask.long 0x0 0.--31. 1. "XBUF0,Transmit buffers for serializers." line.long 0x4 "MCASP_TXBUF1" hexmask.long 0x4 0.--31. 1. "XBUF1,Transmit buffers for serializers." line.long 0x8 "MCASP_TXBUF2" hexmask.long 0x8 0.--31. 1. "XBUF2,Transmit buffers for serializers." line.long 0xC "MCASP_TXBUF3" hexmask.long 0xC 0.--31. 1. "XBUF3,Transmit buffers for serializers." line.long 0x10 "MCASP_TXBUF4" hexmask.long 0x10 0.--31. 1. "XBUF4,Transmit buffers for serializers." line.long 0x14 "MCASP_TXBUF5" hexmask.long 0x14 0.--31. 1. "XBUF5,Transmit buffers for serializers." line.long 0x18 "MCASP_TXBUF6" hexmask.long 0x18 0.--31. 1. "XBUF6,Transmit buffers for serializers." line.long 0x1C "MCASP_TXBUF7" hexmask.long 0x1C 0.--31. 1. "XBUF7,Transmit buffers for serializers." line.long 0x20 "MCASP_TXBUF8" hexmask.long 0x20 0.--31. 1. "XBUF8,Transmit buffers for serializers." line.long 0x24 "MCASP_TXBUF9" hexmask.long 0x24 0.--31. 1. "XBUF9,Transmit buffers for serializers." line.long 0x28 "MCASP_TXBUF10" hexmask.long 0x28 0.--31. 1. "XBUF10,Transmit buffers for serializers." line.long 0x2C "MCASP_TXBUF11" hexmask.long 0x2C 0.--31. 1. "XBUF11,Transmit buffers for serializers." line.long 0x30 "MCASP_TXBUF12" hexmask.long 0x30 0.--31. 1. "XBUF12,Transmit buffers for serializers." line.long 0x34 "MCASP_TXBUF13" hexmask.long 0x34 0.--31. 1. "XBUF13,Transmit buffers for serializers." line.long 0x38 "MCASP_TXBUF14" hexmask.long 0x38 0.--31. 1. "XBUF14,Transmit buffers for serializers." line.long 0x3C "MCASP_TXBUF15" hexmask.long 0x3C 0.--31. 1. "XBUF15,Transmit buffers for serializers." group.long 0x280++0x3F line.long 0x0 "MCASP_RXBUF0" hexmask.long 0x0 0.--31. 1. "RBUF0,Receive buffers for serializers." line.long 0x4 "MCASP_RXBUF1" hexmask.long 0x4 0.--31. 1. "RBUF1,Receive buffers for serializers." line.long 0x8 "MCASP_RXBUF2" hexmask.long 0x8 0.--31. 1. "RBUF2,Receive buffers for serializers." line.long 0xC "MCASP_RXBUF3" hexmask.long 0xC 0.--31. 1. "RBUF3,Receive buffers for serializers." line.long 0x10 "MCASP_RXBUF4" hexmask.long 0x10 0.--31. 1. "RBUF4,Receive buffers for serializers." line.long 0x14 "MCASP_RXBUF5" hexmask.long 0x14 0.--31. 1. "RBUF5,Receive buffers for serializers." line.long 0x18 "MCASP_RXBUF6" hexmask.long 0x18 0.--31. 1. "RBUF6,Receive buffers for serializers." line.long 0x1C "MCASP_RXBUF7" hexmask.long 0x1C 0.--31. 1. "RBUF7,Receive buffers for serializers." line.long 0x20 "MCASP_RXBUF8" hexmask.long 0x20 0.--31. 1. "RBUF8,Receive buffers for serializers." line.long 0x24 "MCASP_RXBUF9" hexmask.long 0x24 0.--31. 1. "RBUF9,Receive buffers for serializers." line.long 0x28 "MCASP_RXBUF10" hexmask.long 0x28 0.--31. 1. "RBUF10,Receive buffers for serializers." line.long 0x2C "MCASP_RXBUF11" hexmask.long 0x2C 0.--31. 1. "RBUF11,Receive buffers for serializers." line.long 0x30 "MCASP_RXBUF12" hexmask.long 0x30 0.--31. 1. "RBUF12,Receive buffers for serializers." line.long 0x34 "MCASP_RXBUF13" hexmask.long 0x34 0.--31. 1. "RBUF13,Receive buffers for serializers." line.long 0x38 "MCASP_RXBUF14" hexmask.long 0x38 0.--31. 1. "RBUF14,Receive buffers for serializers." line.long 0x3C "MCASP_RXBUF15" hexmask.long 0x3C 0.--31. 1. "RBUF15,Receive buffers for serializers." tree.end tree "MCASP2_DMA" base ad:0x2B28000 rgroup.long 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers. For receive operations through the DATA port. the Host should read from the same.." hexmask.long 0x0 0.--31. 1. "RXBUF,Rx buffer data." wgroup.long 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port. the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port. the Host should write to the same DATA.." hexmask.long 0x0 0.--31. 1. "TXBUF,Tx buffer data." tree.end tree.end tree "MCSPI" base ad:0x0 tree "MCSPI0_CFG" base ad:0x2100000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this.." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved" bitfld.long 0x4 6. "RETMODE,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see . MCSPI Not Supported Features." hexmask.long 0x0 4.--31. 1. "RSVD,Reads returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally that is regardless of the IP module's internal requirements." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. (Optional) 0h (R/W) = Reset done no pending action 1h (R/W) = Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "0,1" bitfld.long 0x0 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full. Only when Channel 3 is enabled 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow. Only when Channel 3 is enabled. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only). Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information..." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0." bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x8 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0xC 11. "SSB,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line (signal data value)" "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line (signal data value)" "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line (signal data value)" "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line (signal data value)" "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line (signal data value)" "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x10 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "0,1" bitfld.long 0x10 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) =.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i." rbitfld.long 0x14 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x14 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x14 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x14 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i." rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes" hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes" line.long 0x4 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO.." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when" rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO data received with DMA 256 bit aligned address. This field is only used when" tree.end tree "MCSPI1_CFG" base ad:0x2110000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this.." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved" bitfld.long 0x4 6. "RETMODE,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see . MCSPI Not Supported Features." hexmask.long 0x0 4.--31. 1. "RSVD,Reads returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally that is regardless of the IP module's internal requirements." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. (Optional) 0h (R/W) = Reset done no pending action 1h (R/W) = Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "0,1" bitfld.long 0x0 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full. Only when Channel 3 is enabled 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow. Only when Channel 3 is enabled. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only). Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information..." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0." bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x8 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0xC 11. "SSB,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line (signal data value)" "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line (signal data value)" "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line (signal data value)" "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line (signal data value)" "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line (signal data value)" "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x10 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "0,1" bitfld.long 0x10 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) =.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i." rbitfld.long 0x14 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x14 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x14 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x14 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i." rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes" hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes" line.long 0x4 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO.." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when" rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO data received with DMA 256 bit aligned address. This field is only used when" tree.end tree "MCSPI2_CFG" base ad:0x2120000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this.." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved" bitfld.long 0x4 6. "RETMODE,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see . MCSPI Not Supported Features." hexmask.long 0x0 4.--31. 1. "RSVD,Reads returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally that is regardless of the IP module's internal requirements." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. (Optional) 0h (R/W) = Reset done no pending action 1h (R/W) = Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "0,1" bitfld.long 0x0 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full. Only when Channel 3 is enabled 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow. Only when Channel 3 is enabled. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only). Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information..." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0." bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x8 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0xC 11. "SSB,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line (signal data value)" "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line (signal data value)" "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line (signal data value)" "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line (signal data value)" "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line (signal data value)" "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x10 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "0,1" bitfld.long 0x10 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) =.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i." rbitfld.long 0x14 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x14 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x14 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x14 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i." rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes" hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes" line.long 0x4 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO.." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when" rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO data received with DMA 256 bit aligned address. This field is only used when" tree.end tree "MCSPI3_CFG" base ad:0x2130000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this.." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved" bitfld.long 0x4 6. "RETMODE,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see . MCSPI Not Supported Features." hexmask.long 0x0 4.--31. 1. "RSVD,Reads returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally that is regardless of the IP module's internal requirements." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. (Optional) 0h (R/W) = Reset done no pending action 1h (R/W) = Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "0,1" bitfld.long 0x0 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full. Only when Channel 3 is enabled 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow. Only when Channel 3 is enabled. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only). Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information..." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0." bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x8 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0xC 11. "SSB,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line (signal data value)" "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line (signal data value)" "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line (signal data value)" "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line (signal data value)" "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line (signal data value)" "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x10 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "0,1" bitfld.long 0x10 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) =.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i." rbitfld.long 0x14 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x14 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x14 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x14 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i." rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes" hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes" line.long 0x4 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO.." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when" rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO data received with DMA 256 bit aligned address. This field is only used when" tree.end tree "MCSPI4_CFG" base ad:0x2140000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this.." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved" bitfld.long 0x4 6. "RETMODE,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see . MCSPI Not Supported Features." hexmask.long 0x0 4.--31. 1. "RSVD,Reads returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally that is regardless of the IP module's internal requirements." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. (Optional) 0h (R/W) = Reset done no pending action 1h (R/W) = Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "0,1" bitfld.long 0x0 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full. Only when Channel 3 is enabled 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow. Only when Channel 3 is enabled. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only). Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information..." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0." bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x8 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0xC 11. "SSB,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line (signal data value)" "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line (signal data value)" "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line (signal data value)" "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line (signal data value)" "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line (signal data value)" "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x10 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "0,1" bitfld.long 0x10 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) =.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i." rbitfld.long 0x14 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x14 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x14 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x14 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i." rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes" hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes" line.long 0x4 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO.." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when" rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO data received with DMA 256 bit aligned address. This field is only used when" tree.end tree.end tree "MCU" base ad:0x0 tree "MCU_ADC" tree "MCU_ADC0" base ad:0x40200000 rgroup.long 0x0++0x3 line.long 0x0 "ADC_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTLADC_REVISION. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor" group.long 0x0++0x3 line.long 0x0 "ADC_STEPCONFIG_j,The user should write the appropriate value to this register that is required to configure the various functions of each step. Offset = 64h + (j * 8h); where j = 0h to Fh" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 27. "RANGECHECK,0h = Disable ADC_RANGE check 1h = compare ADC data with ADC_RANGE" "0,1" bitfld.long 0x0 26. "FIFOSEL,Sampled data will be stored in FIFO. 0h = FIFO0 1h = FIFO1" "0,1" bitfld.long 0x0 25. "DIFF_CNTRL,DifferentialADC_CONTROL. 0h = Single ended input SEL_INM_SWM must be 8h 1h = Differential input" "0,1" rbitfld.long 0x0 23.--24. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 19.--22. 1. "SEL_INP_SWC,Select source for positive ADC input (INP). 0h = Input (channel) 0 1h = Input (channel) 1 2h = Input (channel) 2 3h = Input (channel) 3 4h = Input (channel) 4 5h = Input (channel) 5 6h = Input (channel) 6 7h = Input (channel) 7 8h = REFN" hexmask.long.byte 0x0 15.--18. 1. "SEL_INM_SWM,Select source for negative ADC input (INM). 0h = Input (channel) 0 1h = Input (channel) 1 2h = Input (channel) 2 3h = Input (channel) 3 4h = Input (channel) 4 5h = Input (channel) 5 6h = Input (channel) 6 7h = Input (channel) 7 8h = REFN" hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--4. "AVERAGING,Number of samplings to average. 0h = no average 1h = 2 samples average 2h = 4 samples average 3h = 8 samples average 4h = 16 samples average" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--1. "MODE,0h = SW enabled one-shot 1h = SW enabled continuous 2h = HW synchronized one-shot 3h = HW synchronized continuous" "0,1,2,3" group.long 0x0++0x3 line.long 0x0 "ADC_STEPDELAY_j,Controls number of SMPL_CLK periods to sample and delay. Offset = 68h + (j × 8h); where j = 0h to Fh" hexmask.long.byte 0x0 24.--31. 1. "SAMPLEDELAY,This register will control the number of SMPL_CLK cycles to sample the input signal (hold SOC high). Any value programmed here will be added to the minimum time of 2 SMPL_CLK cycles." hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x0 0.--17. 1. "OPENDELAY,Program the number of SMPL_CLK cycles to wait after applying the step configuration registers and before sending the start of ADC conversion." group.long 0x20++0x13 line.long 0x0 "ADC_EOI,The End of Interrupt () Register allows the CPU to acknowledge completion of an interrupt by writing to the for interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt sources remain. This.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINENUMEOI,Software End Of Interrupt (EOI) control." "0,1" line.long 0x4 "ADC_STATUS_RAW,The register allows the MCU_ADC0 interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "OUTOFRANGE,Status raw for out of range interrupt." "0,1" bitfld.long 0x4 7. "FIFO1UNFL,Status raw for FIFO1 under-flow interrupt." "0,1" bitfld.long 0x4 6. "FIFO1OVFL,Status raw for FIFO1 over-flow interrupt." "0,1" bitfld.long 0x4 5. "FIFO1THRS,Status raw for FIFO1 threshold interrupt." "0,1" newline bitfld.long 0x4 4. "FIFO0UNFL,Status raw for FIFO0 under-flow interrupt." "0,1" bitfld.long 0x4 3. "FIFO0OVFL,Status raw for FIFO0 over-flow interrupt." "0,1" bitfld.long 0x4 2. "FIFO0THRS,Status raw for FIFO0 threshold interrupt." "0,1" bitfld.long 0x4 1. "ENDOFEQUENCE,Status raw for end of sequence interrupt." "0,1" bitfld.long 0x4 0. "AFE_EOC_MISSING,Status raw for missing AFE EOC interrupt." "0,1" line.long 0x8 "ADC_STATUS,The register allows the MCU_ADC0 interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending" hexmask.long.tbyte 0x8 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "OUTOFRANGE,Enabled status for out of range interrupt." "0,1" bitfld.long 0x8 7. "FIFO1UNFL,Enabled status for FIFO1 under-flow interrupt." "0,1" bitfld.long 0x8 6. "FIFO1OVFL,Enabled status for FIFO1 over-flow interrupt." "0,1" bitfld.long 0x8 5. "FIFO1THRS,Enabled status for FIFO1 threshold interrupt." "0,1" newline bitfld.long 0x8 4. "FIFO0UNFL,Enabled status for FIFO0 under-flow interrupt." "0,1" bitfld.long 0x8 3. "FIFO0OVFL,Enabled status for FIFO0 over-flow interrupt." "0,1" bitfld.long 0x8 2. "FIFO0THRS,Enabled status for FIFO0 threshold interrupt." "0,1" bitfld.long 0x8 1. "ENDOFEQUENCE,Enabled status for end of sequence interrupt." "0,1" bitfld.long 0x8 0. "AFE_EOC_MISSING,Enable status for missing AFE EOC interrupt." "0,1" line.long 0xC "ADC_ENABLE_SET,The register allows the MCU_ADC0 interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled" hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "OUTOFRANGE,Out of range interrupt enable." "0,1" bitfld.long 0xC 7. "FIFO1UNFL,FIFO1 under-flow interrupt enable." "0,1" bitfld.long 0xC 6. "FIFO1OVFL,FIFO1 over-flow interrupt enable." "0,1" bitfld.long 0xC 5. "FIFO1THRS,FIFO1 threshold interrupt enable." "0,1" newline bitfld.long 0xC 4. "FIFO0UNFL,FIFO0 under-flow interrupt enable." "0,1" bitfld.long 0xC 3. "FIFO0OVFL,FIFO0 over-flow interrupt enable." "0,1" bitfld.long 0xC 2. "FIFO0THRS,FIFO0 threshold interrupt enable." "0,1" bitfld.long 0xC 1. "ENDOFEQUENCE,End of sequence interrupt enable." "0,1" bitfld.long 0xC 0. "AFE_EOC_MISSING,Missing AFE EOC interrupt enable." "0,1" line.long 0x10 "ADC_ENABLE_CLR,The register allows the MCU_ADC0 interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "OUTOFRANGE,Out of range interrupt disable." "0,1" bitfld.long 0x10 7. "FIFO1UNFL,FIFO1 under-flow interrupt disable." "0,1" bitfld.long 0x10 6. "FIFO1OVFL,FIFO1 over-flow interrupt disable." "0,1" bitfld.long 0x10 5. "FIFO1THRS,FIFO1 threshold interrupt disable." "0,1" newline bitfld.long 0x10 4. "FIFO0UNFL,FIFO0 under-flow interrupt disable." "0,1" bitfld.long 0x10 3. "FIFO0OVFL,FIFO0 over-flow interrupt disable." "0,1" bitfld.long 0x10 2. "FIFO0THRS,FIFO0 threshold interrupt disable." "0,1" bitfld.long 0x10 1. "ENDOFEQUENCE,End of sequence interrupt disable." "0,1" bitfld.long 0x10 0. "AFE_EOC_MISSING,Missing AFE EOC interrupt disable." "0,1" group.long 0x38++0xB line.long 0x0 "ADC_DMAENABLE_SET,The register allows the enabling of DMA requests." rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" hexmask.long 0x0 2.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "ENABLE1,Enable DMA event to FIFO1" "0,1" bitfld.long 0x0 0. "ENABLE0,Enable DMA event to FIFO0" "0,1" line.long 0x4 "ADC_DMAENABLE_CLR,The register allows the disabling of DMA requests." rbitfld.long 0x4 31. "RESERVED,Reserved" "0,1" hexmask.long 0x4 2.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "ENABLE1,Clears the enable of the DMA event to FIFO1. Disable DMA event to FIFO1 Write 0h = No action Write 1h = Disable DMA event Read 0h = DMA event disabled Read 1h = DMA event enabled" "0,1" bitfld.long 0x4 0. "ENABLE0,Clears the enable of the DMA event to FIFO0. Disable DMA event to FIFO0 Write 0h = No action Write 1h = Disable DMA event Read 0h = DMA event disabled Read 1h = DMA event enabled" "0,1" line.long 0x8 "ADC_CONTROL,Controls various parameters of the cotroller state." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 11. "HI_MID_SEL,Reference select for functional internal diagnostic debug mode. 0h = VMID 1h = REFP" "0,1" bitfld.long 0x8 10. "HI_MID_EN,Functional internal diagnostic debug mode. 0h = disabled 1h = enabled" "0,1" bitfld.long 0x8 9. "HW_PREEMPT,0h = SW steps are not preempted by HW events 1h = SW steps are preempted by HW events" "0,1" bitfld.long 0x8 8. "HW_MAP,0h = HW events are disabled 1h = HW events are enabled" "0,1" newline rbitfld.long 0x8 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "PD,ADC Power Down control. 0h = AFE is powered up 1h = AFE is powered down (default) At default AFE is powered down; Software must write 0 to turn on the power and wait 4 us before starting a conversion" "0,1" bitfld.long 0x8 3. "BIAS_SEL,AFE select bias ADC control register" "0,1" rbitfld.long 0x8 2. "RESERVED,Reserved" "0,1" bitfld.long 0x8 1. "STEP_ID_EN,Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO. 0h = Write zeros 1h = Store the input (channel) ID tag" "0,1" newline bitfld.long 0x8 0. "MODULE_ENABLE,ADC module enable bit. After programming all the configuration and step enable registers write a 1 to this bit to start conversion. Writing a 0 will disable the module after the current conversion. Before turning on again the.." "0,1" rgroup.long 0x44++0x3 line.long 0x0 "ADC_SEQUENCER_STAT,SW can read this register to find out the currently scheduled step id being converted on the ADC port. If you want to turn the controller off and then back on. the step_id bit should be checked and compared to IDLE before enabling the.." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "GPADC_BUSY,Monitor the AFE internal calibration (busy bit)" "0,1" bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" bitfld.long 0x0 6. "MEM_INIT_DONE,ADC_STATUS of RAM initialization for ECC. 1h = RAM initialization to 0 after reset is done." "0,1" bitfld.long 0x0 5. "FSM_BUSY,ADC_STATUS of FSM. 0h = Idle 1h = Conversion in progress" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "STEP_IDLE,10h = Idle 0h - Fh = Corresponds to Step 1 - Step 16" group.long 0x48++0x3 line.long 0x0 "ADC_RANGE,This feature requires the check interrupt bit to be enabled first. The user can decide which input (channel) is compared by programming the RangeCheck bit of the Registers. It is up to software to sort through FIFO data to determine which input.." hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 16.--27. 1. "HIRANGE,Sampled ADC data is compared to this value. If the sampled data is &gt; HIRANGE then interrupt is generated." hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "LOWRANGE,Sampled ADC data is compared to this value. If the sampled data is &lt; LOWRANGE then interrupt is generated." group.long 0x50++0x7 line.long 0x0 "ADC_MISC,Spare inputs of the AFE are driven by this register. spare outputs from the AFE are read." hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "AFE_SPARE_OUT,Connected to AFE Spare Output pins reserved in normal operation." hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "AFE_SPARE_IN,Connected to AFE Spare Input pins reserved in normal operation." line.long 0x4 "ADC_STEPENABLE,Contains the enable bit for each step in the sequencer. When all steps are disabled. the FSM will stay in IDLE state." hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "STEP16,Enable step 16" "0,1" bitfld.long 0x4 15. "STEP15,Enable step 15" "0,1" bitfld.long 0x4 14. "STEP14,Enable step 14" "0,1" bitfld.long 0x4 13. "STEP13,Enable step 13" "0,1" newline bitfld.long 0x4 12. "STEP12,Enable step 12" "0,1" bitfld.long 0x4 11. "STEP11,Enable step 11" "0,1" bitfld.long 0x4 10. "STEP10,Enable step 10" "0,1" bitfld.long 0x4 9. "STEP9,Enable step 9" "0,1" bitfld.long 0x4 8. "STEP8,Enable step 8" "0,1" newline bitfld.long 0x4 7. "STEP7,Enable step 7" "0,1" bitfld.long 0x4 6. "STEP6,Enable step 6" "0,1" bitfld.long 0x4 5. "STEP5,Enable step 5" "0,1" bitfld.long 0x4 4. "STEP4,Enable step 4" "0,1" bitfld.long 0x4 3. "STEP3,Enable step 3" "0,1" newline bitfld.long 0x4 2. "STEP2,Enable step 2" "0,1" bitfld.long 0x4 1. "STEP1,Enable step 1" "0,1" rbitfld.long 0x4 0. "RESERVED,Reserved" "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "ADC_FIFO0WC,FIFO word count" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--8. 1. "NUMWDS,Number of words currently in the FIFO0." group.long 0xE8++0x7 line.long 0x0 "ADC_FIFO0THRESHOLD,FIFO threshold" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "THRESHOLD,Program the desired FIFO0 data sample level minus 1 to reach before generating interrupt to CPU." line.long 0x4 "ADC_FIFO0DMAREQ,DMA request." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "DMAREQLEVEL,Number of words in FIFO0 before generating a DMA request." rgroup.long 0xF0++0x3 line.long 0x0 "ADC_FIFO1WC,FIFO word count" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--8. 1. "NUMWDS,Number of words currently in the FIFO1." group.long 0xF4++0x7 line.long 0x0 "ADC_FIFO1THRESHOLD,FIFO threshold" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "THRESHOLD,Program the desired FIFO1 data sample level minus 1 to reach before generating interrupt to CPU." line.long 0x4 "ADC_FIFO1DMAREQ,DMA request." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "DMAREQLEVEL,Number of words in FIFO1 before generating a DMA request." rgroup.long 0x100++0x3 line.long 0x0 "ADC_FIFO0DATA,A read from this register will auto increment the FIFO read pointer. If you read when FIFO is empty. it will trigger an underflow interrupt." hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of input (channel) that captured the data. If tag option is disabled these bits will be 0." hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,Sampled ADC converted data value stored in FIFO0." rgroup.long 0x200++0x3 line.long 0x0 "ADC_FIFO1DATA,A read from this register will auto increment the FIFO read pointer. If you read when FIFO is empty. it will trigger an underflow interrupt." hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of input (channel) that captured the data. If tag option is disabled these bits will be 0." hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,Sampled ADC converted data value stored in FIFO1." tree.end tree "MCU_ADC0_ECC" base ad:0x40707000 rgroup.long 0x0++0x3 line.long 0x0 "ADC_AGGR_REVISION,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ADC_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1h = Trigger a read on the serial VBUS" "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for" rgroup.long 0xC++0x3 line.long 0x0 "ADC_MISC_STATUS,Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x3C++0x7 line.long 0x0 "ADC_ECC_SEC_EOI_REG,Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR" "0,1" line.long 0x4 "ADC_ECC_SEC_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1" bitfld.long 0x4 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ADC_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ADC_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ADC_ECC_DED_EOI_REG,Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR" "0,1" line.long 0x4 "ADC_ECC_DED_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1" bitfld.long 0x4 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ADC_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ADC_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1" bitfld.long 0x0 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ADC_AGGR_ENABLE_SET,Return to the . AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ADC_AGGR_ENABLE_CLR,Return to the . AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ADC_AGGR_STATUS_SET,Return to the . AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ADC_AGGR_STATUS_CLR,Return to the . AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_ADC0_FIFO" base ad:0x40208000 rgroup.long 0x100++0x3 line.long 0x0 "ADC_FIFO0DMADATA,DMA sample FIFO" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of input (channel) that captured the data. If tag option is disabled these bits will be 0." hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,Sampled ADC converted data value stored in FIFO0." rgroup.long 0x200++0x3 line.long 0x0 "ADC_FIFO1DMADATA,DMA sample FIFO" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "ADCCHANLID,Optional ID tag of input (channel) that captured the data. If tag option is disabled these bits will be 0." hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "ADCDATA,Sampled ADC converted data value stored in FIFO1." tree.end tree.end tree "MCU_ARMSS_VIC_CFG" base ad:0x40F80000 rgroup.long 0x0++0x27 line.long 0x0 "R5FSS_VIM_PID,This register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." line.long 0x4 "R5FSS_VIM_INFO,This contains information about the configuration of the R5FSS_VIM." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Indicates the number of interrupts supported by the VIM." line.long 0x8 "R5FSS_VIM_PRIIRQ,This register contains the number of the highest priority pending IRQ." bitfld.long 0x8 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x8 16.--19. 1. "PRI,This field indicates the priority of the pending IRQ interrupt." hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x8 0.--9. 1. "NUM,This field indicates the interrupt number of the pending IRQ interrupt with the highest priority." line.long 0xC "R5FSS_VIM_PRIFIQ,This register contains the number of the highest priority pending FIQ." bitfld.long 0xC 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0xC 16.--19. 1. "PRI,This field indicates the priority of the pending FIQ interrupt." hexmask.long.byte 0xC 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0xC 0.--9. 1. "NUM,This field indicates the interrupt number of the pending FIQ interrupt with the highest priority." line.long 0x10 "R5FSS_VIM_IRQGSTS,This register indicates which groups of interrupts have pending. unmasked IRQ interrupts." hexmask.long 0x10 0.--31. 1. "STS,This field indicates that one or more interrupts in group M are mapped to IRQ unmasked and pending. Bit 0 corresponds to group 0 bit 1 corresponds to group 1 etc. The interrupts associated with each group are [(M*32)+31:M*32]" line.long 0x14 "R5FSS_VIM_FIQGSTS,This register indicates which groups of interrupts have pending. unmasked FIQ interrupts." hexmask.long 0x14 0.--31. 1. "STS,This field indicates that one or more interrupts in group M are mapped to FIQ unmasked and pending. Bit 0 corresponds to group 0 bit 1 corresponds to group 1 etc. The interrupts associated with each group are [(M*32)+31:M*32]" line.long 0x18 "R5FSS_VIM_IRQVEC,This register contains the 32-bit interrupt vector address of the currently pending IRQ." hexmask.long 0x18 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority IRQ (as indicated by the" bitfld.long 0x18 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" line.long 0x1C "R5FSS_VIM_FIQVEC,This register contains the 32-bit interrupt vector address of the currently pending FIQ." hexmask.long 0x1C 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority FIQ (as indicated by the" bitfld.long 0x1C 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" line.long 0x20 "R5FSS_VIM_ACTIRQ,This register contains the number of the active IRQ." bitfld.long 0x20 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x20 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x20 16.--19. 1. "PRI,This field indicates the priority of the active IRQ interrupt." hexmask.long.byte 0x20 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x20 0.--9. 1. "NUM,This field indicates the interrupt number of the active IRQ interrupt." line.long 0x24 "R5FSS_VIM_ACTFIQ,This register contains the number of the active FIQ." bitfld.long 0x24 31. "VALID,This field indicates if the NUM field of this register is valid." "0,1" hexmask.long.word 0x24 20.--30. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x24 16.--19. 1. "PRI,This field indicates the priority of the active FIQ interrupt." hexmask.long.byte 0x24 10.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.word 0x24 0.--9. 1. "NUM,This field indicates the interrupt number of the active FIQ interrupt." group.long 0x30++0x3 line.long 0x0 "R5FSS_VIM_DEDVEC,This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors." hexmask.long 0x0 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (the address must be 32-bit aligned) of an interrupt to be used if an uncorrectable double-bit error (DED) is detected in any of the interrupt vector addresses." rbitfld.long 0x0 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" group.long 0x400++0x1F line.long 0x0 "R5FSS_VIM_RAW_j,This register indicates the raw status of the events in group M. Offset = 400h + (j * 20h); where j = 0h to Fh." hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x4 "R5FSS_VIM_STS_j,This register indicates the masked status of the events in group M. Offset = 404h + (j * 20h); where j = 0h to Fh." hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status of the events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x8 "R5FSS_VIM_INTR_EN_SET_j,This register is used to enable the mask for the events in group M. Offset = 408h + (j * 20h); where j = 0h to Fh." hexmask.long 0x8 0.--31. 1. "MSK,This field is used to enable the mask of events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0xC "R5FSS_VIM_INTR_EN_CLR_j,This register is used to disable the mask for the events in group M. Offset = 40Ch + (j * 20h); where j = 0h to Fh." hexmask.long 0xC 0.--31. 1. "MSK,This field is used to disable the mask of events in group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x10 "R5FSS_VIM_IRQSTS_j,This register indicates the masked status of the events in Group M that are also mapped as IRQs. Offset = 410h + (j * 20h); where j = 0h to Fh." hexmask.long 0x10 0.--31. 1. "MSK,This is the masked status of the events in group M that are mapped to IRQ. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x14 "R5FSS_VIM_FIQSTS_j,This register indicates the masked status of the events in group M that are also mapped as FIQs. Offset = 414h + (j * 20h); where j = 0h to Fh." hexmask.long 0x14 0.--31. 1. "MSK,This is the masked status of the events in group M that are mapped to FIQ. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x18 "R5FSS_VIM_INTMAP_j,This register is used to map interrupts as IRQ or FIQ. Offset = 418h + (j * 20h); where j = 0h to Fh." hexmask.long 0x18 0.--31. 1. "MSK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." line.long 0x1C "R5FSS_VIM_INTTYPE_j,This register indicates whether an interrupt is a pulse or level source. Offset = 41Ch + (j * 20h); where j = 0h to Fh." hexmask.long 0x1C 0.--31. 1. "MSK,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. Each bit corresponds to event Q where Q = M*32+bit (example: bit 0 is event M*32+0 bit 1 is M*32+1 etc)." group.long 0x1000++0x3 line.long 0x0 "R5FSS_VIM_PRI_INT_j,This register is used to set the priority of interrupt Q. Offset = 1000h + (j * 4h); where j = 0h to 1FFh." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x0 0.--3. 1. "VAL,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration." group.long 0x2000++0x3 line.long 0x0 "R5FSS_VIM_VEC_INT_j,This register contains the vector address associated with interrupt Q. Offset = 2000h + (j * 4h); where j = 0h to 1FFh." hexmask.long 0x0 2.--31. 1. "VAL,These are the upper 30 bits of the 32-bit vector address associated with interrupt Q. It is the address that will be reflected in the" rbitfld.long 0x0 0.--1. "RESERVED,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.)" "0,1,2,3" tree.end base ad:0x0 tree "MCU_CBASS" tree "MCU_CBASS0_ERR" base ad:0x4710000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "MCU_CBASS0_GLB" base ad:0x45B06000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "MCU_CBASS_FW0_ERR" base ad:0x4718000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree.end tree "MCU_CPSW" tree "MCU_CPSW0_ECC" base ad:0x40709000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_ECC_REV,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "CPSW_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "CPSW_ECC_STAT,Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "CPSW_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "CPSW_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPSW_ECC_SEC_STATUS_REG0,Interrupt Status Register 0" hexmask.long.word 0x4 20.--31. 1. "RESERVED" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1" bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1" newline bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1" bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1" bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1" newline bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1" bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1" bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1" bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1" newline bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1" bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1" bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1" newline bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1" bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1" bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1" newline bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "CPSW_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1" bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1" newline bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1" newline bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1" bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1" bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "CPSW_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1" bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1" newline bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1" newline bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1" bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1" bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "CPSW_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPSW_ECC_DED_STATUS_REG0,Interrupt Status Register 0" hexmask.long.word 0x4 20.--31. 1. "RESERVED" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1" bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1" newline bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1" bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1" bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1" newline bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1" bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1" bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1" bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1" newline bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1" bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1" bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1" newline bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1" bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1" bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1" newline bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "CPSW_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1" bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1" newline bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1" newline bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1" bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1" bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "CPSW_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1" bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1" newline bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1" bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1" newline bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1" bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1" bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1" newline bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "CPSW_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CPSW_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CPSW_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CPSW_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_CPSW0_NUSS_ALE" base ad:0x46000000 rgroup.long 0x3E000++0x7 line.long 0x0 "CPSW_ALE_MOD_VER,The Module and Version Register identifies the module identifier of the ALE_2g64i module." hexmask.long.word 0x0 16.--31. 1. "MODULE_ID,ALE module ID." hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version." newline bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision." line.long 0x4 "CPSW_ALE_STATUS,The ALE status provides information on the ALE configuration and state. The RAMDEPTH is used to determine how IPv6 entries are stored in the table. IPv6 entries are stored in two entries where IPv6 Entry Hi is designated by the odd slice.." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8.A value of 4 indicates 32 policer engines total." newline bitfld.long 0x4 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both RAMDEPTH128 and RAMDEPTH32 are zero the depth is 64." "0,1" bitfld.long 0x4 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both RAMDEPTH128 and RAMDEPTH32 are zero the depth is 64." "0,1" newline bitfld.long 0x4 5. "RESERVED" "0,1" hexmask.long.byte 0x4 0.--4. 1. "KLUENTRIES,This is the number of table entries total divided by 1024.A value of 1h indicates 1024 table entries. A value of 8h indicates 8192 table entries." group.long 0x3E008++0xF line.long 0x0 "CPSW_ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports." bitfld.long 0x0 31. "ENABLE_ALE,Enable ALE.0h = Drop all packets 1h = Enable ALE packet processing" "0,1" bitfld.long 0x0 30. "CLEAR_TABLE,Clear ALE address table. Setting this bit causes the ALE hardware to write all table bit values to zero.Software must perform a clear table operation as part of the ALE setup/configuration process. Setting this bit causes all ALE accesses to.." "0,1" newline bitfld.long 0x0 29. "AGE_OUT_NOW,Age Out Address Table Now. Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit.This bit is cleared when the age out process has completed. This bit may be read. The age out.." "0,1" hexmask.long.byte 0x0 25.--28. 1. "RESERVED" newline bitfld.long 0x0 24. "MIRROR_DP,Mirror Destination Port. This field defines the port to which destination traffic destined will be duplicated.That is all traffic that is forwarded to this port will also be mirrored to the MIRROR_TOP port." "0,1" bitfld.long 0x0 21.--23. "UPD_BW_CTRL,The UPD_BW_CTRL field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur.At frequencies of 350Mhz the table update rate should be at it lowest or 5 Million updates per second. When.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 17.--20. 1. "RESERVED" bitfld.long 0x0 16. "MIRROR_TOP,Mirror To Port. This field defines the destination port for the mirror traffic.If the traffic is received or transmitted on the mirror destination port it will not be duplicated. Traffic defined as mirror traffic only may be dropped by the.." "0,1" newline bitfld.long 0x0 15. "UPD_STATIC,Update Static Entries - A static Entry is an entry that is not agable.When clear this bit will prevent any static entry (agable bit clear) from being updated due to port change. When set it allows static entries (agable bit clear) to update.." "0,1" bitfld.long 0x0 14. "RESERVED" "0,1" newline bitfld.long 0x0 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn. This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled." "0,1" bitfld.long 0x0 12. "MIRROR_MEN,Mirror Match Entry Enable. This field enables the match mirror option.When this bit is set any traffic whose destination source VLAN or OUI matches the ~imirror_midx entry index will have that traffic also sent to the ~imirror_top port." "0,1" newline bitfld.long 0x0 11. "MIRROR_DEN,Mirror Destination Port Enable - This field enables the destination port mirror option.When this bit is set any traffic destined for the ~imirror_dp port will have its transmit traffic also sent to the ~imirror_top port." "0,1" bitfld.long 0x0 10. "MIRROR_SEN,Mirror Source Port Enable - This field enables the source port mirror option.When this bit is set any port with the Iy_REG_P0_MIRROR_SP set in the CPSW_Iy_ALE_PORTCTL0_y registers set will have its received traffic also sent to the MIRROR_TOP.." "0,1" newline bitfld.long 0x0 9. "RESERVED" "0,1" bitfld.long 0x0 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host.0h = Unknown unicast packets are not sent to the host.1h = Unknown unicast packets flood to host port as well as other ports." "0,1" newline bitfld.long 0x0 7. "LEARN_NO_VLANID,Learn No VID.0h = VID is learned with the source address.1h = VID is not learned with the source address (source address is not tied to VID). Determines the entry type." "0,1" bitfld.long 0x0 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode0h = Process the priority tagged packet with VID = PORT_VLAN[11:0]. 1h = Process the priority tagged packet with VID = 0h." "0,1" newline bitfld.long 0x0 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode.0h = Any packet source address matching an OUI address table entry will be dropped to the host unless the destination address matches with a supervisory destination address table entry.1h = Any packet with a.." "0,1" bitfld.long 0x0 4. "ENABLE_BYPASS,ALE Bypass. When set packets received on non-host ports are sent to the host.It is expected that packets from the host are directed to the particular port. 0h = No bypass 1h = Bypass the ALE" "0,1" newline bitfld.long 0x0 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode.0h = Broadcast and multicast rate limit counters are received port based.1h = Broadcast and multicast rate limit counters are transmit port based." "0,1" bitfld.long 0x0 2. "ALE_VLAN_AWARE,ALE VLAN Aware. Determines how traffic is forwarded using VLAN rules.0h = Simple switch rules packets forwarded to all ports for unknown destinations. 1h = VLAN Aware rules packets forwarded based on VLAN members" "0,1" newline bitfld.long 0x0 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode. Mac authorization mode requires that all table entries be made by the host software.There is no auto learning of addresses in authorization mode and the packet will be dropped if the source address is not.." "0,1" bitfld.long 0x0 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit0h = Broadcast/Multicast rates not limited 1h = Broadcast/Multicast packet reception limited to the port control register rate limit fields." "0,1" line.long 0x4 "CPSW_ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports." bitfld.long 0x4 31. "TRK_EN_DST,Trunk Enable Destination Address.This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" bitfld.long 0x4 30. "TRK_EN_SRC,Trunk Enable Source Address.This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" newline bitfld.long 0x4 29. "TRK_EN_PRI,Trunk Enable Priority.This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. In the event that DSCP mapping is enabled and there is no VLAN the DSCP.." "0,1" bitfld.long 0x4 28. "RESERVED" "0,1" newline bitfld.long 0x4 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN.This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1" bitfld.long 0x4 26. "RESERVED" "0,1" newline bitfld.long 0x4 25. "TRK_EN_SIP,Trunk Enable Source IP Address.This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN tagged .." "0,1" bitfld.long 0x4 24. "TRK_EN_DIP,Trunk Enable Destination IP Address.This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN.." "0,1" newline bitfld.long 0x4 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet.Ethertypes 0-1500 are 802.3 lengths all others are Ether types." "0,1" bitfld.long 0x4 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set." "0,1" newline bitfld.long 0x4 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found." "0,1" bitfld.long 0x4 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match theCPSW_ALE_NXT_HDR register values." "0,1" newline bitfld.long 0x4 19. "RESERVED" "0,1" bitfld.long 0x4 16.--18. "TRK_BASE,Trunk Base. This field is the hash formula starting value.Changing this value will cause the packet distribution on trunk ports to be changed. If all the [31]TRK_EN_DST [30]TRK_EN_SRC [29]TRK_EN_PRI and [27]TRK_EN_VLAN bits are cleared (value:.." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "MIRROR_MIDX,Mirror Index. This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the MIRROR_TOP port.That is any VLAN ONU or address with or withou VLAN can be selected for traffic mirroring." line.long 0x8 "CPSW_ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "ALE_PRESCALE,ALE Prescale. The input clock is divided by this value for use in the multicast/broadcast rate limiters.The minimum operating value is 10h. The prescaler is off when the value is zero." line.long 0xC "CPSW_ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur. This value specifies the minimum time between aging starts." bitfld.long 0xC 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable.When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1" bitfld.long 0xC 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable. When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1" newline hexmask.long.byte 0xC 24.--29. 1. "RESERVED" hexmask.long.tbyte 0xC 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer." group.long 0x3E01C++0x7 line.long 0x0 "CPSW_ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header. It is enabled via the DEFLMTNXTHDR bit in the VLAN entry. All four IP_NXT_HDR0 to IP_NXT_HDR3 bits are compared when enabled. so if.." hexmask.long.byte 0x0 24.--31. 1. "IP_NXT_HDR3,The IP_NXT_HDR3 is the forth protocol or next header compared when enabled." hexmask.long.byte 0x0 16.--23. 1. "IP_NXT_HDR2,The IP_NXT_HDR2 is the third protocol or next header compared when enabled." newline hexmask.long.byte 0x0 8.--15. 1. "IP_NXT_HDR1,The IP_NXT_HDR1 is the second protocol or next header compared when enabled." hexmask.long.byte 0x0 0.--7. 1. "IP_NXT_HDR0,The IP_NXT_HDR0 is the first protocol or next header compared when enabled." line.long 0x4 "CPSW_ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries. After writing to this register any read or write to any ALE register will be stalled until the read or write operation completes." bitfld.long 0x4 31. "TABLEWR,Table Write. This bit is used to write the table words to the lookup table.0h = Table Read Operation is performed. The contents of the TABLEIDX bit will be read into the CPSW_ALE_TBLWx registers (where x = 0 to 2).1h = Table write operation is.." "0,1" hexmask.long 0x4 6.--30. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--5. 1. "TABLEIDX,The table index is used to determine which lookup table entry is read or written." group.long 0x3E034++0xF line.long 0x0 "CPSW_ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry." hexmask.long 0x0 7.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--6. 1. "TABLEWRD2,Table Entry bits [71-64]" line.long 0x4 "CPSW_ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry." hexmask.long 0x4 0.--31. 1. "TABLEWRD1,Table Entry bits [63-32]" line.long 0x8 "CPSW_ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry." hexmask.long 0x8 0.--31. 1. "TABLEWRD0,Table Entry bits [31-0]" line.long 0xC "CPSW_Iy_ALE_PORTCTL0_y,The ALE Port Control Register sets the port specific modes of operation. Offset = 0003E040h + (y * 4h); where y = 0 to 1" hexmask.long.byte 0xC 24.--31. 1. "Iy_REG_P0_BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter.The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.." hexmask.long.byte 0xC 16.--23. 1. "Iy_REG_P0_MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter.The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.." newline bitfld.long 0xC 15. "Iy_REG_P0_DROP_DOUBLE_VLAN,Drop Double VLAN.When set cause any received packet with double VLANs to be dropped. That is if there are two ctag or two stag fields in the packet it will be dropped." "0,1" bitfld.long 0xC 14. "Iy_REG_P0_DROP_DUAL_VLAN,Drop Dual VLAN. When set will cause any received packet with dual VLAN stag followed by ctag to be dropped." "0,1" newline bitfld.long 0xC 13. "Iy_REG_P0_MACONLY_CAF,Mac Only Copy All Frames.When set a Mac Only port will transfer all received good frames to the host. When clear a Mac Only port will transfer packets to the host based on ALE destination address lookup operation (which operates.." "0,1" bitfld.long 0xC 12. "Iy_REG_P0_DIS_PAUTHMOD,Disable Port authorization. When set will allow unknown addresses to arrive on a switch in authorization mode. It is intended for device to device network connection on ports which do not require MACSEC encryption." "0,1" newline bitfld.long 0xC 11. "Iy_REG_P0_MACONLY,MAC Only.When set enables this port be treated like a MAC port for the host. All traffic received is only sent to the host. The host must direct traffic to this port as the lookup engine will not send traffic to the ports with the.." "0,1" bitfld.long 0xC 10. "Iy_REG_P0_TRUNKEN,Trunk Enable. This field is used to enable a port into a trunk.Any port can be used as a trunk port any two or more ports with the Iy_REG_P0_TRUNKEN bit is set and having the same Iy_REG_P0_TRUNKNUM will be placed in the same trunk." "0,1" newline bitfld.long 0xC 8.--9. "Iy_REG_P0_TRUNKNUM,Trunk Number. This field is used as the trunk number when the Iy_REG_P0_TRUNKEN bit is also set.Ports with the same trunk number that have the Iy_REG_P0_TRUNKEN bit is also set will have traffic distributed within the trunk based on.." "0,1,2,3" bitfld.long 0xC 7. "Iy_REG_P0_MIRROR_SP,Mirror Source Port - This field enables the source port mirror option.When this bit is set any traffic received on the port with the Iy_REG_P0_MIRROR_SP bit set will have its received traffic also sent to the MIRROR_TOP port." "0,1" newline bitfld.long 0xC 6. "RESERVED" "0,1" bitfld.long 0xC 5. "Iy_REG_P0_NO_SA_UPDATE,No Source Address Update.When set will not update the source addresses for this port." "0,1" newline bitfld.long 0xC 4. "Iy_REG_P0_NO_LEARN,No Learn.When set will not learn the source addresses for this port." "0,1" bitfld.long 0xC 3. "Iy_REG_P0_VID_INGRESS_CHECK,VLAN Ingress Check.When set if a packet received is not a member of the VLAN the packet will be dropped." "0,1" newline bitfld.long 0xC 2. "Iy_REG_P0_DROP_UN_TAGGED,If Drop Untagged. When set will drop packets without a VLAN tag." "0,1" bitfld.long 0xC 0.--1. "Iy_REG_P0_PORTSTATE,Port State. Defins the current port state used for lookup operations.0h = Disabled 1h = Blocked 2h = Learning 3h = Forwarding" "0,1,2,3" group.long 0x3E090++0xF line.long 0x0 "CPSW_ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List." "0,1,2,3" line.long 0x4 "CPSW_ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID." hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 0.--1. "UVLAN_UNREG_MCAST_FLOOD_MASK,Unknown VLAN Unregister Multicast Flood Mask." "0,1,2,3" line.long 0x8 "CPSW_ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID." hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 0.--1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask." "0,1,2,3" line.long 0xC "CPSW_ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 0.--1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask." "0,1,2,3" group.long 0x3E0B8++0x7 line.long 0x0 "CPSW_ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters. This register is for diagnostic only." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "PBCAST_DIAG,When set and the PORT_DIAG is set to zero will allow all ports to see the same stat diagnostic increment." "0,1" newline hexmask.long.byte 0x0 9.--14. 1. "RESERVED" bitfld.long 0x0 8. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" hexmask.long.byte 0x0 0.--3. 1. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received.For the selected Port. 0h = Disabled 1h = Destination Equal Source Drop Stat will count 2h = VLAN Ingress Check Drop Stat will count 3h = Source Multicast.." line.long 0x4 "CPSW_ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port." hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 0.--1. "OAM_LB_CTRL,The OAM_LB_CTRL bit field allows any port to be put into OAM loopback that is any packet received will be returned to the same port with anCPSW_ALE_EGRESSOP[31-24] EGRESS_OP of 0xFF which swaps the source (SA) and destination address (DA)." "0,1,2,3" rgroup.long 0x3E0C0++0x3 line.long 0x0 "CPSW_ALE_MSK_MUX0,VLAN Mask Mux 0. The ALE Mask Mux 0 register is used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for VLAN registered and unregister mask respectively." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "VLAN_MASK_MUX_0,VLAN Mask Mux 0." "0,1,2,3" group.long 0x3E0C4++0x3 line.long 0x0 "CPSW_Ix_ALE_MSK_MUXx,VLAN Mask Mux x (where x = 1 to 3). The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for VLAN registered and unregister mask respectively." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "Ix_REG_VLAN_MASK_MUX_x,VLAN Mask Mux x (where x = 1 to 3)." "0,1,2,3" group.long 0x3E0FC++0x17 line.long 0x0 "CPSW_ALE_EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions. If the packet was destined for the host. but matches a clasifier that has a.." hexmask.long.byte 0x0 24.--31. 1. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations0h = NOP : 1-n: Defines which egress Operation will be performed. This allows Inter VLAN routing to be configured for high bandwidth traffic reducing CPU.." bitfld.long 0x0 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well.The DA SA and VLAN are ignored for trunk generation on InterVLAN Routing so that this field is the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions.The packet will be routed to the host it was destined to." "0,1" hexmask.long.tbyte 0x0 2.--19. 1. "RESERVED" newline bitfld.long 0x0 0.--1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to.If a destination is a Trunk all the port bits for that trunck must be set." "0,1,2,3" line.long 0x4 "CPSW_ALE_POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching." bitfld.long 0x4 31. "PORT_MEN,Port Match Enable." "0,1" bitfld.long 0x4 30. "TRUNKID,Trunk ID." "0,1" newline hexmask.long.byte 0x4 26.--29. 1. "RESERVED" bitfld.long 0x4 25. "PORT_NUM,Port Number." "0,1" newline hexmask.long.byte 0x4 20.--24. 1. "RESERVED" bitfld.long 0x4 19. "PRI_MEN,Priority Match Enable." "0,1" newline bitfld.long 0x4 16.--18. "PRI_VAL,Priority Value." "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "ONU_MEN,OUI Match Enable." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "ONU_INDEX,OUI Table Entry Index." line.long 0x8 "CPSW_ALE_POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses." bitfld.long 0x8 31. "DST_MEN,Destination Address Match Enable." "0,1" hexmask.long.word 0x8 22.--30. 1. "RESERVED" newline hexmask.long.byte 0x8 16.--21. 1. "DST_INDEX,Destination Address Table Entry Index." bitfld.long 0x8 15. "SRC_MEN,Source Address Match Enable." "0,1" newline hexmask.long.word 0x8 6.--14. 1. "RESERVED" hexmask.long.byte 0x8 0.--5. 1. "SRC_INDEX,Source Address Table Entry Index." line.long 0xC "CPSW_ALE_POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses." bitfld.long 0xC 31. "OVLAN_MEN,Outer VLAN Match Enable." "0,1" hexmask.long.word 0xC 22.--30. 1. "RESERVED" newline hexmask.long.byte 0xC 16.--21. 1. "OVLAN_INDEX,Outer VLAN Table Entry Index." bitfld.long 0xC 15. "IVLAN_MEN,Inner VLAN Match Enable." "0,1" newline hexmask.long.word 0xC 6.--14. 1. "RESERVED" hexmask.long.byte 0xC 0.--5. 1. "IVLAN_INDEX,Inner VLAN Table Entry Index." line.long 0x10 "CPSW_ALE_POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address." bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable." "0,1" hexmask.long.word 0x10 22.--30. 1. "RESERVED" newline hexmask.long.byte 0x10 16.--21. 1. "ETHERTYPE_INDEX,EtherType Table Entry Index." bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable." "0,1" newline hexmask.long.word 0x10 6.--14. 1. "RESERVED" hexmask.long.byte 0x10 0.--5. 1. "IPSRC_INDEX,IP Source Address Table Entry Index." line.long 0x14 "CPSW_ALE_POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address" bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable." "0,1" hexmask.long.word 0x14 22.--30. 1. "RESERVED" newline hexmask.long.byte 0x14 16.--21. 1. "IPDST_INDEX,IP Destination Address Table Entry Index." hexmask.long.word 0x14 0.--15. 1. "RESERVED" group.long 0x3E118++0x13 line.long 0x0 "CPSW_ALE_POLICECFG6,The PIR counter is a 37 bit internal counter where PIR_IDLE_INC_VAL is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time. If the counter is negative the packet will be marked RED. else it can.." hexmask.long 0x0 0.--31. 1. "PIR_IDLE_INC_VAL,Peak Information Rate Idle Increment Value." line.long 0x4 "CPSW_ALE_POLICECFG7,The CIR counter is a 37 bit internal counter where CIR_IDLE_INC_VAL is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time. If the counter is positive the packet will be marked GREEN..." hexmask.long 0x4 0.--31. 1. "CIR_IDLE_INC_VAL,Committed Information Idle Increment Value - The number added to the CIR counter every clock cycle.If zero the CIR counter is disabled and packets will never be marked or processed as YELLOW." line.long 0x8 "CPSW_ALE_POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry. The selected policing/classifier entry is only read or written after this register is written based on the value of the WRITE_ENABLE bit." bitfld.long 0x8 31. "WRITE_ENABLE,Write Enable." "0,1" hexmask.long 0x8 3.--30. 1. "RESERVED" newline bitfld.long 0x8 0.--2. "POL_TBL_IDX,Policer Entry Index." "0,1,2,3,4,5,6,7" line.long 0xC "CPSW_ALE_POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules." bitfld.long 0xC 31. "POLICING_EN,Policing Enable - Enables the policing to color the packets this also enables red or yellow drop capabilities." "0,1" bitfld.long 0xC 30. "RESERVED" "0,1" newline bitfld.long 0xC 29. "RED_DROP_EN,RED Drop Enable - Enables the ALE to drop the red colored packets." "0,1" bitfld.long 0xC 28. "YELLOW_DROP_EN,WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the YELLOWTHRESH bit value.This field would normally not be used as to let the switch drop packets at a buffer threshold instead. In the event that the switch does not.." "0,1" newline bitfld.long 0xC 27. "RESERVED" "0,1" bitfld.long 0xC 24.--26. "YELLOWTHRESH,Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the YELLOW_DROP_EN bit enable.0h = 100% 1h =50% 2h = 33% 3h = 25% 4h = 20% 5h = 17% 6h = 14% 7h = 13%" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 22.--23. "POLMCHMODE,Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier entry.0h = No Hit packets are marked GREEN 1h = No Hit packets are marked YELLOW 2h = No Hit packets are marked RED 3h = No Hit.." "0,1,2,3" bitfld.long 0xC 21. "PRIORITY_THREAD_EN,Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled." "0,1" newline bitfld.long 0xC 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports.That is the default thread will be {port priority}. If the traffic matches a classifier with a thread mapping the classifier thread mapping.." "0,1" hexmask.long.tbyte 0xC 0.--19. 1. "RESERVED" line.long 0x10 "CPSW_ALE_POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition." bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear - This bit clears all the policing/classifier hit bits.This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit." "0,1" bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED - This bit clears all the policing/classifier RED hit bits.This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a RED condition." "0,1" newline bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits.This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a YELLOW condition." "0,1" bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected - This bit clears the selected policing/classifier hit redhit and yellowhit bits.This bit is self clearing." "0,1" newline hexmask.long 0x10 3.--27. 1. "RESERVED" bitfld.long 0x10 0.--2. "POL_TEST_IDX,Policer Test Index - This field selects which policing/classifier hit bits will be read or written." "0,1,2,3,4,5,6,7" rgroup.long 0x3E12C++0x3 line.long 0x0 "CPSW_ALE_POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier." bitfld.long 0x0 31. "POL_HIT,Policer Hit." "0,1" bitfld.long 0x0 30. "POL_REDHIT,Policer Hit RED." "0,1" newline bitfld.long 0x0 29. "POL_YELLOWHIT,Policer Hit YELLOW." "0,1" hexmask.long 0x0 0.--28. 1. "RESERVED" group.long 0x3E134++0xB line.long 0x0 "CPSW_ALE_THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "DEFTHREAD_EN,Default Tread Enable." "0,1" newline hexmask.long.word 0x0 6.--14. 1. "RESERVED" hexmask.long.byte 0x0 0.--5. 1. "DEFTHREADVAL,Default Thread Value." line.long 0x4 "CPSW_ALE_THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host. This allows particular classifier matched traffic to be placed an a particular hosts queue." hexmask.long 0x4 3.--31. 1. "RESERVED" bitfld.long 0x4 0.--2. "CLASSINDEX,Classifier Index." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_ALE_THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry." hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "THREAD_EN,Thread Enable." "0,1" newline hexmask.long.word 0x8 6.--14. 1. "RESERVED" hexmask.long.byte 0x8 0.--5. 1. "THREADVAL,Thread Value." tree.end tree "MCU_CPSW0_NUSS_CONTROL" base ad:0x46000000 rgroup.long 0x20000++0x3 line.long 0x0 "CPSW_CPSW_ID_VER_REG,CPSW ID Version Register." hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification Value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version Value" bitfld.long 0x0 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM_VER,Custom Version Value" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_VER,Minor Version Value" group.long 0x20004++0x3 line.long 0x0 "CPSW_CONTROL_REG,CPSW Switch Control Register." bitfld.long 0x0 31. "ECC_CRC_MODE,ECC CRC Mode." "0,1" hexmask.long.word 0x0 19.--30. 1. "RESERVED" bitfld.long 0x0 18. "EST_ENABLE,Enhanced Scheduled Traffic enable (EST)" "0,1" newline bitfld.long 0x0 17. "IET_ENABLE,Intersperced Express Traffic enable (IET)" "0,1" bitfld.long 0x0 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1" bitfld.long 0x0 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1" newline bitfld.long 0x0 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1" bitfld.long 0x0 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove." "0,1" bitfld.long 0x0 12. "RESERVED" "0,1" newline bitfld.long 0x0 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1" bitfld.long 0x0 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1" bitfld.long 0x0 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1" bitfld.long 0x0 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1" bitfld.long 0x0 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1" bitfld.long 0x0 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1" bitfld.long 0x0 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 2. "P0_ENABLE,Port 0 Enable" "0,1" bitfld.long 0x0 1. "VLAN_AWARE,VLAN Aware Mode:" "0,1" bitfld.long 0x0 0. "S_CN_SWITCH,Service or Customer VLAN switch." "0,1" group.long 0x20010++0x37 line.long 0x0 "CPSW_EM_CONTROL_REG,CPSW Emulation Control Register." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_STAT_PORT_EN_REG,CPSW Statistics Port Enable Register." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "P8_STAT_EN,Port 8 Statistics Enable (if N &gt; 8)" "0,1" bitfld.long 0x4 7. "P7_STAT_EN,Port 7 Statistics Enable (if N &gt; 7)" "0,1" newline bitfld.long 0x4 6. "P6_STAT_EN,Port 6 Statistics Enable (if N &gt; 6)" "0,1" bitfld.long 0x4 5. "P5_STAT_EN,Port 5 Statistics Enable (if N &gt; 5)" "0,1" bitfld.long 0x4 4. "P4_STAT_EN,Port 4 Statistics Enable (if N &gt; 4)" "0,1" newline bitfld.long 0x4 3. "P3_STAT_EN,Port 3 Statistics Enable (if N &gt; 3)" "0,1" bitfld.long 0x4 2. "P2_STAT_EN,Port 2 Statistics Enable (if N &gt; 2)" "0,1" bitfld.long 0x4 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1" newline bitfld.long 0x4 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1" line.long 0x8 "CPSW_PTYPE_REG,CPSW Transmit Priority Type Register." hexmask.long.word 0x8 17.--31. 1. "RESERVED" bitfld.long 0x8 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate (if N &gt; 8)" "0,1" bitfld.long 0x8 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate (if N &gt; 7)" "0,1" newline bitfld.long 0x8 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate (if N &gt; 6)" "0,1" bitfld.long 0x8 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate (if N &gt; 5)" "0,1" bitfld.long 0x8 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate (if N &gt; 4)" "0,1" newline bitfld.long 0x8 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate (if N &gt; 3)" "0,1" bitfld.long 0x8 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate (if N &gt; 2)" "0,1" bitfld.long 0x8 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1" newline bitfld.long 0x8 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1" bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "ESC_PRI_LD_VAL,Escalate Priority Load Value" line.long 0xC "CPSW_SOFT_IDLE_REG,CPSW Software Idle" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "SOFT_IDLE,Software Idle." "0,1" line.long 0x10 "CPSW_THRU_RATE_REG,CPSW Thru Rate Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 12.--15. 1. "SL_RX_THRU_RATE,Ethernet Port Switch FIFO receive through rate." hexmask.long.byte 0x10 4.--11. 1. "RESERVED" newline hexmask.long.byte 0x10 0.--3. 1. "P0_RX_THRU_RATE,CPPI FIFO (port 0) receive through rate." line.long 0x14 "CPSW_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold Register." hexmask.long 0x14 5.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--4. 1. "GAP_THRESH,Ethernet Port Short Gap Threshold." line.long 0x18 "CPSW_TX_START_WDS_REG,CPSW Transmit FIFO Start Words Register." hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED" hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit (egress) Start Words." line.long 0x1C "CPSW_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value Register." hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED" hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value." line.long 0x20 "CPSW_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set" hexmask.long.byte 0x20 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" hexmask.long.byte 0x20 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" hexmask.long.byte 0x20 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" newline hexmask.long.byte 0x20 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" hexmask.long.byte 0x20 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" hexmask.long.byte 0x20 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x20 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" hexmask.long.byte 0x20 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0x24 "CPSW_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear Register." hexmask.long.byte 0x24 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" hexmask.long.byte 0x24 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" hexmask.long.byte 0x24 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" newline hexmask.long.byte 0x24 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" hexmask.long.byte 0x24 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" hexmask.long.byte 0x24 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x24 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" hexmask.long.byte 0x24 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0x28 "CPSW_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low Register." hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" newline hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x2C "CPSW_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High Register." hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" newline hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" line.long 0x30 "CPSW_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low Register." hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" newline hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x34 "CPSW_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High Register." hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" newline hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" group.long 0x20050++0x7 line.long 0x0 "CPSW_VLAN_LTYPE_REG,VLAN LTYPE Outer and Inner Register." hexmask.long.word 0x0 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LTYPE" hexmask.long.word 0x0 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LTYPE" line.long 0x4 "CPSW_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain Register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain." group.long 0x20100++0x1F line.long 0x0 "CPSW_TX_PRI0_MAXLEN_REG,Priority 0 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Packet Length" line.long 0x4 "CPSW_TX_PRI1_MAXLEN_REG,Priority 1 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Packet Length" line.long 0x8 "CPSW_TX_PRI2_MAXLEN_REG,Priority 2 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Packet Length" line.long 0xC "CPSW_TX_PRI3_MAXLEN_REG,Priority 3 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Packet Length" line.long 0x10 "CPSW_TX_PRI4_MAXLEN_REG,Priority 4 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Packet Length" line.long 0x14 "CPSW_TX_PRI5_MAXLEN_REG,Priority 5 Maximum Transmit Packet Length Register. Transmit Priority 5 Maximum Length Priority 5 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Packet Length" line.long 0x18 "CPSW_TX_PRI6_MAXLEN_REG,Priority 6 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x18 14.--31. 1. "RESERVED" hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Packet Length" line.long 0x1C "CPSW_TX_PRI7_MAXLEN_REG,Priority 7 Maximum Transmit Packet Length Register." hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED" hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Packet Length" group.long 0x21004++0x7 line.long 0x0 "CPSW_P0_CONTROL_REG,CPPI Port 0 Control Register." hexmask.long.word 0x0 19.--31. 1. "RESERVED" bitfld.long 0x0 18. "RX_REMAP_DSCP_V6,Port 0 receive remap thread to DSCP IPV6 priority." "0,1" bitfld.long 0x0 17. "RX_REMAP_DSCP_V4,Port 0 receive remap thread to DSCP IPV6 priority." "0,1" newline bitfld.long 0x0 16. "RX_REMAP_VLAN,Port 0 receive remap thread to VLAN." "0,1" bitfld.long 0x0 15. "RX_ECC_ERR_EN,Port 0 receive ECC Error Enable" "0,1" bitfld.long 0x0 14. "TX_ECC_ERR_EN,Port 0 transmit ECC Error Enable" "0,1" newline hexmask.long.word 0x0 3.--13. 1. "RESERVED" bitfld.long 0x0 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1" bitfld.long 0x0 1. "DSCP_IPV4_EN,Port 0 IPV4 DSCP enable" "0,1" newline bitfld.long 0x0 0. "RX_CHECKSUM_EN,Port 0 Receive (port 0 ingress) Checksum Enable" "0,1" line.long 0x4 "CPSW_P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Transmit FLOW ID Offset Register." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0" rgroup.long 0x21010++0x3 line.long 0x0 "CPSW_P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count Register." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED" hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Port 0 Transmit Block Count Usage." bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT,Port 0 Receive Block Count Usage." group.long 0x21014++0x17 line.long 0x0 "CPSW_P0_PORT_VLAN_REG,CPPI Port 0 VLAN Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x4 "CPSW_P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping" bitfld.long 0x4 31. "RESERVED" "0,1" bitfld.long 0x4 28.--30. "PRI7,Priority 7." "0,1,2,3,4,5,6,7" bitfld.long 0x4 27. "RESERVED" "0,1" newline bitfld.long 0x4 24.--26. "PRI6,Priority 6." "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "RESERVED" "0,1" bitfld.long 0x4 20.--22. "PRI5,Priority 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED" "0,1" bitfld.long 0x4 16.--18. "PRI4,Priority 4." "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "RESERVED" "0,1" newline bitfld.long 0x4 12.--14. "PRI3,Priority 3." "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "RESERVED" "0,1" bitfld.long 0x4 8.--10. "PRI2,Priority 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RESERVED" "0,1" bitfld.long 0x4 4.--6. "PRI1,Priority 1." "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "RESERVED" "0,1" newline bitfld.long 0x4 0.--2. "PRI0,Priority 0." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_P0_PRI_CTL_REG,CPPI Port 0 Priority Control Register." hexmask.long.byte 0x8 24.--31. 1. "RESERVED" hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)." hexmask.long.byte 0x8 9.--15. 1. "RESERVED" newline bitfld.long 0x8 8. "RX_PTYPE,Receive Priority Type" "0,1" hexmask.long.byte 0x8 0.--7. 1. "RESERVED" line.long 0xC "CPSW_P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map." bitfld.long 0xC 31. "RESERVED" "0,1" bitfld.long 0xC 28.--30. "PRI7,Priority 7." "0,1,2,3,4,5,6,7" bitfld.long 0xC 27. "RESERVED" "0,1" newline bitfld.long 0xC 24.--26. "PRI6,Priority 6." "0,1,2,3,4,5,6,7" bitfld.long 0xC 23. "RESERVED" "0,1" bitfld.long 0xC 20.--22. "PRI5,Priority 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 19. "RESERVED" "0,1" bitfld.long 0xC 16.--18. "PRI4,Priority 4." "0,1,2,3,4,5,6,7" bitfld.long 0xC 15. "RESERVED" "0,1" newline bitfld.long 0xC 12.--14. "PRI3,Priority 3." "0,1,2,3,4,5,6,7" bitfld.long 0xC 11. "RESERVED" "0,1" bitfld.long 0xC 8.--10. "PRI2,Priority 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 7. "RESERVED" "0,1" bitfld.long 0xC 4.--6. "PRI1,Priority 1." "0,1,2,3,4,5,6,7" bitfld.long 0xC 3. "RESERVED" "0,1" newline bitfld.long 0xC 0.--2. "PRI0,Priority 0." "0,1,2,3,4,5,6,7" line.long 0x10 "CPSW_P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length." hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length." line.long 0x14 "CPSW_P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority Register." hexmask.long.byte 0x14 28.--31. 1. "PRI7,Port Transmit Blocks Priority 7" hexmask.long.byte 0x14 24.--27. 1. "PRI6,Port Transmit Blocks Priority 6" hexmask.long.byte 0x14 20.--23. 1. "PRI5,Port Transmit Blocks Priority 5" newline hexmask.long.byte 0x14 16.--19. 1. "PRI4,Port Transmit Blocks Priority 4" hexmask.long.byte 0x14 12.--15. 1. "PRI3,Port Transmit Blocks Priority 3" hexmask.long.byte 0x14 8.--11. 1. "PRI2,Port Transmit Blocks Priority 2" newline hexmask.long.byte 0x14 4.--7. 1. "PRI1,Port Transmit Blocks Priority 1" hexmask.long.byte 0x14 0.--3. 1. "PRI0,Port Transmit Blocks Priority 0" group.long 0x21030++0x7 line.long 0x0 "CPSW_P0_IDLE2LPI_REG,CPPI Port 0 EEE Idle to LPI Count Register." hexmask.long.byte 0x0 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value." line.long 0x4 "CPSW_P0_LPI2WAKE_REG,CPPI Port 0 EEE LPI to Wakeup Count Register." hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value." rgroup.long 0x21038++0x3 line.long 0x0 "CPSW_P0_EEE_STATUS_REG,CPPI Port 0 EEE Port Status Register." hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "TX_FIFO_EMPTY,Port 0 Transmit FIFO packet count zero." "0,1" bitfld.long 0x0 5. "RX_FIFO_EMPTY,Port 0 Receive FIFO packet count zero." "0,1" newline bitfld.long 0x0 4. "TX_FIFO_HOLD,Port 0 Transmit FIFO hold." "0,1" bitfld.long 0x0 3. "TX_WAKE,Port 0 Receive Wake Time." "0,1" bitfld.long 0x0 2. "TX_LPI,Port 0 LPI." "0,1" newline bitfld.long 0x0 1. "RX_LPI,Port 0 LPI." "0,1" bitfld.long 0x0 0. "WAIT_IDLE2LPI,Transmit Wait Idle to LPI." "0,1" group.long 0x2103C++0x3 line.long 0x0 "CPSW_P0_RX_PKTS_PRI_REG,CPPI Port 0 Receive Packets Per Priority Register." hexmask.long.byte 0x0 28.--31. 1. "PRI7,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 7" hexmask.long.byte 0x0 24.--27. 1. "PRI6,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 6" hexmask.long.byte 0x0 20.--23. 1. "PRI5,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 5" newline hexmask.long.byte 0x0 16.--19. 1. "PRI4,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 4" hexmask.long.byte 0x0 12.--15. 1. "PRI3,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 3" hexmask.long.byte 0x0 8.--11. 1. "PRI2,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 2" newline hexmask.long.byte 0x0 4.--7. 1. "PRI1,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 1" hexmask.long.byte 0x0 0.--3. 1. "PRI0,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 0" group.long 0x2104C++0x3 line.long 0x0 "CPSW_P0_RX_GAP_REG,CPPI Port 0 Receive Gap Register." hexmask.long.byte 0x0 26.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--25. 1. "RX_GAP_CNT,Receive Gap Count." hexmask.long.byte 0x0 8.--15. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RX_GAP_EN,Port 0 Receive Gap Enable" rgroup.long 0x21050++0x3 line.long 0x0 "CPSW_P0_FIFO_STATUS_REG,Port 0 FIFO Status" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,Port 0 Transmit FIFO Priority Active." group.long 0x21120++0x3 line.long 0x0 "CPSW_P0_RX_DSCP_MAP_REG_y,CPPI Port 0 Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers. Offset = 00021120h + (y * 4h); where y = 0h to 7h" bitfld.long 0x0 31. "RESERVED" "0,1" bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "RESERVED" "0,1" newline bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "RESERVED" "0,1" bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "RESERVED" "0,1" bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "RESERVED" "0,1" newline bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "RESERVED" "0,1" bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "RESERVED" "0,1" bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RESERVED" "0,1" newline bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7" group.long 0x21140++0x3 line.long 0x0 "CPSW_P0_PRI_CIR_REG_y,CPPI Port 0 Rx Priority 0 to Priority 7 Committed Information Rate Registers. Offset = 00021140h + (y * 4h); where y = 0h to 7h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority “y” Committed Information Rate Count Value" group.long 0x21160++0x3 line.long 0x0 "CPSW_P0_PRI_EIR_REG_y,CPPI Port 0 Rx Priority 0 to Priority 7 Excess Information Rate Registers. Offset = 00021160h + (y * 4h); where y = 0h to 7h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority “y” Excess Information Rate Count Value" group.long 0x21180++0x1F line.long 0x0 "CPSW_P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x4 "CPSW_P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" bitfld.long 0x4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" bitfld.long 0x4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x8 "CPSW_P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low" bitfld.long 0x8 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" bitfld.long 0x8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" bitfld.long 0x8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0xC "CPSW_P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High" bitfld.long 0xC 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" bitfld.long 0xC 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" bitfld.long 0xC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline bitfld.long 0xC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" line.long 0x10 "CPSW_P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low" bitfld.long 0x10 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" bitfld.long 0x10 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" bitfld.long 0x10 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline bitfld.long 0x10 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x14 "CPSW_P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High" bitfld.long 0x14 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" bitfld.long 0x14 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" bitfld.long 0x14 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline bitfld.long 0x14 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x18 "CPSW_P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" bitfld.long 0x18 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline bitfld.long 0x18 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0x1C "CPSW_P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" bitfld.long 0x1C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" bitfld.long 0x1C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline bitfld.long 0x1C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" group.long 0x21300++0x3 line.long 0x0 "CPSW_P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved." hexmask.long.byte 0x0 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value." group.long 0x21320++0x3 line.long 0x0 "CPSW_P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority" hexmask.long.byte 0x0 28.--31. 1. "PRI7,Host Blocks Per Priority 7" hexmask.long.byte 0x0 24.--27. 1. "PRI6,Host Blocks Per Priority 6" hexmask.long.byte 0x0 20.--23. 1. "PRI5,Host Blocks Per Priority 5" newline hexmask.long.byte 0x0 16.--19. 1. "PRI4,Host Blocks Per Priority 4" hexmask.long.byte 0x0 12.--15. 1. "PRI3,Host Blocks Per Priority 3" hexmask.long.byte 0x0 8.--11. 1. "PRI2,Host Blocks Per Priority 2" newline hexmask.long.byte 0x0 4.--7. 1. "PRI1,Host Blocks Per Priority 1" hexmask.long.byte 0x0 0.--3. 1. "PRI0,Host Blocks Per Priority 0" rgroup.long 0x22000++0x3 line.long 0x0 "CPSW_PN_RESERVED_REG,Reserved" hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved register for memory map alignment" group.long 0x22004++0x7 line.long 0x0 "CPSW_PN_CONTROL_REG,Enet Port N Control" hexmask.long.word 0x0 18.--31. 1. "RESERVED" bitfld.long 0x0 17. "EST_PORT_EN,EST Port Enable." "0,1" bitfld.long 0x0 16. "IET_PORT_EN,Intersperced Express Traffic (IET) Port Enable." "0,1" newline bitfld.long 0x0 15. "RX_ECC_ERR_EN,Port N receive ECC Error Enable" "0,1" bitfld.long 0x0 14. "TX_ECC_ERR_EN,Port N transmit ECC Error Enable" "0,1" bitfld.long 0x0 13. "RESERVED" "0,1" newline bitfld.long 0x0 12. "TX_LPI_CLKSTOP_EN,Transmit LPI Clock Stop Enable." "0,1" hexmask.long.word 0x0 3.--11. 1. "RESERVED" bitfld.long 0x0 2. "DSCP_IPV6_EN,IPV6 DSCP enable" "0,1" newline bitfld.long 0x0 1. "DSCP_IPV4_EN,IPV4 DSCP enable" "0,1" bitfld.long 0x0 0. "RESERVED" "0,1" line.long 0x4 "CPSW_PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 8.--15. 1. "TX_MAX_BLKS,Transmit Max Blocks." hexmask.long.byte 0x4 0.--7. 1. "RX_MAX_BLKS,Receive Max Blocks." rgroup.long 0x22010++0x3 line.long 0x0 "CPSW_PN_BLK_CNT_REG,Enet Port N FIFO Block Usage Count" hexmask.long.word 0x0 22.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--21. 1. "RX_BLK_CNT_P,Receive Express Block Count Usage." bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Transmit Block Count Usage." bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT_E,Receive Express Block Count Usage." group.long 0x22014++0x23 line.long 0x0 "CPSW_PN_PORT_VLAN_REG,Enet Port N VLAN" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x4 "CPSW_PN_TX_PRI_MAP_REG,Enet Port N Tx Header Pri to Switch Pri Mapping" bitfld.long 0x4 31. "RESERVED" "0,1" bitfld.long 0x4 28.--30. "PRI7,Priority 7. A packet header priority of 7h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 27. "RESERVED" "0,1" newline bitfld.long 0x4 24.--26. "PRI6,Priority 6. A packet header priority of 6h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 23. "RESERVED" "0,1" bitfld.long 0x4 20.--22. "PRI5,Priority 5. A packet header priority of 5h is given this switch queue pri." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED" "0,1" bitfld.long 0x4 16.--18. "PRI4,Priority 4. A packet header priority of 4h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "RESERVED" "0,1" newline bitfld.long 0x4 12.--14. "PRI3,Priority 3. A packet header priority of 3h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "RESERVED" "0,1" bitfld.long 0x4 8.--10. "PRI2,Priority 2. A packet header priority of 2h is given this switch queue pri." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RESERVED" "0,1" bitfld.long 0x4 4.--6. "PRI1,Priority 1. A packet header priority of 1h is given this switch queue pri." "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "RESERVED" "0,1" newline bitfld.long 0x4 0.--2. "PRI0,Priority 0. A packet header priority of 0h is given this switch queue pri." "0,1,2,3,4,5,6,7" line.long 0x8 "CPSW_PN_PRI_CTL_REG,Enet Port N Priority Control" hexmask.long.byte 0x8 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)" hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)" hexmask.long.byte 0x8 12.--15. 1. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" newline hexmask.long.word 0x8 0.--11. 1. "RESERVED" line.long 0xC "CPSW_PN_RX_PRI_MAP_REG,Enet Port N RX Pkt Pri to Header Pri Map" bitfld.long 0xC 31. "RESERVED" "0,1" bitfld.long 0xC 28.--30. "PRI7,Priority 7." "0,1,2,3,4,5,6,7" bitfld.long 0xC 27. "RESERVED" "0,1" newline bitfld.long 0xC 24.--26. "PRI6,Priority 6." "0,1,2,3,4,5,6,7" bitfld.long 0xC 23. "RESERVED" "0,1" bitfld.long 0xC 20.--22. "PRI5,Priority 5." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 19. "RESERVED" "0,1" bitfld.long 0xC 16.--18. "PRI4,Priority 4." "0,1,2,3,4,5,6,7" bitfld.long 0xC 15. "RESERVED" "0,1" newline bitfld.long 0xC 12.--14. "PRI3,Priority 3." "0,1,2,3,4,5,6,7" bitfld.long 0xC 11. "RESERVED" "0,1" bitfld.long 0xC 8.--10. "PRI2,Priority 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 7. "RESERVED" "0,1" bitfld.long 0xC 4.--6. "PRI1,Priority 1." "0,1,2,3,4,5,6,7" bitfld.long 0xC 3. "RESERVED" "0,1" newline bitfld.long 0xC 0.--2. "PRI0,Priority 0." "0,1,2,3,4,5,6,7" line.long 0x10 "CPSW_PN_RX_MAXLEN_REG,Enet Port N Receive Frame Max Length" hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length." line.long 0x14 "CPSW_PN_TX_BLKS_PRI_REG,Enet Port N Transmit Block Sub Per Priority" hexmask.long.byte 0x14 28.--31. 1. "PRI7,Transmit Blocks Per Priority (subtract value) 7" hexmask.long.byte 0x14 24.--27. 1. "PRI6,Transmit Blocks Per Priority (subtract value) 6" hexmask.long.byte 0x14 20.--23. 1. "PRI5,Transmit Blocks Per Priority (subtract value) 5" newline hexmask.long.byte 0x14 16.--19. 1. "PRI4,Transmit Blocks Per Priority (subtract value) 4" hexmask.long.byte 0x14 12.--15. 1. "PRI3,Transmit Blocks Per Priority (subtract value) 3" hexmask.long.byte 0x14 8.--11. 1. "PRI2,Transmit Blocks Per Priority (subtract value) 2" newline hexmask.long.byte 0x14 4.--7. 1. "PRI1,Transmit Blocks Per Priority (subtract value) 1" hexmask.long.byte 0x14 0.--3. 1. "PRI0,Transmit Blocks Per Priority (subtract value) 0" line.long 0x18 "CPSW_PN_RX_FLOW_THRESH_REG,Enet MAC Receive Flow Threshold in Receive Buffer Words" hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED" hexmask.long.word 0x18 0.--8. 1. "COUNT,Receive Flow Control Threshold in Words." line.long 0x1C "CPSW_PN_IDLE2LPI_REG,Enet Port N EEE Idle to LPI counter" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x1C 0.--23. 1. "COUNT,EEE Idle to LPI counter load value." line.long 0x20 "CPSW_PN_LPI2WAKE_REG,Enet Port N EEE LPI to wake counter" hexmask.long.byte 0x20 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x20 0.--23. 1. "COUNT,EEE LPI to wake counter load value." rgroup.long 0x22038++0x3 line.long 0x0 "CPSW_PN_EEE_STATUS_REG,Enet Port N EEE status" hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "TX_FIFO_EMPTY,Port N Transmit FIFO packet count zero." "0,1" bitfld.long 0x0 5. "RX_FIFO_EMPTY,Port N Receive FIFO packet count zero." "0,1" newline bitfld.long 0x0 4. "TX_FIFO_HOLD,Port N Transmit FIFO hold." "0,1" bitfld.long 0x0 3. "TX_WAKE,Port N Receive Wake Time." "0,1" bitfld.long 0x0 2. "TX_LPI,Port N Transmit LPI." "0,1" newline bitfld.long 0x0 1. "RX_LPI,Port N Receive LPI." "0,1" bitfld.long 0x0 0. "WAIT_IDLE2LPI,Transmit Wait Idle to LPI." "0,1" group.long 0x22040++0x3 line.long 0x0 "CPSW_PN_IET_CONTROL_REG,Enet Port N IET Control" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "MAC_PREMPT,Mac Preempt Queue – Indicates which transmit FIFO queues are sent to the preempt MAC. Bit 0 indicates queue zero bit 1 queue 1 and so on. Packets will be sent to the preempt MAC only when MAC_PENABLE is set and when MAC_VERIFIED.." hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8.--10. "MAC_ADDFRAGSIZE,Mac Fragment Size – An integer in the range 0:7 indicating as a multiple of 64 the minimum additional length for nonfinal mPackets. 0 = 64 1 = 128 2 = 192 3 = 256 4 = 320 5 = 384 6 = 448 7 = 512" "0: 64,1: 128,2: 192,3: 256,4: 320,5: 384,6: 448,7: 512" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "MAC_LINKFAIL,Mac Link Fail – Link Fail Indicator to reset the verify state machine. This bit is reset high. Verify and response frames will be sent/allowed when this bit is cleared." "0,1" newline bitfld.long 0x0 2. "MAC_DISABLEVERIFY,Mac Disable Verify – Disables verification on the port when set. If this bit is set then packets will be sent to the preempt Mac when MAC_PENABLE is set (This is a forced mode with no IET verification)." "0,1" bitfld.long 0x0 1. "MAC_HOLD,Mac Hold – Hold Preemption on the port." "0,1" bitfld.long 0x0 0. "MAC_PENABLE,Mac Preemption Enable – Port Preemption Enable. This takes effect only when IET_PORT_EN is set." "0,1" rgroup.long 0x22044++0x3 line.long 0x0 "CPSW_PN_IET_STATUS_REG,Enet Port N IET Status" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "MAC_VERIFY_ERR,Mac Received Verify Packet with Errors – Set when a verify packet with errors is received. Cleared when MAC_PENABLE is cleared to zero." "0,1" bitfld.long 0x0 2. "MAC_RESPOND_ERR,Mac Received Respond Packet with Errors – Set when a respond packet with errors is received. Cleared when MAC_PENABLE is cleared to zero." "0,1" newline bitfld.long 0x0 1. "MAC_VERIFY_FAIL,Mac Verification Failed – Indication that verification was unsuccessful." "0,1" bitfld.long 0x0 0. "MAC_VERIFIED,Mac Verified – Indication that verification was successful." "0,1" group.long 0x22048++0x3 line.long 0x0 "CPSW_PN_IET_VERIFY_REG,Enet Port N IET VERIFY" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x0 0.--23. 1. "MAC_VERIFY_CNT,Mac Verify Timeout Count – The number of wireside clocks contained in the verify timeout counter. The default is 0x1312D0 (10ms at 125MHz in gig mode)." rgroup.long 0x22050++0x3 line.long 0x0 "CPSW_PN_FIFO_STATUS_REG,Enet Port N FIFO STATUS" hexmask.long.word 0x0 19.--31. 1. "RESERVED" bitfld.long 0x0 18. "EST_BUFACT,EST RAM active buffer." "0,1" bitfld.long 0x0 17. "EST_ADD_ERR,EST Address Error." "0,1" newline bitfld.long 0x0 16. "EST_CNT_ERR,EST Fetch Count Error." "0,1" hexmask.long.byte 0x0 8.--15. 1. "TX_E_MAC_ALLOW,EST transmit MAC allow." hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,EST Transmit Priority Active." group.long 0x22060++0x3 line.long 0x0 "CPSW_PN_EST_CONTROL_REG,Enet Port N EST CONTROL" hexmask.long.byte 0x0 26.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--25. 1. "EST_FILL_MARGIN,EST Fill Margin." hexmask.long.byte 0x0 9.--15. 1. "RESERVED" newline bitfld.long 0x0 8. "EST_FILL_EN,EST Fill Enable." "0,1" bitfld.long 0x0 5.--7. "EST_TS_PRI,EST Timestamp Express Priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "EST_TS_ONEPRI,EST Timestamp One Express Priority." "0,1" newline bitfld.long 0x0 3. "EST_TS_FIRST,EST Timestamp First Express Packet only." "0,1" bitfld.long 0x0 2. "EST_TS_EN,EST Timestamp Enable." "0,1" bitfld.long 0x0 1. "EST_BUFSEL,EST Buffer Select." "0,1" newline bitfld.long 0x0 0. "EST_ONEBUF,EST One Fetch Buffer." "0,1" group.long 0x22120++0x3 line.long 0x0 "CPSW_PN_RX_DSCP_MAP_REG_y,Enet Port N Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers. Offset = 00022120h + (y * 4h); where y = 0h to 7h" bitfld.long 0x0 31. "RESERVED" "0,1" bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "RESERVED" "0,1" newline bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "RESERVED" "0,1" bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "RESERVED" "0,1" bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "RESERVED" "0,1" newline bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "RESERVED" "0,1" bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "RESERVED" "0,1" bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "RESERVED" "0,1" newline bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7" group.long 0x22140++0x3 line.long 0x0 "CPSW_PN_PRI_CIR_REG_y,Ethernet Port N Rx Priority 0 to Priority 7 Committed Information Rate Registers. Offset = 00022140h + (y * 4h); where y = 0h to 7h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority “y” Committed Information Rate Count Value" group.long 0x22160++0x3 line.long 0x0 "CPSW_PN_PRI_EIR_REG_y,Ethernet Port N Rx Priority 0 to Priority 7 Excess Information Rate Registers Offset = 00022160h + (y * 4h); where y = 0h to 7h" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority “y” Excess Information Rate Count Value" group.long 0x22180++0x1F line.long 0x0 "CPSW_PN_TX_D_THRESH_SET_L_REG,Enet Port N Tx PFC Destination Threshold Set Low" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x4 "CPSW_PN_TX_D_THRESH_SET_H_REG,Enet Port N Tx PFC Destination Threshold Set High" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" bitfld.long 0x4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" bitfld.long 0x4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x8 "CPSW_PN_TX_D_THRESH_CLR_L_REG,Enet Port N Tx PFC Destination Threshold Clr Low" bitfld.long 0x8 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" bitfld.long 0x8 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" bitfld.long 0x8 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline bitfld.long 0x8 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0xC "CPSW_PN_TX_D_THRESH_CLR_H_REG,Enet Port N Tx PFC Destination Threshold Clr High" bitfld.long 0xC 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" bitfld.long 0xC 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" bitfld.long 0xC 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline bitfld.long 0xC 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" line.long 0x10 "CPSW_PN_TX_G_BUF_THRESH_SET_L_REG,Enet Port N Tx PFC Global Buffer Threshold Set Low" bitfld.long 0x10 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" bitfld.long 0x10 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" bitfld.long 0x10 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" newline bitfld.long 0x10 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" line.long 0x14 "CPSW_PN_TX_G_BUF_THRESH_SET_H_REG,Enet Port N Tx PFC Global Buffer Threshold Set High" bitfld.long 0x14 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" bitfld.long 0x14 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" bitfld.long 0x14 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" newline bitfld.long 0x14 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" line.long 0x18 "CPSW_PN_TX_G_BUF_THRESH_CLR_L_REG,Enet Port N Tx PFC Global Buffer Threshold Clr Low" bitfld.long 0x18 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" bitfld.long 0x18 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" bitfld.long 0x18 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" newline bitfld.long 0x18 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" line.long 0x1C "CPSW_PN_TX_G_BUF_THRESH_CLR_H_REG,Enet Port N Tx PFC Global Buffer Threshold Clr High" bitfld.long 0x1C 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" bitfld.long 0x1C 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" bitfld.long 0x1C 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" newline bitfld.long 0x1C 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" group.long 0x22300++0x23 line.long 0x0 "CPSW_PN_TX_D_OFLOW_ADDVAL_L_REG,Enet Port N Tx Destination Out Flow Add Values Low" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" line.long 0x4 "CPSW_PN_TX_D_OFLOW_ADDVAL_H_REG,Enet Port N Tx Destination Out Flow Add Values High" bitfld.long 0x4 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" bitfld.long 0x4 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" bitfld.long 0x4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" newline bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" line.long 0x8 "CPSW_PN_SA_L_REG,Enet Port N Tx Pause Frame Source Address Low" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" hexmask.long.byte 0x8 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15-8 (byte 1)" line.long 0xC "CPSW_PN_SA_H_REG,Enet Port N Tx Pause Frame Source Address High" hexmask.long.byte 0xC 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23-16 (byte 2)" hexmask.long.byte 0xC 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31-24 (byte 3)" hexmask.long.byte 0xC 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39-32 (byte 4)" newline hexmask.long.byte 0xC 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47-40 (byte 5)" line.long 0x10 "CPSW_PN_TS_CTL_REG,Enet Port N Time Sync Control" hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable." hexmask.long.byte 0x10 12.--15. 1. "RESERVED" bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable." "0,1" newline bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Sync Transmit Annex E enable." "0,1" bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Sync Receive Annex E enable." "0,1" bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable (transmit and receive)." "0,1" newline bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Sync Transmit Annex D enable." "0,1" bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_EN,Time Sync Transmit VLAN LTYPE 2 enable." "0,1" bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_EN,Time Sync Transmit VLAN LTYPE 1 enable." "0,1" newline bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Sync Transmit Annex F enable." "0,1" bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Sync Receive Annex D enable." "0,1" bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_EN,Time Sync Receive VLAN LTYPE 2 enable." "0,1" newline bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_EN,Time Sync Receive VLAN LTYPE 1 enable." "0,1" bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Sync Receive Annex F Enable." "0,1" line.long 0x14 "CPSW_PN_TS_SEQ_LTYPE_REG,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)" hexmask.long.word 0x14 22.--31. 1. "RESERVED" hexmask.long.byte 0x14 16.--21. 1. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1" line.long 0x18 "CPSW_PN_TS_VLAN_LTYPE_REG,Enet Port N Time Sync VLAN2 and VLAN2" hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2" hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1" line.long 0x1C "CPSW_PN_TS_CTL_LTYPE2_REG,Enet Port N Time Sync Control and LTYPE 2" hexmask.long.byte 0x1C 25.--31. 1. "RESERVED" bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1" bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1" newline bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1" bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1" bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1" newline bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1" bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1" bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1" newline bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1" hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2" line.long 0x20 "CPSW_PN_TS_CTL2_REG,Enet Port N Time Sync Control 2" hexmask.long.word 0x20 22.--31. 1. "RESERVED" hexmask.long.byte 0x20 16.--21. 1. "TS_DOMAIN_OFFSET,Time Sync Domain Offset." hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable." group.long 0x22330++0x3 line.long 0x0 "CPSW_PN_MAC_CONTROL_REG,Enet Port N Mac Control" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable." "0,1" bitfld.long 0x0 23. "RX_CSF_EN,RX Copy Short Frames Enable." "0,1" newline bitfld.long 0x0 22. "RX_CEF_EN,RX Copy Error Frames Enable." "0,1" bitfld.long 0x0 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1" bitfld.long 0x0 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable." "0,1" newline bitfld.long 0x0 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable." "0,1" bitfld.long 0x0 18. "CTL_EN,External Control Enable." "0,1" bitfld.long 0x0 17. "GIG_FORCE,Gigabit Mode Force." "0,1" newline bitfld.long 0x0 16. "IFCTL_B,Interface Control B." "0,1" bitfld.long 0x0 15. "IFCTL_A,Interface Control A." "0,1" bitfld.long 0x0 13.--14. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 12. "CRC_TYPE,Port CRC Type" "0,1" bitfld.long 0x0 11. "CMD_IDLE,Command Idle" "0,1" bitfld.long 0x0 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable" "0,1" newline bitfld.long 0x0 8.--9. "RESERVED" "0,1,2,3" bitfld.long 0x0 7. "GIG,Gigabit Mode." "0,1" bitfld.long 0x0 6. "TX_PACE,Transmit Pacing Enable" "0,1" newline bitfld.long 0x0 5. "GMII_EN,GMII Enable." "0,1" bitfld.long 0x0 4. "TX_FLOW_EN,Transmit Flow Control Enable." "0,1" bitfld.long 0x0 3. "RX_FLOW_EN,Receive Flow Control Enable." "0,1" newline bitfld.long 0x0 2. "MTEST,Manufacturing Test mode." "0,1" bitfld.long 0x0 1. "LOOPBACK,Loop Back Mode." "0,1" bitfld.long 0x0 0. "FULLDUPLEX,Full Duplex mode." "0,1" rgroup.long 0x22334++0x3 line.long 0x0 "CPSW_PN_MAC_STATUS_REG,Enet Port N Mac Status" bitfld.long 0x0 31. "IDLE,Enet IDLE." "0,1" bitfld.long 0x0 30. "E_IDLE,Express MAC is Idle." "0,1" bitfld.long 0x0 29. "P_IDLE,Prempt MAC is Idle." "0,1" newline bitfld.long 0x0 28. "TX_IDLE,Mac Transmit Idle." "0,1" bitfld.long 0x0 27. "TORF,Top of receive FIFO flow control trigger occurred." "0,1" bitfld.long 0x0 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)" hexmask.long.byte 0x0 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)" bitfld.long 0x0 7. "RESERVED" "0,1" newline bitfld.long 0x0 6. "EXT_RX_FLOW_EN,External Receive Flow Control Enable." "0,1" bitfld.long 0x0 5. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable." "0,1" bitfld.long 0x0 4. "EXT_GIG,External GIG." "0,1" newline bitfld.long 0x0 3. "EXT_FULLDUPLEX,External Fullduplex." "0,1" bitfld.long 0x0 2. "RESERVED" "0,1" bitfld.long 0x0 1. "RX_FLOW_ACT,Receive Flow Control Active." "0,1" newline bitfld.long 0x0 0. "TX_FLOW_ACT,Transmit Flow Control Active." "0,1" group.long 0x22338++0xB line.long 0x0 "CPSW_PN_MAC_SOFT_RESET_REG,Enet Port N Mac Soft Reset" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Software reset." "0,1" line.long 0x4 "CPSW_PN_MAC_BOFFTEST_REG,Enet Port N Mac Backoff Test" bitfld.long 0x4 31. "RESERVED" "0,1" hexmask.long.byte 0x4 26.--30. 1. "PACEVAL,Pacing Current Value." hexmask.long.word 0x4 16.--25. 1. "RNDNUM,Backoff Random Number Generator." newline hexmask.long.byte 0x4 12.--15. 1. "COLL_COUNT,Collision Count." bitfld.long 0x4 10.--11. "RESERVED" "0,1,2,3" hexmask.long.word 0x4 0.--9. 1. "TX_BACKOFF,Backoff Count." line.long 0x8 "CPSW_PN_MAC_RX_PAUSETIMER_REG,Enet Port N 802.3 Receive Pause Timer" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value." group.long 0x22350++0x3 line.long 0x0 "CPSW_PN_MAC_RXN_PAUSETIMER_REG_y,Ethernet Port N PFC Priority 0 to Priority 7 Rx Pause Timer Registers. Offset = 00022350h + (y * 4h); where y = 0h to 7h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "RX_PAUSETIMER,Rx “y” Pause Timer Value." group.long 0x22370++0x3 line.long 0x0 "CPSW_PN_MAC_TX_PAUSETIMER_REG,Enet Port N 802.3 Tx Pause Timer" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,802.3 Tx Pause Timer Value." group.long 0x22380++0x3 line.long 0x0 "CPSW_PN_MAC_TXN_PAUSETIMER_REG_y,Ethernet Port N PFC Priority 0 to Priority 7 Tx Pause Timer Registers. Offset = 00022380h + (y * 4h); where y = 0h to 7h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,PFC Tx ”y” Pause Timer Value." group.long 0x223A0++0x7 line.long 0x0 "CPSW_PN_MAC_EMCONTROL_REG,Enet Port N Emulation Control" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_PN_MAC_TX_GAP_REG,Enet Port N Tx Inter Packet Gap" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap" group.long 0x223AC++0x13 line.long 0x0 "CPSW_PN_INTERVLAN_OPX_POINTER_REG,Enet Port N Tx Egress InterVLAN Operation Pointer" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "INTERVLAN_OPX_POINTER,Egress InterVLAN Operation Pointer" "0,1,2,3,4,5,6,7" line.long 0x4 "CPSW_PN_INTERVLAN_OPX_A_REG,Enet Port N Tx Egress InterVLAN A" hexmask.long.byte 0x4 24.--31. 1. "DA_23_16,Destination Address bits 23-16 – DA byte 4 on wire." hexmask.long.byte 0x4 16.--23. 1. "DA_31_24,Destination Address bits 31-24 – DA byte 3 on wire." hexmask.long.byte 0x4 8.--15. 1. "DA_39_32,Destination Address bits 39-32 – DA byte 2 on wire." newline hexmask.long.byte 0x4 0.--7. 1. "DA_47_40,Destination Address bits 47-40 – DA byte 1 on wire." line.long 0x8 "CPSW_PN_INTERVLAN_OPX_B_REG,Enet Port N Tx Egress InterVLAN B" hexmask.long.byte 0x8 24.--31. 1. "SA_39_32,Source Address bits 39-32 – SA byte 2 on wire." hexmask.long.byte 0x8 16.--23. 1. "SA_47_40,Source Address bits 47-40 – SA byte 1 on wire." hexmask.long.byte 0x8 8.--15. 1. "DA_7_0,Destination Address bits 7-0 – DA byte 6 on wire." newline hexmask.long.byte 0x8 0.--7. 1. "DA_15_8,Destination Address bits 15-8 – DA byte 5 on wire." line.long 0xC "CPSW_PN_INTERVLAN_OPX_C_REG,Enet Port N Tx Egress InterVLAN C" hexmask.long.byte 0xC 24.--31. 1. "SA_7_0,Source Address bits 7-0 – SA byte 6 on wire." hexmask.long.byte 0xC 16.--23. 1. "SA_15_8,Source Address bits 15-8 – SA byte 5 on wire." hexmask.long.byte 0xC 8.--15. 1. "SA_23_16,Source Address bits 23-16 – SA byte 4 on wire." newline hexmask.long.byte 0xC 0.--7. 1. "SA_31_24,Source Address bits 31-24 – SA byte 3 on wire." line.long 0x10 "CPSW_PN_INTERVLAN_OPX_D_REG,Enet Port N Tx Egress InterVLAN D" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "INTERVLAN_OPX_D,Egress InterVLAN D" tree.end tree "MCU_CPSW0_NUSS_CPINT" base ad:0x46000000 rgroup.long 0x1000++0x3 line.long 0x0 "CPSW_INT_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,MajorCPSW_INT_REVISION" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CustomCPSW_INT_REVISION" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,MinorCPSW_INT_REVISION" group.long 0x1010++0x3 line.long 0x0 "CPSW_INT_EOI_REG,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x1014++0x3 line.long 0x0 "CPSW_INT_INTR_VECTOR_REG,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" group.long 0x1100++0x3 line.long 0x0 "CPSW_INT_ENABLE_REG_OUT_PULSE_0,Enable Register 0" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA,Enable Set for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA,Enable Set for out_pulse_en_mdio_penda" "0,1" bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA,Enable Set for out_pulse_en_evnt_penda" "0,1" group.long 0x1300++0x3 line.long 0x0 "CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0,Enable Clear Register 0" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR,Enable Clear for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR,Enable Clear for out_pulse_en_mdio_penda" "0,1" bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR,Enable Clear for out_pulse_en_evnt_penda" "0,1" rgroup.long 0x1500++0x3 line.long 0x0 "CPSW_INT_STATUS_REG_OUT_PULSE_0,Status Register 0" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 2. "STATUS_OUT_PULSE_STAT_PENDA,Status for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "STATUS_OUT_PULSE_MDIO_PENDA,Status for out_pulse_en_mdio_penda" "0,1" bitfld.long 0x0 0. "STATUS_OUT_PULSE_EVNT_PENDA,Status for out_pulse_en_evnt_penda" "0,1" rgroup.long 0x1A80++0x3 line.long 0x0 "CPSW_INT_INTR_VECTOR_REG_OUT_PULSE,Interrupt Vector for out_pulse" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_OUT_PULSE,Interrupt Vector" tree.end tree "MCU_CPSW0_NUSS_CPTS" base ad:0x46000000 rgroup.long 0x3D000++0x3 line.long 0x0 "CPSW_CPTS_IDVER_REG,MCU_CPSW0_NUSS CPTS Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,TX Identification Value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" bitfld.long 0x0 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor Version Value" group.long 0x3D004++0x7 line.long 0x0 "CPSW_CPTS_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output time stamp counter bit select" hexmask.long.word 0x0 18.--27. 1. "RESERVED" bitfld.long 0x0 17. "TX_GENF_CLR_EN,GENF (and ESTF) Clear Enable. 0h = A CPTS_GENFn output is not cleared when the associated CPSW_GENF0_LENGTH_REG/ CPSW_GENF1_LENGTH_REG[31:0] is cleared to zero. 1h = A CPTS_GENFn output is cleared when the associated CPSW_GENF0_LENGTH_REG/.." "0,1" bitfld.long 0x0 16. "TS_RX_NO_EVENT,Timestamp Ethernet Receive produces no events." "0,1" newline bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" newline bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" newline bitfld.long 0x0 7. "TS_PPM_DIR,PPM Correction Direction" "0,1" bitfld.long 0x0 6. "TS_COMP_TOG,Time stamp Compare Toggle mode" "0,1" bitfld.long 0x0 5. "MODE,64-Bit Mode." "0,1" bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable." "0,1" newline bitfld.long 0x0 3. "TSTAMP_EN,Host Receive time stamp Enable" "0,1" bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP Polarity" "0,1" bitfld.long 0x0 1. "INT_TEST,Interrupt Test." "0,1" bitfld.long 0x0 0. "CPTS_EN,Time Sync Enable." "0,1" line.long 0x4 "CPSW_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long 0x4 5.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select. This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference. 0h = Selects CPSWHSDIV_CLKOUT2 clock 1h = Selects MAINHSDIV_CLKOUT3 clock 2h = Selects.." wgroup.long 0x3D00C++0x3 line.long 0x0 "CPSW_CPTS_TS_PUSH_REG,Time Stamp Event Push Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push." "0,1" group.long 0x3D010++0x3 line.long 0x0 "CPSW_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" wgroup.long 0x3D014++0x3 line.long 0x0 "CPSW_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_LOAD_EN,Time Stamp Load Enable." "0,1" group.long 0x3D018++0xB line.long 0x0 "CPSW_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value (lower 32-bits) Register." hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time Stamp Comparison Low Value." line.long 0x4 "CPSW_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register." hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time Stamp Comparison Length." line.long 0x8 "CPSW_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)." "0,1" rgroup.long 0x3D024++0x3 line.long 0x0 "CPSW_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)." "0,1" group.long 0x3D028++0x7 line.long 0x0 "CPSW_CPTS_INT_ENABLE_REG,Interrupt Enable Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable." "0,1" line.long 0x4 "CPSW_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Value Register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,Time stamp Comparison Nudge Value." wgroup.long 0x3D030++0x3 line.long 0x0 "CPSW_CPTS_EVENT_POP_REG,Event Interrupt Pop Register." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EVENT_POP,Event Pop." "0,1" rgroup.long 0x3D034++0xF line.long 0x0 "CPSW_CPTS_EVENT_0_REG,Lower 32-bits of the Event Value Register." hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp." line.long 0x4 "CPSW_CPTS_EVENT_1_REG,Lower Middle 32-bits of the Event Value Register." bitfld.long 0x4 30.--31. "RESERVED" "0,1,2,3" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port Number." hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Time Sync Event Type" newline hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type." hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID." line.long 0x8 "CPSW_CPTS_EVENT_2_REG,Upper Middle 32-bits of the Event Value Register." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain." line.long 0xC "CPSW_CPTS_EVENT_3_REG,Upper 32-bits of the Event Value Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp." group.long 0x3D044++0x17 line.long 0x0 "CPSW_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value (upper 32-bits) Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time Stamp Load high Value." line.long 0x4 "CPSW_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value (upper 32-bits) Register." hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time Stamp Comparison High Value." line.long 0x8 "CPSW_CPTS_TS_ADD_VAL_REG,TS Add Value Register" hexmask.long 0x8 3.--31. 1. "RESERVED" bitfld.long 0x8 0.--2. "ADD_VAL,The ts_add_value[2:0] is added to 1 to comprise the time stamp increment value." "0,1,2,3,4,5,6,7" line.long 0xC "CPSW_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Load Low Value (lower 32-bits) Register." hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time Stamp PPM Low Value." line.long 0x10 "CPSW_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM Load High Value (upper 32-bits) Register." hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time Stamp PPM High Value." line.long 0x14 "CPSW_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge Value. The minimum value of the Time Stamp PPM is 0x400 (all 42 bits:" group.long 0x3D0E0++0x1B line.long 0x0 "CPSW_GENF0_COMP_LOW_REG_L,Time Stamp Generate Function (GENF0) Comparison Low Value (lower 32-bits). Offset = 0003D0E0h + (l * 20h); where l = 0 to 1" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value (lower 32-bits)." line.long 0x4 "CPSW_GENF0_COMP_HIGH_REG_L,Time Stamp Generate Function (GENF0) Comparison high Value (upper 32-bits). Offset = 0003D0E4h + (l * 20h); where l = 0 to 1" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value (upper 32-bits)." line.long 0x8 "CPSW_GENF0_TS_GENF_CONTROL_REG,Time Stamp Generate Function (GENF0) Control Registers. Offset = 0003D0E8h + (l * 20h); where l = 0 to 1" hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction." "0,1" line.long 0xC "CPSW_GENF0_LENGTH_REG_L,Time Stamp Generate Function (GENF0) Length Value. Offset = 0003D0ECh + (l * 20h); where l = 0 to 1" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "CPSW_GENF0_PPM_LOW_REG_L,Time Stamp Generate Function (GENF0) PPM Low Value (lower 32-bits). Offset = 0003D0F0h + (l * 20h); where l = 0 to 1" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value." line.long 0x14 "CPSW_GENF0_PPM_HIGH_REG_L,Time Stamp Generate Function (GENF0) PPM High Value (upper 32-bits). Offset = 0003D0F4h + (l * 20h); where l = 0 to 1" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value." line.long 0x18 "CPSW_GENF0_NUDGE_REG_L,Time Stamp Generate Function (GENF0) Nudge Value Registers. Offset = 0003D0F8h + (l * 20h); where l = 0 to 1" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value." group.long 0x3D100++0x1B line.long 0x0 "CPSW_GENF1_COMP_LOW_REG,Time Stamp Generate Function (GENF1) Comparison Low Value." hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function (GENF1) Comparison Low Value (lower 32-bits)." line.long 0x4 "CPSW_GENF1_COMP_HIGH_REG,Time Stamp Generate Function (GENF1) Comparison high Value (upper 32-bits)." hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function (GENF1) Comparison High Value (upper 32-bits)." line.long 0x8 "CPSW_GENF1_CONTROL_REG,Time Stamp Generate Function (GENF1) Control Register." hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function (GENF1) Polarity Invert." "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function (GENF1) PPM Direction." "0,1" line.long 0xC "CPSW_GENF1_LENGTH_REG,Time Stamp Generate Function (GENF1) Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function (GENF1) Length Value" line.long 0x10 "CPSW_GENF1_PPM_LOW_REG,Time Stamp Generate Function (GENF1) PPM Low Value (lower 32-bits)." hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function (GENF1) PPM Low Value" line.long 0x14 "CPSW_GENF1_PPM_HIGH_REG,Time Stamp Generate Function (GENF1) PPM High Value (upper 32-bits)." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function (GENF1) PPM High Value." line.long 0x18 "CPSW_GENF1_NUDGE_REG,Time Stamp Generate Function (GENF1) Nudge Value." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function (GENF1) Nudge Value ." group.long 0x3D200++0x1B line.long 0x0 "CPSW_ESTF1_COMP_LOW_REG,Time Stamp Generate Function (ESTF1) Comparison Low Value." hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function (ESTF1) Comparison Low Value (lower 32-bits)." line.long 0x4 "CPSW_ESTF1_COMP_HIGH_REG,Time Stamp Generate Function (ESTF1) Comparison high Value (upper 32-bits)." hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function (ESTF1) Comparison High Value (upper 32-bits)." line.long 0x8 "CPSW_ESTF1_CONTROL_REG,Time Stamp Generate Function (ESTF1) Control Register." hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function (ESTF1) Polarity Invert." "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function (ESTF1) PPM Direction." "0,1" line.long 0xC "CPSW_ESTF1_LENGTH_REG,Time Stamp Generate Function (ESTF1) Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function (ESTF1) Length Value" line.long 0x10 "CPSW_ESTF1_PPM_LOW_REG,Time Stamp Generate Function (ESTF1) PPM Low Value (lower 32-bits)." hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function (ESTF1) PPM Low Value" line.long 0x14 "CPSW_ESTF1_PPM_HIGH_REG,Time Stamp Generate Function (ESTF1) PPM High Value (upper 32-bits)." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function (ESTF1) PPM High Value." line.long 0x18 "CPSW_ESTF1_NUDGE_REG,Time Stamp Generate Function (ESTF1) Nudge Value." hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function (ESTF1) Nudge Value ." tree.end tree "MCU_CPSW0_NUSS_MDIO" base ad:0x46000000 rgroup.long 0xF00++0x3 line.long 0x0 "CPSW_MDIO_VERSION_REG,MDIO Version Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0xF04++0x7 line.long 0x0 "CPSW_MDIO_CONTROL_REG,MDIO Control Register" rbitfld.long 0x0 31. "IDLE,MDIO state machine IDLE." "0,1" bitfld.long 0x0 30. "ENABLE,Enable control." "0,1" bitfld.long 0x0 29. "RESERVED" "0,1" hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel." newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "PREAMBLE,Preamble disable." "0,1" bitfld.long 0x0 19. "FAULT,Fault indicator." "0,1" bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable." "0,1" newline bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable." "0,1" bitfld.long 0x0 16. "RESERVED" "0,1" hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock Divider." line.long 0x4 "CPSW_MDIO_ALIVE_REG,MDIO Alive Register" hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO Alive." rgroup.long 0xF0C++0x3 line.long 0x0 "CPSW_MDIO_LINK_REG,MDIO Link Register" hexmask.long 0x0 0.--31. 1. "LINK,MDIO Link state." group.long 0xF10++0x37 line.long 0x0 "CPSW_MDIO_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value." "0,1,2,3" line.long 0x4 "CPSW_MDIO_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value." "0,1,2,3" line.long 0x8 "CPSW_MDIO_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set." "0,1" line.long 0xC "CPSW_MDIO_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear." "0,1" line.long 0x10 "CPSW_MDIO_USER_INT_RAW_REG,MDIO User Interrupt Raw Register" hexmask.long 0x10 2.--31. 1. "RESERVED" bitfld.long 0x10 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively." "0,1,2,3" line.long 0x14 "CPSW_MDIO_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register" hexmask.long 0x14 2.--31. 1. "RESERVED" bitfld.long 0x14 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively." "0,1,2,3" line.long 0x18 "CPSW_MDIO_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register" hexmask.long 0x18 2.--31. 1. "RESERVED" bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for" "0,1,2,3" line.long 0x1C "CPSW_MDIO_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register" hexmask.long 0x1C 2.--31. 1. "RESERVED" bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user command complete interrupt mask clear for" "0,1,2,3" line.long 0x20 "CPSW_MDIO_MANUAL_IF_REG,MDIO Manual Interface Register" hexmask.long 0x20 3.--31. 1. "RESERVED" bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output." "0,1" bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable." "0,1" bitfld.long 0x20 0. "MDIO_PIN,MDIO_Pin Value." "0,1" line.long 0x24 "CPSW_MDIO_POLL_REG,MDIO Poll Register" bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode." "0,1" bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode." "0,1" hexmask.long.tbyte 0x24 8.--29. 1. "RESERVED" hexmask.long.byte 0x24 0.--7. 1. "IPG,Polling Inter Packet Gap Value." line.long 0x28 "CPSW_MDIO_POLL_EN_REG,MDIO Poll Enable Register" hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable." line.long 0x2C "CPSW_MDIO_CLAUS45_REG,MDIO Clause45 Enable Register" hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO clause 45 mode." line.long 0x30 "CPSW_MDIO_USER_ADDR0_REG,MDIO Address 0 Register" hexmask.long.word 0x30 16.--31. 1. "RESERVED" hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO User Address 0." line.long 0x34 "CPSW_MDIO_USER_ADDR1_REG,MDIO Address 1 Register" hexmask.long.word 0x34 16.--31. 1. "RESERVED" hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO User Address 1." group.long 0xF80++0x7 line.long 0x0 "CPSW_MDIO_USER_ACCESS_REG_k,MDIO User Access Register Offset = F80h + (k * 8h); where k = 0h to 1h" bitfld.long 0x0 31. "GO,Go." "0,1" bitfld.long 0x0 30. "WRITE,Write enable." "0,1" bitfld.long 0x0 29. "ACK,Acknowledge." "0,1" bitfld.long 0x0 26.--28. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 21.--25. 1. "REGADR,Register address." hexmask.long.byte 0x0 16.--20. 1. "PHYADR,PHY address." hexmask.long.word 0x0 0.--15. 1. "DATA,User data." line.long 0x4 "CPSW_MDIO_USER_PHY_SEL_REG_k,MDIO User PHY Select Register Offset = F84h + (k * 8h); where k = 0h to 1h" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "LINKSEL,Link status determination select." "0,1" bitfld.long 0x4 6. "LINKINT_ENABLE,Link change interrupt enable." "0,1" bitfld.long 0x4 5. "RESERVED" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "PHYADR_MON,PHY address whose link status is monitored." tree.end tree "MCU_CPSW0_NUSS_RAM" base ad:0x46000000 group.long 0x32000++0x3 line.long 0x0 "CPSW_FETCH_LOC_y,These are the RAM locations for one Ethernet port. Offset = 00032000h + (y * 4h); where y = 0h to 7Fh" hexmask.long.word 0x0 22.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location" tree.end tree "MCU_CPSW0_NUSS_SGMII" base ad:0x46000000 rgroup.long 0x100++0x3 line.long 0x0 "CPSW_SGMII_IDVER_REG,SGMII IDVER register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Module value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x104++0x3 line.long 0x0 "CPSW_SGMII_SOFT_RESET_REG,SGMII Soft Reset Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "RT_SOFT_RESET,Transmit and Receive Software Reset.This bit is intended to be used when changing between loopback mode and normal mode of operation." "0,1" bitfld.long 0x0 0. "SOFT_RESET,Software Reset." "0,1" group.long 0x110++0x3 line.long 0x0 "CPSW_SGMII_CONTROL_REG,SGMII Control Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "TEST_PATTERN_EN,Test Pattern Enable." "0,1" bitfld.long 0x0 5. "MASTER,Master Mode." "0,1" bitfld.long 0x0 4. "LOOPBACK,Loopback mode." "0,1" newline bitfld.long 0x0 3. "MR_NP_LOADED,Next Page Loaded." "0,1" bitfld.long 0x0 2. "FAST_LINK_TIMER,Fast Link Timer." "0,1" bitfld.long 0x0 1. "MR_AN_RESTART,Auto Negotiation Restart." "0,1" bitfld.long 0x0 0. "MR_AN_ENABLE,Auto Negotiation Enable." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "CPSW_SGMII_STATUS_REG,SGMII Status Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "FIB_SIG_DETECT,Fiber Signal Detect." "0,1" bitfld.long 0x0 4. "LOCK,Lock." "0,1" bitfld.long 0x0 3. "MR_PAGE_RX,Next Page Received." "0,1" newline bitfld.long 0x0 2. "MR_AN_COMPLETE,Auto negotiation complete." "0,1" bitfld.long 0x0 1. "AN_ERROR,Auto negotiation error." "0,1" bitfld.long 0x0 0. "LINK,Link indicator." "0,1" group.long 0x118++0x7 line.long 0x0 "CPSW_SGMII_MR_ADV_ABILITY_REG,SGMII MR Advertized Ability Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "MR_ADV_ABILITY,Advertised Ability." line.long 0x4 "CPSW_SGMII_MR_NP_TX_REG,SGMII Next Pate Transmit Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "MR_NP_TX,Next Page Transmit." rgroup.long 0x120++0x7 line.long 0x0 "CPSW_SGMII_MR_LP_ADV_ABILITY_REG,SGMII Link Partner Advertized Ability Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "MR_LP_ADV_ABILITY,Link Partner Advertised Ability." line.long 0x4 "CPSW_SGMII_MR_LP_NP_RX_REG,SGMII Link Partner Next Page Receive Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received." group.long 0x130++0xB line.long 0x0 "CPSW_SGMII_TX_CFG_REG,SGMII Transmit Configuration Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0x0 0.--31. 1. "TX_CFG,Transmit configuration register output" line.long 0x4 "CPSW_SGMII_RX_CFG_REG,SGMII Receive Configuration Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0x4 0.--31. 1. "RX_CFG,Receive configuration register output" line.long 0x8 "CPSW_SGMII_AUX_CFG_REG,SGMII Auxiliary Configuration Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0x8 0.--31. 1. "AUX_CFG,Auxiliary configuration register output" group.long 0x140++0x7 line.long 0x0 "CPSW_SGMII_DIAG_CLEAR_REG,SGMII Diagnostics Clear Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "DIAG_CLEAR,Diagnostics Clear." "0,1" line.long 0x4 "CPSW_SGMII_DIAG_CONTROL_REG,SGMII Diagnostics Control Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0x4 7.--31. 1. "RESERVED" bitfld.long 0x4 4.--6. "DIAG_SM_SEL,Diagnostic Select." "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "RESERVED" "0,1,2,3" bitfld.long 0x4 0.--1. "DIAG_EDGE_SEL,Diagnostis Hold Signals Edge Select" "0,1,2,3" rgroup.long 0x148++0x3 line.long 0x0 "CPSW_SGMII_DIAG_STATUS_REG,SGMII Diagnostics Status Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "DIAG_STATUS,Diagnostics status" tree.end tree "MCU_CPSW0_NUSS_SS" base ad:0x46000000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_SS_CPSW_NUSS_IDVER_REG,CPSW_NUSS ID Version Register" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x4++0xF line.long 0x0 "CPSW_SS_SYNCE_COUNT_REG,CPSW_NUSS SYNCE Count Register" hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,Sync E Count Value" line.long 0x4 "CPSW_SS_SYNCE_MUX_REG,CPSW_NUSS Synce Mux Register" hexmask.long 0x4 6.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "SYNCE_SEL,Sync E Select Value" line.long 0x8 "CPSW_SS_CONTROL_REG,CPSW_NUSS Control Register" hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode:0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW 1=The low power indicate state does not gate the clock to the CPSW" "0: The low power indicate state includes gating off..,1: The low power indicate state does not gate the.." newline bitfld.long 0x8 0. "EEE_EN,Energy Efficient Ethernet Enable:0=EEE is disabled 1=EEE is enabled" "0: EEE is disabled,1: EEE is enabled" line.long 0xC "CPSW_SS_SGMII_MODE_REG,CPSW_NUSS SyncE Mux Register Note: SGMII mode is not supported on the 2-port CPSW module." hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "SYNCE_SEL,SGMII_MODE InputNote: SGMII mode is not supported on the 2-port CPSW module." "0,1" rgroup.long 0x18++0x7 line.long 0x0 "CPSW_SS_RGMII_STATUS_REG,CPSW_NUSS RGMII Status Register" hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "FULLDUPLEX,Rgmii full dulex:0=Half-duplex 1=Full-duplex" "0: Half-duplex,1: Full-duplex" newline bitfld.long 0x0 1.--2. "SPEED,Rgmii speed:00=10Mbps 01=100Mbps 10=1000Mbps 11=reserved" "0: 10Mbps,1: 100Mbps,?,?" bitfld.long 0x0 0. "LINK,Rgmii link indicator:0=Link is down 1=Link is up" "0: Link is down,1: Link is up" line.long 0x4 "CPSW_SS_SUBSSYSTEM_STATUS_REG,CPSW_NUSS Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1" tree.end tree "MCU_CPSW0_NUSS_STAT0" base ad:0x46000000 group.long 0x3A000++0xB line.long 0x0 "CPSW_STAT0_RXGOODFRAMES,The total number of good frames received on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Had a length of 64 to.." hexmask.long 0x0 0.--31. 1. "COUNT,Total number of good frames received." line.long 0x4 "CPSW_STAT0_RXBROADCASTFRAMES,The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF- Had a length of [13-0] RX_MAXLEN.." hexmask.long 0x4 0.--31. 1. "COUNT,Total number of good broadcast frames received." line.long 0x8 "CPSW_STAT0_RXMULTICASTFRAMES,The total number of good multicast frames received on the port. A good multicast frame is defined to be:- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF- Had a length of.." hexmask.long 0x8 0.--31. 1. "COUNT,Total number of good multicast frames received." group.long 0x3A010++0x3 line.long 0x0 "CPSW_STAT0_RXCRCERRORS,The total number of frames received on the port that experienced a CRC error. Such a frame:- Was any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Was of.." hexmask.long 0x0 0.--31. 1. "COUNT,Total number of CRC errors frames received." group.long 0x3A018++0x3 line.long 0x0 "CPSW_STAT0_RXOVERSIZEDFRAMES,The total number of oversized frames received on the port. An oversized frame is defined to be:- Was any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode-.." hexmask.long 0x0 0.--31. 1. "COUNT,Total number of oversized frames received." group.long 0x3A020++0x1F line.long 0x0 "CPSW_STAT0_RXUNDERSIZEDFRAMES,The total number of undersized frames received on the port. An undersized frame is defined to be:- Was any data frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Was less than.." hexmask.long 0x0 0.--31. 1. "COUNT,Total number of undersized frames received." line.long 0x4 "CPSW_STAT0_RXFRAGMENTS,The total number of frame fragments received on the port. A frame fragment is defined to be:- Any data frame (address matching does not matter)- Less than 64 bytes long- Having a CRC error. an alignment error. or a code error- Not.." hexmask.long 0x4 0.--31. 1. "COUNT,Total number of fragmented frames received." line.long 0x8 "CPSW_STAT0_ALE_DROP,Total number of frames dropped by the ALE." hexmask.long 0x8 0.--31. 1. "COUNT,Total number of frames dropped by the ALE." line.long 0xC "CPSW_STAT0_ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE." hexmask.long 0xC 0.--31. 1. "COUNT,Total number of overrun frames dropped by the ALE." line.long 0x10 "CPSW_STAT0_RXOCTETS,The total number of bytes in all good frames received on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Of length 64.." hexmask.long 0x10 0.--31. 1. "COUNT,Total number of received bytes in good frames" line.long 0x14 "CPSW_STAT0_TXGOODFRAMES,The total number of good frames received on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Any length- Had no.." hexmask.long 0x14 0.--31. 1. "COUNT,Total number of good frames transmitted" line.long 0x18 "CPSW_STAT0_TXBROADCASTFRAMES,The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF- Any length- Had no late or excessive.." hexmask.long 0x18 0.--31. 1. "COUNT,Total number of good broadcast frames transmitted." line.long 0x1C "CPSW_STAT0_TXMULTICASTFRAMES,The total number of good multicast frames received on the port. A good multicast frame is defined to be:- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF- Any length- Had.." hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of good multicast frames transmitted." group.long 0x3A064++0x7B line.long 0x0 "CPSW_STAT0_TXOCTETS,The total number of bytes in all good frames transmitted on the port. A good frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Was any size- Had no late or.." hexmask.long 0x0 0.--31. 1. "COUNT,Total number of bytes in all good frames transmitted" line.long 0x4 "CPSW_STAT0_OCTETFRAMES64,The total number of 64-byte frames received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did not experience late.." hexmask.long 0x4 0.--31. 1. "COUNT,Total number of 64-byte frames received and transmitted" line.long 0x8 "CPSW_STAT0_OCTETFRAMES65T127,The total number of frames of size 65 to 127 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0x8 0.--31. 1. "COUNT,Total number of frames of size 65 to 127 bytes received and transmitted" line.long 0xC "CPSW_STAT0_OCTETFRAMES128T255,The total number of frames of size 128 to 255 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0xC 0.--31. 1. "COUNT,Total number of frames of size 128 to 255 bytes received and transmitted" line.long 0x10 "CPSW_STAT0_OCTETFRAMES256T511,The total number of frames of size 256 to 511 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0x10 0.--31. 1. "COUNT,Total number of frames of size 256 to 511 bytes received and transmitted." line.long 0x14 "CPSW_STAT0_OCTETFRAMES512T1023,The total number of frames of size 512 to 1023 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address-.." hexmask.long 0x14 0.--31. 1. "COUNT,Total number of frames of size 512 to 1023 bytes received and transmitted." line.long 0x18 "CPSW_STAT0_OCTETFRAMES1024TUP,The total number of frames of size 1024 to [13-0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast.." hexmask.long 0x18 0.--31. 1. "COUNT,Total number of frames of size 1024 to" line.long 0x1C "CPSW_STAT0_NETOCTETS,The total number of bytes of frame data received and transmitted on the port. Each frame counted:- was any data or MAC control frame destined for any unicast. broadcast or multicast address (address match does not matter)- Any length.." hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of bytes received and transmitted" line.long 0x20 "CPSW_STAT0_RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop." hexmask.long 0x20 0.--31. 1. "COUNT,Receive Bottom of FIFO Drop." line.long 0x24 "CPSW_STAT0_PORTMASK_DROP,Total number of dropped frames received due to portmask." hexmask.long 0x24 0.--31. 1. "COUNT,Total number of dropped frames received due to portmask." line.long 0x28 "CPSW_STAT0_RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop." hexmask.long 0x28 0.--31. 1. "COUNT,Receive Top of FIFO Drop." line.long 0x2C "CPSW_STAT0_ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting." hexmask.long 0x2C 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Rate Limiting." line.long 0x30 "CPSW_STAT0_ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress." hexmask.long 0x30 0.--31. 1. "COUNT,Total number of dropped frames due to ALE VID Ingress." line.long 0x34 "CPSW_STAT0_ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA." hexmask.long 0x34 0.--31. 1. "COUNT,Total number of dropped frames due to DA=SA." line.long 0x38 "CPSW_STAT0_ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode." hexmask.long 0x38 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Block Mode." line.long 0x3C "CPSW_STAT0_ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode." hexmask.long 0x3C 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Secure Mode." line.long 0x40 "CPSW_STAT0_ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication." hexmask.long 0x40 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Authentication." line.long 0x44 "CPSW_STAT0_ALE_UNKN_UNI,ALE Receive Unknown Unicast." hexmask.long 0x44 0.--31. 1. "COUNT,ALE Receive Unknown Unicast." line.long 0x48 "CPSW_STAT0_ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount." hexmask.long 0x48 0.--31. 1. "COUNT,ALE Receive Unknown Unicast Bytecount." line.long 0x4C "CPSW_STAT0_ALE_UNKN_MLT,ALE Receive Unknown Multicast." hexmask.long 0x4C 0.--31. 1. "COUNT,ALE Receive Unknown Multicast." line.long 0x50 "CPSW_STAT0_ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount." hexmask.long 0x50 0.--31. 1. "COUNT,ALE Receive Unknown Multicast Bytecount." line.long 0x54 "CPSW_STAT0_ALE_UNKN_BRD,ALE Receive Unknown Broadcast." hexmask.long 0x54 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast." line.long 0x58 "CPSW_STAT0_ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount." hexmask.long 0x58 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast Bytecount." line.long 0x5C "CPSW_STAT0_ALE_POL_MATCH,ALE Policer Matched." hexmask.long 0x5C 0.--31. 1. "COUNT,ALE Policer Matched." line.long 0x60 "CPSW_STAT0_ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red." hexmask.long 0x60 0.--31. 1. "COUNT,ALE Policer Matched and Condition Red." line.long 0x64 "CPSW_STAT0_ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow." hexmask.long 0x64 0.--31. 1. "COUNT,ALE Policer Matched and Condition Yellow." line.long 0x68 "CPSW_STAT0_ALE_MULT_SA_DROP,ALE Multicast Source Address Drop." hexmask.long 0x68 0.--31. 1. "COUNT,ALE Multicast Source Address drop." line.long 0x6C "CPSW_STAT0_ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop." hexmask.long 0x6C 0.--31. 1. "COUNT,ALE Dual VLAN drop." line.long 0x70 "CPSW_STAT0_ALE_LEN_ERROR_DROP,ALE Length Error Drop." hexmask.long 0x70 0.--31. 1. "COUNT,ALE Length Error drop." line.long 0x74 "CPSW_STAT0_ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop." hexmask.long 0x74 0.--31. 1. "COUNT,ALE Next Header drop." line.long 0x78 "CPSW_STAT0_ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop." hexmask.long 0x78 0.--31. 1. "COUNT,ALE IPV4 Fragment drop." group.long 0x3A140++0x17 line.long 0x0 "CPSW_STAT0_IET_RX_ASSEMBLY_ERROR_REG,IET Receive Assembly Error. Note: IET functionallity is not supported for MCU_CPSW0 Port 0." hexmask.long 0x0 0.--31. 1. "IET_RX_ASSEMBLY_ERROR,IET Receive Assembly ErrorNote: IET functionallity is not supported for MCU_CPSW0 Port 0." line.long 0x4 "CPSW_STAT0_IET_RX_ASSEMBLY_OK_REG,IET Receive Assembly Ok. Note: IET functionallity is not supported for MCU_CPSW0 Port 0." hexmask.long 0x4 0.--31. 1. "IET_RX_ASSEMBLY_OK,IET Receive Assembly Ok.Note: IET functionallity is not supported for MCU_CPSW0 Port 0." line.long 0x8 "CPSW_STAT0_IET_RX_SMD_ERROR_REG,IET Receive Smd Error. Note: IET functionallity is not supported for MCU_CPSW0 Port 0." hexmask.long 0x8 0.--31. 1. "IET_RX_SMD_ERROR,IET Receive Smd Error.Note: IET functionallity is not supported for MCU_CPSW0 Port 0." line.long 0xC "CPSW_STAT0_IET_RX_FRAG_REG,IET Receive Frag. Note: IET functionallity is not supported for MCU_CPSW0 Port 0." hexmask.long 0xC 0.--31. 1. "IET_RX_FRAG,IET Receive Frag.Note: IET functionallity is not supported for MCU_CPSW0 Port 0." line.long 0x10 "CPSW_STAT0_IET_TX_HOLD_REG,IET Transmit Hold. Note: IET functionallity is not supported for MCU_CPSW0 Port 0." hexmask.long 0x10 0.--31. 1. "IET_TX_HOLD,IET Transmit Hold.Note: IET functionallity is not supported for MCU_CPSW0 Port 0." line.long 0x14 "CPSW_STAT0_IET_TX_FRAG_REG,IET Transmit Frag. Note: IET functionallity is not supported for MCU_CPSW0 Port 0." hexmask.long 0x14 0.--31. 1. "IET_TX_FRAG,IET Transmit Frag.Note: IET functionallity is not supported for MCU_CPSW0 Port 0." group.long 0x3A17C++0x3 line.long 0x0 "CPSW_STAT0_TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error.Note: If there is a memorry protect error then this COUNT value will increment and issue a STAT_PEND0 interrupt when this bit field is non-zero.That is different from the other stats which only issue an interrupt.." tree.end tree "MCU_CPSW0_NUSS_STAT1" base ad:0x46000000 group.long 0x3A200++0xDF line.long 0x0 "CPSW_STAT1_RXGOODFRAMES,The total number of good frames received on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Had a length of 64 to.." hexmask.long 0x0 0.--31. 1. "COUNT,Total number of good frames received" line.long 0x4 "CPSW_STAT1_RXBROADCASTFRAMES,The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF- Had a length of [13-0] RX_MAXLEN.." hexmask.long 0x4 0.--31. 1. "COUNT,Total number of good broadcast frames received" line.long 0x8 "CPSW_STAT1_RXMULTICASTFRAMES,The total number of good multicast frames received on the port. A good multicast frame is defined to be:- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF- Had a length of.." hexmask.long 0x8 0.--31. 1. "COUNT,Total number of good multicast frames received" line.long 0xC "CPSW_STAT1_RXPAUSEFRAMES,The total number of IEEE 802.3X pause frames received by the port (whether acted upon or not). Such a frame:- Contained any unicast. broadcast. or multicast address- Contained the length/type field value 88.08 (hex) and the.." hexmask.long 0xC 0.--31. 1. "COUNT,Total number of pause frames received" line.long 0x10 "CPSW_STAT1_RXCRCERRORS,The total number of frames received on the port that experienced a CRC error. Such a frame:- Was any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Was of.." hexmask.long 0x10 0.--31. 1. "COUNT,Total number of CRC errors frames received." line.long 0x14 "CPSW_STAT1_RXALIGNCODEERRORS,The total number of frames received on the port that experienced an alignment error or code error. Such a frame:- Was any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to.." hexmask.long 0x14 0.--31. 1. "COUNT,Total number of alignment/code errors received" line.long 0x18 "CPSW_STAT1_RXOVERSIZEDFRAMES,The total number of oversized frames received on the port. An oversized frame is defined to be:- Was any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode-.." hexmask.long 0x18 0.--31. 1. "COUNT,Total number of oversized frames received" line.long 0x1C "CPSW_STAT1_RXJABBERFRAMES,The total number of jabber frames received on the port. A jabber frame:- Was any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Was greater than [13-0].." hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of jabber frames received." line.long 0x20 "CPSW_STAT1_RXUNDERSIZEDFRAMES,The total number of undersized frames received on the port. An undersized frame is defined to be:- Was any data frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Was less than.." hexmask.long 0x20 0.--31. 1. "COUNT,Total number of undersized frames received" line.long 0x24 "CPSW_STAT1_RXFRAGMENTS,The total number of frame fragments received on the port. A frame fragment is defined to be:- Any data frame (address matching does not matter)- Less than 64 bytes long- Having a CRC error. an alignment error. or a code error- Not.." hexmask.long 0x24 0.--31. 1. "COUNT,Total number of fragmented frames received." line.long 0x28 "CPSW_STAT1_ALE_DROP,Total number of frames dropped by the ALE." hexmask.long 0x28 0.--31. 1. "COUNT,Total number of frames dropped by the ALE." line.long 0x2C "CPSW_STAT1_ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE." hexmask.long 0x2C 0.--31. 1. "COUNT,Total number of overrun frames dropped by the ALE" line.long 0x30 "CPSW_STAT1_RXOCTETS,The total number of bytes in all good frames received on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Of length 64.." hexmask.long 0x30 0.--31. 1. "COUNT,Total number of received bytes in good frames" line.long 0x34 "CPSW_STAT1_TXGOODFRAMES,The total number of good frames received on the port. A good frame is defined to be:- Any data or MAC control frame which matched a unicast. broadcast or multicast address. or matched due to promiscuous mode- Any length- Had no.." hexmask.long 0x34 0.--31. 1. "COUNT,Total number of good frames transmitted" line.long 0x38 "CPSW_STAT1_TXBROADCASTFRAMES,The total number of good broadcast frames received on the port. A good broadcast frame is defined to be:- Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF- Any length- Had no late or excessive.." hexmask.long 0x38 0.--31. 1. "COUNT,Total number of good broadcast frames transmitted" line.long 0x3C "CPSW_STAT1_TXMULTICASTFRAMES,The total number of good multicast frames received on the port. A good multicast frame is defined to be:- Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF- Any length- Had.." hexmask.long 0x3C 0.--31. 1. "COUNT,Total number of good multicast frames transmitted" line.long 0x40 "CPSW_STAT1_TXPAUSEFRAMES,This statistic indicates the number of IEEE 802.3X pause frames transmitted by the port. Pause frames cannot underrun or contain a CRC error because they are created in the transmitting MAC. so these error conditions have no.." hexmask.long 0x40 0.--31. 1. "COUNT,Total number of pause frames transmitted" line.long 0x44 "CPSW_STAT1_TXDEFERREDFRAMES,The total number of frames transmitted on the port that first experienced deferment. Such a frame:- Was any data or MAC control frame destined for any unicast. broadcast or multicast address- Was any size- Had no carrier loss.." hexmask.long 0x44 0.--31. 1. "COUNT,Total number of deferred frames transmitted" line.long 0x48 "CPSW_STAT1_TXCOLLISIONFRAMES,This statistic records the total number of times that the port experienced a collision. Collisions occur under two circumstances.1. When a transmit data or MAC control frame:- Was destined for any unicast. broadcast or.." hexmask.long 0x48 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a collision" line.long 0x4C "CPSW_STAT1_TXSINGLECOLLFRAMES,The total number of frames transmitted on the port that experienced exactly one collision. Such a frame:- Was any data or MAC control frame destined for any unicast. broadcast or multicast address- Was any size- Had no.." hexmask.long 0x4C 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a single collision" line.long 0x50 "CPSW_STAT1_TXMULTCOLLFRAMES,The total number of frames transmitted on the port that experienced multiple collisions. Such a frame:- Was any data or MAC control frame destined for any unicast. broadcast or multicast address- Was any size- Had no carrier.." hexmask.long 0x50 0.--31. 1. "COUNT,Total number of transmitted frames experiencing multiple collisions" line.long 0x54 "CPSW_STAT1_TXEXCESSIVECOLLISIONS,The total number of frames for which transmission was abandoned due to excessive collisions. Such a frame:- Was any data or MAC control frame destined for any unicast. broadcast or multicast address- Was any size- Had no.." hexmask.long 0x54 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to excessive collisions" line.long 0x58 "CPSW_STAT1_TXLATECOLLISIONS,The total number of frames on the port for which transmission was abandoned because they experienced a late collision. Such a frame:- Was any data or MAC control frame destined for any unicast. broadcast or multicast address-.." hexmask.long 0x58 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to a late collision" line.long 0x5C "CPSW_STAT1_RXIPGERROR,Total number of receive inter-packet gap errors (10G only)." hexmask.long 0x5C 0.--31. 1. "COUNT,Total number of receive inter-packet gap errors (10G only)" line.long 0x60 "CPSW_STAT1_TXCARRIERSENSEERRORS,The total number of frames received on the port that had a middle of frame (MOF) overrun. MOF overrun frame is defined to be:- Was any data or MAC control frame destined for any unicast. broadcast or multicast address- Was.." hexmask.long 0x60 0.--31. 1. "COUNT,Total number of transmitted frames that experienced a carrier loss" line.long 0x64 "CPSW_STAT1_TXOCTETS,The total number of bytes in all good frames transmitted on the port. A good frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Was any size- Had no late or.." hexmask.long 0x64 0.--31. 1. "COUNT,Total number of bytes in all good frames transmitted" line.long 0x68 "CPSW_STAT1_OCTETFRAMES64,The total number of 64-byte frames received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did not experience late.." hexmask.long 0x68 0.--31. 1. "COUNT,Total number of 64-byte frames received and transmitted" line.long 0x6C "CPSW_STAT1_OCTETFRAMES65T127,The total number of frames of size 65 to 127 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0x6C 0.--31. 1. "COUNT,Total number of frames of size 65 to 127 bytes received and transmitted" line.long 0x70 "CPSW_STAT1_OCTETFRAMES128T255,The total number of frames of size 128 to 255 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0x70 0.--31. 1. "COUNT,Total number of frames of size 128 to 255 bytes received and transmitted" line.long 0x74 "CPSW_STAT1_OCTETFRAMES256T511,The total number of frames of size 256 to 511 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address- Did.." hexmask.long 0x74 0.--31. 1. "COUNT,Total number of frames of size 256 to 511 bytes received and transmitted" line.long 0x78 "CPSW_STAT1_OCTETFRAMES512T1023,The total number of frames of size 512 to 1023 bytes received and transmitted on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast or multicast address-.." hexmask.long 0x78 0.--31. 1. "COUNT,Total number of frames of size 512 to 1023 bytes received and transmitted" line.long 0x7C "CPSW_STAT1_OCTETFRAMES1024TUP,The total number of frames of size 1024 to [13-0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port. Such a frame is defined to be:- Any data or MAC control frame which was destined for any unicast. broadcast.." hexmask.long 0x7C 0.--31. 1. "COUNT,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted" line.long 0x80 "CPSW_STAT1_NETOCTETS,The total number of bytes of frame data received and transmitted on the port. Each frame counted:- was any data or MAC control frame destined for any unicast. broadcast or multicast address (address match does not matter)- Any length.." hexmask.long 0x80 0.--31. 1. "COUNT,Total number of bytes received and transmitted" line.long 0x84 "CPSW_STAT1_RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop." hexmask.long 0x84 0.--31. 1. "COUNT,Receive Bottom of FIFO Drop." line.long 0x88 "CPSW_STAT1_PORTMASK_DROP,Total number of dropped frames received due to portmask." hexmask.long 0x88 0.--31. 1. "COUNT,Total number of dropped frames received due to portmask." line.long 0x8C "CPSW_STAT1_RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop." hexmask.long 0x8C 0.--31. 1. "COUNT,Receive Top of FIFO Drop." line.long 0x90 "CPSW_STAT1_ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting." hexmask.long 0x90 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Rate Limiting." line.long 0x94 "CPSW_STAT1_ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress." hexmask.long 0x94 0.--31. 1. "COUNT,Total number of dropped frames due to ALE VID Ingress." line.long 0x98 "CPSW_STAT1_ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA." hexmask.long 0x98 0.--31. 1. "COUNT,Total number of dropped frames due to DA=SA." line.long 0x9C "CPSW_STAT1_ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode." hexmask.long 0x9C 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Block Mode." line.long 0xA0 "CPSW_STAT1_ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode." hexmask.long 0xA0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Secure Mode." line.long 0xA4 "CPSW_STAT1_ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication." hexmask.long 0xA4 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Authentication." line.long 0xA8 "CPSW_STAT1_ALE_UNKN_UNI,ALE Receive Unknown Unicast." hexmask.long 0xA8 0.--31. 1. "COUNT,ALE Receive Unknown Unicast." line.long 0xAC "CPSW_STAT1_ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount." hexmask.long 0xAC 0.--31. 1. "COUNT,ALE Receive Unknown Unicast Bytecount." line.long 0xB0 "CPSW_STAT1_ALE_UNKN_MLT,ALE Receive Unknown Multicast." hexmask.long 0xB0 0.--31. 1. "COUNT,ALE Receive Unknown Multicast." line.long 0xB4 "CPSW_STAT1_ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount." hexmask.long 0xB4 0.--31. 1. "COUNT,ALE Receive Unknown Multicast Bytecount." line.long 0xB8 "CPSW_STAT1_ALE_UNKN_BRD,ALE Receive Unknown Broadcast." hexmask.long 0xB8 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast." line.long 0xBC "CPSW_STAT1_ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount." hexmask.long 0xBC 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast Bytecount." line.long 0xC0 "CPSW_STAT1_ALE_POL_MATCH,ALE Policer Matched." hexmask.long 0xC0 0.--31. 1. "COUNT,ALE Policer Matched." line.long 0xC4 "CPSW_STAT1_ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red." hexmask.long 0xC4 0.--31. 1. "COUNT,ALE Policer Matched and Condition Red." line.long 0xC8 "CPSW_STAT1_ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow." hexmask.long 0xC8 0.--31. 1. "COUNT,ALE Policer Matched and Condition Yellow." line.long 0xCC "CPSW_STAT1_ALE_MULT_SA_DROP,ALE Multicast Source Address Drop" hexmask.long 0xCC 0.--31. 1. "COUNT,ALE Multicast Source Address drop" line.long 0xD0 "CPSW_STAT1_ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop" hexmask.long 0xD0 0.--31. 1. "COUNT,ALE Dual VLAN drop" line.long 0xD4 "CPSW_STAT1_ALE_LEN_ERROR_DROP,ALE Length Error Drop" hexmask.long 0xD4 0.--31. 1. "COUNT,ALE Length Error drop" line.long 0xD8 "CPSW_STAT1_ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop" hexmask.long 0xD8 0.--31. 1. "COUNT,ALE Next Header drop" line.long 0xDC "CPSW_STAT1_ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop" hexmask.long 0xDC 0.--31. 1. "COUNT,ALE IPV4 Fragment drop" group.long 0x3A340++0x17 line.long 0x0 "CPSW_STAT1_IET_RX_ASSEMBLY_ERROR_REG,IET Receive Assembly Error" hexmask.long 0x0 0.--31. 1. "IET_RX_ASSEMBLY_ERROR,IET Receive Assembly Error" line.long 0x4 "CPSW_STAT1_IET_RX_ASSEMBLY_OK_REG,IET Receive Assembly Ok" hexmask.long 0x4 0.--31. 1. "IET_RX_ASSEMBLY_OK,IET Receive Assembly Ok" line.long 0x8 "CPSW_STAT1_IET_RX_SMD_ERROR_REG,IET Receive Smd Error" hexmask.long 0x8 0.--31. 1. "IET_RX_SMD_ERROR,IET Receive Smd Error" line.long 0xC "CPSW_STAT1_IET_RX_FRAG_REG,IET Receive Frag" hexmask.long 0xC 0.--31. 1. "IET_RX_FRAG,IET Receive Frag" line.long 0x10 "CPSW_STAT1_IET_TX_HOLD_REG,IET Transmit Hold" hexmask.long 0x10 0.--31. 1. "IET_TX_HOLD,IET Transmit Hold" line.long 0x14 "CPSW_STAT1_IET_TX_FRAG_REG,IET Transmit Frag" hexmask.long 0x14 0.--31. 1. "IET_TX_FRAG,IET Transmit Frag" group.long 0x3A37C++0x7 line.long 0x0 "CPSW_STAT1_TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error." line.long 0x4 "CPSW_STAT1_ENET_PN_TX_PRI_REG_y,ENET Port n PRIORITY N Packet Count. Offset = 0003A380h + (y * 4h); where y = 0h to 7h." hexmask.long 0x4 0.--31. 1. "PN_TX_PRIN,Enet Port n Priority N Packet Count." group.long 0x3A3A0++0x3 line.long 0x0 "CPSW_STAT1_ENET_PN_TX_PRI_BCNT_REG_y,ENET Port n PRIORITY N Packet Byte Count. Offset = 0003A3A0h + (y * 4h); where y = 0h to 7h." hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_BCNT,ENET Port n PRIORITY N Packet Byte Count." group.long 0x3A3C0++0x3 line.long 0x0 "CPSW_STAT1_ENET_PN_TX_PRI_DROP_REG_y,ENET Port n PRIORITY N Packet Drop Count. Offset = 0003A3C0h + (y * 4h); where y = 0h to 7h." hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP,ENET Port n PRIORITY N Packet Drop Count." group.long 0x3A3E0++0x3 line.long 0x0 "CPSW_STAT1_ENET_PN_TX_PRI_DROP_BCNT_REG_y,ENET Port n PRIORITY N Packet Drop Byte Count. Offset = 0003A3E0h + (y * 4h); where y = 0h to 7h." hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP_BCNT,ENET Port n PRIORITY N Packet Drop Byte Count." tree.end tree.end tree "MCU_CTRL_MMR0_CFG0" base ad:0x40F00000 rgroup.long 0x2000++0x3 line.long 0x0 "CTRLMMR_MCU_PID" bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module functional identifier - CTRL MMR" newline hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL revision number" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision number" rgroup.long 0x2008++0x3 line.long 0x0 "CTRLMMR_MCU_MMR_CFG1" bitfld.long 0x0 31. "PROXY_EN,Proxy addressing enabled" "0,1" hexmask.long.tbyte 0x0 8.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "PARTITIONS,Indicates present partitions" group.long 0x2100++0x7 line.long 0x0 "CTRLMMR_MCU_IPC_SET0" hexmask.long 0x0 4.--31. 1. "IPC_SRC_SET,Read returns current value" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "IPC_SET,Read returns 0" "0,1" line.long 0x4 "CTRLMMR_MCU_IPC_SET1" hexmask.long 0x4 4.--31. 1. "IPC_SRC_SET,Read returns current value" rbitfld.long 0x4 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "IPC_SET,Read returns 0" "0,1" group.long 0x2120++0x3 line.long 0x0 "CTRLMMR_MCU_IPC_SET8" hexmask.long 0x0 4.--31. 1. "IPC_SRC_SET,Read returns current value" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "IPC_SET,Read returns 0" "0,1" group.long 0x2180++0x7 line.long 0x0 "CTRLMMR_MCU_IPC_CLR0" hexmask.long 0x0 4.--31. 1. "IPC_SRC_CLR,Read returns current value" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "IPC_CLR,Read returns current value" "0,1" line.long 0x4 "CTRLMMR_MCU_IPC_CLR1" hexmask.long 0x4 4.--31. 1. "IPC_SRC_CLR,Read returns current value" rbitfld.long 0x4 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "IPC_CLR,Read returns current value" "0,1" group.long 0x21A0++0x3 line.long 0x0 "CTRLMMR_MCU_IPC_CLR8" hexmask.long 0x0 4.--31. 1. "IPC_SRC_CLR,Read returns current value" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "IPC_CLR,Read returns current value" "0,1" group.long 0x2200++0x7 line.long 0x0 "CTRLMMR_MCU_MAC_ID0" hexmask.long 0x0 0.--31. 1. "MACID_LO,32 lsbs of MAC address" line.long 0x4 "CTRLMMR_MCU_MAC_ID1" hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "MACID_HI,16 msbs of MAC address" group.long 0x3008++0x1B line.long 0x0 "CTRLMMR_MCU_LOCK0_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_MCU_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" line.long 0x8 "CTRLMMR_MCU_INTR_RAW_STAT" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "PROXY_ERR,Proxy violation occurred (attempt to write a Proxy1 claimed register through its Proxy0 address)" "0,1" bitfld.long 0x8 2. "LOCK_ERR,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Address violation occurred (attempt to read or write an invalid register address)" "0,1" bitfld.long 0x8 0. "PROT_ERR,Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)" "0,1" line.long 0xC "CTRLMMR_MCU_INTR_STAT_CLR" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 3. "EN_PROXY_ERR,Enabled proxy interrupt event status" "0,1" bitfld.long 0xC 2. "EN_LOCK_ERR,Enabled lock interrupt event status" "0,1" newline bitfld.long 0xC 1. "EN_ADDR_ERR,Enabled address interrupt event status" "0,1" bitfld.long 0xC 0. "EN_PROT_ERR,Enabled protection interrupt event status" "0,1" line.long 0x10 "CTRLMMR_MCU_INTR_EN_SET" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 3. "PROXY_ERR_EN_SET,Proxy interrupt enable" "0,1" bitfld.long 0x10 2. "LOCK_ERR_EN_SET,Lock interrupt enable" "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_SET,Address interrupt enable" "0,1" bitfld.long 0x10 0. "PROT_ERR_EN_SET,Protection interrupt enable" "0,1" line.long 0x14 "CTRLMMR_MCU_INTR_EN_CLR" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy interrupt disable" "0,1" bitfld.long 0x14 2. "LOCK_ERR_EN_CLR,Lock interrupt disable" "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Address interrupt disable" "0,1" bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection interrupt disable" "0,1" line.long 0x18 "CTRLMMR_MCU_EOI" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x18 0.--7. 1. "VECTOR" rgroup.long 0x3024++0xB line.long 0x0 "CTRLMMR_MCU_FAULT_ADDR" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address of the faulted access" line.long 0x4 "CTRLMMR_MCU_FAULT_TYPE" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--5. 1. "TYPE,Type of access which faulted 0h - No fault 1h - User execute access 2h - User write access 4h - User read access 8h - Supervisor execute access 10h - Supervisor write access 20h - Supervisor read access" line.long 0x8 "CTRLMMR_MCU_FAULT_ATTR" hexmask.long.word 0x8 20.--31. 1. "XID,Transaction ID" hexmask.long.word 0x8 8.--19. 1. "ROUTEID,Route ID" hexmask.long.byte 0x8 0.--7. 1. "PRIVID,Privilege ID" group.long 0x3030++0x3 line.long 0x0 "CTRLMMR_MCU_FAULT_CLR" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CLEAR,Fault clear" "0,1" group.long 0x3100++0x13 line.long 0x0 "CTRLMMR_MCU_P0_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_MCU_P0_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_MCU_P0_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_MCU_P0_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_MCU_P0_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x6030++0x3 line.long 0x0 "CTRLMMR_MCU_MSMC_CFG" bitfld.long 0x0 31. "DDR_ASSYM_EMIF_SEL,In the asymmetric interleave controls which EMIF controller implements the separated range of the memory window" "0,1" rbitfld.long 0x0 30. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 24.--29. 1. "DDR_INTRLV_GRAN,Defines the size of each memory stripe for interleaved memory space" newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "DDR_INTRLV_SIZE,Defines the memory window size for the interleaved region starting at the bottom of the external memory address range." hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "MEM_SIZE,Indicates the size of MSMC shared SRAM/Cache 0h - 0.0 MB 1h - 0.25 MB 2h - 0.5 MB 3h - 0.75 MB 4h - 1.0 MB 5h - 1.25 MB 6h - 1.5 MB 7h - 1.75 MB 8h - 2.0 MB" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "MEM_INIT_DIS,Disables MSMC SRAM initialization (Data Cache Tags and Snoop Filters). This is required for proper initial ECC initialization." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED,Reserved" group.long 0x6040++0x3 line.long 0x0 "CTRLMMR_MCU_ENET_CTRL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "RGMII_ID_MODE,Port1 RGMII internal transmit delay selection" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MODE_SEL,Selects Ethernet switch Port1 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII (not supported)" "0,1,2,3" group.long 0x6060++0x3 line.long 0x0 "CTRLMMR_MCU_SPI1_CTRL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "SPI1_LINKDIS,Disables direct connection of MCU_SPI1 to SPI3 0h - MCU_SPI1 is tied as a slave to SPI3. MCU_SPI1 CLK DATA1 and CS0 are driven from SPI3 DATA OUT drives SPI3 DATA0 1h - MCU_SPI1 is NOT tied as a slave to SPI3. MCU_SPI1 CLK DATA0 DATA1.." "0,1" group.long 0x6070++0x7 line.long 0x0 "CTRLMMR_MCU_I3C0_CTRL0" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" hexmask.long.word 0x0 16.--30. 1. "PID_MFR_ID,Manufacturer ID" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "ROLE,Master Role" "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "PID_INSTANCE,Provisional ID Instance. This input corresponds to bits[15:12] of the Provisional ID. It is intended to provide a way of differentiating several I3C devices if there would be no other way to have each manufactured device have a unique.." line.long 0x4 "CTRLMMR_MCU_I3C0_CTRL1" hexmask.long.byte 0x4 24.--31. 1. "BUS_AVAIL_TIME,Indicates the number of pclk cycles in the Bus Available condition" hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--17. 1. "BUS_IDLE_TIME,Indicates the number of pclk cycles in the Bus Idle condition" group.long 0x6080++0x7 line.long 0x0 "CTRLMMR_MCU_I2C0_CTRL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "HS_MCS_EN,HS Mode master current source enable." "0,1" line.long 0x4 "CTRLMMR_MCU_I2C1_CTRL" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "HS_MCS_EN,HS Mode master current source enable." "0,1" group.long 0x60A0++0x3 line.long 0x0 "CTRLMMR_MCU_FSS_CTRL" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RESERVED,Reserved" "0,1" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "S0_BOOT_SIZE,Selects the size of the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface" "0,1" newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "S0_BOOT_SEG,Selects the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or wrap.." group.long 0x60B0++0x3 line.long 0x0 "CTRLMMR_MCU_ADC0_CTRL" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "GPI_MODE_EN,Enables MCU_ADC0 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC0" "0,1" hexmask.long.word 0x0 5.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "TRIG_SEL,Selects the source of the ADC hardware event trigger 0h - MCU_ADC_EXT_TRIGGER0 pin 1h - MCU_ADC_EXT_TRIGGER1 pin 2h - eHRPWM SOCA event 3h - eHRPWM SOCB event 4h - MCU Timer0 PWM output 5h - MCU Timer1 PWM output 6h - MCU Timer2 PWM output 7h -.." group.long 0x60C0++0x3 line.long 0x0 "CTRLMMR_MCU_ADC0_TRIM" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24.--26. "TRIM5,Refer to AFE specification" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21.--23. "TRIM4,Refer to AFE specification" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "TRIM3,Refer to AFE specification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 14.--17. 1. "TRIM2,Refer to AFE specification" hexmask.long.byte 0x0 10.--13. 1. "TRIM1,Refer to AFE specification" newline hexmask.long.byte 0x0 5.--9. 1. "ENABLE_CALB,Refer to AFE specification" hexmask.long.byte 0x0 0.--4. 1. "ENABLE_CAL,Refer to AFE specification" group.long 0x6200++0x27 line.long 0x0 "CTRLMMR_MCU_TIMER0_CTRL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0x4 "CTRLMMR_MCU_TIMER1_CTRL" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "CASCADE_EN,When set enables cascading of MCU_TIMER1 to MCU_TIMER0" "0,1" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0x8 "CTRLMMR_MCU_TIMER2_CTRL" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0xC "CTRLMMR_MCU_TIMER3_CTRL" hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "CASCADE_EN,When set enables cascading of MCU_TIMER3 to MCU_TIMER2" "0,1" hexmask.long.byte 0xC 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xC 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0x10 "CTRLMMR_MCU_TIMER4_CTRL" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0x14 "CTRLMMR_MCU_TIMER5_CTRL" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 8. "CASCADE_EN,When set enables cascading of MCU_TIMER5 to MCU_TIMER4" "0,1" hexmask.long.byte 0x14 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0x18 "CTRLMMR_MCU_TIMER6_CTRL" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x18 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0x1C "CTRLMMR_MCU_TIMER7_CTRL" hexmask.long.tbyte 0x1C 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 8. "CASCADE_EN,When set enables cascading of MCU_TIMER7 to MCU_TIMER6" "0,1" hexmask.long.byte 0x1C 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0x20 "CTRLMMR_MCU_TIMER8_CTRL" hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x20 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." line.long 0x24 "CTRLMMR_MCU_TIMER9_CTRL" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 8. "CASCADE_EN,When set enables cascading of MCU_TIMER9 to MCU_TIMER8" "0,1" hexmask.long.byte 0x24 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 0.--3. 1. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h.." group.long 0x6280++0x27 line.long 0x0 "CTRLMMR_MCU_TIMERIO0_CTRL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO0 output 0h - MCU_TIMERIO0 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO0 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO0 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO0 is driven by MCU_TIMER3 output 4h -.." line.long 0x4 "CTRLMMR_MCU_TIMERIO1_CTRL" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO1 output 0h - MCU_TIMERIO1 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO1 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO1 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO1 is driven by MCU_TIMER3 output 4h -.." line.long 0x8 "CTRLMMR_MCU_TIMERIO2_CTRL" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO2 output 0h - MCU_TIMERIO2 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO2 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO2 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO2 is driven by MCU_TIMER3 output 4h -.." line.long 0xC "CTRLMMR_MCU_TIMERIO3_CTRL" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO3 output 0h - MCU_TIMERIO3 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO3 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO3 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO3 is driven by MCU_TIMER3 output 4h -.." line.long 0x10 "CTRLMMR_MCU_TIMERIO4_CTRL" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO4 output 0h - MCU_TIMERIO4 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO4 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO4 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO4 is driven by MCU_TIMER3 output 4h -.." line.long 0x14 "CTRLMMR_MCU_TIMERIO5_CTRL" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO5 output 0h - MCU_TIMERIO5 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO5 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO5 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO5 is driven by MCU_TIMER3 output 4h -.." line.long 0x18 "CTRLMMR_MCU_TIMERIO6_CTRL" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x18 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO6 output 0h - MCU_TIMERIO6 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO6 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO6 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO6 is driven by MCU_TIMER3 output 4h -.." line.long 0x1C "CTRLMMR_MCU_TIMERIO7_CTRL" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x1C 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO7 output 0h - MCU_TIMERIO7 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO7 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO7 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO7 is driven by MCU_TIMER3 output 4h -.." line.long 0x20 "CTRLMMR_MCU_TIMERIO8_CTRL" hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x20 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO8 output 0h - MCU_TIMERIO8 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO8 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO8 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO8 is driven by MCU_TIMER3 output 4h -.." line.long 0x24 "CTRLMMR_MCU_TIMERIO9_CTRL" hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x24 0.--3. 1. "OUT_SEL,Selects the source of the MCU_TIMERIO9 output 0h - MCU_TIMERIO9 is driven by MCU_TIMER0 output 1h - MCU_TIMERIO9 is driven by MCU_TIMER1 output 2h - MCU_TIMERIO9 is driven by MCU_TIMER2 output 3h - MCU_TIMERIO9 is driven by MCU_TIMER3 output 4h -.." group.long 0x6300++0x3 line.long 0x0 "CTRLMMR_MCU_MTOG0_CTRL" rbitfld.long 0x0 31. "IDLE_STAT,Idle status" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "FORCE_TIMEOUT,Force Timeout" newline bitfld.long 0x0 15. "TIMEOUT_EN,Timeout Enable" "0,1" hexmask.long.word 0x0 3.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TIMEOUT_VAL,Gasket Timeout Value 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16 384 clock cycles 3h - 65 536 clock cycles 4h - 262 144 clock cycles 5h - 1 048 576 clock cycles 6h - 2 097 152 clock cycles 7h - 4 194 303 clock cycles" "0,1,2,3,4,5,6,7" group.long 0x7008++0x7 line.long 0x0 "CTRLMMR_MCU_LOCK1_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_MCU_LOCK1_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers" group.long 0x7100++0x1B line.long 0x0 "CTRLMMR_MCU_P1_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_MCU_P1_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_MCU_P1_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_MCU_P1_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_MCU_P1_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_MCU_P1_CLAIM5" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x18 "CTRLMMR_MCU_P1_CLAIM6" hexmask.long 0x18 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0xA010++0x3 line.long 0x0 "CTRLMMR_MCU_CLKOUT0_CTRL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "CLK_EN,When set enables MCU_CLKOUT0 output" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "CLK_SEL,Selects MCU_CLKOUT0 clock source" "0,1" group.long 0xA018++0x3 line.long 0x0 "CTRLMMR_MCU_EFUSE_CLKSEL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CLK_SEL,Selects the clock source 0h - EFUSE_CLK (HFOSC0_CLKOUT or CLK_12M_RC) 1h - MCU_SYSCLK0 / 8" "0,1" group.long 0xA020++0x7 line.long 0x0 "CTRLMMR_MCU_MCAN0_CLKSEL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "CLK_SEL,MCU_MCAN MCAN_CLK selection" "0,1,2,3" line.long 0x4 "CTRLMMR_MCU_MCAN1_CLKSEL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--1. "CLK_SEL,MCU_MCAN MCAN_CLK selection" "0,1,2,3" group.long 0xA030++0x3 line.long 0x0 "CTRLMMR_MCU_OSPI0_CLKSEL" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "LOOPCLK_SEL,OBSPI0 Loopback clock source" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "CLK_SEL,OSPI0 reference clock selection" "0,1" group.long 0xA040++0x3 line.long 0x0 "CTRLMMR_MCU_ADC0_CLKSEL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "CLK_SEL,Selects the sampling clock source for ADC0 0h - HFOSC0_CLKOUT 1h - MCU_PLL1_HSDIV1_CLKOUT1 2h - MCU_PLL0_HSDIV1_CLKOUT1 3h - MCU_EXT_REFCLK0" "0,1,2,3" group.long 0xA050++0x3 line.long 0x0 "CTRLMMR_MCU_ENET_CLKSEL" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "CPTS_CLKSEL,Selects the clock source for the CPSW2x Ethernet switch Common Platform Time Stamp module 0h - MAIN_PLL3_HSDIV1_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h -.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "RMII_CLK_SEL,Selects the rmii clock (rmii_mhz_50_clk) source. This defaults to the internal 50 MHz clock source for proper clockstop operation" "0,1" group.long 0xA080++0x3 line.long 0x0 "CTRLMMR_MCU_R5_CORE0_CLKSEL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CLK_SEL,Selects the Core 0 functional clock and mcu/interface clock ratio." "0,1" group.long 0xA100++0x27 line.long 0x0 "CTRLMMR_MCU_TIMER0_CLKSEL" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_MCU_TIMER1_CLKSEL" hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x8 "CTRLMMR_MCU_TIMER2_CLKSEL" hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0xC "CTRLMMR_MCU_TIMER3_CLKSEL" hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x10 "CTRLMMR_MCU_TIMER4_CLKSEL" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x14 "CTRLMMR_MCU_TIMER5_CLKSEL" hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x18 "CTRLMMR_MCU_TIMER6_CLKSEL" hexmask.long 0x18 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x1C "CTRLMMR_MCU_TIMER7_CLKSEL" hexmask.long 0x1C 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x1C 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x20 "CTRLMMR_MCU_TIMER8_CLKSEL" hexmask.long 0x20 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x20 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x24 "CTRLMMR_MCU_TIMER9_CLKSEL" hexmask.long 0x24 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x24 0.--2. "CLK_SEL,Timer functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - MCU_SYSCLK0 / 4 2h - CLK_12M_RC 3h - MCU_PLL2_HSDIV2_CLKOUT 4h - MCU_EXT_REFCLK0 5h - LFXOSC_CLKOUT 6h - CPSW_GENF0 7h - CLK_32K" "0,1,2,3,4,5,6,7" group.long 0xA180++0x7 line.long 0x0 "CTRLMMR_MCU_RTI0_CLKSEL" bitfld.long 0x0 31. "WRTLOCK,When set locks further writes to" "0,1" hexmask.long 0x0 3.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "CLK_SEL,RTI functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - LFXOSC_CLKOUT 2h - CLK_12M_RC 3h - CLK_32K" "0,1,2,3,4,5,6,7" line.long 0x4 "CTRLMMR_MCU_RTI1_CLKSEL" bitfld.long 0x4 31. "WRTLOCK,When set locks further writes to" "0,1" hexmask.long 0x4 3.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "CLK_SEL,RTI functional clock input select mux control 0h - HFOSC0_CLKOUT 1h - LFXOSC_CLKOUT 2h - CLK_12M_RC 3h - CLK_32K" "0,1,2,3,4,5,6,7" group.long 0xA1C0++0x3 line.long 0x0 "CTRLMMR_MCU_USART_CLKSEL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CLK_SEL,MCU_USART0 FCLK selection" "0,1" group.long 0xB008++0x7 line.long 0x0 "CTRLMMR_MCU_LOCK2_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_MCU_LOCK2_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers" group.long 0xB100++0xF line.long 0x0 "CTRLMMR_MCU_P2_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_MCU_P2_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_MCU_P2_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_MCU_P2_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0xE000++0x1B line.long 0x0 "CTRLMMR_MCU_LBIST_CTRL" bitfld.long 0x0 31. "BIST_RESET,Reset LBIST macro" "0,1" rbitfld.long 0x0 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--27. 1. "BIST_RUN,Starts LBIST if all bits are 1" newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "RUNBIST_MODE,Runbist mode enable if all bits are 1" rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3" bitfld.long 0x0 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" rbitfld.long 0x0 5.--6. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--4. 1. "DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CTRLMMR_MCU_LBIST_PATCOUNT" rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x4 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "SET_PC_DEF,Number of set patterns to run" hexmask.long.byte 0x4 4.--7. 1. "RESET_PC_DEF,Number of reset patterns to run" hexmask.long.byte 0x4 0.--3. 1. "SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CTRLMMR_MCU_LBIST_SEED0" hexmask.long 0x8 0.--31. 1. "PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CTRLMMR_MCU_LBIST_SEED1" hexmask.long.word 0xC 21.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0xC 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CTRLMMR_MCU_LBIST_SPARE0" hexmask.long 0x10 2.--31. 1. "SPARE0,LBIST spare bits" bitfld.long 0x10 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1" bitfld.long 0x10 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CTRLMMR_MCU_LBIST_SPARE1" hexmask.long 0x14 0.--31. 1. "SPARE1,LBIST spare bits" line.long 0x18 "CTRLMMR_MCU_LBIST_STAT" rbitfld.long 0x18 31. "BIST_DONE,LBIST is done" "0,1" hexmask.long.word 0x18 16.--30. 1. "RESERVED,Reserved" rbitfld.long 0x18 15. "BIST_RUNNING,LBIST is running" "0,1" newline hexmask.long.byte 0x18 10.--14. 1. "RESERVED,Reserved" bitfld.long 0x18 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3" hexmask.long.byte 0x18 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE01C++0x3 line.long 0x0 "CTRLMMR_MCU_LBIST_MISR" hexmask.long 0x0 0.--31. 1. "MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" rgroup.long 0xE280++0x3 line.long 0x0 "CTRLMMR_MCU_LBIST_SIG" hexmask.long 0x0 0.--31. 1. "MISR_SIG,MISR signature" group.long 0xF008++0x7 line.long 0x0 "CTRLMMR_MCU_LOCK3_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_MCU_LOCK3_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers" group.long 0xF100++0x17 line.long 0x0 "CTRLMMR_MCU_P3_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_MCU_P3_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_MCU_P3_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_MCU_P3_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_MCU_P3_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_MCU_P3_CLAIM5" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x13008++0x7 line.long 0x0 "CTRLMMR_MCU_LOCK4_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CTRLMMR_MCU_LOCK4_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition4 registers" group.long 0x13100++0x1B line.long 0x0 "CTRLMMR_MCU_P4_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_MCU_P4_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_MCU_P4_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_MCU_P4_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_MCU_P4_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_MCU_P4_CLAIM5" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x18 "CTRLMMR_MCU_P4_CLAIM6" hexmask.long 0x18 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" tree.end base ad:0x0 tree "MCU_DCC" tree "MCU_DCC0" base ad:0x40100000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree "MCU_DCC1" base ad:0x40110000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree "MCU_DCC2" base ad:0x40120000 group.long 0x0++0x3 line.long 0x0 "DCC_GCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC." hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc." rgroup.long 0x4++0x3 line.long 0x0 "DCC_REV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability." hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g." group.long 0x8++0xF line.long 0x0 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)." line.long 0x4 "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0." line.long 0x8 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)." line.long 0xC "DCC_STATUS,Specifies the status of the DCC Module." hexmask.long 0xC 2.--31. 1. "RESERVED" bitfld.long 0xC 1. "DONE,Indicates when single-shot mode is complete without error." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC_CNT0,Value of the counter attached to clock source 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0." line.long 0x4 "DCC_VALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0." line.long 0x8 "DCC_CNT1,Value of the counter attached to clock source 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1." group.long 0x24++0xB line.long 0x0 "DCC_CLKSRC1,Selects the clock source for counter 1." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1." hexmask.long.byte 0x0 5.--11. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature." line.long 0x4 "DCC_CLKSRC0,Selects the clock source for counter 0." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0." hexmask.long.byte 0x4 4.--11. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0." line.long 0x8 "DCC_GCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value." hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition." rgroup.long 0x30++0x3 line.long 0x0 "DCC_STATUS2,Specifies the status of the DCC FIFOs." hexmask.long 0x0 6.--31. 1. "RESERVED" bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full." "0,1" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full." "0,1" bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full." "0,1" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty." "0,1" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty." "0,1" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty." "0,1" group.long 0x34++0x3 line.long 0x0 "DCC_ERRCNT,Counts number of errors since last clear." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset." tree.end tree.end tree "MCU_ESM0_CFG" base ad:0x40800000 rgroup.long 0x0++0x7 line.long 0x0 "ESM_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,Always reads as 1h. Writes have no affect." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit:2h = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID. Always read as the assigned functional ID. Writes have no affect." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom. Special version." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "ESM_INFO,The Info Register gives the configuration information of this ESM." bitfld.long 0x4 31. "LAST_RESET,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Indicates the number of event groups that are pulse (as opposed to level) driven." hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Indicates the total number of groups that exist in the ESM." group.long 0x8++0x3 line.long 0x0 "ESM_EN,The Global Enable Register has the master interrupt mask" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,This field is the global mask for all interrupts. It is reset by the warm reset. The purpose is to leave all of the raw status and per-interrupt enable bits alone so that after a warm reset software may observe the state of the ESM before the warm.." wgroup.long 0xC++0x3 line.long 0x0 "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset field. Writing to this field can cause all of the raw status and all enables to be cleared. This can be used to reset the ESM state after debugging because of a warm reset." group.long 0x10++0xF line.long 0x0 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--7. 1. "STS,This is the raw status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0h." line.long 0x4 "ESM_ERR_STS,Config Error Enable and Clear Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x4 0.--7. 1. "MSK,This is the masked status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0." line.long 0x8 "ESM_ERR_EN_SET,Config Error Enable Set Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x8 0.--7. 1. "MSK,This is the mask enable for errors in the configuration for Group N. If the corresponding bit and the" line.long 0xC "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0xC 0.--7. 1. "MSK,This is the mask clear for errors in the configuration for Group N. If the corresponding bit and the" rgroup.long 0x20++0xF line.long 0x0 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt" hexmask.long.word 0x0 16.--31. 1. "PLS,Indicates what the highest priority low priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." hexmask.long.word 0x0 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for High Priority while.." line.long 0x4 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt" hexmask.long.word 0x4 16.--31. 1. "PLS,Indicates what the highest priority high priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." hexmask.long.word 0x4 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." line.long 0x8 "ESM_LOW,Shows which groups have outstanding low priority interrupts" hexmask.long 0x8 0.--31. 1. "STS,Indicates which Event Groups have one or more low priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0 bit 1 is for Event Group 1 etc… (bit N is for Event Group N)." line.long 0xC "ESM_HI,Shows which groups have outstanding high priority interrupts" hexmask.long 0xC 0.--31. 1. "STS,Indicates which Event Groups have one or more high priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0 bit 1 is for Event Group 1 etc… (bit N is for Event Group N)." wgroup.long 0x30++0x3 line.long 0x0 "ESM_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced. Writing the corresponding vector to this field will cause a re-evaluation of interrupts. If when the vector is written there are still pending interrupts a new pulse will be generated. Reads always return 0." group.long 0x40++0x3 line.long 0x0 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin control key. This field controls behavior of the error pin. Note during reset the field is 0h but the error pin is asserted (active low). Immediately after reset the error pin de-asserts. This field is only reset by a Power-On-Reset (not warm.." rgroup.long 0x44++0x7 line.long 0x0 "ESM_PIN_STS,This register reflects the status of the error_pin_n output" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." bitfld.long 0x0 0. "VAL,This field indicates the status of the error pin as looped back from the I/O. This field reflects the state of the ERR_I pin. Since the ERR_O pin is only affected by Power-On-Reset then the value of this field may be 1h after the release of Warm.." "0,1" line.long 0x4 "ESM_PIN_CNTR,This register shows the current value of the error pin counter" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,This field indicates the current value of the time interval counter. See" group.long 0x4C++0x3 line.long 0x0 "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,This is the value that will be pre-loaded in to the counter field of the" group.long 0x400++0x1B line.long 0x0 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…)" line.long 0x4 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will.." line.long 0x8 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x8 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) If the corresponding bit and the global enable" line.long 0xC "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0xC 0.--31. 1. "MSK,This field is used to disable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) If the corresponding bit and the global enable" line.long 0x10 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x10 0.--31. 1. "MSK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset.." line.long 0x14 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x14 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft.." line.long 0x18 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x18 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft.." tree.end base ad:0x0 tree "MCU_FSS" tree "MCU_FSS0_CFG" base ad:0x47000000 rgroup.long 0x0++0x3 line.long 0x0 "MCU_FSS0_REVISION,Revision Register Used by software to track features. bugs. and compatibility." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Revision" bitfld.long 0x0 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCU_FSS0_SYSCONFIG,Configuration Register Controls various parameters of the cotroller state." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "OSPI_32B_DISABLE_MODE,0h = OSPI 32-bit mode enabled 1h = OSPI 32-bit mode disabled" "0,1" bitfld.long 0x0 7. "DISXIP,0h = XIP prefetch enabled 1h = XIP prefetch disabled" "0,1" bitfld.long 0x0 6. "OSPI_DDR_DISABLE_MODE,0h = OSPI DDR mode enabled 1h = OSPI DDR mode disabled" "0,1" newline rbitfld.long 0x0 4.--5. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 3. "ECC_DISABLE_ADR,Block Address ECC Calculation 0h = Block address within ECC calculation 1h = Block address not within ECC calculation" "0,1" rbitfld.long 0x0 2. "FSS_AES_EN_IPCFG,Security Enable 0h = Disable security 1h = Enable security" "0,1" bitfld.long 0x0 1. "HB_OSPI,Path Select 0h = Select OSPI path 1h = Select HyperBus interface path" "0,1" newline bitfld.long 0x0 0. "ECC_EN,ECC Enable 0h = ECC disabled 1h = ECC enabled" "0,1" group.long 0x10++0x13 line.long 0x0 "MCU_FSS0_EOI,End Of Interrupt (EOI) MISC Register The End Of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to it for misc interrupt sources. An EOI write signal will be generated and another interrupt.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_VECTOR,EOI Vector Write with bit position of targeted interrupt (example: external FSS ECC is bit 0). Upon write level interrupt will clear and if un-serviced will issue another pulse interrupt." "0,1" line.long 0x4 "MCU_FSS0_STATUS_RAW,Interrupt Source Set Register The Interrupt Source Set Register allows the interrupt sources to be manually set when writing 1h to a specific bit. Write 0h = No action Write 1h = Set event Read 0h = No event pending Read 1h = Event.." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "ECC_WRITE_NONALIGN,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte." "0,1" bitfld.long 0x4 1. "ECC_ERROR_2BIT,ECC Error on 2 Bits Not correctable." "0,1" bitfld.long 0x4 0. "ECC_ERROR_1BIT,ECC Error on 1 Bit Correctable." "0,1" line.long 0x8 "MCU_FSS0_STATUS,Interrupt Source Clear Register The Interrupt Source Clear Register allows the interrupt sources to be manually cleared when writing 1h to a specific bit. Write 0h = No action Write 1h = Clear event Read 0h = No event pending Read 1h =.." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "ECC_WRITE_NONALIGN,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte." "0,1" bitfld.long 0x8 1. "ECC_ERROR_2BIT,ECC Error on 2 Bits Not correctable." "0,1" bitfld.long 0x8 0. "ECC_ERROR_1BIT,ECC Error on 1 Bit Correctable." "0,1" line.long 0xC "MCU_FSS0_ENABLE_SET,Interrupt Source Enable Register The Interrupt Source Enable Register allows the interrupt sources to be manually enabled when writing 1h to a specific bit. Write 0h = No action Write 1h = Enable event Read 0h = Event is disabled Read.." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "ECC_WRITE_NONALIGN,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte." "0,1" bitfld.long 0xC 1. "ECC_ERROR_2BIT,ECC Error on 2 Bits Not correctable." "0,1" bitfld.long 0xC 0. "ECC_ERROR_1BIT,ECC Error on 1 Bit Correctable." "0,1" line.long 0x10 "MCU_FSS0_ENABLE_CLR,Interrupt Source Disable Register The Interrupt Source Disable Register allows the interrupt sources to be manually disabled when writing 1h to a specific bit. Write 0h = No action Write 1h = Disable event Read 0h = Event is disabled.." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "ECC_WRITE_NONALIGN,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte." "0,1" bitfld.long 0x10 1. "ECC_ERROR_2BIT,ECC Error on 2 Bits Not correctable." "0,1" bitfld.long 0x10 0. "ECC_ERROR_1BIT,ECC Error on 1 Bit Correctable." "0,1" group.long 0x30++0x7 line.long 0x0 "MCU_FSS0_ECC_RGSTRT_j,ECC Region Start Register The ECC Region Start Register defines the start of the ECC region in 4 KB steps. Offset = 30h + (j × 8h); where j = 0h to 3h MCU_FSS0_ECC_RGSTRT_0: 4700 0030h MCU_FSS0_ECC_RGSTRT_1: 4700 0038h.." hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x0 0.--19. 1. "R_START,ECC Region Start Address This bit field defines the start of the ECC region in 4 KB steps. Address start = {start[19:0] 000h} 0h = start is 0000 0000h 1h = start is 0000 1000h Ah = start is 0000 A000h" line.long 0x4 "MCU_FSS0_ECC_RGSIZ_j,ECC Region Size Register The ECC Region Size Register defines the size of the ECC region in 4 KB steps. Offset = 34h + (j × 8h); where j = 0h to 3h MCU_FSS0_ECC_RGSIZ_0: 4700 0034h MCU_FSS0_ECC_RGSIZ_1: 4700 0042h.." hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--19. 1. "R_SIZE,ECC Region Size This bit field defines the size of the ECC region in 4 KB steps. 0h = size is zero and disabled 1h = size is 4 KB Ah = size is 40 KB F FFFFh = size is 4 GB" rgroup.long 0x70++0x3 line.long 0x0 "MCU_FSS0_ECC_BLOCK_ADR,ECC Error Block Address Register The ECC Error Block Address Register holds the current top of stack ECC error block address. this is only valid when the [31] ECC_ERR_VALID bit is set." hexmask.long 0x0 5.--31. 1. "ECC_ERROR_BLOCK_ADDR,ECC Error Block Address ECC 32-byte aligned block address" hexmask.long.byte 0x0 0.--4. 1. "RESERVED,Reserved" group.long 0x74++0x7 line.long 0x0 "MCU_FSS0_ECC_TYPE,ECC Error Type Register The ECC Error Type Register holds the current top of stack ECC error info. this is only valid when the [31] ECC_ERR_VALID bit is set." bitfld.long 0x0 31. "ECC_ERR_VALID,ECC Error Valid When set indicates that there is valid ECC error information available. Writing a 1h to this register will pop the top of the stack." "0,1" hexmask.long 0x0 6.--30. 1. "RESERVED,Reserved" rbitfld.long 0x0 5. "ECC_ERR_ADR,ECC Error Address When set indicates that there was a single error detected within the address field." "0,1" rbitfld.long 0x0 4. "ECC_ERR_MAC,ECC Error MAC When set indicates that there was a single error detected within the MAC field." "0,1" newline rbitfld.long 0x0 3. "ECC_ERR_DA1,ECC Error High Data Word When set indicates that there was a single error detected within the High Data word." "0,1" rbitfld.long 0x0 2. "ECC_ERR_DA0,ECC Error Low Data Word When set indicates that there was a single error detected within the Low Data word." "0,1" rbitfld.long 0x0 1. "ECC_ERR_DED,ECC Error (DED) When set indicates that there was a double error detected for the block." "0,1" rbitfld.long 0x0 0. "ECC_ERR_SEC,ECC Error (SEC) When set indicates that there was a single error detected for the block." "0,1" line.long 0x4 "MCU_FSS0_WRT_TYPE,Error Write Type Register The Error Write Type Register holds the current top of stack write error info. this is only valid when the [31] WRT_ERR_VALID bit is set." bitfld.long 0x4 31. "WRT_ERR_VALID,Write Error Valid When set indicates that there is valid write error information available. Writing a 1h to this register will pop the top of the stack." "0,1" hexmask.long.tbyte 0x4 14.--30. 1. "RESERVED,Reserved" rbitfld.long 0x4 13. "WRT_ERR_BEN,Write Error Non-Contiguous Byte Enables When set indicates that there was a write error due to a non-contiguous byte enables." "0,1" rbitfld.long 0x4 12. "WRT_ERR_ADR,Write Error Address When set indicates that there was a write error due to a non-aligned address." "0,1" newline hexmask.long.word 0x4 0.--11. 1. "WRT_ERR_ROUTEID,Write Error Route ID Indicates the Route ID for the Master that caused the write error." tree.end tree "MCU_FSS0_HPB_CTRL" base ad:0x47034000 rgroup.long 0x0++0x3 line.long 0x0 "MCU_FSS0_HPB0_MC_CSR,Controller Status Register The Controller Status Register is used to access the internal status of the HBMC." hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 26. "WRSTOERR,Write RSTO Error This bit indicates whether HyperBus memory is under reset state in the latest write operation. When this bit is set HBMC responds by AXI SLVERR. 0h = Normal operation 1h = HyperBus memory is under reset" "0,1" bitfld.long 0x0 25. "WTRSERR,Write Transaction Error This bit indicates whether AXI protocol is acceptable by HBMC in the latest write transaction. When this bit is set HBMC responds by AXI SLVERR. 0h = Normal operation 1h = This protocol is not supported" "0,1" bitfld.long 0x0 24. "WDECERR,Write Decode Error This bit indicates whether access address is acceptable in the latest write transaction. When this bit is set HBMC responds by AXI DECERR. 0h = Normal operation 1h = Access address is not reachable" "0,1" hexmask.long.byte 0x0 17.--23. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "WACT,Write Active This bit indicates whether write transaction is in progress or not. When receiving write request on write address channel this bit becomes 1h. When retrieving response signaling on write response channel this bit becomes 0h. 0h =.." "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 11. "RDSSTALL,RDS Stall This bit indicates whether read data transfer from HyperBus memory is stalled (RDS Stall remains LOW) in the latest read transaction. When this bit is set HBMC responds by AXI SLVERR. 0h = Normal operation 1h = RDS is stalled" "0,1" bitfld.long 0x0 10. "RRSTOERR,Read RSTO Error This bit indicates whether HyperBus memory is under reset state in the latest read operation. When this bit is set HBMC responds by AXI SLVERR. 0h = Normal operation 1h = HyperBus memory is under reset" "0,1" bitfld.long 0x0 9. "RTRSERR,Read Transaction Error This bit indicates whether AXI protocol is acceptable by HBMC in the latest read transaction. When this bit is set HBMC responds by AXI SLVERR. 0h = Normal operation 1h = This protocol is not supported" "0,1" bitfld.long 0x0 8. "RDECERR,Read Decode Error This bit indicates whether access address is acceptable in the latest read transaction. When this bit is set HBMC responds by AXI DECERR. 0h = Normal operation 1h = Access address is not reachable" "0,1" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RACT,Read Active This bit indicates whether read transaction is in progress or not. When receiving read request on read address channel this bit becomes 1h. When retrieving all requested data on read data channel this bit becomes 0h. 0h = Read is idle.." "0,1" group.long 0x4++0x3 line.long 0x0 "MCU_FSS0_HPB0_MC_IER,Interrupt Enable Register The HBMC outputs optional interrupt signal by condition enabled by the Interrupt Enable Register." bitfld.long 0x0 31. "INTP,Interrupt Polarity Control This bit is used to choose the polarity of optional interrupt signal (IENOn). 0h = IENOn signal is active low 1h = IENOn signal is active high (Reversed mode)" "0,1" hexmask.long 0x0 1.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RPCINTE,HyperBus Memory Interrupt Enable 0h = Disable interrupt 1h = Enable interrupt by INT# signal of HyperBus memory" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MCU_FSS0_HPB0_MC_ISR,Interrupt Status Register The Interrupt Status Register is used to read the status for the interrupts generated." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RPCINTS,HyperBus Memory Interrupt 0h = No interrupt 1h = This bit displays interrupt from INT# signal of HyperBus memory" "0,1" group.long 0x10++0x3 line.long 0x0 "MCU_FSS0_HPB0_MC_MBAR_y,Memory Base Address Register for device connected to CS# The base address of addressable region to Hyperflash memory can be set-up using this register. The controller can't assert two chip selects CS0# and CS1# at a time. Hence.." hexmask.long.byte 0x0 24.--31. 1. "A_MSB,MSB 8 bit of the base address of addressable region to HyperBus memory" hexmask.long.tbyte 0x0 0.--23. 1. "A_LSB,Since register can be set in 16 MB boundary lower 24 bit is fixed to 0h if read this field will always return 0h." group.long 0x20++0x3 line.long 0x0 "MCU_FSS0_HPB0_MC_MCR_y,Memory Configuration Register for CS# Offset = 20h + (y × 4h); where y = 0h to 1h" bitfld.long 0x0 31. "MAXEN,Maximum Length Enable When this bit is set to 1h CS# low time can be configurable by MAXLEN bit. 0h = No configurable CS# low time 1h = Configurable CS# low time" "0,1" hexmask.long.byte 0x0 27.--30. 1. "RESERVED,Reserved" hexmask.long.word 0x0 18.--26. 1. "MAXLEN,Maximum Length This bit indicates maximum read/write transaction length to memory. This bit is ignored when MAXEN bit is 0h. 0h = 2 Byte (1 HyperBus CK) 1h = 4 Byte (2 HyperBus CK) 2h = 6 Byte (3 HyperBus CK) .... 1FFh = 1024 Byte (512 HyperBus CK)" bitfld.long 0x0 17. "TCMO,True Continuous Merge Option Note that this function can be used with the HyperFlash with specific function. Please confirm whether it is available on the corresponding HyperFlash before enabling this function. When HyperBus memory doesn't accept.." "0,1" bitfld.long 0x0 16. "ACS,Asymmetry Cache Support This function should be disabled if the HyperBus memory itself supports the asymmetry cache system. 0h = No asymmetry cache system support 1h = Asymmetry cache system support" "0,1" hexmask.long.word 0x0 6.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 5. "CRT,Configuration Register Target This bit indicates whether the read or write operation accesses the memory or CR space. This bit is mapped to CA-46 bit in HyperRAM. When using HyperFlash this bit should be set to 0h. 0h = Memory space 1h = CR space" "0,1" newline bitfld.long 0x0 4. "DEVTYPE,Device Type Device type for control target. 0h = HyperFlash 1h = HyperRAM" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 0.--1. "WRAPSIZE,Wrap Size The wrap burst length of HyperBus memory. This bit is ignored when the asymmetry cache support bit is 0h. When the asymmetry cache support is 1h this bit should be set the same as wrap size of configuration register in HyperBus.." "0,1,2,3" group.long 0x30++0x3 line.long 0x0 "MCU_FSS0_HPB0_MC_MTR_y,Memory Timing Register Memory access timings for CS# can be configured using the Memory Timing Register. Offset = 30h + (y × 4h); where y = 0h to 1h" hexmask.long.byte 0x0 28.--31. 1. "RCSHI,Read Chip Select High Between Operations This bit indicates CS# high time for read between operations. 0h = corresponds to 1.5 clock cycle Fh = corresponds to 16.5 clock cycle" hexmask.long.byte 0x0 24.--27. 1. "WCSHI,Write Chip Select High Between Operations This bit indicates CS# high time for write between operations. 0h = corresponds to 1.5 clock cycle Fh = corresponds to 16.5 clock cycle" hexmask.long.byte 0x0 20.--23. 1. "RCSS,Read Chip Select Setup to next CK rising edge This bit indicates CS# setup time for read from CS# assertion. 0h = corresponds to 1 clock cycle Fh = corresponds to 16 clock cycle" hexmask.long.byte 0x0 16.--19. 1. "WCSS,Write Chip Select Setup to next CK rising edge This bit indicates CS# setup time for write from CS# assertion. 0h = corresponds to 1 clock cycle Fh = corresponds to 16 clock cycle" hexmask.long.byte 0x0 12.--15. 1. "RCSH,Read Chip Select Hold after CK falling edge This bit indicates CS# hold time for read to CS# de-assertion. 0h = corresponds to 1 clock cycle Fh = corresponds to 16 clock cycle" hexmask.long.byte 0x0 8.--11. 1. "WCSH,Write Chip Select Hold after CK falling edge This bit indicates CS# hold time for write to CS# de-assertion. 0h = corresponds to 1 clock cycle Fh = corresponding to 16 clock cycle" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "LTCY,Latency Cycle Only uses in HyperRAM This bit indicates initial latency code for read/write access. This bit is ignored when the 0h = 5 clock latency 1h = 6 clock latency 2h = Reserved .... Dh = Reserved Eh = 3 clock latency Fh = 4 clock latency" group.long 0x40++0xB line.long 0x0 "MCU_FSS0_HPB0_MC_GPOR,General Purpose Output Register Output signal polarity can be configured using the General Purpose Output Register. General Purpose Output register () of the HBMC is not used (see . HyperBus Not Supported Features)." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "GPO,General Purpose Output Interface 0h = Output signal polarity is LOW 1h = Output signal polarity is HIGH" "0,1,2,3" line.long 0x4 "MCU_FSS0_HPB0_MC_WPR,Write Protection Register Write protection can be configured using the Write Protection Register. WPn pin is not used on Cypress flash devices (see )." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "WP,Write Protection Control 0h = Not Protected WP# signal is HIGH 1h = Protected WP# signal is LOW" "0,1" line.long 0x8 "MCU_FSS0_HPB0_MC_LBR,Loop Back Register Loopback settings can be configured using the Loop Back Register." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0. "LOOPBACK,The write transaction data written on AXI bus is looped back as the read data from RPC bus. The loop-back is performed between WDAT FIFO and RDAT FIFO in AXI interface controller. 0h = Disable loopback 1h = Enable loopback" "0,1" tree.end tree "MCU_FSS0_HPB_ECC_AGGR" base ad:0x47060000 rgroup.long 0x0++0x3 line.long 0x0 "MCU_FSS0_HPB0_ECC_REV,Aggregator Revision Register Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCU_FSS0_HPB0_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCU_FSS0_HPB0_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCU_FSS0_HPB0_ECC_SEC_EOI_REG,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI" "0,1" line.long 0x4 "MCU_FSS0_HPB0_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 14. "MEM_ARID_FIFO_PEND,Interrupt Pending Status for mem_arid_fifo_pend" "0,1" bitfld.long 0x4 13. "MEM_AR_FIFO_PEND,Interrupt Pending Status for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x4 12. "MEM_AWID1_FIFO_PEND,Interrupt Pending Status for mem_awid1_fifo_pend" "0,1" bitfld.long 0x4 11. "MEM_WID1_FIFO_PEND,Interrupt Pending Status for mem_wid1_fifo_pend" "0,1" bitfld.long 0x4 10. "MEM_AW1_FIFO_PEND,Interrupt Pending Status for mem_aw1_fifo_pend" "0,1" newline bitfld.long 0x4 9. "MEM_AWID0_FIFO_PEND,Interrupt Pending Status for mem_awid0_fifo_pend" "0,1" bitfld.long 0x4 8. "MEM_WID0_FIFO_PEND,Interrupt Pending Status for mem_wid0_fifo_pend" "0,1" bitfld.long 0x4 7. "MEM_AW0_FIFO_PEND,Interrupt Pending Status for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x4 6. "MEM_RX_FIFO_PEND,Interrupt Pending Status for mem_rx_fifo_pend" "0,1" bitfld.long 0x4 5. "MEM_RDAT_FIFO_PEND,Interrupt Pending Status for mem_rdat_fifo_pend" "0,1" bitfld.long 0x4 4. "MEM_BDAT1_FIFO_PEND,Interrupt Pending Status for mem_bdat1_fifo_pend" "0,1" newline bitfld.long 0x4 3. "MEM_BDAT0_FIFO_PEND,Interrupt Pending Status for mem_bdat0_fifo_pend" "0,1" bitfld.long 0x4 2. "MEM_WDAT1_FIFO_PEND,Interrupt Pending Status for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x4 1. "MEM_WDAT0_FIFO_PEND,Interrupt Pending Status for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x4 0. "MEM_ADR_FIFO_PEND,Interrupt Pending Status for mem_adr_fifo_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "MCU_FSS0_HPB0_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 14. "MEM_ARID_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_arid_fifo_pend" "0,1" bitfld.long 0x0 13. "MEM_AR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x0 12. "MEM_AWID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid1_fifo_pend" "0,1" bitfld.long 0x0 11. "MEM_WID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid1_fifo_pend" "0,1" bitfld.long 0x0 10. "MEM_AW1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw1_fifo_pend" "0,1" newline bitfld.long 0x0 9. "MEM_AWID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid0_fifo_pend" "0,1" bitfld.long 0x0 8. "MEM_WID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid0_fifo_pend" "0,1" bitfld.long 0x0 7. "MEM_AW0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x0 6. "MEM_RX_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rx_fifo_pend" "0,1" bitfld.long 0x0 5. "MEM_RDAT_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rdat_fifo_pend" "0,1" bitfld.long 0x0 4. "MEM_BDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat1_fifo_pend" "0,1" newline bitfld.long 0x0 3. "MEM_BDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat0_fifo_pend" "0,1" bitfld.long 0x0 2. "MEM_WDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x0 1. "MEM_WDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x0 0. "MEM_ADR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_adr_fifo_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCU_FSS0_HPB0_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 14. "MEM_ARID_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_arid_fifo_pend" "0,1" bitfld.long 0x0 13. "MEM_AR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x0 12. "MEM_AWID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid1_fifo_pend" "0,1" bitfld.long 0x0 11. "MEM_WID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid1_fifo_pend" "0,1" bitfld.long 0x0 10. "MEM_AW1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw1_fifo_pend" "0,1" newline bitfld.long 0x0 9. "MEM_AWID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid0_fifo_pend" "0,1" bitfld.long 0x0 8. "MEM_WID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid0_fifo_pend" "0,1" bitfld.long 0x0 7. "MEM_AW0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x0 6. "MEM_RX_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rx_fifo_pend" "0,1" bitfld.long 0x0 5. "MEM_RDAT_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rdat_fifo_pend" "0,1" bitfld.long 0x0 4. "MEM_BDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat1_fifo_pend" "0,1" newline bitfld.long 0x0 3. "MEM_BDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat0_fifo_pend" "0,1" bitfld.long 0x0 2. "MEM_WDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x0 1. "MEM_WDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x0 0. "MEM_ADR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_adr_fifo_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCU_FSS0_HPB0_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI" "0,1" line.long 0x4 "MCU_FSS0_HPB0_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 14. "MEM_ARID_FIFO_PEND,Interrupt Pending Status for mem_arid_fifo_pend" "0,1" bitfld.long 0x4 13. "MEM_AR_FIFO_PEND,Interrupt Pending Status for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x4 12. "MEM_AWID1_FIFO_PEND,Interrupt Pending Status for mem_awid1_fifo_pend" "0,1" bitfld.long 0x4 11. "MEM_WID1_FIFO_PEND,Interrupt Pending Status for mem_wid1_fifo_pend" "0,1" bitfld.long 0x4 10. "MEM_AW1_FIFO_PEND,Interrupt Pending Status for mem_aw1_fifo_pend" "0,1" newline bitfld.long 0x4 9. "MEM_AWID0_FIFO_PEND,Interrupt Pending Status for mem_awid0_fifo_pend" "0,1" bitfld.long 0x4 8. "MEM_WID0_FIFO_PEND,Interrupt Pending Status for mem_wid0_fifo_pend" "0,1" bitfld.long 0x4 7. "MEM_AW0_FIFO_PEND,Interrupt Pending Status for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x4 6. "MEM_RX_FIFO_PEND,Interrupt Pending Status for mem_rx_fifo_pend" "0,1" bitfld.long 0x4 5. "MEM_RDAT_FIFO_PEND,Interrupt Pending Status for mem_rdat_fifo_pend" "0,1" bitfld.long 0x4 4. "MEM_BDAT1_FIFO_PEND,Interrupt Pending Status for mem_bdat1_fifo_pend" "0,1" newline bitfld.long 0x4 3. "MEM_BDAT0_FIFO_PEND,Interrupt Pending Status for mem_bdat0_fifo_pend" "0,1" bitfld.long 0x4 2. "MEM_WDAT1_FIFO_PEND,Interrupt Pending Status for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x4 1. "MEM_WDAT0_FIFO_PEND,Interrupt Pending Status for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x4 0. "MEM_ADR_FIFO_PEND,Interrupt Pending Status for mem_adr_fifo_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "MCU_FSS0_HPB0_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 14. "MEM_ARID_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_arid_fifo_pend" "0,1" bitfld.long 0x0 13. "MEM_AR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x0 12. "MEM_AWID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid1_fifo_pend" "0,1" bitfld.long 0x0 11. "MEM_WID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid1_fifo_pend" "0,1" bitfld.long 0x0 10. "MEM_AW1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw1_fifo_pend" "0,1" newline bitfld.long 0x0 9. "MEM_AWID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid0_fifo_pend" "0,1" bitfld.long 0x0 8. "MEM_WID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid0_fifo_pend" "0,1" bitfld.long 0x0 7. "MEM_AW0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x0 6. "MEM_RX_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rx_fifo_pend" "0,1" bitfld.long 0x0 5. "MEM_RDAT_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rdat_fifo_pend" "0,1" bitfld.long 0x0 4. "MEM_BDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat1_fifo_pend" "0,1" newline bitfld.long 0x0 3. "MEM_BDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat0_fifo_pend" "0,1" bitfld.long 0x0 2. "MEM_WDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x0 1. "MEM_WDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x0 0. "MEM_ADR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_adr_fifo_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCU_FSS0_HPB0_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 14. "MEM_ARID_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_arid_fifo_pend" "0,1" bitfld.long 0x0 13. "MEM_AR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_ar_fifo_pend" "0,1" newline bitfld.long 0x0 12. "MEM_AWID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid1_fifo_pend" "0,1" bitfld.long 0x0 11. "MEM_WID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid1_fifo_pend" "0,1" bitfld.long 0x0 10. "MEM_AW1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw1_fifo_pend" "0,1" newline bitfld.long 0x0 9. "MEM_AWID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid0_fifo_pend" "0,1" bitfld.long 0x0 8. "MEM_WID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid0_fifo_pend" "0,1" bitfld.long 0x0 7. "MEM_AW0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw0_fifo_pend" "0,1" newline bitfld.long 0x0 6. "MEM_RX_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rx_fifo_pend" "0,1" bitfld.long 0x0 5. "MEM_RDAT_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rdat_fifo_pend" "0,1" bitfld.long 0x0 4. "MEM_BDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat1_fifo_pend" "0,1" newline bitfld.long 0x0 3. "MEM_BDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat0_fifo_pend" "0,1" bitfld.long 0x0 2. "MEM_WDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat1_fifo_pend" "0,1" bitfld.long 0x0 1. "MEM_WDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat0_fifo_pend" "0,1" newline bitfld.long 0x0 0. "MEM_ADR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_adr_fifo_pend" "0,1" group.long 0x200++0xF line.long 0x0 "MCU_FSS0_HPB0_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for ECC interface timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "MCU_FSS0_HPB0_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for ECC interface timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "MCU_FSS0_HPB0_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for ECC interface timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MCU_FSS0_HPB0_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for ECC interface timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_FSS0_HPB_SS_CFG" base ad:0x47030000 rgroup.long 0x0++0xB line.long 0x0 "MCU_FSS0_HPB0_SS_REVISION_REG,Revision Register The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Revision" bitfld.long 0x0 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" line.long 0x4 "MCU_FSS0_HPB0_SS_DLL_STAT_REG,DLL Status Register" hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--10. 1. "MDLL_CODE,MDLL Code The slave delay line length that is currently enabled is determined by the MDLL Code value." bitfld.long 0x4 1. "SDL_LOCK,MDLL Code Valid" "0,1" bitfld.long 0x4 0. "MDLL_LOCK,MDLL Lock When this bit is set it indicates that the master delay line in the MDLL is locked." "0,1" line.long 0x8 "MCU_FSS0_HPB0_SS_RAM_STAT_REG,RAM Status Register" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 0. "INIT_DONE,FIFO RAM Initialization Done When this bit is set it indicates that all the FIFO RAM auto initialization is complete. Software should check that this bit is set before initiating transactions to the external memory." "0,1" tree.end base ad:0x0 tree "MCU_FSS0_OSPI0_CTRL" group.long 0x47040000++0x2B line.long 0x0 "OSPI_CONFIG_REG,OSPI Configuration Register This register contains basic configuration fields of the controller. Some of the OSPI features described in this section may not be supported on this family of devices. For more information. see . OSPI Not.." rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE." "0,1" bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit." "0,1" rbitfld.long 0x0 26.--28. "CONFIG_RESV2_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable." "0,1" bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder. 0h = Active slave is selected based on the OSPI_CONFIG_REG[13:10] PERIPH_CS_LINES_FLD. 1h = Active slave is selected based on actual data interface address (the partition is calculated with respect to bits.." "0,1" hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master mode baud rate divisor (2 to 32) " newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately.0h = If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction Value=1h = Operate the device in XIP mode immediately. Use this register when the external.." "0,1" bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ.0h = If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction.1h = If XIP is disabled then setting to 1 will inform the controller that the device is.." "0,1" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable Data Interface Address Remapping [Direct Access Mode Only]" "0,1" bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface." "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin." "0,1" hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines.If OSPI_CONFIG_REG[9] PERIPH_SEL_DEC_FLD = 0 ss[3:0] are output thus:else ss[3-0] directly drives N_SS_OUT[3-0] ." newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode.0h = only 1 of 4 selects N_SS_OUT[3:0] is active 1h = allow external 4-to-16 decode [N_SS_OUT = ss]" "0,1" bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable.0h = Use Direct Access Controller/Indirect Access Controller 1h = Legacy Mode is enabled. In this mode any write to the controller via the data interface is serialized and sent to the FLASH device. Any valid.." "0,1" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller.0h = Disable the Direct Access Controller once current transfer of the data word is complete.1h = Enable the Direct Access Controller. When the Direct Access Controller and Indirect Access Controller.." "0,1" bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration.0h = RESET feature on DQ3 pin of the device 1h = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]." "0,1" newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature." "0,1" bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature." "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable." "0,1" bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase.Selects whether the clock is in an active or inactive phase outside the SPI word 0h = The SPI clock is active outside the word 1h = The SPI clock is inactive outside the word" "0,1" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word.0h = The SPI clock is quiescent low 1h = The SPI clock is quiescent high" "0,1" bitfld.long 0x0 0. "ENB_SPI_FLD,OSPI Enable.0h = Disable the OSPI once current transfer of the data wordis complete.1h = Enable the OSPI when this bit is set to 0 all output enables are inactive and all pins are set to input mode." "0,1" line.long 0x4 "OSPI_DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register. This register defines the configuration of Multiple-SPI READ instruction. This register should be setup while the controller is idle." rbitfld.long 0x4 29.--31. "RD_INSTR_RESV5_FLD,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles." newline rbitfld.long 0x4 21.--23. "RD_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable." "0,1" newline rbitfld.long 0x4 18.--19. "RD_INSTR_RESV3_FLD,Reserved" "0,1,2,3" bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers DQ0 and DQ1 are used as both.." "0,1,2,3" newline rbitfld.long 0x4 14.--15. "RD_INSTR_RESV2_FLD,Reserved" "0,1,2,3" bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0 DQ1 DQ2 .." "0,1,2,3" newline rbitfld.long 0x4 11. "RD_INSTR_RESV1_FLD,Reserved" "0,1" bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable." "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type.0h = Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1h = Use DIO-SPI mode [Instructions Address and Data always sent on DQ0 and DQ1] 2h = Use QIO-SPI mode [Instructions Address and Data.." "0,1,2,3" hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "OSPI_DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register. This register defines the configuration of Multiple-SPI WRITE (Program Page) instruction. This register should be setup while the controller is idle." rbitfld.long 0x8 29.--31. "WR_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles." newline hexmask.long.byte 0x8 18.--23. 1. "WR_INSTR_RESV3_FLD,Reserved" bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers DQ0 and DQ1 are used as both.." "0,1,2,3" newline rbitfld.long 0x8 14.--15. "WR_INSTR_RESV2_FLD,Reserved" "0,1,2,3" bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0 DQ1 DQ2." "0,1,2,3" newline rbitfld.long 0x8 9.--11. "WR_INSTR_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "OSPI_DEV_DELAY_REG,OSPI Device Delay Register. This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the OSPI REFERENCE CLOCK/ext_clk. defined in this table as SPI master.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert." hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit." hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with N_SS_OUT." line.long 0x10 "OSPI_RD_DATA_CAPTURE_REG,Read Data Capture Register. This register is used to adjust SPI transfer conditions in order to fetch and capture data reliably. This register should be setup while the controller is idle." hexmask.long.word 0x10 20.--31. 1. "RD_DATA_RESV3_FLD,Reserved" hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay." newline hexmask.long.byte 0x10 9.--15. 1. "RD_DATA_RESV2_FLD,Reserved" bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit." "0,1" newline rbitfld.long 0x10 6.--7. "RD_DATA_RESV1_FLD,Reserved" "0,1,2,3" bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection." "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay." bitfld.long 0x10 0. "BYPASS_FLD,Bypass." "0,1" line.long 0x14 "OSPI_DEV_SIZE_CONFIG_REG,Device Size Configuration Register. This register allows to define the memory organization of using Flash Devices. This register should be setup while the controller is idle." rbitfld.long 0x14 29.--31. "DEV_SIZE_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin:0h = size of 512Mb 1h = size of 1Gb2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3" bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin:0h = size of 512Mb1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb" "0,1,2,3" hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page." hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes." line.long 0x18 "OSPI_SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register." hexmask.long.tbyte 0x18 8.--31. 1. "SRAM_PARTITION_RESV_FLD,Reserved" hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size." line.long 0x1C "OSPI_IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register. This register allowsto define the address distinguishing DAC access from triggered INDAC one. This register should be setup while the controller is idle." hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,Indirect Trigger Address." line.long 0x20 "OSPI_DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register. This register allows to define the parameters of DMA peripheral controller. This register should be setup while the controller is idle. Some of the OSPI features described in this section.." hexmask.long.tbyte 0x20 12.--31. 1. "DMA_PERIPH_RESV2_FLD,Reserved" hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes." newline hexmask.long.byte 0x20 4.--7. 1. "DMA_PERIPH_RESV1_FLD,Reserved" hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes." line.long 0x24 "OSPI_REMAP_ADDR_REG,Remap Address Register. This register allows to define the address offset for DAC accesses. This register should be setup while the controller is idle." hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming data address to a different address used by the FLASH device." line.long 0x28 "OSPI_MODE_BIT_CONFIG_REG,Mode Bit Configuration Register. This register allows to define the mode bits for corresponding Flash Device. It also provides configuration for CRC aware SPI transfers. This register should be setup while the controller is idle." hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower]." hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper]." newline bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit." "0,1" hexmask.long.byte 0x28 11.--14. 1. "MODE_BIT_RESV1_FLD,Reserved" newline bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x4704002C++0x3 line.long 0x0 "OSPI_SRAM_FILL_REG,SRAM Fill Register. This register keeps the values of current fill levels of both SRAM partitions." hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]." hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]." group.long 0x47040030++0x17 line.long 0x0 "OSPI_TX_THRESH_REG,TX Threshold Register. This register allows to define the TX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle." hexmask.long 0x0 5.--31. 1. "TX_THRESH_RESV_FLD,Reserved" hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "OSPI_RX_THRESH_REG,RX Threshold Register. This register allows to define the RX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle." hexmask.long 0x4 5.--31. 1. "RX_THRESH_RESV_FLD,Reserved" hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated." line.long 0x8 "OSPI_WRITE_COMPLETION_CTRL_REG,Write Completion Control Register. This register defines how the controller will poll the device following a write transfer." hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Polling repetition delay." hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Polling count." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Enable polling expiration." "0,1" bitfld.long 0x8 14. "DISABLE_POLLING_FLD,Disable polling." "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Polling polarity." "0,1" rbitfld.long 0x8 11.--12. "WR_COMP_CTRL_RESV1_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Polling bit index." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Polling opcode." line.long 0xC "OSPI_NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register. This register defines maximum number of poll cycles. If the expected value of the bit being polled is not gotten after number defined in this register. the auto-polling is done on the next phase." hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Defines the numbers of poll cycles after which auto-polling phase terminates and polling expiration interrupt is generated." line.long 0x10 "OSPI_IRQ_STATUS_REG,Interrupt Status Register. The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set. the interrupt output is asserted high. The.." hexmask.long.word 0x10 20.--31. 1. "IRQ_STAT_RESV_FLD,Reserved" bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken." "0,1" bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid." "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error." "0,1" rbitfld.long 0x10 15. "IRQ_STAT_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired." "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow." "0,1" bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full.Current FIFO status can be ignored in non-SPI legacy mode.0h = FIFO is not full 1h = FIFO is full" "0,1" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty. Current FIFO status can be ignored in non-SPI legacy mode. 0h = FIFO has less than RX THRESHOLD entries. 1h = FIFO has &gt;= THRESHOLD entries." "0,1" bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full. Current FIFO status can be ignored in non-SPI legacy mode 0h = FIFO is not full 1h = FIFO is full" "0,1" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full.Current FIFO status can be ignored in non-SPI legacy mode 0h = FIFO has &gt;= THRESHOLD entries.1h = FIFO has less than THRESHOLD entries." "0,1" bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow. This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read If a new push to the RX.." "0,1" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached." "0,1" bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" bitfld.long 0x10 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation." "0,1" bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected:0h = no underflow has been detected 1h = underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "0,1" newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure. Mode M failure indicates the voltage on pin N_SS_IN is inconsistent with the SPI mode. Set =1 if N_SS_IN is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI." "0,1" line.long 0x14 "OSPI_IRQ_MASK_REG,Interrupt Mask Register. This register allows the user to mask/unmask particular interrupt sources. This register should be setup while the controller is idle. 0h = the interrupt for the corresponding interrupt status register bit is.." hexmask.long.word 0x14 20.--31. 1. "IRQ_MASK_RESV_FLD,Reserved" bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" rbitfld.long 0x14 15. "IRQ_MASK_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" bitfld.long 0x14 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" group.long 0x47040050++0xB line.long 0x0 "OSPI_LOWER_WR_PROT_REG,Lower Write Protection Register. This register allows to define lower boundary of the write protection area. This register should be setup while the controller is idle." hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,Lower Block Number.The block number that defines the lower block in the range of blocks that is to be locked from writing." line.long 0x4 "OSPI_UPPER_WR_PROT_REG,Upper Write Protection Register. This register allows to define upper boundary of the write protection area. This register should be setup while the controller is idle." hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,Lower Block Number." line.long 0x8 "OSPI_WR_PROT_CTRL_REG,Write Protection Control Register. This register allows to define the configuration of write protection settings. This register should be setup while the controller is idle." hexmask.long 0x8 2.--31. 1. "WR_PROT_CTRL_RESV_FLD,Reserved" bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit." "0,1" group.long 0x47040060++0x23 line.long 0x0 "OSPI_INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register. This register allows control of the Indirect Read Transfer logic." hexmask.long.tbyte 0x0 8.--31. 1. "INDIR_RD_XFER_RESV_FLD,Reserved" rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status." "0,1" rbitfld.long 0x0 4. "RD_QUEUED_FLD,Queued Indirect Read Operations." "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full. SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it indirect operation [status]." "0,1" rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status." "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read." "0,1" bitfld.long 0x0 0. "START_FLD,Start Indirect Read." "0,1" line.long 0x4 "OSPI_INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register. This register allows to define watermark level for Indirect read transfers. This register should be setup before an indirect read transfer is triggered. Some of the OSPI.." hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value." line.long 0x8 "OSPI_INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register. This register allows to define start address of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is.." hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Start of Indirect Access." line.long 0xC "OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register. This register allows to define number of bytes to be read of indirect read transfer which is about to be triggered. This register should be setup before an indirect read.." hexmask.long 0xC 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes." line.long 0x10 "OSPI_INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register. This register allows control of the Indirect Write Transfer logic." hexmask.long.tbyte 0x10 8.--31. 1. "INDIR_WR_XFER_RESV2_FLD,Reserved" rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status." "0,1" rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued." "0,1" newline rbitfld.long 0x10 3. "INDIR_WR_XFER_RESV1_FLD,Reserved" "0,1" rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status." "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write." "0,1" bitfld.long 0x10 0. "START_FLD,Start Indirect Write." "0,1" line.long 0x14 "OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register. This register allows to define watermark level for Indirect write transfers. This register should be setup before an indirect write transfer is triggered. Some of the OSPI.." hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value." line.long 0x18 "OSPI_INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register. This register allows to define start address of indirect write transfer which is about to be triggered. This register should be setup before an indirect write transfer is.." hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access." line.long 0x1C "OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register. This register allows to define number of bytes to be written of indirect read transfer which is about to be triggered. This register should be setup before an indirect.." hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes." line.long 0x20 "OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register. This register allows the user to define the indirect trigger address range. If the configured range exceeds number of bytes programmed for particular indirect transfer. there.." hexmask.long 0x20 4.--31. 1. "IND_RANGE_RESV1_FLD,Reserved" hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,Indirect Range Width." group.long 0x4704008C++0xB line.long 0x0 "OSPI_FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register. This register controls the Memory Bank accesses. It also defines the number of bytes intended to get by STIG access configured to use the STIG Memory Bank." rbitfld.long 0x0 29.--31. "FLASH_COMMAND_CTRL_MEM_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,Memory Bank Address." newline rbitfld.long 0x0 19. "FLASH_COMMAND_CTRL_MEM_RESV2_FLD,Reserved" "0,1" bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,Number of STIG Memory Bank Read Bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Memory Bank Read Data." hexmask.long.byte 0x0 2.--7. 1. "FLASH_COMMAND_CTRL_MEM_RESV3_FLD,Reserved" newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "OSPI_FLASH_CMD_CTRL_REG,Flash Command Control Register. This register controls SPI transactions generated by STIG. It allows to define corresponding SPI frame to particular command. triggering the transfer and polling for its completion." hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode." bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable. Set to 1 if the command specified in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command Set to 0 for 1 byte and 7 for 8 bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable.Set to 1 if the command specified in OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires an address This should be setup before triggering the command via writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes" "0,1" bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes. Set to the number of address bytes required [the address itself is programmed in the OSPI_FLASH_CMD_ADDR_REG. This should be setup before triggering the command via the OSPI_FLASH_CMD_CTRL_REG[0].." "0,1,2,3" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable." "0,1" bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles." hexmask.long.byte 0x4 3.--6. 1. "FLASH_CMD_CTRL_RESV1_FLD,Reserved" newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "OSPI_FLASH_CMD_ADDR_REG,Flash Command Address Register. This register allows to define the address of the command using by the STIG controller. This register should be setup while the controller is idle." hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address." rgroup.long 0x470400A0++0x7 line.long 0x0 "OSPI_FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower). This register keeps the last 4 bytes read by STIG SPI access." hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Read Data (Lower)." line.long 0x4 "OSPI_FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper). This register keeps the last but 4 bytes read by STIG SPI access. This register in conjunction with the register enables the controller to keep 8 last bytes read from the Flash Device.." hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Read Data (Upper)." group.long 0x470400A8++0x13 line.long 0x0 "OSPI_FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower). This register takes the first 4 bytes to be written by STIG." hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte." line.long 0x4 "OSPI_FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper). This register takes the bytes ranging from 5 to 8 to be written by STIG." hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte." line.long 0x8 "OSPI_POLLING_FLASH_STATUS_REG,Polling Flash Status Register. This register provides auto-polling data. It acts as the extension for the register where full status is not available and any action can be taken only relying on the indication of single bit.." hexmask.long.word 0x8 20.--31. 1. "DEVICE_STATUS_RSVD_FLD2,Reserved" hexmask.long.byte 0x8 16.--19. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling." newline hexmask.long.byte 0x8 9.--15. 1. "DEVICE_STATUS_RSVD_FLD1,Reserved" rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device." line.long 0xC "OSPI_PHY_CONFIGURATION_REG,PHY Configuration Register. This register defines the configuration of PHY Module and controls the internal DLL. This register should be setup while the controller is idle." bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,Re-synchronisation DLL." "0,1" bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass." "0,1" hexmask.long.byte 0xC 23.--28. 1. "PHY_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay." hexmask.long.word 0xC 7.--15. 1. "PHY_CONFIG_RESV1_FLD,Reserved" newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay." line.long 0x10 "OSPI_PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register. This register defines the configuration and control logic of DLL intended to work in DLL Master Mode." hexmask.long.byte 0x10 25.--31. 1. "PHY_MASTER_CONTROL_RESV3_FLD,Reserved" bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay. This bit need not be written by software. If DLL does not lock in full cycle it will automatically try to lock in half cycle mode." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs.Master DLL is disabled with only 1 delay element in its delay line. The slave delay lines decode delays in absolute delay elements rather than as fractional delays.Delays.." "0,1" bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "PHY_MASTER_CONTROL_RESV2_FLD,Reserved" "0,1" bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 7.--15. 1. "PHY_MASTER_CONTROL_RESV1_FLD,Reserved" hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the Master DLL." rgroup.long 0x470400BC++0x7 line.long 0x0 "OSPI_DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower. This register allows to observe and debug DLL status." hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative lock incremental steps when the" hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative lock decremental steps when the" newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,DLL Lock Value." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,DLL Unlock Counter." bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,DLL Locked Mode." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,DLL Lock." "0,1" line.long 0x4 "OSPI_DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper. This register allows to observe and debug DLL status." hexmask.long.word 0x4 23.--31. 1. "DLL_OBSERVABLE_UPPER_RESV2_FLD,Reserved" hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,TX DLL decoder output." newline hexmask.long.word 0x4 7.--15. 1. "DLL_OBSERVABLE_UPPER_RESV1_FLD,Reserved" hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE_UPPER_RX_DECODER_OUTPUT_FLD,RX DLL decoder output." group.long 0x470400E0++0x7 line.long 0x0 "OSPI_OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower). This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by [30] DUAL_BYTE_OPCODE_EN_FLD bit." hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcoded defined in the" hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode defined in the" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode defined in the" hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode defined in the" line.long 0x4 "OSPI_OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper). This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by [30] DUAL_BYTE_OPCODE_EN_FLD bit." hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,WEL Opcode byte 1." hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,WEL Opcode byte 2 (Optional)." newline hexmask.long.word 0x4 0.--15. 1. "OPCODE_EXT_UPPER_RESV1_FLD,Reserved" rgroup.long 0x470400FC++0x3 line.long 0x0 "OSPI_MODULE_ID_REG,Module ID Register. This register provides the IP release number and the configuration data." hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline hexmask.long.byte 0x0 2.--7. 1. "MODULE_ID_RESV_FLD,Reserved" bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number:0h = OCTAL + PHY Configuration 1h = OCTAL Configuration 2h = QUAD + PHY Configuration 3h = QUAD Configuration" "0,1,2,3" tree.end tree "MCU_FSS0_OSPI0_ECC_AGGR" base ad:0x8000 rgroup.long 0x47060000++0x3 line.long 0x0 "OSPI_ECC_REV,Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x47060008++0x3 line.long 0x0 "OSPI_ECC_VECTOR,ECC Vector Register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0x4706000C++0x3 line.long 0x0 "OSPI_ECC_STAT,Miscellaneous status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator." group.long 0x47060010++0x3 line.long 0x0 "OSPI_RESERVED_SVBUS_Y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x4706003C++0x7 line.long 0x0 "OSPI_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI_ECC_SEC_STATUS_REG0,Interrupt Status Register 0." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x47060080++0x3 line.long 0x0 "OSPI_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0x470600C0++0x3 line.long 0x0 "OSPI_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x4706013C++0x7 line.long 0x0 "OSPI_ECC_DED_EOI_REG,EOI Register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI_ECC_DED_STATUS_REG0,Interrupt Status Register 0." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend." "0,1" group.long 0x47060180++0x3 line.long 0x0 "OSPI_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend." "0,1" group.long 0x470601C0++0x3 line.long 0x0 "OSPI_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend." "0,1" group.long 0x47060200++0xF line.long 0x0 "OSPI_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors." "0,1" line.long 0x4 "OSPI_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors." "0,1" line.long 0x8 "OSPI_ECC_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors." "0,1,2,3" line.long 0xC "OSPI_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors." "0,1,2,3" tree.end tree "MCU_FSS0_OSPI0_SS_CFG" base ad:0x4000 rgroup.long 0x47040000++0x3 line.long 0x0 "OSPI_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit:10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x47040004++0x3 line.long 0x0 "OSPI_CTRL,The Control Register contains general control bits for the OSPI." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "PIPELINE_MODE_FLUSH,1h = Flush Flash Controller FIFO by forcing data interface slave select signal low. 0h = Data interface slave select signal to Controller is 1." "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x47040008++0x3 line.long 0x0 "OSPI_STAT,The Status register provide general status bits for the OSPI." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "MEM_INIT_DONE,0h = Memory initialization is in progress 1h = Memory intialization is done." "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0x47040020++0x3 line.long 0x0 "OSPI_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targetted interrupt.(that is Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1 will issue another pulse interrupt." tree.end tree.end tree "MCU_I2C" tree "MCU_I2C0_CFG" base ad:0x40B00000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "MCU_I2C1_CFG" base ad:0x40B10000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree.end tree "MCU_I3C" tree "MCU_I3C0_MMR_MMRVBP" base ad:0x40B80000 rgroup.long 0x0++0x3 line.long 0x0 "I3C_PID,Return to the . The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit:" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end tree "MCU_I3C0_P_ECC_AGGR_CFG" base ad:0x40720000 rgroup.long 0x0++0x3 line.long 0x0 "I3C_P_REV,Return to the . Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "I3C_P_VECTOR,Return to the . ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "I3C_P_STAT,Return to the . Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "I3C_P_RESERVED_SVBUS_y,Return to the . Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "I3C_P_SEC_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "I3C_P_SEC_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "I3C_P_SEC_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "I3C_P_SEC_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "I3C_P_DED_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "I3C_P_DED_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "I3C_P_DED_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "I3C_P_DED_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" group.long 0x200++0xF line.long 0x0 "I3C_P_AGGR_ENABLE_SET,Return to the . AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "I3C_P_AGGR_ENABLE_CLR,Return to the . AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "I3C_P_AGGR_STATUS_SET,Return to the . AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "I3C_P_AGGR_STATUS_CLR,Return to the . AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_I3C0_S_ECC_AGGR_CFG" base ad:0x40721000 rgroup.long 0x0++0x3 line.long 0x0 "I3C_S_REV,Return to the . Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "I3C_S_VECTOR,Return to the . ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "I3C_S_STAT,Return to the . Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "I3C_S_RESERVED_SVBUS_y,Return to the . Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "I3C_S_SEC_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "I3C_S_SEC_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1" bitfld.long 0x4 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1" bitfld.long 0x4 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1" newline bitfld.long 0x4 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1" bitfld.long 0x4 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1" bitfld.long 0x4 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1" bitfld.long 0x4 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1" newline bitfld.long 0x4 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1" bitfld.long 0x4 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "I3C_S_SEC_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1" bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1" newline bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "I3C_S_SEC_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1" bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1" newline bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "I3C_S_DED_EOI_REG,Return to the . EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "I3C_S_DED_STATUS_REG0,Return to the . Interrupt Status Register 0" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1" bitfld.long 0x4 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1" bitfld.long 0x4 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1" newline bitfld.long 0x4 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1" bitfld.long 0x4 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1" bitfld.long 0x4 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1" bitfld.long 0x4 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1" newline bitfld.long 0x4 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1" bitfld.long 0x4 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "I3C_S_DED_ENABLE_SET_REG0,Return to the . Interrupt Enable Set Register 0" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1" bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1" newline bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "I3C_S_DED_ENABLE_CLR_REG0,Return to the . Interrupt Enable Clear Register 0" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" bitfld.long 0x0 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1" bitfld.long 0x0 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1" bitfld.long 0x0 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1" newline bitfld.long 0x0 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1" bitfld.long 0x0 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1" bitfld.long 0x0 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1" bitfld.long 0x0 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1" newline bitfld.long 0x0 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1" bitfld.long 0x0 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1" group.long 0x200++0xF line.long 0x0 "I3C_S_AGGR_ENABLE_SET,Return to the . AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "I3C_S_AGGR_ENABLE_CLR,Return to the . AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "I3C_S_AGGR_STATUS_SET,Return to the . AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "I3C_S_AGGR_STATUS_CLR,Return to the . AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST" base ad:0x40B88000 rgroup.long 0x0++0xF line.long 0x0 "I3C_DEV_ID,Return to the . This register holds the IP identifier." hexmask.long.word 0x0 16.--31. 1. "RSVD0,Reserved." hexmask.long.word 0x0 0.--15. 1. "DEV_ID,Unique IP identifier within IP portfolio" line.long 0x4 "I3C_CONF_STATUS0,Return to the . The read-only Configuration Status Register 0 indicates the hardware configuration options chosen for implementation of the I3C-Master." bitfld.long 0x4 29.--31. "CMDR_MEM_DEPTH,CMD Resp MEM depth coded into 3 bits." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "ASF,Indicates supported ASF checks." newline hexmask.long.byte 0x4 16.--23. 1. "GPO_NUM,Returns the value of User GPO" hexmask.long.byte 0x4 8.--15. 1. "GPI_NUM,Returns the value of User GPI" newline bitfld.long 0x4 6.--7. "IBIR_MEM_DEPTH,IBI Resp MEM depth coded into 2 bits." "0,1,2,3" bitfld.long 0x4 5. "DDR,Indicates if DDR is supported." "0,1" newline bitfld.long 0x4 4. "DEV_ROLE,Returns status of Device Role [Main/Secondary Master]." "0,1" hexmask.long.byte 0x4 0.--3. 1. "DEVS_NUM,Returns the number of retaining registers for I3C Slave devices [Addresses and Characteristics] the max value is 11." line.long 0x8 "I3C_CONF_STATUS1,Return to the . The read-only Configuration Status Register 1 indicates the hardware configuration options chosen for implementation of the I3C-Master." hexmask.long.byte 0x8 28.--31. 1. "IBI_HW_RES,IBI resources" bitfld.long 0x8 26.--27. "CMD_MEM_DEPTH,CMD FIFO depth coded into 3 bits." "0,1,2,3" newline hexmask.long.byte 0x8 21.--25. 1. "SLV_DDR_RX_MEM_DEPTH,SLV DDR RX FIFO depth coded into 5 bits." hexmask.long.byte 0x8 16.--20. 1. "SLV_DDR_TX_MEM_DEPTH,SLV DDR TX FIFO depth coded into 5 bits." newline bitfld.long 0x8 13.--15. "RSVD0,Reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x8 10.--12. "IBI_MEM_DEPTH,IBI FIFO depth coded into 3 bits." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 5.--9. 1. "RX_MEM_DEPTH,RX FIFO depth coded into 5 bits." hexmask.long.byte 0x8 0.--4. 1. "TX_MEM_DEPTH,TX FIFO depth coded into 5 bits." line.long 0xC "I3C_REV_ID,Return to the . This register gives an information about particular version of the IP." hexmask.long.word 0xC 20.--31. 1. "VID,VENDOR_ID: IP vendor ID affected to IP [reset = 0xCAD]." hexmask.long.word 0xC 8.--19. 1. "PID,PRODUCT_ID: unique IP identifier within CDNS IP portfolio [reset = 0x13C]." newline bitfld.long 0xC 5.--7. "REV_MAJOR,X: Major revision value." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--4. 1. "REV_MINOR,Y: Minor revision value." group.long 0x10++0xB line.long 0x0 "I3C_CTRL,Return to the . Control Register for I3C Master IP - register that provides main control and configuration options for the controller." bitfld.long 0x0 31. "DEV_EN,When set HIGH the I3C-Master is enabled and it can initiates the I3C/I2C transactions." "0,1" bitfld.long 0x0 30. "HALT_EN,Enable halt on abort behavior." "0,1" newline bitfld.long 0x0 29. "MCS,Manual Command Start writing 1 starts execution of the commands currently in CMD Memories." "0,1" bitfld.long 0x0 28. "MCS_EN,Manual Command Start Enable if set 1 the IP will wait with starting of command execution until MCS but [" "0,1" newline rbitfld.long 0x0 27. "RSVD2,Reserved." "0,1" bitfld.long 0x0 26. "I3C_11_SUPP,Enables support for timing parameter that has been changed in v1.1 i.e." "0,1" newline bitfld.long 0x0 24.--25. "THD_DEL,Field that provides option to add data hold delay with respect to the SCL clock on which data on SDA is launched [applied only during actual Data transfer]" "0,1,2,3" hexmask.long.word 0x0 9.--23. 1. "RSVD1,Reserved." newline bitfld.long 0x0 8. "HJ_DISEC,This bit controls the HW response for ACK'ed HJ request." "0,1" bitfld.long 0x0 7. "MST_ACK,Specifies ACK response type for GETACCMST CCC it can be either ACK response type [mst_ack = 1] or NACK response type [mst_ack = 0]." "0,1" newline bitfld.long 0x0 6. "HJ_ACK,Specifies ACK response type for HJ request it can be either ACK response type [hj_ack = 1] or NACK response type [hj_ack = 0]." "0,1" bitfld.long 0x0 5. "HJ_INIT,Initiate HJ request - applicable only for Secondary master in slave mode." "0,1" newline bitfld.long 0x0 4. "MST_INIT,Initiate Mastership request - applicable only in slave mode." "0,1" bitfld.long 0x0 3. "AHDR_OPT,Enable[1]/Disable[0] the Address Header optimization." "0,1" newline rbitfld.long 0x0 2. "RSVD0,Reserved" "0,1" bitfld.long 0x0 0.--1. "BUS_MODE,Bus Mode" "0,1,2,3" line.long 0x4 "I3C_PRESCL_CTRL0,Return to the . Prescale settings for SDR/I2C modes" hexmask.long.word 0x4 16.--31. 1. "I2C,Prescaler value for I2C SCL clock generation." hexmask.long.byte 0x4 10.--15. 1. "RSVD0,Reserved" newline hexmask.long.word 0x4 0.--9. 1. "I3C,Prescaler value for I3C Push-Pull SDR Mode SCL clock generation." line.long 0x8 "I3C_PRESCL_CTRL1,Return to the . Prescale settings related to Open Drain / Push Pull I3C timings" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "PP_LOW,Counter for low period of SCL clock for Push Pull in I3C." newline hexmask.long.byte 0x8 0.--7. 1. "OD_LOW,Counter for low period of SCL clock for Open Drain in I3C." group.long 0x20++0x7 line.long 0x0 "I3C_MST_IER,Return to the . The write only Interrupt Enable Register is used to enable interrupts by setting bits in the read only Interrupt Mask Register - Master Mode (). See Interrupt Status Register - Master Mode () description for details on.." hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x0 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Enable." "0,1" bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Enable" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Enable." "0,1" bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Enable" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Enable." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Enable." "0,1" bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Enable" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Enable" "0,1" bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Enable." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Enable." "0,1" bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Enable." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Enable." "0,1" bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Enable." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Enable." "0,1" bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Enable." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Enable." "0,1" bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Enable." "0,1" line.long 0x4 "I3C_MST_IDR,Return to the . The write only Interrupt Disable Register is used to disable interrupts by clearing the bits in the read only Interrupt Mask Register - Master Mode (). See Interrupt Status Register - Master Mode () description for details on.." hexmask.long.word 0x4 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x4 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x4 17. "MR_DONE,Mastership handoff done Disable." "0,1" bitfld.long 0x4 16. "IMM_COMP,Immediate Commmand Completed Disable" "0,1" newline bitfld.long 0x4 15. "TX_THR,Tx Data Threshold Disable." "0,1" bitfld.long 0x4 14. "TX_OVF,Tx Data MEM Underflow Disable" "0,1" newline bitfld.long 0x4 13. "RSVD0,Reserved." "0,1" bitfld.long 0x4 12. "IBID_THR,IBI Data MEM threshold Disable." "0,1" newline bitfld.long 0x4 11. "IBID_UNF,IBI Data MEM underflow Disable." "0,1" bitfld.long 0x4 10. "IBIR_THR,IBI Response Queue threshold Disable" "0,1" newline bitfld.long 0x4 9. "IBIR_UNF,IBI Response Queue underflow Disable" "0,1" bitfld.long 0x4 8. "IBIR_OVF,IBI Response Queue onverflow Disable." "0,1" newline bitfld.long 0x4 7. "RX_THR,Rx Data MEM threshold Disable." "0,1" bitfld.long 0x4 6. "RX_UNF,Rx Data MEM underflow Disable." "0,1" newline bitfld.long 0x4 5. "CMDD_EMP,Command Request Queue Empty Disable." "0,1" bitfld.long 0x4 4. "CMDD_THR,Command Request Queue Threshold Disable." "0,1" newline bitfld.long 0x4 3. "CMDD_OVF,Command Request Queue Overflow Disable." "0,1" bitfld.long 0x4 2. "CMDR_THR,Command Response Queue Threshold Disable." "0,1" newline bitfld.long 0x4 1. "CMDR_UNF,Command Response Queue Underflow Disable." "0,1" bitfld.long 0x4 0. "CMDR_OVF,Command Response Queue Overflow Disable." "0,1" rgroup.long 0x28++0x3 line.long 0x0 "I3C_MST_IMR,Return to the . This read only register. indicates the current state of the interrupts mask. See Interrupt Status Register - Master Mode () description for details on specific interrupt conditions. A high value indicates the interrupt is.." hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x0 18. "HALTED,Controller in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Mask." "0,1" bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Mask." "0,1" bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Mask." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Mask." "0,1" bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1" bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Mask." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Mask." "0,1" bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Mask." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Mask." "0,1" bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Mask." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Mask." "0,1" bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Mask." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Mask." "0,1" bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Mask." "0,1" group.long 0x2C++0x3 line.long 0x0 "I3C_MST_ICR,Return to the . Interrupt Clear Register for Master Mode of the cdnsi3c_master controller. Write 1 to clear (change from 1 to 0) corresponding bit in . Writing 0 has no effect" hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x0 18. "HALTED,Controller is in halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done Mask." "0,1" bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold Mask." "0,1" bitfld.long 0x0 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold Mask." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow Mask." "0,1" bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1" bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow Mask." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold Mask." "0,1" bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow Mask." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty Mask." "0,1" bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold Mask." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow Mask." "0,1" bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold Mask." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow Mask." "0,1" bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow Mask." "0,1" rgroup.long 0x30++0x3 line.long 0x0 "I3C_MST_ISR,Return to the . Interrupt Status Register for Master Mode of the cdnsi3c_master controller" hexmask.long.word 0x0 19.--31. 1. "RSVD1,Reserved." bitfld.long 0x0 18. "HALTED,Controller in Halted state." "0,1" newline bitfld.long 0x0 17. "MR_DONE,Mastership handoff done." "0,1" bitfld.long 0x0 16. "IMM_COMP,Immediate Commmand Completed" "0,1" newline bitfld.long 0x0 15. "TX_THR,Tx Data Threshold." "0,1" bitfld.long 0x0 14. "TX_OVF,Tx Data MEM overflow" "0,1" newline bitfld.long 0x0 13. "RSVD0,Reserved." "0,1" bitfld.long 0x0 12. "IBID_THR,IBI Data MEM threshold." "0,1" newline bitfld.long 0x0 11. "IBID_UNF,IBI Data MEM underflow." "0,1" bitfld.long 0x0 10. "IBIR_THR,IBI Response Queue threshold" "0,1" newline bitfld.long 0x0 9. "IBIR_UNF,IBI Response Queue underflow" "0,1" bitfld.long 0x0 8. "IBIR_OVF,IBI Response Queue onverflow." "0,1" newline bitfld.long 0x0 7. "RX_THR,Rx Data MEM threshold." "0,1" bitfld.long 0x0 6. "RX_UNF,Rx Data MEM underflow." "0,1" newline bitfld.long 0x0 5. "CMDD_EMP,Command Request Queue Empty." "0,1" bitfld.long 0x0 4. "CMDD_THR,Command Request Queue Threshold." "0,1" newline bitfld.long 0x0 3. "CMDD_OVF,Command Request Queue Overflow." "0,1" bitfld.long 0x0 2. "CMDR_THR,Command Response Queue Threshold." "0,1" newline bitfld.long 0x0 1. "CMDR_UNF,Command Response Queue Underflow." "0,1" bitfld.long 0x0 0. "CMDR_OVF,Command Response Queue Overflow." "0,1" group.long 0x34++0x3 line.long 0x0 "I3C_MST_STATUS0,Return to the . Status Register for I3C Master IP. meaningful only when controller operates in Master mode." hexmask.long.word 0x0 19.--31. 1. "RSVD2,Reserved" rbitfld.long 0x0 18. "IDLE,Indicates when the core is IDLE and ready to accept new commands." "0,1" newline bitfld.long 0x0 17. "HALTED,Core Halted." "0,1" rbitfld.long 0x0 16. "OP_MODE,Indicates current mode of the controller:" "0,1" newline rbitfld.long 0x0 14.--15. "RSVD1,Reserved." "0,1,2,3" rbitfld.long 0x0 13. "TX_FULL,TX Full." "0,1" newline rbitfld.long 0x0 12. "IBID_FULL,IBID Full." "0,1" rbitfld.long 0x0 11. "IBIR_FULL" "0,1" newline rbitfld.long 0x0 10. "RX_FULL,RX Full." "0,1" rbitfld.long 0x0 9. "CMDD_FULL,CMDD Full." "0,1" newline rbitfld.long 0x0 8. "CMDR_FULL" "0,1" rbitfld.long 0x0 6.--7. "RSVD0,Reserved." "0,1,2,3" newline rbitfld.long 0x0 5. "TX_EMP,TX Empty." "0,1" rbitfld.long 0x0 4. "IBID_EMP,IBID Empty." "0,1" newline rbitfld.long 0x0 3. "IBIR_EMP" "0,1" rbitfld.long 0x0 2. "RX_EMP,RX Empty." "0,1" newline rbitfld.long 0x0 1. "CMDD_EMP,CMDD Empty." "0,1" rbitfld.long 0x0 0. "CMDR_EMP" "0,1" rgroup.long 0x38++0x7 line.long 0x0 "I3C_CMDR,Return to the . Stores status on completion of each command. works on FIFO-basis." hexmask.long.byte 0x0 28.--31. 1. "RSVD1,Reserved." hexmask.long.byte 0x0 24.--27. 1. "ERROR,This field contains the code of an error that has occured during the last transaction." newline hexmask.long.byte 0x0 20.--23. 1. "RSVD0,Reserved." hexmask.long.word 0x0 8.--19. 1. "XFER_BYTES,The number of transferred bytes [SDR] or transferred words [DDR] during the last command." newline hexmask.long.byte 0x0 0.--7. 1. "CMD_ID,CMD_ID - command identifier." line.long 0x4 "I3C_IBIR,Return to the . Stores status of SIR on its completion. works on FIFO-basis." hexmask.long.tbyte 0x4 13.--31. 1. "RSVD0,Reserved" bitfld.long 0x4 12. "RESP,If HIGH IBI has been ACKed NACK response otherwise" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "SLV_ID,ID of a Slave that has issued an IBI request" bitfld.long 0x4 7. "ERROR,Set to 1 if IBI Data FIFO overflow has occured during the transaction." "0,1" newline hexmask.long.byte 0x4 2.--6. 1. "XFER_BYTES,Number of received DATA bytes." bitfld.long 0x4 0.--1. "IBI_TYPE,This field contains the type of an IBI." "0,1,2,3" wgroup.long 0x40++0x7 line.long 0x0 "I3C_SLV_IER,Return to the . The write only Interrupt Enable Register is used to enable interrupts by setting bits in the read only Interrupt Mask Register - Slave Mode (). See Interrupt Status Register - Slave Mode () description for details on specific.." hexmask.long.word 0x0 22.--31. 1. "RESERVED" bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Enable." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Enable." "0,1" bitfld.long 0x0 19. "ERROR,ERROR interrupt Enable." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Enable." "0,1" bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Enable." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Enable." "0,1" bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Enable" "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Enable" "0,1" bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Enable" "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Enable." "0,1" bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Enable." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Enable." "0,1" bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Enable." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SLV_SDR_TX_THR interrupt Enable." "0,1" bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Enable." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Enable." "0,1" bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Enable." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Enable." "0,1" bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Enable." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Enable." "0,1" bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Enable." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Enable." "0,1" line.long 0x4 "I3C_SLV_IDR,Return to the . The write only Interrupt Disable Register is used to disable interrupts by clearing the bits in the read only Interrupt Mask Register - Slave Mode (). See Interrupt Status Register - Slave Mode () description for details on.." hexmask.long.word 0x4 22.--31. 1. "RESERVED" bitfld.long 0x4 21. "DEFSLVS,DEFSLVS interrupt Disable." "0,1" newline bitfld.long 0x4 20. "TM,TM interrupt Disable." "0,1" bitfld.long 0x4 19. "ERROR,ERROR interrupt Disable." "0,1" newline bitfld.long 0x4 18. "EVENT_UP,EVENT_UP interrupt Disable." "0,1" bitfld.long 0x4 17. "HJ_DONE,HJ_DONE interrupt Disable." "0,1" newline bitfld.long 0x4 16. "MR_DONE,MR_DONE interrupt Disable." "0,1" bitfld.long 0x4 15. "DA_UPDATE,DA_UPDATE interrupt Disable." "0,1" newline bitfld.long 0x4 14. "SDR_FAIL,SDR_FAIL interrupt Disable" "0,1" bitfld.long 0x4 13. "DDR_FAIL,DDR_FAIL interrupt Disable" "0,1" newline bitfld.long 0x4 12. "M_RD_ABORT,M_RD_ABORT interrupt Disable." "0,1" bitfld.long 0x4 11. "DDR_RX_THR,DDR_RX_THR interrupt Disable." "0,1" newline bitfld.long 0x4 10. "DDR_TX_THR,DDR_TX_THR interrupt Disable." "0,1" bitfld.long 0x4 9. "SDR_RX_THR,SDR_RX_THR interrupt Disable." "0,1" newline bitfld.long 0x4 8. "SDR_TX_THR,SDR_TX_THR interrupt Disable." "0,1" bitfld.long 0x4 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Disable." "0,1" newline bitfld.long 0x4 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Disable." "0,1" bitfld.long 0x4 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Disable." "0,1" newline bitfld.long 0x4 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Disable." "0,1" bitfld.long 0x4 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Disable." "0,1" newline bitfld.long 0x4 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Disable." "0,1" bitfld.long 0x4 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Disable." "0,1" newline bitfld.long 0x4 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Disable." "0,1" rgroup.long 0x48++0x3 line.long 0x0 "I3C_SLV_IMR,Return to the . This read only register. indicates the current state of the interrupts mask. See Interrupt Status Register - Slave Mode () description for details on specific interrupt conditions. A high value indicates the interrupt is.." hexmask.long.word 0x0 22.--31. 1. "RESERVED" bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Mask." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Mask." "0,1" bitfld.long 0x0 19. "ERROR,ERROR interrupt Mask." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Mask." "0,1" bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Mask." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Mask." "0,1" bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Mask." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Mask" "0,1" bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Mask" "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Mask." "0,1" bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Mask." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Mask." "0,1" bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Mask." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SDR_TX_THR interrupt Mask." "0,1" bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Mask." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Mask." "0,1" bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Mask." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Mask." "0,1" bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Mask." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Mask." "0,1" bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Mask." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Mask." "0,1" wgroup.long 0x4C++0x3 line.long 0x0 "I3C_SLV_ICR,Return to the . Interrupt Clear Register for Slave Mode of the cdnsi3c_master controller. Write 1 to clear (change from 1 to 0) corresponding bit in . Writing 0 has no effect" hexmask.long.word 0x0 22.--31. 1. "RESERVED" bitfld.long 0x0 21. "DEFSLVS,DEFSLVS interrupt Clear." "0,1" newline bitfld.long 0x0 20. "TM,TM interrupt Clear." "0,1" bitfld.long 0x0 19. "ERROR,ERROR interrupt Clear." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,EVENT_UP interrupt Clear." "0,1" bitfld.long 0x0 17. "HJ_DONE,HJ_DONE interrupt Clear." "0,1" newline bitfld.long 0x0 16. "MR_DONE,MR_DONE interrupt Clear." "0,1" bitfld.long 0x0 15. "DA_UPDATE,DA_UPDATE interrupt Clear." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,SDR_FAIL interrupt Clear." "0,1" bitfld.long 0x0 13. "DDR_FAIL,DDR_FAIL interrupt Clear." "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,M_RD_ABORT interrupt Clear." "0,1" bitfld.long 0x0 11. "DDR_RX_THR,DDR_RX_THR interrupt Clear." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,DDR_TX_THR interrupt Clear." "0,1" bitfld.long 0x0 9. "SDR_RX_THR,SDR_RX_THR interrupt Clear." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,SDR_TX_THR interrupt Clear." "0,1" bitfld.long 0x0 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Clear." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Clear." "0,1" bitfld.long 0x0 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Clear." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Clear." "0,1" bitfld.long 0x0 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Clear." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Clear." "0,1" bitfld.long 0x0 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Clear." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Clear." "0,1" rgroup.long 0x50++0xB line.long 0x0 "I3C_SLV_ISR,Return to the . Interrupt Status Register for Slave Mode of the cdnsi3c_master controller" hexmask.long.word 0x0 22.--31. 1. "RESERVED" bitfld.long 0x0 21. "DEFSLVS,This interrupt is triggered whenever I3C-Slave DEFSLVS CCC command is received." "0,1" newline bitfld.long 0x0 20. "TM,This interrupt is triggered whenever I3C-Slave is not in Test Mode and ENTTM CCC command with byte value of 0x01 [general Test Mode] is received." "0,1" bitfld.long 0x0 19. "ERROR,This event is triggered whenever SDR Error is detected - applicable for S0 S1 S2 S4 and S5 Errors from MIPI spec." "0,1" newline bitfld.long 0x0 18. "EVENT_UP,This event is triggered whenever DISEC CCC or ENEC CCC is received." "0,1" bitfld.long 0x0 17. "HJ_DONE,This event is triggered whenever Hot-Join request is completed." "0,1" newline bitfld.long 0x0 16. "MR_DONE,This event is triggered whenever Mastership Request is completed." "0,1" bitfld.long 0x0 15. "DA_UPDATE,This event is triggered whenever Dynamic Address of the device has been updated." "0,1" newline bitfld.long 0x0 14. "SDR_FAIL,This event is triggered whenever fail event during SDR transfer is detected [applicable for Private Write transfers only]." "0,1" bitfld.long 0x0 13. "DDR_FAIL,This event is triggered whenever fail event during DDR transfer is detected." "0,1" newline bitfld.long 0x0 12. "M_RD_ABORT,Read Transfer Aborted by Master." "0,1" bitfld.long 0x0 11. "DDR_RX_THR,This event is triggered whenever threshold level for DDR Rx DATA Buffer is reached." "0,1" newline bitfld.long 0x0 10. "DDR_TX_THR,This event is triggered whenever threshold level for DDR Tx DATA Buffer is reached." "0,1" bitfld.long 0x0 9. "SDR_RX_THR,Rx DATA Buffer Threshold." "0,1" newline bitfld.long 0x0 8. "SDR_TX_THR,Tx DATA Buffer Threshold." "0,1" bitfld.long 0x0 7. "DDR_RX_UNF,Set if the host attempts to read from the DDR_RX_FIFO register when there is no more data." "0,1" newline bitfld.long 0x0 6. "DDR_TX_OVF,Set if the host attempts to write to DDR_TX_FIFO register more times than the FIFO depth." "0,1" bitfld.long 0x0 5. "SDR_RX_UNF,Rx DATA Buffer Underflow." "0,1" newline bitfld.long 0x0 4. "SDR_TX_OVF,Tx DATA Buffer Overflow." "0,1" bitfld.long 0x0 3. "DDR_RD_COMP,This bit is set whenever the Slave terminates the DDR Read transfer." "0,1" newline bitfld.long 0x0 2. "DDR_WR_COMP,This bit is set whenever the Master terminates the DDR Write transfer." "0,1" bitfld.long 0x0 1. "SDR_RD_COMP,This bit is set whenever the Slave terminates the SDR Private Read transfer." "0,1" newline bitfld.long 0x0 0. "SDR_WR_COMP,This bit is set whenever the Master terminates the SDR Private Write transfer." "0,1" line.long 0x4 "I3C_SLV_STATUS0,Return to the . The read only Status 0 register () is provided to enable the continuous monitoring of the raw unmasked status information of the I3C-Master operating in Slave mode." hexmask.long.byte 0x4 24.--31. 1. "RSVD0,Reserved" hexmask.long.byte 0x4 16.--23. 1. "REG_ADDR,Private Read/Write Address." newline hexmask.long.word 0x4 0.--15. 1. "XFERRED_BYTES,Number of transferred bytes in SDR transactions." line.long 0x8 "I3C_SLV_STATUS1,Return to the . The read only Status 1 register () is provided to enable the continuous monitoring of the raw unmasked status information of the I3C-Master operating in Slave mode." hexmask.long.word 0x8 22.--31. 1. "RSVD1,Reserved" bitfld.long 0x8 20.--21. "ENTAS,Bits that indicate current Activity State." "0,1,2,3" newline bitfld.long 0x8 19. "VEN_TM,Vendor Test Mode." "0,1" bitfld.long 0x8 18. "HJ_DIS,Hot-Join Disabled." "0,1" newline bitfld.long 0x8 17. "MR_DIS,This bit is set whenever MR request is disabled by Current I3C-Master using DISEC CCC." "0,1" bitfld.long 0x8 16. "PROT_ERROR,Protocol Error Condition Indicator." "0,1" newline hexmask.long.byte 0x8 9.--15. 1. "DA,Slave Dynamic Address." bitfld.long 0x8 8. "HAS_DA,This bit is set whenever Slave has Dynamic Address assigned." "0,1" newline bitfld.long 0x8 7. "DDRRX_FULL,This bit is set whenever" "0,1" bitfld.long 0x8 6. "DDRTX_FULL,This bit is set whenever" "0,1" newline bitfld.long 0x8 5. "DDRRX_EMPTY,This bit is set whenever" "0,1" bitfld.long 0x8 4. "DDRTX_EMPTY,This bit is set whenever" "0,1" newline bitfld.long 0x8 3. "SDRRX_FULL,This bit is set whenever SDR_RX_FIFO is full." "0,1" bitfld.long 0x8 2. "SDRTX_FULL,This bit is set whenever SDR_TX_FIFO is full." "0,1" newline bitfld.long 0x8 1. "SDRRX_EMPTY,This bit is set whenever SDR_RX_FIFO is empty." "0,1" bitfld.long 0x8 0. "SDRTX_EMPTY,This bit is set whenever SDR_TX_FIFO is empty." "0,1" wgroup.long 0x60++0x3 line.long 0x0 "I3C_CMD0_FIFO,Return to the . Command0 FIFO. When implemented. the commands will be executed sequentially in order of arrival from the FW." bitfld.long 0x0 31. "IS_DDR,IS_DDR - DDR command." "0,1" bitfld.long 0x0 30. "IS_CCC,IsCCC." "0,1" newline bitfld.long 0x0 29. "BCH,BCH - Broadcast Header." "0,1" bitfld.long 0x0 27.--28. "XMIT_MODE,Defines transfer modes for I3C private read/write commands [not CCC] the following options are available:" "0,1,2,3" newline bitfld.long 0x0 26. "SBCA,SBCA - Sixteen Bits CSR Addressing." "0,1" bitfld.long 0x0 25. "RSBC,RSBC - Repeated Start Between Commands." "0,1" newline bitfld.long 0x0 24. "IS10B,Is10B - Normal/Extended Address." "0,1" hexmask.long.word 0x0 12.--23. 1. "PL_LEN,PL_LEN - Payload Length." newline bitfld.long 0x0 11. "RESERVED" "0,1" bitfld.long 0x0 8.--10. "DEV_ADDR_MSB,DEV_ADDR_MSB - legacy I2C Extended Address." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address." bitfld.long 0x0 0. "RNW,RnW - Read no Write." "0,1" group.long 0x64++0x3 line.long 0x0 "I3C_CMD1_FIFO,Return to the . Command 1 FIFO. When implemented. the commands will be executed sequentially in order of arrival from the FW." hexmask.long.byte 0x0 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]." hexmask.long.byte 0x0 16.--23. 1. "RSVD0,Reserved" newline hexmask.long.byte 0x0 8.--15. 1. "CSRADDR1,CSR ADDR" hexmask.long.byte 0x0 0.--7. 1. "CCC_CSRADDR0,CCC/CSR ADDR" wgroup.long 0x68++0x3 line.long 0x0 "I3C_TX_FIFO,Return to the . Tx Data FIFO which stores number of bytes to be sent with particular command. APB->I3C direction" hexmask.long 0x0 0.--31. 1. "DATA,Tx Data FIFO which stores number of bytes to be sent with particular command" wgroup.long 0x70++0x3 line.long 0x0 "I3C_IMD_CMD0,Return to the . High priority command register. When the core currently is executing a particular command from the CMD FIFO and new immediate command is sent. the core finish the standard command and then will execute the immediate command..." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED" bitfld.long 0x0 12.--14. "PL_LEN,PL_LEN - Payload Length." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address." newline bitfld.long 0x0 0. "RNW,RnW - Read no Write." "0,1" group.long 0x74++0x7 line.long 0x0 "I3C_IMD_CMD1,Return to the . High priority command register. When the core currently is executing a particular command from the CMD FIFO and new immediate command is sent. the core finish the standard command and then will execute the immediate command..." hexmask.long.byte 0x0 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]." hexmask.long.word 0x0 8.--23. 1. "RSVD0,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "CCC,CCC code" line.long 0x4 "I3C_IMD_DATA,Return to the . Payload/Data for a particular immediate command." hexmask.long 0x4 0.--31. 1. "DATA,Payload/Data for a particular immediate command." rgroup.long 0x80++0x7 line.long 0x0 "I3C_RX_FIFO,Return to the . Rx Data FIFO which stores number of bytes to be received with particular command. I3C->APB direction" hexmask.long 0x0 0.--31. 1. "DATA,Rx Data FIFO which stores number of bytes to be received with particular command." line.long 0x4 "I3C_IBI_DATA_FIFO,Return to the . IBI Data FIFO which stores number of bytes to be received for particular IBI request when BCR[2]=1 I3C->APB direction" hexmask.long 0x4 0.--31. 1. "DATA,IBI Data FIFO which stores number of bytes to be received for particular IBI request." wgroup.long 0x88++0x3 line.long 0x0 "I3C_SLV_DDR_TX_FIFO,Return to the . DDR Tx Data FIFO stores number of words to be sent with particular DDR command in slave mode. APB->I3C direction" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "DDR_SLAVE_TX_DATA_FIFO,DDR Tx Data FIFO stores number of words to be sent with particular DDR command in slave mode" rgroup.long 0x8C++0x3 line.long 0x0 "I3C_SLV_DDR_RX_FIFO,Return to the . DDR Rx Data FIFO stores number of words to be received with particular DDR command in slave mode. APB->I3C direction" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--19. 1. "DDR_SLAVE_RX_DATA_FIFO,DDR Rx Data FIFO stores number of words to be received with particular DDR command in slave mode" group.long 0x90++0xB line.long 0x0 "I3C_CMD_IBI_THR_CTRL,Return to the . Configuration register for Command and In-Band Interrupt data buffer thresholds." rbitfld.long 0x0 30.--31. "RSVD3,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "IBIR_THR,Threshold configuration value for IBI RESP memory block" newline rbitfld.long 0x0 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "CMDR_THR,Threshold configuration value for Command RESP memory block" newline rbitfld.long 0x0 14.--15. "RSVD1,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "IBID_THR,Threshold configuration value for IBI DATA memory block" newline rbitfld.long 0x0 5.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "CMDD_THR,Threshold configuration value for Command REQ memory block" line.long 0x4 "I3C_TX_RX_THR_CTRL,Return to the . Configuration register for Tx and Rx data buffer thresholds." hexmask.long.word 0x4 16.--31. 1. "RX_THR,Threshold configuration value for Rx Data memory block" hexmask.long.word 0x4 0.--15. 1. "TX_THR,Threshold configuration value for Tx Data memory block" line.long 0x8 "I3C_SLV_DDR_TX_RX_THR_CTRL,Return to the . Configuration register for Tx and Rx thresholds associated with Slave Mode DDR Data memory blocks." hexmask.long.word 0x8 16.--31. 1. "SLV_DDR_RX_THR,Threshold configuration value for Slave Mode DDR Rx Data memory block" hexmask.long.word 0x8 0.--15. 1. "SLV_DDR_TX_THR,Threshold configuration value for Slave Mode DDR Tx Data memory block" wgroup.long 0x9C++0x3 line.long 0x0 "I3C_FLUSH_CTRL,Return to the . Control register for FIFO soft flush control" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "IBI_RESP_FLUSH,When asserted while controller is disabled the IBI Response Queue read/write pointers will be set to 0 effectively make the FIFO empty." "0,1" newline bitfld.long 0x0 23. "CMD_RESP_FLUSH,When asserted while controller is disabled the Command Response Queue read/write pointers will be set to 0 effectively make the FIFO empty." "0,1" bitfld.long 0x0 22. "SLV_DDR_RX_FLUSH,When asserted while controller is disabled the SLV DDR Rx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty." "0,1" newline bitfld.long 0x0 21. "SLV_DDR_TX_FLUSH,When asserted while controller is disabled the SLV DDR Tx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty." "0,1" bitfld.long 0x0 20. "IMM_CMD_FLUSH,When asserted while controller is disabled the immediate command/data register will be cleared." "0,1" newline bitfld.long 0x0 19. "IBI_FLUSH,When asserted while controller is disabled the IBI data memory block read/write pointers will be set to 0." "0,1" bitfld.long 0x0 18. "RX_FLUSH,When asserted while controller is disabled the Rx Data memory block read/write pointers will be set to 0." "0,1" newline bitfld.long 0x0 17. "TX_FLUSH,When asserted while controller is disabled the Tx Data memory block read/write pointers will be set to 0." "0,1" bitfld.long 0x0 16. "CMD_FLUSH,When asserted while controller is disabled the command Command memory block read/write pointers will be set to 0." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED" group.long 0xB0++0xB line.long 0x0 "I3C_TTO_PRESCL_CTRL0,Return to the . Prescale settings for First SCL high timeout detection" hexmask.long.byte 0x0 26.--31. 1. "RSVD1,Reserved" hexmask.long.word 0x0 16.--25. 1. "DIV_B,Divider B" newline hexmask.long.byte 0x0 11.--15. 1. "RSVD0,Reserved" hexmask.long.word 0x0 0.--10. 1. "DIV_A,Divider A" line.long 0x4 "I3C_TTO_PRESCL_CTRL1,Return to the . Prescale settings for SCL high and low timeout detection" hexmask.long.byte 0x4 26.--31. 1. "RSVD1,Reserved" hexmask.long.word 0x4 16.--25. 1. "DIV_B,Divider B" newline hexmask.long.byte 0x4 8.--15. 1. "RSVD0,Reserved" hexmask.long.byte 0x4 0.--7. 1. "DIV_A,Divider A" line.long 0x8 "I3C_DEVS_CTRL,Return to the . Device control register" hexmask.long.byte 0x8 28.--31. 1. "RSVD1,Reserved." bitfld.long 0x8 27. "DEV11_CLR,Clear DevID11 retaining registers set." "0,1" newline bitfld.long 0x8 26. "DEV10_CLR,Clear DevID10 retaining registers set." "0,1" bitfld.long 0x8 25. "DEV9_CLR,Clear DevID9 retaining registers set." "0,1" newline bitfld.long 0x8 24. "DEV8_CLR,Clear DevID8 retaining registers set." "0,1" bitfld.long 0x8 23. "DEV7_CLR,Clear DevID7 retaining registers set." "0,1" newline bitfld.long 0x8 22. "DEV6_CLR,Clear DevID6 retaining registers set." "0,1" bitfld.long 0x8 21. "DEV5_CLR,Clear DevID5 retaining registers set." "0,1" newline bitfld.long 0x8 20. "DEV4_CLR,Clear DevID4 retaining registers set." "0,1" bitfld.long 0x8 19. "DEV3_CLR,Clear DevID3 retaining registers set." "0,1" newline bitfld.long 0x8 18. "DEV2_CLR,Clear DevID2 retaining registers set." "0,1" bitfld.long 0x8 17. "DEV1_CLR,Clear DevID1 retaining registers set." "0,1" newline hexmask.long.byte 0x8 12.--16. 1. "RSVD0,Reserved." bitfld.long 0x8 11. "DEV11_ACTIVE,DevID11 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 10. "DEV10_ACTIVE,DevID10 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 9. "DEV9_ACTIVE,DevID9 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 8. "DEV8_ACTIVE,DevID8 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 7. "DEV7_ACTIVE,DevID7 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 6. "DEV6_ACTIVE,DevID6 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 5. "DEV5_ACTIVE,DevID5 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 4. "DEV4_ACTIVE,DevID4 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 3. "DEV3_ACTIVE,DevID3 is active - has either valid DA or SA." "0,1" newline bitfld.long 0x8 2. "DEV2_ACTIVE,DevID2 is active - has either valid DA or SA." "0,1" bitfld.long 0x8 1. "DEV1_ACTIVE,DevID1 is active - has either valid DA or SA." "0,1" newline rbitfld.long 0x8 0. "DEV0_ACTIVE,DevID0 is active - has either valid DA or SA." "0,1" group.long 0xC0++0xB line.long 0x0 "I3C_DEV_ID0_RR0,Return to the . Device ID 0 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 0 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" rbitfld.long 0x0 9. "IS_I3C,Device 0 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 0 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID0_RR1,Return to the . Device ID 0 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 0 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID0_RR2,Return to the . Device ID 0 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 0 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 0 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 0 DCR [if I3C device] or LVR [if I2C device] register" group.long 0xD0++0xB line.long 0x0 "I3C_DEV_ID1_RR0,Return to the . Device ID 1 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 1 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 1 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 1 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID1_RR1,Return to the . Device ID 1 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 1 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID1_RR2,Return to the . Device ID 1 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 1 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 1 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 1 DCR [if I3C device] or LVR [if I2C device] register" group.long 0xE0++0xB line.long 0x0 "I3C_DEV_ID2_RR0,Return to the . Device ID 2 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 2 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 2 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 2 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID2_RR1,Return to the . Device ID 2 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 2 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID2_RR2,Return to the . Device ID 2 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 2 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 2 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 2 DCR [if I3C device] or LVR [if I2C device] register" group.long 0xF0++0xB line.long 0x0 "I3C_DEV_ID3_RR0,Return to the . Device ID 3 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 3 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 3 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 3 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID3_RR1,Return to the . Device ID 3 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 3 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID3_RR2,Return to the . Device ID 3 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 3 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 3 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 3 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x100++0xB line.long 0x0 "I3C_DEV_ID4_RR0,Return to the . Device ID 4 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 4 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 4 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 4 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID4_RR1,Return to the . Device ID 4 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 4 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID4_RR2,Return to the . Device ID 4 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 4 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 4 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 4 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x110++0xB line.long 0x0 "I3C_DEV_ID5_RR0,Return to the . Device ID 5 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 5 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 5 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 5 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID5_RR1,Return to the . Device ID 5 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 5 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID5_RR2,Return to the . Device ID 5 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 5 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 5 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 5 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x120++0xB line.long 0x0 "I3C_DEV_ID6_RR0,Return to the . Device ID 6 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 6 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 6 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 6 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID6_RR1,Return to the . Device ID 6 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 6 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID6_RR2,Return to the . Device ID 6 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 6 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 6 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 6 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x130++0xB line.long 0x0 "I3C_DEV_ID7_RR0,Return to the . Device ID 7 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 7 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 7 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 7 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID7_RR1,Return to the . Device ID 7 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 7 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID7_RR2,Return to the . Device ID 7 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 7 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 7 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 7 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x140++0xB line.long 0x0 "I3C_DEV_ID8_RR0,Return to the . Device ID 8 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 8 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 8 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 8 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID8_RR1,Return to the . Device ID 8 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 8 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID8_RR2,Return to the . Device ID 8 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 8 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 8 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 8 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x150++0xB line.long 0x0 "I3C_DEV_ID9_RR0,Return to the . Device ID 9 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 9 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 9 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 9 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID9_RR1,Return to the . Device ID 9 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 9 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID9_RR2,Return to the . Device ID 9 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 9 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 9 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 9 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x160++0xB line.long 0x0 "I3C_DEV_ID10_RR0,Return to the . Device ID 10 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 10 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 10 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 10 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID10_RR1,Return to the . Device ID 10 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 10 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID10_RR2,Return to the . Device ID 10 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 10 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 10 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 10 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x170++0xB line.long 0x0 "I3C_DEV_ID11_RR0,Return to the . Device ID 11 Retaining Register 0 : Configuration Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 12. "RSVD2,Reserved" "0,1" bitfld.long 0x0 11. "LVR_EXT_ADDR,Device 11 Address mode used:" "0,1" newline rbitfld.long 0x0 10. "RSVD1,Reserved" "0,1" bitfld.long 0x0 9. "IS_I3C,Device 11 I3C mode Operation" "0,1" newline rbitfld.long 0x0 8. "RSVD0,Reserved" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DEV_ADDR,Device 11 Slave Dynamic [Static/Legacy] Address bits" line.long 0x4 "I3C_DEV_ID11_RR1,Return to the . Device ID 11 Retaining Register 1 : Provisional ID MSB 32-bits" hexmask.long 0x4 0.--31. 1. "PID_MSB,Device 11 48 to 16 Dev ID bits" line.long 0x8 "I3C_DEV_ID11_RR2,Return to the . Device ID 11 Retaining Register 2 : Provisional ID LSB 16-bits. BCR. DCR or LVR (for legacy Mode)" hexmask.long.word 0x8 16.--31. 1. "PID_LSB,Device 11 15 to 0 Dev ID bits" hexmask.long.byte 0x8 8.--15. 1. "BCR,Device 11 BCR register" newline hexmask.long.byte 0x8 0.--7. 1. "DCR_LVR,Device 11 DCR [if I3C device] or LVR [if I2C device] register" group.long 0x180++0x17 line.long 0x0 "I3C_SIR_MAP0,Return to the . Slave-initiated request Device ID Detection register0" bitfld.long 0x0 30.--31. "DEVID1_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3" bitfld.long 0x0 29. "DEVID1_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "DEVID1_PL,Slave-initiated request Device ID0 payload length" hexmask.long.byte 0x0 17.--23. 1. "DEVID1_DA,Slave-initiated request Device ID0 DA" newline bitfld.long 0x0 16. "DEVID1_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1" bitfld.long 0x0 14.--15. "DEVID0_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3" newline bitfld.long 0x0 13. "DEVID0_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x0 8.--12. 1. "DEVID0_PL,Slave-initiated request Device ID0 payload length" newline hexmask.long.byte 0x0 1.--7. 1. "DEVID0_DA,Slave-initiated request Device ID0 DA" bitfld.long 0x0 0. "DEVID0_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1" line.long 0x4 "I3C_SIR_MAP1,Return to the . Slave-initiated request Device ID Detection register1" bitfld.long 0x4 30.--31. "DEVID3_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3" bitfld.long 0x4 29. "DEVID3_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0x4 24.--28. 1. "DEVID3_PL,Slave-initiated request Device ID2 payload length" hexmask.long.byte 0x4 17.--23. 1. "DEVID3_DA,Slave-initiated request Device ID2 DA" newline bitfld.long 0x4 16. "DEVID3_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1" bitfld.long 0x4 14.--15. "DEVID2_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3" newline bitfld.long 0x4 13. "DEVID2_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x4 8.--12. 1. "DEVID2_PL,Slave-initiated request Device ID2 payload length" newline hexmask.long.byte 0x4 1.--7. 1. "DEVID2_DA,Slave-initiated request Device ID2 DA" bitfld.long 0x4 0. "DEVID2_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1" line.long 0x8 "I3C_SIR_MAP2,Return to the . Slave-initiated request Device ID Detection register2" bitfld.long 0x8 30.--31. "DEVID5_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3" bitfld.long 0x8 29. "DEVID5_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0x8 24.--28. 1. "DEVID5_PL,Slave-initiated request Device ID4 payload length" hexmask.long.byte 0x8 17.--23. 1. "DEVID5_DA,Slave-initiated request Device ID4 DA" newline bitfld.long 0x8 16. "DEVID5_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1" bitfld.long 0x8 14.--15. "DEVID4_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3" newline bitfld.long 0x8 13. "DEVID4_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x8 8.--12. 1. "DEVID4_PL,Slave-initiated request Device ID4 payload length" newline hexmask.long.byte 0x8 1.--7. 1. "DEVID4_DA,Slave-initiated request Device ID4 DA" bitfld.long 0x8 0. "DEVID4_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1" line.long 0xC "I3C_SIR_MAP3,Return to the . Slave-initiated request Device ID Detection register3" bitfld.long 0xC 30.--31. "DEVID7_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3" bitfld.long 0xC 29. "DEVID7_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0xC 24.--28. 1. "DEVID7_PL,Slave-initiated request Device ID6 payload length" hexmask.long.byte 0xC 17.--23. 1. "DEVID7_DA,Slave-initiated request Device ID6 DA" newline bitfld.long 0xC 16. "DEVID7_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1" bitfld.long 0xC 14.--15. "DEVID6_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3" newline bitfld.long 0xC 13. "DEVID6_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1" hexmask.long.byte 0xC 8.--12. 1. "DEVID6_PL,Slave-initiated request Device ID6 payload length" newline hexmask.long.byte 0xC 1.--7. 1. "DEVID6_DA,Slave-initiated request Device ID6 DA" bitfld.long 0xC 0. "DEVID6_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1" line.long 0x10 "I3C_SIR_MAP4,Return to the . Slave-initiated request Device ID Detection register4" bitfld.long 0x10 30.--31. "DEVID9_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3" bitfld.long 0x10 29. "DEVID9_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1" newline hexmask.long.byte 0x10 24.--28. 1. "DEVID9_PL,Slave-initiated request Device ID8 payload length" hexmask.long.byte 0x10 17.--23. 1. "DEVID9_DA,Slave-initiated request Device ID8 DA" newline bitfld.long 0x10 16. "DEVID9_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1" bitfld.long 0x10 14.--15. "DEVID8_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3" newline bitfld.long 0x10 13. "DEVID8_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x10 8.--12. 1. "DEVID8_PL,Slave-initiated request Device ID8 payload length" newline hexmask.long.byte 0x10 1.--7. 1. "DEVID8_DA,Slave-initiated request Device ID8 DA" bitfld.long 0x10 0. "DEVID8_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1" line.long 0x14 "I3C_SIR_MAP5,Return to the . Slave-initiated request Device ID Detection register5" hexmask.long.word 0x14 16.--31. 1. "RESERVED" bitfld.long 0x14 14.--15. "DEVID10_ROLE,Slave-initiated request Device ID10 BCR role" "0,1,2,3" newline bitfld.long 0x14 13. "DEVID10_SLOW,Slave-initiated request Device ID10 Max Data Speed Limitation" "0,1" hexmask.long.byte 0x14 8.--12. 1. "DEVID10_PL,Slave-initiated request Device ID10 payload length" newline hexmask.long.byte 0x14 1.--7. 1. "DEVID10_DA,Slave-initiated request Device ID10 DA" bitfld.long 0x14 0. "DEVID10_RESP,Slave-initiated request Device ID10 Ack/Nack response" "0,1" rgroup.long 0x1A0++0x3 line.long 0x0 "I3C_GPIR_WORD0,Return to the . User Defined GPI Word 0: four 8-bits GPI Registers" hexmask.long.byte 0x0 24.--31. 1. "RSVD2,Reserved" hexmask.long.byte 0x0 16.--23. 1. "RSVD1,Reserved" newline hexmask.long.byte 0x0 8.--15. 1. "RSVD0,Reserved" hexmask.long.byte 0x0 0.--7. 1. "GPI0,User Defined GPI Register 0" rgroup.long 0x220++0x3 line.long 0x0 "I3C_GPOR_WORD0,Return to the . User Defined GPO Word 0: four 8-bits GPO Registers" hexmask.long.byte 0x0 24.--31. 1. "RSVD2,Reserved" hexmask.long.byte 0x0 16.--23. 1. "RSVD1,Reserved" newline hexmask.long.byte 0x0 8.--15. 1. "RSVD0,Reserved" hexmask.long.byte 0x0 0.--7. 1. "GPO0,User Defined GPO Register 0" group.long 0x300++0x13 line.long 0x0 "I3C_ASF_INT_STATUS,Return to the . ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the asf_fatal or.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "I3C_ASF_INT_RAW_STATUS,Return to the . ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both registers. For test.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "I3C_ASF_INT_MASK,Return to the . The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "I3C_ASF_INT_TEST,Return to the . The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "I3C_ASF_FATAL_NONFATAL_SELECT,Return to the . The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then fatal interrupt.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x320++0x7 line.long 0x0 "I3C_ASF_SRAM_CORR_FAULT_STATUS,Return to the . Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "I3C_ASF_SRAM_UNCORR_FAULT_STATUS,Return to the . Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." group.long 0x328++0x3 line.long 0x0 "I3C_ASF_SRAM_FAULT_STATS,Return to the . Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented." hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented." group.long 0x330++0xB line.long 0x0 "I3C_ASF_TRANS_TO_CTRL,Return to the . Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "I3C_ASF_TRANS_TO_FAULT_MASK,Return to the . Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The width.." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x4 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask bit for apb transaction timeout fault." "0,1" newline bitfld.long 0x4 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask bit for I3C transaction SCL low timeout fault." "0,1" bitfld.long 0x4 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask bit for I3C transaction SCL high timeout fault." "0,1" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask bit for I3C transaction first SCL high timeout fault." "0,1" line.long 0x8 "I3C_ASF_TRANS_TO_FAULT_STATUS,Return to the . Status register for transaction timeouts fault. If a fault occurs the relevant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x8 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for apb transaction timeout fault." "0,1" newline bitfld.long 0x8 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for I3C transaction SCL low timeout fault." "0,1" bitfld.long 0x8 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for I3C transaction SCL high timeout fault." "0,1" newline bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for I3C transaction first SCL high timeout fault." "0,1" group.long 0x340++0x7 line.long 0x0 "I3C_ASF_PROTOCOL_FAULT_MASK,Return to the . Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The width of this.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x0 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_MASK,Mask bit for slv_sdr_rd_abort protocol fault source." "0,1" newline bitfld.long 0x0 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_MASK,Mask bit for slv_ddr_fail protocol fault source." "0,1" bitfld.long 0x0 10. "ASF_PROTOCOL_FAULT_S5_MASK,Mask bit for s5 protocol fault source." "0,1" newline bitfld.long 0x0 9. "ASF_PROTOCOL_FAULT_S4_MASK,Mask bit for s4 protocol fault source." "0,1" bitfld.long 0x0 8. "ASF_PROTOCOL_FAULT_S3_MASK,Mask bit for s3 protocol fault source." "0,1" newline bitfld.long 0x0 7. "ASF_PROTOCOL_FAULT_S2_MASK,Mask bit for s2 protocol fault source." "0,1" bitfld.long 0x0 6. "ASF_PROTOCOL_FAULT_S1_MASK,Mask bit for s1 protocol fault source." "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_FAULT_S0_MASK,Mask bit for s0 protocol fault source." "0,1" bitfld.long 0x0 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_MASK,Mask bit for mst_sdr_rd_abort protocol fault source." "0,1" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_MASK,Mask bit for mst_ddr_fail protocol fault source." "0,1" bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_M2_MASK,Mask bit for m2 protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_M1_MASK,Mask bit for m1 protocol fault source." "0,1" bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_M0_MASK,Mask bit for m0 protocol fault source." "0,1" line.long 0x4 "I3C_ASF_PROTOCOL_FAULT_STATUS,Return to the . Status register for protocol faults. If a fault occurs the relevant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved read as 0 ignored on write." bitfld.long 0x4 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_STATUS,Status bit for slv_sdr_rd_abort protocol fault." "0,1" newline bitfld.long 0x4 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_STATUS,Status bit for slv_ddr_fail protocol fault." "0,1" bitfld.long 0x4 10. "ASF_PROTOCOL_FAULT_S5_STATUS,Status bit for s5 protocol fault." "0,1" newline bitfld.long 0x4 9. "ASF_PROTOCOL_FAULT_S4_STATUS,Status bit for s4 protocol fault." "0,1" bitfld.long 0x4 8. "ASF_PROTOCOL_FAULT_S3_STATUS,Status bit for s3 protocol fault." "0,1" newline bitfld.long 0x4 7. "ASF_PROTOCOL_FAULT_S2_STATUS,Status bit for s2 protocol fault." "0,1" bitfld.long 0x4 6. "ASF_PROTOCOL_FAULT_S1_STATUS,Status bit for s1 protocol fault." "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_FAULT_S0_STATUS,Status bit for s0 protocol fault." "0,1" bitfld.long 0x4 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_STATUS,Status bit for mst_sdr_rd_abort protocol fault." "0,1" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_STATUS,Status bit for mst_ddr_fail protocol fault." "0,1" bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_M2_STATUS,Status bit for m2 protocol fault." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_M1_STATUS,Status bit for m1 protocol fault." "0,1" bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_M0_STATUS,Status bit for m0 protocol fault." "0,1" tree.end tree.end tree "MCU_MCAN" tree "MCU_MCAN0_CFG" base ad:0x40528000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCU_MCAN0_ECC_AGGR" base ad:0x40700000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCU_MCAN0_SS" base ad:0x40520000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree "MCU_MCAN1_CFG" base ad:0x40568000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_CREL,Core Release Register Release dependent constant (version + date)." hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded." line.long 0x4 "MCAN_ENDN,Endian Register Constant 8765 4321h." hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 8765 4321h." group.long 0xC++0x23 line.long 0x0 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation 0h = Transmitter Delay Compensation disabled 1h = Transmitter Delay Compensation enabled" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual.." rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "MCAN_TEST,Test Register Test mode selection. Write access to the register has to be enabled by setting the [7] TEST bit. All register functions are set to their reset values when the [7] TEST bit is reset. Loopback Mode and software control of the MCAN.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" rbitfld.long 0x4 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin 0h = The CAN bus is dominant (MCAN RX = 0h) 1h = The CAN bus is recessive (MCAN RX = 1h)" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin 0h = Reset value the MCAN TX pin controlled by the CAN Core updated at the end of the CAN bit time 1h = Sample Point can be monitored at the MCAN TX pin 2h = Dominant ('0') level at the MCAN TX pin 3h = Recessive ('1') at the.." "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loopback Mode 0h = Reset value Loopback Mode is disabled 1h = Loopback Mode is enabled (see Test Modes)" "0,1" hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" line.long 0x8 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the [7-0] WDC field. The counter.." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled." line.long 0xC "MCAN_CCCR,CC Control Register Operation mode configuration. For details about setting and resetting of single bits. see . Software Initialization." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "NISO,Non ISO Operation 0h = CAN FD frame format according to ISO 11898-1:2015. 1h = CAN FD frame format according to Bosch CAN FD Specification 1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling) . 0h = Transmit pause disabled 1h = Transmit pause enabled" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration 0h = Edge filtering disabled 1h = Two consecutive dominant t" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable 0h = Protocol exception handling enabled 1h = Protocol exception handling disabled Note:When protocol exception handling is disabled the MCAN module will transmit an error frame when it detects a protocol.." "0,1" rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable 0h = Bit rate switching for transmissions disabled 1h = Bit rate switching for transmissions enabled Note:When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h the MCAN_CCCR[9] BRSE bit is not evaluated." "0,1" newline bitfld.long 0xC 8. "FDOE,FD Operation Enable 0h = FD operation disabled 1h = FD operation enabled" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable 0h = Normal operation. The 1h = Test Mode. Write access to the" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission 0h = Automatic retransmission of messages not transmitted successfully enabled 1h = Automatic retransmission disabled" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode The 0h = Bus Monitoring Mode is disabled 1h = Bus Monitoring Mode is enabled" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request 0h = No clock stop is requested 1h = Clock stop requested. When clock stop is requested first the" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge 0h = No clock stop acknowledged 1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode The 0h = Normal CAN operation 1h = Restricted Operation Mode active" "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable 0h = The Host CPU has no write access to the protected configuration registers 1h = The Host CPU has write access to the protected configuration registers (while the" "0,1" bitfld.long 0xC 0. "INIT,Initialization 0h = Normal Operation 1h = Initialization is started Note:Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the.." "0,1" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing. This register is only writable if the [1] CCE and [0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN.." hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used." rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Note:With a CAN clock (MCAN functional clock) of 8 MHz .." line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector. For a description of the Timestamp Counter. see . Timestamp Generation." hexmask.long.word 0x14 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x14 2.--15. 1. "RESERVED,Reserved" bitfld.long 0x14 0.--1. "TSS,Timestamp Select 0h = Timestamp counter value always 0h 1h = Timestamp counter value incremented according to the 2h = External timestamp counter value used 3h = Same as 0h" "0,1,2,3" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter." hexmask.long.word 0x18 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the [1-16] depending on the configuration of the Write access resets the counter to zero. When the Note:A 'wrap around' is a change.." line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode. For a description of the Timeout Counter. see . Timeout Counter." hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period." hexmask.long.word 0x1C 3.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to the 0h = Continuous operation 1h = Timeout controlled by Tx Event FIFO 2h = Timeout controlled by Rx FIFO 0 3h = Timeout controlled by Rx FIFO 1" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter 0h = Timeout Counter disabled 1h = Timeout Counter enabled" "0,1" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter." hexmask.long.word 0x20 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the" bitfld.long 0x0 15. "RP,Receive Error Passive 0h = The Receive Error Counter is below the error passive level of 128 1h = The Receive Error Counter has reached the error passive level of 128" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255. Note:When the MCAN_CCCR[2] ASM bit is set the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN.." line.long 0x4 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value." hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the" bitfld.long 0x4 15. "RESERVED,Reserved" "0,1" bitfld.long 0x4 14. "PXE,Protocol Exception Event 0h = No protocol exception event occurred since last read access 1h = Protocol exception event occurred" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering. 0h = Since this bit was reset by the Host CPU no CAN FD message has been received 1h = Message in CAN FD format with FDF flag set has been received" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its BRS flag set 1h = Last received CAN FD message had its BRS flag set" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with the 0h = Last received CAN FD message did not have its ESI flag set 1h = Last received CAN FD message had its ESI flag set" "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status 0h = The MCAN module is not Bus_Off 1h = The MCAN module is in Bus_Off state" "0,1" bitfld.long 0x4 6. "EW,Warning Status 0h = Both error counters are below the Error_Warning limit of 96 1h = At least one of error counter has reached the Error_Warning limit of 96" "0,1" bitfld.long 0x4 5. "EP,Error Passive 0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1h = The MCAN module is in the Error_Passive state" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity Monitors the module's CAN communication state. 0h = Synchronizing - node is synchronizing on CAN communication 1h = Idle - node is neither receiver nor transmitter 2h = Receiver - node is operating as receiver 3h = Transmitter - node is.." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code The 0h = No Error: No error occurred since the 1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2h = Form Error: A fixed format part of a received frame.." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh)." rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled.." group.long 0x50++0xF line.long 0x0 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no.." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "ARA,Access to Reserved Address 0h = No access to reserved address occurred 1h = Access to reserved address occurred" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase 0h = No protocol error in data phase 1h = Protocol error in data phase detected (" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase 0h = No protocol error in arbitration phase 1h = Protocol error in arbitration phase detected (" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt 0h = No Message RAM Watchdog event occurred 1h = Message RAM Watchdog event due to missing READY" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status 0h = Bus_Off status unchanged 1h = Bus_Off status changed" "0,1" bitfld.long 0x0 24. "EW,Warning Status 0h = Error_Warning status unchanged 1h = Error_Warning status changed" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive 0h = Error_Passive status unchanged 1h = Error_Passive status changed" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow 0h = CAN Error Logging Counter did not overflow 1h = Overflow of CAN Error Logging Counter occurred" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the 0h = No bit error detected when reading from.." "0,1" rbitfld.long 0x0 20. "RESERVED,Reserved" "0,1" bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0h = No Rx Buffer updated 1h = At least one received message stored into an Rx Buffer" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred 0h = No timeout 1h = Timeout reached" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound 0h = No timestamp counter wrap-around 1h = Timestamp counter wrapped around" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached 0h = Tx Event FIFO fill level below watermark 1h = Tx Event FIFO fill level reached watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry 0h = Tx Event FIFO unchanged 1h = Tx Handler wrote Tx Event FIFO element" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty 0h = Tx FIFO non-empty 1h = Tx FIFO empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished 0h = No transmission cancellation finished 1h = Transmission cancellation finished" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed 0h = No transmission completed 1h = Transmission completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message 0h = No high priority message received 1h = High priority message received" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached 0h = Rx FIFO 1 fill level below watermark 1h = Rx FIFO 1 fill level reached watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message 0h = No new message written to Rx FIFO 1 1h = New message written to Rx FIFO 1" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero" "0,1" newline bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached 0h = Rx FIFO 0 fill level below watermark 1h = Rx FIFO 0 fill level reached watermark" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message 0h = No new message written to Rx FIFO 0 1h = New message written to Rx FIFO 0" "0,1" line.long 0x4 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable 0h = Interrupt disabled 1h = Interrupt enabled" "0,1" line.long 0x8 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be.." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line 0h = Interrupt assigned to interrupt line INT0 1h = Interrupt assigned to interrupt line INT1" "0,1" line.long 0xC "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1. Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the [0] EINT0 and [1] EINT1 bits." hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1 0h = Interrupt line INT1 disabled 1h = Interrupt line INT1 enabled" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0 0h = Interrupt line INT0 disabled 1h = Interrupt line INT0 enabled" "0,1" group.long 0x80++0xB line.long 0x0 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames. Global settings for Message ID filtering. The register controls the filter path for standard and extended messages (see and )." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 0h = Accept in Rx FIFO 0 1h = Accept in Rx FIFO 1 2h = Reject 3h = Reject" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard 0h = Filter remote frames with 11-bit standard IDs 1h = Reject all remote frames with 11-bit standard IDs" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended 0h = Filter remote frames with 29-bit extended IDs 1h = Reject all remote frames with 29-bit extended IDs" "0,1" line.long 0x4 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard 0h = No standard Message ID filter 1h-80h (1-128) = Number of standard Message ID filter elements &gt; 80h (128) = Values greater than 128 are interpreted as 128" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list. Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see )." hexmask.long.word 0x8 23.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended 0h = No extended Message ID filter 1h-40h (1-64) = Number of extended Message ID filter elements &gt; 40h (64) = Values greater than 64 are interpreted as 64" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x90++0x3 line.long 0x0 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939." rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages. This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of.." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "FLST,Filter List Indicates the filter list of the matching filter element. 0h = Standard Filter List 1h = Extended Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index Index of matching filter element. Range is 0 to" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator 0h = No FIFO selected 1h = FIFO message lost 2h = Message stored in FIFO 0 3h = Message stored in FIFO 1" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when the" group.long 0x98++0xB line.long 0x0 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31. The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU.." bitfld.long 0x0 31. "ND31,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 30. "ND30,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 29. "ND29,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 28. "ND28,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 27. "ND27,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 26. "ND26,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 25. "ND25,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 24. "ND24,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 23. "ND23,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 22. "ND22,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 21. "ND21,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 20. "ND20,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 19. "ND19,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 18. "ND18,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 17. "ND17,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 16. "ND16,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 15. "ND15,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 14. "ND14,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 13. "ND13,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 12. "ND12,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 11. "ND11,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 10. "ND10,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 9. "ND9,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 8. "ND8,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 7. "ND7,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 6. "ND6,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 5. "ND5,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 4. "ND4,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x0 3. "ND3,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 2. "ND2,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 1. "ND1,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x0 0. "ND0,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x4 "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63. The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host.." bitfld.long 0x4 31. "ND63,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 30. "ND62,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 29. "ND61,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 28. "ND60,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 27. "ND59,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 26. "ND58,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 25. "ND57,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 24. "ND56,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 23. "ND55,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 22. "ND54,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 21. "ND53,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 20. "ND52,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 19. "ND51,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 18. "ND50,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 17. "ND49,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 16. "ND48,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 15. "ND47,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 14. "ND46,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 13. "ND45,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 12. "ND44,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 11. "ND43,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 10. "ND42,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 9. "ND41,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 8. "ND40,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 7. "ND39,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 6. "ND38,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 5. "ND37,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 4. "ND36,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" newline bitfld.long 0x4 3. "ND35,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 2. "ND34,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 1. "ND33,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" bitfld.long 0x4 0. "ND32,New Data 0h = Rx Buffer not updated 1h = Rx Buffer updated from new message" "0,1" line.long 0x8 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size 0h = No Rx FIFO 0 1h-40h (1-64) = Number of Rx FIFO 0 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 0 message lost 1h = Rx FIFO 0 message lost also set after write attempt to Rx FIFO 0 of size zero Note:Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will.." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full 0h = Rx FIFO 0 not full 1h = Rx FIFO 0 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63." newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the" line.long 0x4 "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see ). Also used to reference debug messages A B C. Note:Debug feature is not supported." rbitfld.long 0x4 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x8 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address." bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark 0h = Watermark interrupt disabled 1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt ( &gt; 40h (64) = Watermark interrupt disabled" rbitfld.long 0x8 23. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size 0h = No Rx FIFO 1 1h-40h (1-64) = Number of Rx FIFO 1 elements &gt; 40h (64) = Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to" hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level." bitfld.long 0x0 30.--31. "DMS,Debug Message Status 0h = Idle state wait for reception of debug messages DMA request is cleared 1h = Debug message A received 2h = Debug messages A B received 3h = Debug messages A B C received DMA request is set Note:Debug feature is not.." "0,1,2,3" hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag 0h = No Rx FIFO 1 message lost 1h = Rx FIFO 1 message lost also set after write attempt to Rx FIFO 1 of size zero Note:Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will.." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full 0h = Rx FIFO 1 not full 1h = Rx FIFO 1 full" "0,1" bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63." bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63." bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level." hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to the" line.long 0x4 "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames." hexmask.long.tbyte 0x4 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data field size.." "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address." rbitfld.long 0x8 31. "RESERVED,Reserved" "0,1" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode 0h = Tx FIFO operation 1h = Tx Queue operation" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size 0h = No Tx FIFO/Queue 1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue &gt; 20h (32) = Values greater than 32 are interpreted as 32" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers 0h = No Dedicated Tx Buffers 1h-20h (1-32) = Number of Dedicated Tx Buffers &gt; 20h (32) = Values greater than 32 are interpreted as 32" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.." rbitfld.long 0x8 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level. The Tx FIFO/Queue status is related to the pending Tx requests listed in the register. Therefore the effect of Add/Cancellation requests may be.." hexmask.long.word 0x0 22.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full 0h = Tx FIFO/Queue not full 1h = Tx FIFO/Queue full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." group.long 0xC8++0x3 line.long 0x0 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size 0h = 8 byte data field 1h = 12 byte data field 2h = 16 byte data field 3h = 20 byte data field 4h = 24 byte data field 5h = 32 byte data field 6h = 48 byte data field 7h = 64 byte data field Note:In case the data length.." "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the register. The bits are reset after a requested transmission has completed or has been.." bitfld.long 0x0 31. "TRP31,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 24. "TRP24,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 17. "TRP17,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 16. "TRP16,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" newline bitfld.long 0x0 3. "TRP3,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 1. "TRP1,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0h = No transmission request pending 1h = Transmission request pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests. Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple.." bitfld.long 0x0 31. "AR31,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 30. "AR30,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 29. "AR29,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 28. "AR28,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 27. "AR27,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 26. "AR26,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 25. "AR25,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 24. "AR24,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 23. "AR23,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 22. "AR22,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 21. "AR21,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 20. "AR20,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 19. "AR19,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 18. "AR18,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 17. "AR17,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 16. "AR16,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 15. "AR15,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 14. "AR14,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 13. "AR13,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 12. "AR12,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 11. "AR11,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 9. "AR9,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 8. "AR8,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 7. "AR7,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 6. "AR6,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 5. "AR5,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 4. "AR4,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" newline bitfld.long 0x0 3. "AR3,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 2. "AR2,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 1. "AR1,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" bitfld.long 0x0 0. "AR0,Add Request 0h = No transmission request added 1h = Transmission requested added" "0,1" line.long 0x4 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions. Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the.." bitfld.long 0x4 31. "CR31,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 24. "CR24,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 17. "CR17,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 16. "CR16,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" newline bitfld.long 0x4 3. "CR3,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 1. "CR1,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0h = No cancellation pending 1h = Cancellation pending" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding bit is cleared after a successful.." bitfld.long 0x0 31. "TO31,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 24. "TO24,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 17. "TO17,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 16. "TO16,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" newline bitfld.long 0x0 3. "TO3,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 1. "TO1,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0h = No transmission occurred 1h = Transmission occurred" "0,1" line.long 0x4 "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding bit is.." bitfld.long 0x4 31. "CF31,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 24. "CF24,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 17. "CF17,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 16. "CF16,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" newline bitfld.long 0x4 3. "CF3,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 1. "CF1,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0h = No transmit buffer cancellation 1h = Transmit buffer cancellation finished" "0,1" group.long 0xE0++0x7 line.long 0x0 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers." bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" newline bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0h = Transmission interrupt disabled 1h = Transmission interrupt enable" "0,1" line.long 0x4 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers." bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" newline bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0h = Cancellation finished interrupt disabled 1h = Cancellation finished interrupt enabled" "0,1" group.long 0xF0++0x3 line.long 0x0 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark 0h = Watermark interrupt disabled 1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt ( &gt; 20h (32) = Watermark interrupt disabled" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size 0h = Tx Event FIFO disabled 1h-20h (1-32) = Number of Tx Event FIFO elements &gt; 20h (32) = Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level." hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 25. "TEFL,This bit is a copy of interrupt flag 0h = No Tx Event FIFO element lost 1h = Tx Event FIFO element lost also set after write attempt to Tx Event FIFO of size zero." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full 0h = Tx Event FIFO not full 1h = Tx Event FIFO full" "0,1" bitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31." bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31." newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level." hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the" tree.end tree "MCU_MCAN1_ECC_AGGR" base ad:0x40701000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MCANSS_ECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" newline bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MCANSS_ECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator." group.long 0x3C++0x7 line.long 0x0 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1" line.long 0x4 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x80++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0xC0++0x3 line.long 0x0 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x13C++0x7 line.long 0x0 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1" line.long 0x4 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x180++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1" group.long 0x200++0xF line.long 0x0 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1" line.long 0x4 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1" line.long 0x8 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3" line.long 0xC "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3" tree.end tree "MCU_MCAN1_SS" base ad:0x40560000 rgroup.long 0x0++0x3 line.long 0x0 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Revision" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" group.long 0x4++0x3 line.long 0x0 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend" "0,1" rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x8++0x3 line.long 0x0 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS." hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xC++0xF line.long 0x0 "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits." "0,1" line.long 0x4 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits." hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits." "0,1" line.long 0x8 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits." hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" eventfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits." "0,1" line.long 0xC "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits." hexmask.long 0xC 1.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" group.long 0x20++0x7 line.long 0x0 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter &gt; 1h will issue another pulse interrupt. 0h = EOI value for.." line.long 0x4 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h." rgroup.long 0x28++0x3 line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If &gt; 1h an EOI write will issue another pulse interrupt." tree.end tree.end tree "MCU_MCSPI" tree "MCU_MCSPI0_CFG" base ad:0x40300000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this.." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved" bitfld.long 0x4 6. "RETMODE,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see . MCSPI Not Supported Features." hexmask.long 0x0 4.--31. 1. "RSVD,Reads returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally that is regardless of the IP module's internal requirements." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. (Optional) 0h (R/W) = Reset done no pending action 1h (R/W) = Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "0,1" bitfld.long 0x0 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full. Only when Channel 3 is enabled 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow. Only when Channel 3 is enabled. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only). Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information..." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0." bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x8 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0xC 11. "SSB,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line (signal data value)" "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line (signal data value)" "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line (signal data value)" "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line (signal data value)" "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line (signal data value)" "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x10 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "0,1" bitfld.long 0x10 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) =.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i." rbitfld.long 0x14 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x14 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x14 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x14 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i." rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes" hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes" line.long 0x4 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO.." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when" rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO data received with DMA 256 bit aligned address. This field is only used when" tree.end tree "MCU_MCSPI1_CFG" base ad:0x40310000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this.." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved" bitfld.long 0x4 6. "RETMODE,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see . MCSPI Not Supported Features." hexmask.long 0x0 4.--31. 1. "RSVD,Reads returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally that is regardless of the IP module's internal requirements." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. (Optional) 0h (R/W) = Reset done no pending action 1h (R/W) = Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "0,1" bitfld.long 0x0 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full. Only when Channel 3 is enabled 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow. Only when Channel 3 is enabled. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only). Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information..." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0." bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x8 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0xC 11. "SSB,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line (signal data value)" "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line (signal data value)" "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line (signal data value)" "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line (signal data value)" "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line (signal data value)" "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x10 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "0,1" bitfld.long 0x10 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) =.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i." rbitfld.long 0x14 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x14 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x14 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x14 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i." rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes" hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes" line.long 0x4 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO.." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when" rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO data received with DMA 256 bit aligned address. This field is only used when" tree.end tree "MCU_MCSPI2_CFG" base ad:0x40320000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" line.long 0x4 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. Some of the MCSPI features described in this.." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved" bitfld.long 0x4 6. "RETMODE,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see . MCSPI Not Supported Features." hexmask.long 0x0 4.--31. 1. "RSVD,Reads returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. 0h (R/W) = Force-idle mode: local target's IDLE state follows (acknowledges) the system's clock stop requests unconditionally that is regardless of the IP module's internal requirements." "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal. 0h (R/W) = IP module is sensitive to emulation suspend. 1h (R/W) = IP module is not sensitive to emulation suspend." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset. (Optional) 0h (R/W) = Reset done no pending action 1h (R/W) = Initiate software reset" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" group.long 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off. 1h (R/W) = Interface clock is maintained. Functional clock may be switched off. 2h (R/W) = Functional clock is maintained. Interface.." "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode. Interrupt DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is.." "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled. 1h (R/W) = Wake-up capability is enabled." "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. During reads it always returns 0. 0h (R/W) = (write) Normal mode 1h (R/W) = (write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic interface clock gating strategy is applied based on the configuration interface activity." "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information." bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "0,1" bitfld.long 0x0 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full. Only when Channel 3 is enabled 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow. Only when Channel 3 is enabled. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty. 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty. Channel 2 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty. Channel 1 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only). Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty. Channel 0 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "0,1" line.long 0x4 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more information..." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0." bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable. 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0." "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 3 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 2 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0." "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 1 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable. Channel 0 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "0,1" line.long 0x8 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis. Some of the MCSPI features described in this section may not be supported on this family of devices. For more.." hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x8 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "0,1" line.long 0xC "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0xC 11. "SSB,Set status bit 0h (R/W) = No action. Writing 0 does not clear already set status bits. This bit must be cleared before trying to clear a status bit of the 1h (R/W) = Force to 1 all status bits of" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line. 0h (R/W) = Output (as in master mode) 1h (R/W) = Input (as in slave mode)" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]. 0h (R/W) = Output 1h (R/W) = Input" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output (signal data value of internal signal to system). 0h (R/W) = The pin is driven low. 1h (R/W) = The pin is driven high." "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line (signal data value)" "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line (signal data value)" "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line (signal data value)" "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line (signal data value)" "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line (signal data value)" "0,1" line.long 0x10 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0." bitfld.long 0x10 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers. 1h (R/W) = FIFO data managed by" "0,1" bitfld.long 0x10 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer. 1h (R/W) = The controller wait 4 MCSPI bus clock 2h (R/W) = The controller wait 8 MCSPI bus clock 3h (R/W) = The controller wait 16 MCSPI bus clock 4h (R/W) =.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "0,1" newline bitfld.long 0x10 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]. 1h (R/W) = Slave - The module receives the SPICLK and SPIEN[3:0]." "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select. 1h (R/W) = SPIEN is not used. In this mode all related options to chip-select have no meaning." "0,1" bitfld.long 0x10 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode. 1h (R/W) = Only one channel will be used in master mode. This bit must be set in Force SPIEN[i] mode." "0,1" line.long 0x14 "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i." rbitfld.long 0x14 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x14 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x14 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x14 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x14 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x14 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x14 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x14 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x140++0x3 line.long 0x0 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i." rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x154++0x3 line.long 0x0 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI_CHCTRL_2,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel i is not active. 1h (R/W) = Channel i is active." "0,1" line.long 0x4 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x168++0x3 line.long 0x0 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i" rbitfld.long 0x0 30.--31. "RESERVED,Read returns 0." "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to receive data. 1h (R/W) = The buffer is used to receive data." "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set. 0h (R/W) = The buffer is not used to transmit data. 1h (R/W) = The buffer is used to transmit data." "0,1" bitfld.long 0x0 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer. 1h (R/W) = Start-bit polarity is held to 1 during MCSPI transfer." "0,1" bitfld.long 0x0 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1" bitfld.long 0x0 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection. 0h (R/W) = Detection enabled only on SPIEN[0] 1h (R/W) = Detection enabled only on SPIEN[1] 2h (R/W) = Detection enabled only on SPIEN[2] 3h (R/W) = Detection enabled only.." "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only). 0h (R/W) = Writing 0 into this bit drives low the SPIEN line when 1h (R/W) = Writing 1 into this bit drives high the SPIEN line when" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer). 1h (R/W) = Turbo is activated to maximize the throughput for multiple MCSPI words transfer." "0,1" newline bitfld.long 0x0 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1" bitfld.long 0x0 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1" bitfld.long 0x0 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1" bitfld.long 0x0 14. "DMAW,DMA write request. 0h (R/W) = DMA write request disabled 1h (R/W) = DMA write request enabled" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." bitfld.long 0x0 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state. 1h (R/W) = SPIEN is held low during the ACTIVE state." "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device). A programmable clock divider divides the MCSPI reference clock (SPICLKREF) with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data." bitfld.long 0x0 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK." "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i." hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0." bitfld.long 0x0 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1" bitfld.long 0x0 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1" bitfld.long 0x0 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1" bitfld.long 0x0 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1" newline bitfld.long 0x0 2. "EOT,Channel i end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes turbo mode). See dedicated chapters for details. 0h (R) = This flag is automatically.." "0,1" bitfld.long 0x0 1. "TXS,Channel i transmitter register status 0h (R) = Register is full. 1h (R) = Register is empty." "0,1" bitfld.long 0x0 0. "RXS,Channel i receiver register status 0h (R) = Register is empty. 1h (R) = Register is full." "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0." hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1. 1h (R/W) = Clock ratio is CLKD + 1 + 16. FFh (R/W) = Clock ratio is CLKD + 1 + 4080." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0." bitfld.long 0x0 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active. 1h (R/W) = Channel 'i' is active." "0,1" line.long 0x4 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is." hexmask.long 0x4 0.--31. 1. "TDATA,Channel i data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel i received data" group.long 0x17C++0x7 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,SPI word counter. 0h (R/W) = Counter not used 1h (R/W) = One word FFFEh (R/W) = 65534 MCSPI word FFFFh (R/W) = 65535 MCSPI word" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes" hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer almost empty. 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255 bytes FFh (R/W) = 256bytes" line.long 0x4 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX registers corresponding to the channel which has its FIFO.." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO data to transmit with DMA 256 bit aligned address. This field is only used when" rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_RX registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO data received with DMA 256 bit aligned address. This field is only used when" tree.end tree.end tree "MCU_NAVSS" tree "MCU_NAVSS0_CFG" base ad:0x28520000 rgroup.long 0x0++0x3 line.long 0x0 "MCU_NAVSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end tree "MCU_NAVSS0_INTR0_CFG" base ad:0x28540000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version 10h - NAVSS0 Fh - MCU_NAVSS0" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_MUXCNTL_y,Interrupt mux control register Offset = 4h + (y * 4); where y = 0h to 1FFh for NAVSS0 Offset = 4h + (y * 4); where y = 0h to 3Fh for MCU_NAVSS0" hexmask.long.word 0x0 17.--31. 1. "RESERVED" bitfld.long 0x0 16. "INT_ENABLE,Interrupt output enable for interrupt y" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "MUX_CONTROL,Mux control for interrupt y Avoid programming the mux control when input interrutps are enabled via INT_ENABLE." tree.end tree "MCU_NAVSS0_MCRC" base ad:0x2A264000 group.long 0x0++0x3 line.long 0x0 "MCRC_CRC_CTRL0,CRC Global Control Register 0" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" newline bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" group.long 0x8++0x3 line.long 0x0 "MCRC_CRC_CTRL1,CRC Global Control Register 1" hexmask.long 0x0 1.--31. 1. "RESERVED" newline bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" group.long 0x10++0x3 line.long 0x0 "MCRC_CRC_CTRL2,Channel Mode Control Register" hexmask.long.byte 0x0 26.--31. 1. "RESERVED" newline bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 2.--3. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" group.long 0x18++0x3 line.long 0x0 "MCRC_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIME_OUT_ENS,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt enable" group.long 0x20++0x3 line.long 0x0 "MCRC_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt disable" group.long 0x28++0x3 line.long 0x0 "MCRC_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode. 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode. 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "MCRC_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "MCRC_CRC_BUSY,CRC Busy Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" newline bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" group.long 0x40++0x7 line.long 0x0 "MCRC_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.word 0x0 20.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "MCRC_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0x4C++0x7 line.long 0x0 "MCRC_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." group.long 0x60++0xF line.long 0x0 "MCRC_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "MCRC_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "MCRC_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "MCRC_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "MCRC_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "MCRC_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "MCRC_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x80++0x7 line.long 0x0 "MCRC_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.word 0x0 20.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "MCRC_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0x8C++0x7 line.long 0x0 "MCRC_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0xA0++0xF line.long 0x0 "MCRC_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "MCRC_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "MCRC_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "MCRC_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "MCRC_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "MCRC_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "MCRC_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0xC0++0x7 line.long 0x0 "MCRC_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.word 0x0 20.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "MCRC_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0xCC++0x7 line.long 0x0 "MCRC_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0xE0++0xF line.long 0x0 "MCRC_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "MCRC_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "MCRC_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "MCRC_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "MCRC_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "MCRC_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "MCRC_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x100++0x7 line.long 0x0 "MCRC_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.word 0x0 20.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "MCRC_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." group.long 0x10C++0x7 line.long 0x0 "MCRC_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0x120++0xF line.long 0x0 "MCRC_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "MCRC_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "MCRC_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "MCRC_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "MCRC_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "MCRC_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "MCRC_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x140++0x3 line.long 0x0 "MCRC_BUS_SEL,Data bus tracing selection" hexmask.long 0x0 3.--31. 1. "RESERVED" newline bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." wgroup.long 0x200++0x3 line.long 0x0 "MCRC_I0_PSA_SIGREG1_CPY_Y,Channel 1 PSA signature block region Offset = 200h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." wgroup.long 0x280++0x3 line.long 0x0 "MCRC_I0_PSA_SIGREG2_CPY_Y,Channel 2 PSA signature block region Offset = 280h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." wgroup.long 0x300++0x3 line.long 0x0 "MCRC_I0_PSA_SIGREG3_CPY_Y,Channel 3 PSA signature block region Offset = 300h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." wgroup.long 0x380++0x3 line.long 0x0 "MCRC_I0_PSA_SIGREG4_CPY_Y,Channel 4 PSA signature block region Offset = 380h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end tree "MCU_NAVSS0_PROXY0_BUF_CFG" base ad:0x2A580000 group.long 0x0++0x3 line.long 0x0 "PROXY_EVT_REG_j,The Proxy Event for the proxy Offset = 0h + (j * 1000h); where j = 0h to 3Fh" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end tree "MCU_NAVSS0_PROXY0_TARGET0_DATA" base ad:0x2A500000 group.long 0x0++0x7 line.long 0x0 "PROXY_CTL_j,The Proxy Control for the proxy. NOTE: This register must be written only via 32-bit accesses. 64-bit writes are not supported and may result in data loss. Offset = 0h + (j * 1000h); where j = 0h to 3Fh" hexmask.long.byte 0x0 27.--31. 1. "RESERVED" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0: 4 bytes,1: 8 bytes,2: 16 bytes,3: 32 bytes,4: 64 bytes,5: 128 bytes,6: 256 bytes,7: 512 bytes" hexmask.long.byte 0x0 18.--23. 1. "RESERVED" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue. 0h = access the head of the queue 1h = access the tail of the queue 2h = peek access the head of the queue 3h = peek access the tail of the queue. NOT SUPPORTED" "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "PROXY_STATUS_j,The Proxy Status for the proxy. NOTE: This register must be written only via 32-bit accesses. 64-bit writes are not supported and may result in data loss. Offset = 4h + (j * 1000h); where j = 0h to 3Fh" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" hexmask.long 0x4 0.--30. 1. "RESERVED" group.long 0x200++0x3 line.long 0x0 "PROXY_DATA_j_y,The Proxy Data for the proxy. target and channel Offset = 200h + (j * 1000h) + (y * 4h); where j = 0h to 3Fh. y = 0h to 7Fh" hexmask.long 0x0 0.--31. 1. "VAL,Proxy Data" tree.end tree "MCU_NAVSS0_PROXY_CFG_BUF" base ad:0x285A0000 group.long 0x0++0x3 line.long 0x0 "PROXY_DATA_y,The Proxy Buffer for the proxy Offset = 0h + (y * 4h); where y = 0h to FFFh" hexmask.long 0x0 0.--31. 1. "VAL,Proxy Buffer Data" tree.end tree "MCU_NAVSS0_PROXY_CFG_GCFG" base ad:0x28590000 rgroup.long 0x0++0x7 line.long 0x0 "PROXY_PID,The Revision Register contains the major and minor revisions for the module. Reset = 66349100h" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.12h in this device." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PROXY_CONFIG,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." group.long 0x14++0x3 line.long 0x0 "PROXY_GLB_EVT,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end tree "MCU_NAVSS0_SEC_PROXY0_CFG" base ad:0x285B0000 rgroup.long 0x0++0x7 line.long 0x0 "SEC_PROXY_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "SEC_PROXY_CONFIG,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." tree.end tree "MCU_NAVSS0_SEC_PROXY0_CFG_RT" base ad:0x2A380000 group.long 0x0++0x7 line.long 0x0 "SEC_PROXY_STATUS_j,The Status Register gives status for proxy thread j. Offset =0h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_RT j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_RT" bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written." line.long 0x4 "SEC_PROXY_THR_j,The Threshold Register controls the threshold for proxy thread j events. Offset =4h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_RT j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_RT" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end tree "MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" base ad:0x2A400000 group.long 0x0++0x13 line.long 0x0 "SEC_PROXY_BUFFER_L,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "SEC_PROXY_BUFFER_H,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "SEC_PROXY_TARGET_L,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "SEC_PROXY_TARGET_H,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "SEC_PROXY_ORDERID,The Buffer OrderID Register contains the bus value for the buffer memory access." hexmask.long 0x10 5.--31. 1. "RESERVED" bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus OrderID value for the buffer access with the ORDERID register field. 0 = bypass and use the OrderID from the source transaction for the destination transaction. 1 = use the ORDERID register field value for the.." "0: bypass and use the OrderID from the source..,1: use the ORDERID register field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus OrderID value for the buffer access." group.long 0x1000++0xB line.long 0x0 "SEC_PROXY_CTL_j,The Control Register defines controls for proxy thread a. Offset = 1000h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 24.--30. 1. "RESERVED" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "SEC_PROXY_EVT_MAP_j,The Event Map Register defines the event numbers for proxy thread a. Offset = 1004h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "SEC_PROXY_DST_j,The Destination Register defines the destination proxy thread for outbound proxy thread a. Offset = 1008h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end tree "MCU_NAVSS0_SEC_PROXY0_TARGET_DATA" base ad:0x2A480000 rgroup.long 0x0++0x3 line.long 0x0 "SEC_PROXY_DATA_j,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message. Offset = 0h + (j * 1000h); where j = 0h to 9Fh for.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." group.long 0x4++0x3 line.long 0x0 "SEC_PROXY_MESSAGE_j_y,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte. Offset = 4h + (j * 1000h) + (y * 4h); where j = 0h to 9Fh. y = 0h to Eh for NAVSS0_SEC_PROXY0_SRC_TARGET_DATA j = 0h to 59h. y = 0h.." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end tree "MCU_NAVSS0_UDMASS_ECCAGGR0" base ad:0x28381000 rgroup.long 0x0++0x3 line.long 0x0 "MCU_NAVSS_REV,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "MCU_NAVSS_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" newline bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MCU_NAVSS_STAT,Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x3C++0x13 line.long 0x0 "MCU_NAVSS_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED" newline bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MCU_NAVSS_SEC_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 31. "UDMAP0_RPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMAP0_RPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "UDMAP0_RFFW_RAMECC_PEND,Interrupt Pending Status for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "UDMAP0_TPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "UDMAP0_TPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "UDMAP0_TPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "UDMAP0_TSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "UDMAP0_RPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "UDMAP0_RPCU_SB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RPCU_SB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_RPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_RPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_RPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_RPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_TPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_TPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_TPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_TPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_RPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_RPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_RPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_RPRQ_RAMECC_PEND,Interrupt Pending Status for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_RPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_RPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_TPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_TPCU_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_TPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_TPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_TPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_TPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_TPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "MCU_NAVSS_SEC_STATUS_REG1,Interrupt Status Register 1" bitfld.long 0x8 31. "UDMASS_INTA0_SR_ECC_PEND,Interrupt Pending Status for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x8 30. "UDMASS_INTA0_IM_ECC_PEND,Interrupt Pending Status for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 28. "RINGACC0_ECC_PEND,Interrupt Pending Status for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 22. "UDMAP0_RRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "UDMAP0_TRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "UDMAP0_PSILTID_RAMECC_PEND,Interrupt Pending Status for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "UDMAP0_PSILR_RAMECC_PEND,Interrupt Pending Status for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "UDMAP0_SDEC3_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "UDMAP0_SDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "UDMAP0_RDEC2_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "UDMAP0_RDEC1_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "UDMAP0_RDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "UDMAP0_REVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "UDMAP0_TEVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "UDMAP0_STS_RAMECC3_PEND,Interrupt Pending Status for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x8 10. "UDMAP0_STS_RAMECC2_PEND,Interrupt Pending Status for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x8 9. "UDMAP0_STS_RAMECC1_PEND,Interrupt Pending Status for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x8 8. "UDMAP0_STS_RAMECC0_PEND,Interrupt Pending Status for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x8 7. "UDMAP0_EH_RAMECC_PEND,Interrupt Pending Status for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "UDMAP0_PROXY_RAMECC_PEND,Interrupt Pending Status for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "UDMAP0_RSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "UDMAP0_RFLOW1_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "UDMAP0_RFLOW0_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "UDMAP0_RPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "UDMAP0_RPCF3_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "UDMAP0_RPCF2_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0xC "MCU_NAVSS_SEC_STATUS_REG2,Interrupt Status Register 2" bitfld.long 0xC 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 2. "UDMASS_INTA0_GC_ECC_PEND,Interrupt Pending Status for udmass_inta0_gc_ecc_pend" "0,1" newline bitfld.long 0xC 1. "UDMASS_INTA0_MC_ECC_PEND,Interrupt Pending Status for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0xC 0. "UDMASS_INTA0_LC_ECC_PEND,Interrupt Pending Status for udmass_inta0_lc_ecc_pend" "0,1" line.long 0x10 "MCU_NAVSS_SEC_STATUS_REG3,Interrupt Status Register 3" hexmask.long.byte 0x10 24.--31. 1. "RESERVED" newline bitfld.long 0x10 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" group.long 0x80++0xF line.long 0x0 "MCU_NAVSS_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "UDMAP0_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "UDMAP0_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "UDMAP0_RFFW_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "UDMAP0_TPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "UDMAP0_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "UDMAP0_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "UDMAP0_TSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "UDMAP0_RPRQ_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "UDMAP0_RPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "UDMAP0_TPCU_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "UDMAP0_TPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "MCU_NAVSS_SEC_ENABLE_SET_REG1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "UDMASS_INTA0_SR_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMASS_INTA0_IM_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x4 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RINGACC0_ECC_ENABLE_SET,Interrupt Enable Set Register for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x4 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_PSILTID_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_PSILR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_SDEC3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_SDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_RDEC2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_RDEC1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_RDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_STS_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_STS_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_EH_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_PROXY_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_RSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_RPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_RPCF3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "UDMAP0_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0x8 "MCU_NAVSS_SEC_ENABLE_SET_REG2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 2. "UDMASS_INTA0_GC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_gc_ecc_pend" "0,1" newline bitfld.long 0x8 1. "UDMASS_INTA0_MC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x8 0. "UDMASS_INTA0_LC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_lc_ecc_pend" "0,1" line.long 0xC "MCU_NAVSS_SEC_ENABLE_SET_REG3,Interrupt Enable Set Register 3" hexmask.long.byte 0xC 24.--31. 1. "RESERVED" newline bitfld.long 0xC 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" group.long 0xC0++0xF line.long 0x0 "MCU_NAVSS_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "UDMAP0_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "UDMAP0_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "UDMAP0_RFFW_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "UDMAP0_TPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "UDMAP0_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "UDMAP0_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "UDMAP0_TSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "UDMAP0_RPRQ_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "UDMAP0_RPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "UDMAP0_TPCU_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "UDMAP0_TPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "MCU_NAVSS_SEC_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "UDMASS_INTA0_SR_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMASS_INTA0_IM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x4 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RINGACC0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x4 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_PSILTID_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_PSILR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_SDEC3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_SDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_RDEC2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_RDEC1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_RDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_STS_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_STS_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_EH_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_PROXY_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_RSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_RPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_RPCF3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "UDMAP0_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0x8 "MCU_NAVSS_SEC_ENABLE_CLR_REG2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 2. "UDMASS_INTA0_GC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_gc_ecc_pend" "0,1" newline bitfld.long 0x8 1. "UDMASS_INTA0_MC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x8 0. "UDMASS_INTA0_LC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_lc_ecc_pend" "0,1" line.long 0xC "MCU_NAVSS_SEC_ENABLE_CLR_REG3,Interrupt Enable Clear Register 3" hexmask.long.byte 0xC 24.--31. 1. "RESERVED" newline bitfld.long 0xC 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" group.long 0x13C++0x13 line.long 0x0 "MCU_NAVSS_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED" newline bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MCU_NAVSS_DED_STATUS_REG0,Interrupt Status Register 0" bitfld.long 0x4 31. "UDMAP0_RPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMAP0_RPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "UDMAP0_RFFW_RAMECC_PEND,Interrupt Pending Status for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "UDMAP0_TPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "UDMAP0_TPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "UDMAP0_TPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "UDMAP0_TSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "UDMAP0_RPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "UDMAP0_RPCU_SB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RPCU_SB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_RPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_RPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_RPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_RPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_TPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_TPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_TPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_TPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_RPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_RPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_RPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_RPRQ_RAMECC_PEND,Interrupt Pending Status for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_RPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_RPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_TPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_TPCU_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_TPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_TPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_TPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_TPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_TPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" line.long 0x8 "MCU_NAVSS_DED_STATUS_REG1,Interrupt Status Register 1" bitfld.long 0x8 31. "UDMASS_INTA0_SR_ECC_PEND,Interrupt Pending Status for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x8 30. "UDMASS_INTA0_IM_ECC_PEND,Interrupt Pending Status for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 28. "RINGACC0_ECC_PEND,Interrupt Pending Status for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x8 22. "UDMAP0_RRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "UDMAP0_TRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "UDMAP0_PSILTID_RAMECC_PEND,Interrupt Pending Status for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "UDMAP0_PSILR_RAMECC_PEND,Interrupt Pending Status for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "UDMAP0_SDEC3_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "UDMAP0_SDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "UDMAP0_RDEC2_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "UDMAP0_RDEC1_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "UDMAP0_RDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "UDMAP0_REVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "UDMAP0_TEVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "UDMAP0_STS_RAMECC3_PEND,Interrupt Pending Status for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x8 10. "UDMAP0_STS_RAMECC2_PEND,Interrupt Pending Status for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x8 9. "UDMAP0_STS_RAMECC1_PEND,Interrupt Pending Status for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x8 8. "UDMAP0_STS_RAMECC0_PEND,Interrupt Pending Status for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x8 7. "UDMAP0_EH_RAMECC_PEND,Interrupt Pending Status for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "UDMAP0_PROXY_RAMECC_PEND,Interrupt Pending Status for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "UDMAP0_RSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "UDMAP0_RFLOW1_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "UDMAP0_RFLOW0_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "UDMAP0_RPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "UDMAP0_RPCF3_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "UDMAP0_RPCF2_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0xC "MCU_NAVSS_DED_STATUS_REG2,Interrupt Status Register 2" bitfld.long 0xC 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0xC 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0xC 2. "UDMASS_INTA0_GC_ECC_PEND,Interrupt Pending Status for udmass_inta0_gc_ecc_pend" "0,1" newline bitfld.long 0xC 1. "UDMASS_INTA0_MC_ECC_PEND,Interrupt Pending Status for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0xC 0. "UDMASS_INTA0_LC_ECC_PEND,Interrupt Pending Status for udmass_inta0_lc_ecc_pend" "0,1" line.long 0x10 "MCU_NAVSS_DED_STATUS_REG3,Interrupt Status Register 3" hexmask.long.byte 0x10 24.--31. 1. "RESERVED" newline bitfld.long 0x10 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1" newline bitfld.long 0x10 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1" group.long 0x180++0xF line.long 0x0 "MCU_NAVSS_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "UDMAP0_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "UDMAP0_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "UDMAP0_RFFW_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "UDMAP0_TPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "UDMAP0_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "UDMAP0_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "UDMAP0_TSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "UDMAP0_RPRQ_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "UDMAP0_RPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "UDMAP0_TPCU_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "UDMAP0_TPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" line.long 0x4 "MCU_NAVSS_DED_ENABLE_SET_REG1,Interrupt Enable Set Register 1" bitfld.long 0x4 31. "UDMASS_INTA0_SR_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMASS_INTA0_IM_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x4 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RINGACC0_ECC_ENABLE_SET,Interrupt Enable Set Register for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x4 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_PSILTID_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_PSILR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_SDEC3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_SDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_RDEC2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_RDEC1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_RDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_STS_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_STS_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_EH_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_PROXY_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_RSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_RPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_RPCF3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "UDMAP0_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0x8 "MCU_NAVSS_DED_ENABLE_SET_REG2,Interrupt Enable Set Register 2" bitfld.long 0x8 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0x8 2. "UDMASS_INTA0_GC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_gc_ecc_pend" "0,1" newline bitfld.long 0x8 1. "UDMASS_INTA0_MC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x8 0. "UDMASS_INTA0_LC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_lc_ecc_pend" "0,1" line.long 0xC "MCU_NAVSS_DED_ENABLE_SET_REG3,Interrupt Enable Set Register 3" hexmask.long.byte 0xC 24.--31. 1. "RESERVED" newline bitfld.long 0xC 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" newline bitfld.long 0xC 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1" group.long 0x1C0++0xF line.long 0x0 "MCU_NAVSS_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "UDMAP0_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "UDMAP0_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "UDMAP0_RFFW_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rffw_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "UDMAP0_TPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf4_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "UDMAP0_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "UDMAP0_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "UDMAP0_TSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tstate_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb1_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb0_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb2_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb1_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "UDMAP0_RPRQ_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rprq_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "UDMAP0_RPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_cntr_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "UDMAP0_TPCU_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_pf_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_df_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_cf_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "UDMAP0_TPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcfg_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpstate_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" line.long 0x4 "MCU_NAVSS_DED_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1" bitfld.long 0x4 31. "UDMASS_INTA0_SR_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_sr_ecc_pend" "0,1" newline bitfld.long 0x4 30. "UDMASS_INTA0_IM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_im_ecc_pend" "0,1" newline bitfld.long 0x4 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 28. "RINGACC0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc0_ecc_pend" "0,1" newline bitfld.long 0x4 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1" newline bitfld.long 0x4 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1" newline bitfld.long 0x4 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1" newline bitfld.long 0x4 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rrngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_trngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "UDMAP0_PSILTID_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psiltid_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "UDMAP0_PSILR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psilr_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "UDMAP0_SDEC3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec3_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "UDMAP0_SDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "UDMAP0_RDEC2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec2_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "UDMAP0_RDEC1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec1_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "UDMAP0_RDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_revtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tevtcntr_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "UDMAP0_STS_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc3_pend" "0,1" newline bitfld.long 0x4 10. "UDMAP0_STS_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc2_pend" "0,1" newline bitfld.long 0x4 9. "UDMAP0_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 8. "UDMAP0_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc0_pend" "0,1" newline bitfld.long 0x4 7. "UDMAP0_EH_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_eh_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "UDMAP0_PROXY_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_proxy_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "UDMAP0_RSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rstate_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "UDMAP0_RPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf4_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "UDMAP0_RPCF3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf3_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "UDMAP0_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf2_ramecc_pend" "0,1" line.long 0x8 "MCU_NAVSS_DED_ENABLE_CLR_REG2,Interrupt Enable Clear Register 2" bitfld.long 0x8 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x8 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0x8 2. "UDMASS_INTA0_GC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_gc_ecc_pend" "0,1" newline bitfld.long 0x8 1. "UDMASS_INTA0_MC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_mc_ecc_pend" "0,1" newline bitfld.long 0x8 0. "UDMASS_INTA0_LC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_lc_ecc_pend" "0,1" line.long 0xC "MCU_NAVSS_DED_ENABLE_CLR_REG3,Interrupt Enable Clear Register 3" hexmask.long.byte 0xC 24.--31. 1. "RESERVED" newline bitfld.long 0xC 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" newline bitfld.long 0xC 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1" group.long 0x200++0xF line.long 0x0 "MCU_NAVSS_AGGR_ENABLE_SET,AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" newline bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MCU_NAVSS_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" newline bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MCU_NAVSS_AGGR_STATUS_SET,AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" newline bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MCU_NAVSS_AGGR_STATUS_CLR,AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" newline bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_NAVSS0_UDMASS_INTA0_CFG" base ad:0x283C0000 rgroup.quad 0x0++0x17 line.quad 0x0 "UDMA_INTA_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.long 0x0 32.--63. 1. "RESERVED" hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revisioн" bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "UDMA_INTA_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.long 0x8 32.--63. 1. "RESERVED" hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers. NOTE: This value is 600h for MCU_NAVSS0_UDMASS_INTR_AGGR0" line.quad 0x10 "UDMA_INTA_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "RESERVED" hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers NOTE: This value is 100h for MCU_NAVSS0_UDMASS_INTR_AGGR0" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers NOTE: This value is 80h for MCU_NAVSS0_UDMASS_INTR_AGGR0" tree.end tree "MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" base ad:0x28480000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_MAP_j,The Global Event Mapping register controls the egress global event index for this event count. Offset =0h + (j * 20h); where j = 0h to 1FFh for NAVSS0_UDMASS_INTA0_CFG_GCNTCFG j = 0h to FFh for MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" hexmask.quad 0x0 16.--63. 1. "RESERVED" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end tree "MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP" base ad:0x28560000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_IMAP_j,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto. Offset = 0h + (j * 8h); where j = 0h to 11FFh for NAVSS0_UDMASS_INTA0_CFG_IMAP j = 0h to 5FFh for.." hexmask.quad 0x0 17.--63. 1. "RESERVED" hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." bitfld.quad 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end tree "MCU_NAVSS0_UDMASS_INTA0_CFG_INTR" base ad:0x2A700000 group.quad 0x0++0x1F line.quad 0x0 "UDMA_INTA_ENABLE_SET_j,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output. Offset.." hexmask.quad 0x0 0.--63. 1. "ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "UDMA_INTA_ENABLE_CLEAR_j,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output." hexmask.quad 0x8 0.--63. 1. "ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "UDMA_INTA_STATUS_SET_j,The Interrupt Status register is read by software to determine the cause of an interrupt. Offset = 10h + (j * 1000h); where j = 0h to FFh" hexmask.quad 0x10 0.--63. 1. "STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "UDMA_INTA_STATUS_CLEAR_j,The Interrupt Status register is read by software to determine the cause of an interrupt. Offset = 18h + (j * 1000h); where j = 0h to FFh" hexmask.quad 0x18 0.--63. 1. "STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" rgroup.quad 0x20++0x7 line.quad 0x0 "UDMA_INTA_STATUSM_j,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt. Offset = 20h + (j * 1000h); where j = 0h to FFh" hexmask.quad 0x0 0.--63. 1. "STATUS,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end tree "MCU_NAVSS0_UDMASS_INTA0_CFG_L2G" base ad:0x28570000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_MAP_j,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event count is determined by.." hexmask.quad.long 0x0 32.--63. 1. "RESERVED" bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 16.--30. 1. "RESERVED" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end tree "MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST" base ad:0x28580000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_MCMAP_j,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this register. which is selected.." hexmask.quad.word 0x0 48.--63. 1. "RESERVED" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." hexmask.quad.word 0x0 16.--31. 1. "RESERVED" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end tree "MCU_NAVSS0_UDMASS_INTA0_GCNTRTI" base ad:0x2A600000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_COUNT_j,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a count has been processed by the.." hexmask.quad.long 0x0 32.--63. 1. "RESERVED" hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end tree "MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY" base ad:0x2A268000 rgroup.long 0x0++0x3 line.long 0x0 "PSIL_CFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x10++0x3 line.long 0x0 "PSIL_CFG_PROXY_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a configuration access. Once set this bit is persistent until manually cleared." "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a configuration read or write transaction and asserting the TOUT bit" group.long 0x100++0xB line.long 0x0 "PSIL_CFG_PROXY_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "BUSY,Indication that a configuration read or write is in progress 0h = No transaction is in progress 1h = Transaction is in progress" "0,1" bitfld.long 0x0 30. "DIR,Direction of configuration transaction 0h = Write transaction 1h = Read transaction" "0,1" bitfld.long 0x0 29. "TO,Indication that a timeout occurred. This bit should be written to 0h on each new transaction. 0h = Transaction completed normally 1h = Timeout occurred" "0,1" hexmask.long.word 0x0 16.--28. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "THREAD_ID,Thread ID to which configuration read or write is being sent. The thread ID mapping is shown in" line.long 0x4 "PSIL_CFG_PROXY_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 16.--27. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "ADDRESS,Word (32-bit) address within thread configuration space for transaction 0h = Peer thread ID register ( 1h = Peer credit register ( 2h = Enable register ( 40h = Capabilities register ( 400h = Static TR register" line.long 0x8 "PSIL_CFG_PROXY_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "WDATA,Configuration data word to be written" group.long 0x140++0x3 line.long 0x0 "PSIL_CFG_PROXY_RDATA,The Read Data Register contains the data which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "RDATA,Configuration data word that was read" tree.end tree "MCU_NAVSS0_UDMASS_RINGACC0_CFG" base ad:0x28440000 group.long 0x40++0x13 line.long 0x0 "RINGACC_BA_LO_J,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or to.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "RINGACC_BA_HI_j,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or to.." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "RINGACC_SIZE_j,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue. 0h = exposed ring mode for SW direct access 1h = messaging mode when all operations are through bus accesses allowing multiple producers or consumers. 2h = credentials mode is message mode plus stores.." "0,1,2,3" bitfld.long 0x8 27.--29. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "0: 4 bytes,1: 8 bytes,2: 16 bytes,3: 32 bytes,4: 64 bytes,5: 128 bytes,6: 256 bytes,7: RESERVED" hexmask.long.byte 0x8 20.--23. 1. "RESERVED" newline hexmask.long.tbyte 0x8 0.--19. 1. "ELCNT,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "RINGACC_EVENT_j,The Ring Event Register contains the event number for the ring for when it is active or empty. Offset = 4Ch + (j * 100h); where j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "EVENT,Defines the event for this ring or queue." line.long 0x10 "RINGACC_ORDERID_j,The Ring OrderID Register contains the bus orderid value for the ring memory access. Offset = 50h + (j * 100h); where j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG" hexmask.long 0x10 5.--31. 1. "RESERVED" bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end tree "MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG" base ad:0x285D0000 rgroup.long 0x0++0x3 line.long 0x0 "RINGACC_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision - for this device." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x10++0x3 line.long 0x0 "RINGACC_TRACE_CTL,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" hexmask.long.word 0x0 16.--28. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." group.long 0x20++0x3 line.long 0x0 "RINGACC_OVRFLOW,Overflow Queue Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages." group.long 0x40++0x3 line.long 0x0 "RINGACC_ERROR_EVT,Error Event Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "RINGACC_ERROR_LOG,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event is pending." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 16.--30. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end tree "MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON" base ad:0x2A280000 group.long 0x0++0xF line.long 0x0 "RINGACC_CONTROL_j,Monitor Control Register Offset = 0h + (j * 1000h); where j = 0h to 1Fh" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 12.--15. 1. "RESERVED" hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count 1 = reserved 2 = reseved" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "RINGACC_QUEUE_j,Monitor Queue Register Offset = 4h + (j * 1000h); where j = 0h to 1Fh" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VAL,Queue to monitor." line.long 0x8 "RINGACC_DATA0_j,Monitor Data Register Offset = 8h + (j * 1000h); where j = 0h to 1Fh" hexmask.long 0x8 0.--31. 1. "VAL,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "RINGACC_DATA1_j,Monitor Data Register Offset = Ch + (j * 1000h); where j = 0h to 1Fh" hexmask.long 0xC 0.--31. 1. "VAL,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end tree "MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT" base ad:0x2B800000 wgroup.long 0x10++0x3 line.long 0x0 "RINGACC_DB_j,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation. Offset = 10h + (j *.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ absolute.." rgroup.long 0x18++0xF line.long 0x0 "RINGACC_OCC_j,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be used for.." hexmask.long.word 0x0 21.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--20. 1. "CNT,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "RINGACC_INDX_j,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel. Offset = 1Ch + (j * 1000h); where j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT j = 0h to.." hexmask.long.word 0x4 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--19. 1. "IDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "RINGACC_HWOCC_j,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.word 0x8 21.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--20. 1. "CNT,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "RINGACC_HWINDX_j,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel. Offset = 24h + (j * 1000h); where j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT j = 0h.." hexmask.long.word 0xC 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xC 0.--19. 1. "IDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end tree "MCU_NAVSS0_UDMASS_RINGACC0_FIFOS" base ad:0x2B000000 group.long 0x0++0x3 line.long 0x0 "RINGACC_RINGHEADDATA_j_y,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are used to access the ring.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head element data" group.long 0x200++0x3 line.long 0x0 "RINGACC_RINGTAILDATA_j_y,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are used to access the ring.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring tail element data" group.long 0x400++0x3 line.long 0x0 "RINGACC_PEEKHEADDATA_j_y,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are used to.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head element data. Not supported in ring mode." group.long 0x600++0x3 line.long 0x0 "RINGACC_PEEKTAILDATA_j_y,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are used to.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring tail element data. Not supported in ring mode." tree.end tree "MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC" base ad:0x45820000 group.long 0x0++0x7 line.long 0x0 "MCU_NAVSS_CONTROL_J,The ISC a Region b Control Register defines the control fields for the ISC. Offset = 0h + (j * 20h); where j = 0h to 11Dh" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared. Has precedence over priv set bits." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 22.--23. "RESERVED" "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure. Has precedence over secure enable bits." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "MCU_NAVSS_CONTROL2_J,The ISC a Region b Control Register 2 defines the control fields for the ISC. Offset = 4h + (j * 20h); where j = 0h to 11Dh" bitfld.long 0x4 31. "PASS_V,No virtID replacement pass through value." "0,1" bitfld.long 0x4 28.--30. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 16.--27. 1. "VIRTID,Virt ID." hexmask.long.word 0x4 0.--15. 1. "RESERVED" tree.end tree "MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG" base ad:0x285C0000 rgroup.long 0x0++0x3 line.long 0x0 "UDMA_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision" bitfld.long 0x0 8.--10. "REVMAJ,Major" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor" group.long 0x4++0x7 line.long 0x0 "UDMA_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "UDMA_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" group.long 0x10++0x3 line.long 0x0 "UDMA_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" group.long 0x1C++0x3 line.long 0x0 "UDMA_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xB line.long 0x0 "UDMA_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" newline bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" newline bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" newline bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "UDMA_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." hexmask.long 0x4 4.--31. 1. "RESERVED" bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "UDMA_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.byte 0x8 27.--31. 1. "RESERVED" hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" rgroup.word 0x2C++0x1 line.word 0x0 "UDMA_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.word 0x0 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" group.long 0x80++0x3 line.long 0x0 "UDMA_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" group.long 0x88++0x3 line.long 0x0 "UDMA_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected until the pend bit is.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" bitfld.long 0x0 30. "RESERVED" "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.byte 0x0 9.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end tree "MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW" base ad:0x28400000 group.long 0x0++0x1F line.long 0x0 "UDMA_RFA_j,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." bitfld.long 0x0 31. "RESERVED" "0,1" bitfld.long 0x0 30. "EINFO,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in the PD and.." "0,1" newline bitfld.long 0x0 29. "PSINFO,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words that are.." "0,1" bitfld.long 0x0 28. "ERR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" bitfld.long 0x0 25. "PS_LOC,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will place the.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "SOP_OFF,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the minimum.." hexmask.long.word 0x0 0.--15. 1. "DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "UDMA_RFB_j,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." hexmask.long.byte 0x4 24.--31. 1. "SRCTAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." hexmask.long.byte 0x4 16.--23. 1. "SRCTAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "DSTTAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." hexmask.long.byte 0x4 0.--7. 1. "DSTTAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "UDMA_RFC_j,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." bitfld.long 0x8 31. "RESERVED" "0,1" bitfld.long 0x8 28.--30. "SRCTAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,7: 0 of the source tag field in Word 3 of the.." newline bitfld.long 0x8 27. "RESERVED" "0,1" bitfld.long 0x8 24.--26. "SRCTAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,7: 0 of the source tag field in Word 3 of the.." newline bitfld.long 0x8 23. "RESERVED" "0,1" bitfld.long 0x8 20.--22. "DSTTAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 19. "RESERVED" "0,1" bitfld.long 0x8 16.--18. "DSTTAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,7: 0 of the destination tag field in word 3 of the.." newline hexmask.long.word 0x8 3.--15. 1. "RESERVED" bitfld.long 0x8 0.--2. "SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the SOP.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "UDMA_RFD_j,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." hexmask.long.word 0xC 16.--31. 1. "FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." hexmask.long.word 0xC 0.--15. 1. "FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "UDMA_RFE_j,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." hexmask.long.word 0x10 16.--31. 1. "FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" hexmask.long.word 0x10 0.--15. 1. "FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "UDMA_RFF_j,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is.." hexmask.long.word 0x14 16.--31. 1. "SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the.." hexmask.long.word 0x14 0.--15. 1. "SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "UDMA_RFG_j,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is.." hexmask.long.word 0x18 16.--31. 1. "SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the.." hexmask.long.word 0x18 0.--15. 1. "FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "UDMA_RFH_j,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is.." hexmask.long.word 0x1C 16.--31. 1. "FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." hexmask.long.word 0x1C 0.--15. 1. "FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end tree "MCU_NAVSS0_UDMASS_UDMAP0_RCHAN" base ad:0x284C0000 group.long 0x0++0x3 line.long 0x0 "UDMA_RCFG_j,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0). Offset = 0h + (j * 100h); where.." bitfld.long 0x0 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." hexmask.long.byte 0x0 26.--30. 1. "RESERVED" newline bitfld.long 0x0 24.--25. "ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate to.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" hexmask.long.byte 0x0 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x0 16.--19. 1. "CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED 1 =.." bitfld.long 0x0 15. "IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated as.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." hexmask.long.byte 0x0 0.--6. 1. "FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." group.long 0x14++0x3 line.long 0x0 "UDMA_RCQ_j,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the channel is disabled.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." group.long 0x20++0x3 line.long 0x0 "UDMA_ROES_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" group.long 0x60++0xB line.long 0x0 "UDMA_REOES_j,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the corresponding register will be.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "UDMA_RPRI_CTRL_j,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface. Offset = 64h + (j * 100h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN j = 0h to 2Fh for.." bitfld.long 0x4 31. "RESERVED" "0,1" bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 19.--27. 1. "RESERVED" bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 4.--15. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "UDMA_THREAD_j,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register. Offset = 68h.." hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." group.long 0x80++0x3 line.long 0x0 "UDMA_RST_SCHED_j,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this register.." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority 3.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." group.long 0xF0++0x3 line.long 0x0 "UDMA_RFLOW_RNG_j,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel. Offset = F0h + (j * 100h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN j =.." bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline bitfld.long 0x0 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end tree "MCU_NAVSS0_UDMASS_UDMAP0_TCHAN" base ad:0x284A0000 group.long 0x0++0x7 line.long 0x0 "UDMA_TCFG_j,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0). Offset = 0h + (j * 100h); where.." bitfld.long 0x0 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." bitfld.long 0x0 30. "FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended packet.." "0: DMA controller will pass extended packet info..,1: DMA controller will filter extended packet info.." newline bitfld.long 0x0 29. "FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,1: DMA controller will filter PS words" bitfld.long 0x0 26.--28. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--25. "ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate to.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" hexmask.long.byte 0x0 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x0 16.--19. 1. "CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED 1 =.." bitfld.long 0x0 8. "NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline bitfld.long 0x0 7. "RESERVED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "UDMA_TCREDIT_j,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This field should not be changed.." hexmask.long 0x4 3.--31. 1. "RESERVED" bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" group.long 0x14++0x3 line.long 0x0 "UDMA_TCQ_j,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel is disabled (tx_enable in.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." group.long 0x20++0x3 line.long 0x0 "UDMA_TOES_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" group.long 0x60++0xB line.long 0x0 "UDMA_TEOES_j,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the corresponding register will be.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "UDMA_TPRI_CTRL_j,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface. Offset = 64h + (j * 100h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN j = 0h to 2Fh for.." bitfld.long 0x4 31. "RESERVED" "0,1" bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 19.--27. 1. "RESERVED" bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 4.--15. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "UDMA_THREAD_j,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register. Offset = 68h.." hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." group.long 0x70++0x3 line.long 0x0 "UDMA_TFIFO_DEPTH_j,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be artificially reduced in.." group.long 0x80++0x3 line.long 0x0 "UDMA_TST_SCHED_j,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this register.." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority 3.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end tree "MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" base ad:0x2A800000 group.long 0x0++0x3 line.long 0x0 "UDMA_RRT_CTL_j,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation. Offset = 0h + (j * 1000h); where j = 0h.." bitfld.long 0x0 31. "EN,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the attached.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "FTDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set teh implementation may choose to bypass data transfers and event generation. This bit is a modifier to the normal rx_teardown.." "0,1" newline hexmask.long 0x0 1.--27. 1. "RESERVED" rbitfld.long 0x0 0. "ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" wgroup.long 0x8++0x3 line.long 0x0 "UDMA_RRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA channel. This register has no.." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" group.long 0x80++0x3 line.long 0x0 "UDMA_RRT_STDATA_j_y,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the channel." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" group.long 0x200++0x3F line.long 0x0 "UDMA_RRT_PEER0_j,This register provides access to the remote peer's realtime register at 0x400. Offset = 200h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "UDMA_RRT_PEER1_j,This register provides access to the remote peer's realtime register at 0x401. Offset = 204h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "UDMA_RRT_PEER2_j,This register provides access to the remote peer's realtime register at 0x402. Offset = 208h + (j * 1000h); where j = 0h to 95h j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "UDMA_RRT_PEER3_j,This register provides access to the remote peer's realtime register at 0x403. Offset = 20Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "UDMA_RRT_PEER4_j,This register provides access to the remote peer's realtime register at 0x404. Offset = 210h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "UDMA_RRT_PEER5_j,This register provides access to the remote peer's realtime register at 0x405. Offset = 214h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "UDMA_RRT_PEER6_j,This register provides access to the remote peer's realtime register at 0x406. Offset = 218h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "UDMA_RRT_PEER7_j,This register provides access to the remote peer's realtime register at 0x407. Offset = 21Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "UDMA_RRT_PEER8_j,This register provides access to the remote peer's realtime register at 0x408. Offset = 220h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "UDMA_RRT_PEER9_j,This register provides access to the remote peer's realtime register at 0x409. Offset = 224h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "UDMA_RRT_PEER10_j,This register provides access to the remote peer's realtime register at 0x40A. Offset = 228h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "UDMA_RRT_PEER11_j,This register provides access to the remote peer's realtime register at 0x40B. Offset = 22Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "UDMA_RRT_PEER12_j,This register provides access to the remote peer's realtime register at 0x40C. Offset = 230h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "UDMA_RRT_PEER13_j,This register provides access to the remote peer's realtime register at 0x40D. Offset = 234h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "UDMA_RRT_PEER14_j,This register provides access to the remote peer's realtime register at 0x40E. Offset = 238h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "UDMA_RRT_PEER15_j,This register provides access to the remote peer's realtime register at 0x40F. Offset = 23Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." group.long 0x400++0x3 line.long 0x0 "UDMA_RRT_PCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 400h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." group.long 0x408++0x3 line.long 0x0 "UDMA_RRT_BCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 408h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "UDMA_RRT_SBCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 410h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree "MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" base ad:0x2AA00000 group.long 0x0++0x3 line.long 0x0 "UDMA_TRT_CTL_j,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation. Offset = 0h + (j * 1000h); where j = 0h.." bitfld.long 0x0 31. "EN,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the attached.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "FTDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the normal tx_teardown.." "0,1" newline hexmask.long 0x0 1.--27. 1. "RESERVED" rbitfld.long 0x0 0. "ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" wgroup.long 0x8++0x3 line.long 0x0 "UDMA_TRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register has no.." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "UDMA_TRT_STDATA_j_Y,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the channel." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" group.long 0x200++0x3F line.long 0x0 "UDMA_TRT_PEER0_j,This register provides access to the remote peer's realtime register at 0x400. Offset = 200h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "UDMA_TRT_PEER1_j,This register provides access to the remote peer's realtime register at 0x401. Offset = 204h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "UDMA_TRT_PEER2_j,This register provides access to the remote peer's realtime register at 0x402. Offset = 208h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "UDMA_TRT_PEER3_j,This register provides access to the remote peer's realtime register at 0x403. Offset = 20Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "UDMA_TRT_PEER4_j,This register provides access to the remote peer's realtime register at 0x404. Offset = 210h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "UDMA_TRT_PEER5_j,This register provides access to the remote peer's realtime register at 0x405. Offset = 214h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "UDMA_TRT_PEER6_j,This register provides access to the remote peer's realtime register at 0x406. Offset = 218h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "UDMA_TRT_PEER7_j,This register provides access to the remote peer's realtime register at 0x407. Offset = 21Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "UDMA_TRT_PEER8_j,This register provides access to the remote peer's realtime register at 0x408. Offset = 220h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "UDMA_TRT_PEER9_j,This register provides access to the remote peer's realtime register at 0x409. Offset = 224h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "UDMA_TRT_PEER10_j,This register provides access to the remote peer's realtime register at 0x40A. Offset = 228h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "UDMA_TRT_PEER11_j,This register provides access to the remote peer's realtime register at 0x40B. Offset = 22Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "UDMA_TRT_PEER12_j,This register provides access to the remote peer's realtime register at 0x40C. Offset = 230h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "UDMA_TRT_PEER13_j,This register provides access to the remote peer's realtime register at 0x40D. Offset = 234h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "UDMA_TRT_PEER14_j,This register provides access to the remote peer's realtime register at 0x40E. Offset = 238h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "UDMA_TRT_PEER15_j,This register provides access to the remote peer's realtime register at 0x40F. Offset = 23Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." group.long 0x400++0x3 line.long 0x0 "UDMA_TRT_PCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 400h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." group.long 0x408++0x3 line.long 0x0 "UDMA_TRT_BCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 408h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "UDMA_TRT_SBCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 410h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree.end tree "MCU_PLL0_CFG" base ad:0x40D00000 rgroup.long 0x0++0x3 line.long 0x0 "MCU_PLL0_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8++0x3 line.long 0x0 "MCU_PLL0_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x10++0x7 line.long 0x0 "MCU_PLL0_LOCKKEY0,Return to the . PLL0 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "MCU_PLL0_LOCKKEY1,Return to the . PLL0 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" group.long 0x20++0x3 line.long 0x0 "MCU_PLL0_CTRL,Return to the . PLL0 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "MCU_PLL0_STAT,Return to the . PLL0 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x30++0xB line.long 0x0 "MCU_PLL0_FREQ_CTRL0,Return to the . PLL0 Frequency Control 0 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported.In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "MCU_PLL0_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "MCU_PLL0_DIV_CTRL,Return to the . PLL0 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x40++0x7 line.long 0x0 "MCU_PLL0_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL0" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "MCU_PLL0_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL0" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x80++0x7 line.long 0x0 "MCU_PLL0_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL0" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "MCU_PLL0_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL0" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x1000++0x3 line.long 0x0 "MCU_PLL1_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x1008++0x3 line.long 0x0 "MCU_PLL1_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x1010++0x7 line.long 0x0 "MCU_PLL1_LOCKKEY0,Return to the . PLL1 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "MCU_PLL1_LOCKKEY1,Return to the . PLL1 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers" group.long 0x1020++0x3 line.long 0x0 "MCU_PLL1_CTRL,Return to the . PLL1 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x1024++0x3 line.long 0x0 "MCU_PLL1_STAT,Return to the . PLL1 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x1030++0xB line.long 0x0 "MCU_PLL1_FREQ_CTRL0,Return to the . PLL1 Frequency Control 1 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "MCU_PLL1_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "MCU_PLL1_DIV_CTRL,Return to the . PLL1 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x1040++0x7 line.long 0x0 "MCU_PLL1_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL1" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "MCU_PLL1_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL1" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x1080++0x13 line.long 0x0 "MCU_PLL1_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL1" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "MCU_PLL1_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL1" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "MCU_PLL1_HSDIV_CTRL2,Return to the . HSDIV_CTRL2 register for PLL1" bitfld.long 0x8 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x8 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x8 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x8 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "MCU_PLL1_HSDIV_CTRL3,Return to the . HSDIV_CTRL3 register for PLL1" bitfld.long 0xC 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0xC 16.--30. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0xC 9.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0xC 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "MCU_PLL1_HSDIV_CTRL4,Return to the . HSDIV_CTRL4 register for PLL1" bitfld.long 0x10 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x10 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x10 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x2000++0x3 line.long 0x0 "MCU_PLL2_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x2008++0x3 line.long 0x0 "MCU_PLL2_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x2010++0x7 line.long 0x0 "MCU_PLL2_LOCKKEY0,Return to the . PLL2 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "MCU_PLL2_LOCKKEY1,Return to the . PLL2 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers" group.long 0x2020++0x3 line.long 0x0 "MCU_PLL2_CTRL,Return to the . PLL2 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x2024++0x3 line.long 0x0 "MCU_PLL2_STAT,Return to the . PLL2 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x2030++0xB line.long 0x0 "MCU_PLL2_FREQ_CTRL0,Return to the . PLL2 Frequency Control 2 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "MCU_PLL2_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "MCU_PLL2_DIV_CTRL,Return to the . PLL2 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x2040++0x7 line.long 0x0 "MCU_PLL2_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL2" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "MCU_PLL2_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL2" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x2080++0x13 line.long 0x0 "MCU_PLL2_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL2" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "MCU_PLL2_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL2" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "MCU_PLL2_HSDIV_CTRL2,Return to the . HSDIV_CTRL2 register for PLL2" bitfld.long 0x8 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x8 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x8 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x8 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "MCU_PLL2_HSDIV_CTRL3,Return to the . HSDIV_CTRL3 register for PLL2" bitfld.long 0xC 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0xC 16.--30. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0xC 9.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0xC 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "MCU_PLL2_HSDIV_CTRL4,Return to the . HSDIV_CTRL4 register for PLL2" bitfld.long 0x10 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x10 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x10 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" tree.end base ad:0x0 tree "MCU_R5FSS" tree "MCU_R5FSS0" base ad:0x4072F000 group.long 0x0++0x3 line.long 0x0 "R5FSS_DISABLE_CR,Return to the . This register contains config bits to enable or disable change requests added to the IP." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "COMBINE_TCM_LOCKSTEP_MODE,This bit disables the CR logic to combine TCM in lockstep mode" "0,1" rgroup.long 0x4++0x13 line.long 0x0 "R5FSS_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS,Return to the . Status bits showing the R5FSS CPU0 EVNT BUS single-bit error counters." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16.--17. "EVNT_BUS8,Status bits showing the R5FSS CPU0 EVNT 8 single-bit error counter" "0,1,2,3" bitfld.long 0x0 14.--15. "EVNT_BUS7,Status bits showing the R5FSS CPU0 EVNT 7 single-bit error counter" "0,1,2,3" newline bitfld.long 0x0 12.--13. "EVNT_BUS6,Status bits showing the R5FSS CPU0 EVNT 6 single-bit error counter" "0,1,2,3" bitfld.long 0x0 10.--11. "EVNT_BUS5,Status bits showing the R5FSS CPU0 EVNT 5 single-bit error counter" "0,1,2,3" bitfld.long 0x0 8.--9. "EVNT_BUS4,Status bits showing the R5FSS CPU0 EVNT 4 single-bit error counter" "0,1,2,3" newline bitfld.long 0x0 6.--7. "EVNT_BUS3,Status bits showing the R5FSS CPU0 EVNT 3 single-bit error counter" "0,1,2,3" bitfld.long 0x0 4.--5. "EVNT_BUS2,Status bits showing the R5FSS CPU0 EVNT 2 single-bit error counter" "0,1,2,3" bitfld.long 0x0 2.--3. "EVNT_BUS1,Status bits showing the R5FSS CPU0 EVNT 1 single-bit error counter" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EVNT_BUS0,Status bits showing the R5FSS CPU0 EVNT 0 single-bit error counter" "0,1,2,3" line.long 0x4 "R5FSS_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS,Return to the . Status bits showing the R5FSS CPU1 EVNT BUS single-bit error counters." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16.--17. "EVNT_BUS8,Status bits showing the R5FSS CPU1 EVNT 8 single-bit error counter" "0,1,2,3" bitfld.long 0x4 14.--15. "EVNT_BUS7,Status bits showing the R5FSS CPU1 EVNT 7 single-bit error counter" "0,1,2,3" newline bitfld.long 0x4 12.--13. "EVNT_BUS6,Status bits showing the R5FSS CPU1 EVNT 6 single-bit error counter" "0,1,2,3" bitfld.long 0x4 10.--11. "EVNT_BUS5,Status bits showing the R5FSS CPU1 EVNT 5 single-bit error counter" "0,1,2,3" bitfld.long 0x4 8.--9. "EVNT_BUS4,Status bits showing the R5FSS CPU1 EVNT 4 single-bit error counter" "0,1,2,3" newline bitfld.long 0x4 6.--7. "EVNT_BUS3,Status bits showing the R5FSS CPU1 EVNT 3 single-bit error counter" "0,1,2,3" bitfld.long 0x4 4.--5. "EVNT_BUS2,Status bits showing the R5FSS CPU1 EVNT 2 single-bit error counter" "0,1,2,3" bitfld.long 0x4 2.--3. "EVNT_BUS1,Status bits showing the R5FSS CPU1 EVNT 1 single-bit error counter" "0,1,2,3" newline bitfld.long 0x4 0.--1. "EVNT_BUS0,Status bits showing the R5FSS CPU1 EVNT 0 single-bit error counter" "0,1,2,3" line.long 0x8 "R5FSS_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS,Return to the . Status bits showing the R5FSS CPU0 EVNT BUS multi-bit error counters." hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 12.--13. "EVNT_BUS6,Status bits showing the R5FSS CPU0 EVNT 6 multi-bit error counter" "0,1,2,3" bitfld.long 0x8 10.--11. "EVNT_BUS5,Status bits showing the R5FSS CPU0 EVNT 5 multi-bit error counter" "0,1,2,3" newline bitfld.long 0x8 8.--9. "EVNT_BUS4,Status bits showing the R5FSS CPU0 EVNT 4 multi-bit error counter" "0,1,2,3" bitfld.long 0x8 6.--7. "EVNT_BUS3,Status bits showing the R5FSS CPU0 EVNT 3 multi-bit error counter" "0,1,2,3" bitfld.long 0x8 4.--5. "EVNT_BUS2,Status bits showing the R5FSS CPU0 EVNT 2 multi-bit error counter" "0,1,2,3" newline bitfld.long 0x8 2.--3. "EVNT_BUS1,Status bits showing the R5FSS CPU0 EVNT 1 multi-bit error counter" "0,1,2,3" bitfld.long 0x8 0.--1. "EVNT_BUS0,Status bits showing the R5FSS CPU0 EVNT 0 multi-bit error counter" "0,1,2,3" line.long 0xC "R5FSS_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS,Return to the . Status bits showing the R5FSS CPU1 EVNT BUS multi-bit error counters." hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 12.--13. "EVNT_BUS6,Status bits showing the R5FSS CPU1 EVNT 6 multi-bit error counter" "0,1,2,3" bitfld.long 0xC 10.--11. "EVNT_BUS5,Status bits showing the R5FSS CPU1 EVNT 5 multi-bit error counter" "0,1,2,3" newline bitfld.long 0xC 8.--9. "EVNT_BUS4,Status bits showing the R5FSS CPU1 EVNT 4 multi-bit error counter" "0,1,2,3" bitfld.long 0xC 6.--7. "EVNT_BUS3,Status bits showing the R5FSS CPU1 EVNT 3 multi-bit error counter" "0,1,2,3" bitfld.long 0xC 4.--5. "EVNT_BUS2,Status bits showing the R5FSS CPU1 EVNT 2 multi-bit error counter" "0,1,2,3" newline bitfld.long 0xC 2.--3. "EVNT_BUS1,Status bits showing the R5FSS CPU1 EVNT 1 multi-bit error counter" "0,1,2,3" bitfld.long 0xC 0.--1. "EVNT_BUS0,Status bits showing the R5FSS CPU1 EVNT 0 multi-bit error counter" "0,1,2,3" line.long 0x10 "R5FSS_EVNT_BUS_ESM_STATUS,Return to the . ESM status bits for the R5FSS EVNT BUS." hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 3. "CPU1_MULTIPLE_BIT_ERROR,ESM status of CPU1 multi-bit errors on EVNT BUS" "0,1" bitfld.long 0x10 2. "CPU1_SINGLE_BIT_ERROR,ESM status of CPU1 single-bit errors on EVNT BUS" "0,1" newline bitfld.long 0x10 1. "CPU0_MULTIPLE_BIT_ERROR,ESM status of CPU0 multi-bit errors on EVNT BUS" "0,1" bitfld.long 0x10 0. "CPU0_SINGLE_BIT_ERROR,ESM status of CPU0 single-bit errors on EVNT BUS" "0,1" group.long 0x18++0xF line.long 0x0 "R5FSS_EVNT_BUS_ESM_SET,Return to the . Set the R5FSS EVNT BUS ESM events." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "CPU1_MULTIPLE_BIT_ERROR,Set CPU1 multi-bit errors ESM event" "0,1" bitfld.long 0x0 2. "CPU1_SINGLE_BIT_ERROR,Set CPU1 single-bit errors ESM event" "0,1" newline bitfld.long 0x0 1. "CPU0_MULTIPLE_BIT_ERROR,Set CPU0 multi-bit error ESM event" "0,1" bitfld.long 0x0 0. "CPU0_SINGLE_BIT_ERROR,Set CPU0 single-bit error ESM event" "0,1" line.long 0x4 "R5FSS_EVNT_BUS_ESM_CLR,Return to the . RESET the R5FSS EVNT BUS ESM events." bitfld.long 0x4 31. "CPU1_EB6_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 31 multi-bit error counter" "0,1" bitfld.long 0x4 30. "CPU1_EB5_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 30 multi-bit error counter" "0,1" bitfld.long 0x4 29. "CPU1_EB4_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 29 multi-bit error counter" "0,1" newline bitfld.long 0x4 28. "CPU1_EB3_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 28 multi-bit error counter" "0,1" bitfld.long 0x4 27. "CPU1_EB2_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 27 multi-bit error counter" "0,1" bitfld.long 0x4 26. "CPU1_EB1_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 26 multi-bit error counter" "0,1" newline bitfld.long 0x4 25. "CPU1_EB0_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 25 multi-bit error counter" "0,1" bitfld.long 0x4 24. "CPU1_EB8_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 24 single-bit error counter" "0,1" bitfld.long 0x4 23. "CPU1_EB7_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 23 single-bit error counter" "0,1" newline bitfld.long 0x4 22. "CPU1_EB6_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 22 single-bit error counter" "0,1" bitfld.long 0x4 21. "CPU1_EB5_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 21 single-bit error counter" "0,1" bitfld.long 0x4 20. "CPU1_EB4_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 20 single-bit error counter" "0,1" newline bitfld.long 0x4 19. "CPU1_EB3_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 19 single-bit error counter" "0,1" bitfld.long 0x4 18. "CPU1_EB2_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 18 single-bit error counter" "0,1" bitfld.long 0x4 17. "CPU1_EB1_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 17 single-bit error counter" "0,1" newline bitfld.long 0x4 16. "CPU1_EB0_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 16 single-bit error counter" "0,1" bitfld.long 0x4 15. "CPU0_EB6_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 15 multi-bit error counter" "0,1" bitfld.long 0x4 14. "CPU0_EB5_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 14 multi-bit error counter" "0,1" newline bitfld.long 0x4 13. "CPU0_EB4_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 13 multi-bit error counter" "0,1" bitfld.long 0x4 12. "CPU0_EB3_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 12 multi-bit error counter" "0,1" bitfld.long 0x4 11. "CPU0_EB2_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 11 multi-bit error counter" "0,1" newline bitfld.long 0x4 10. "CPU0_EB1_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 10 multi-bit error counter" "0,1" bitfld.long 0x4 9. "CPU0_EB0_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 9 multi-bit error counter" "0,1" bitfld.long 0x4 8. "CPU0_EB8_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 8 single-bit error counter" "0,1" newline bitfld.long 0x4 7. "CPU0_EB7_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 7 single-bit error counter" "0,1" bitfld.long 0x4 6. "CPU0_EB6_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 6 single-bit error counter" "0,1" bitfld.long 0x4 5. "CPU0_EB5_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 5 single-bit error counter" "0,1" newline bitfld.long 0x4 4. "CPU0_EB4_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 4 single-bit error counter" "0,1" bitfld.long 0x4 3. "CPU0_EB3_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 3 single-bit error counter" "0,1" bitfld.long 0x4 2. "CPU0_EB2_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 2 single-bit error counter" "0,1" newline bitfld.long 0x4 1. "CPU0_EB1_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 1 single-bit error counter" "0,1" bitfld.long 0x4 0. "CPU0_EB0_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 0 single-bit error counter" "0,1" line.long 0x8 "R5FSS_EVNT_BUS_MASK_ESM_SET,Return to the . Mask the R5FSS EVNT BUS ESM events." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "CPU1_MULTIPLE_BIT_ERROR,Mask CPU1 multi-bit errors ESM event" "0,1" bitfld.long 0x8 2. "CPU1_SINGLE_BIT_ERROR,Mask CPU1 single-bit errors ESM event" "0,1" newline bitfld.long 0x8 1. "CPU0_MULTIPLE_BIT_ERROR,Mask CPU0 multi-bit error ESM event" "0,1" bitfld.long 0x8 0. "CPU0_SINGLE_BIT_ERROR,Mask CPU0 single-bit error ESM event" "0,1" line.long 0xC "R5FSS_EVNT_BUS_MASK_ESM_CLR,Return to the . Unmask the R5FSS EVNT BUS ESM events." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 3. "CPU1_MULTIPLE_BIT_ERROR,Unmask CPU1 multi-bit errors ESM event" "0,1" bitfld.long 0xC 2. "CPU1_SINGLE_BIT_ERROR,Unmask CPU1 single-bit errors ESM event" "0,1" newline bitfld.long 0xC 1. "CPU0_MULTIPLE_BIT_ERROR,Unmask CPU0 multi-bit error ESM event" "0,1" bitfld.long 0xC 0. "CPU0_SINGLE_BIT_ERROR,Unmask CPU0 single-bit error ESM event" "0,1" tree.end tree "MCU_R5FSS0_COMPARE_CFG" base ad:0x400F0000 group.long 0x0++0x7 line.long 0x0 "R5FSS_CCMSR1,This register shows the error and self-test status of the CPU output compare block." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 16. "CMPE1,Compare error for CPU output compare diagnostic." "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 8. "STC1,Self-test complete for CPU output compare diagnostic." "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 1. "STET1,Self-test error type for CPU output compare diagnostic." "0,1" bitfld.long 0x0 0. "STE1,Self-test error for CPU output compare diagnostic." "0,1" line.long 0x4 "R5FSS_CCMKEYR1,This register is used to select the operating mode of the CPU output compare block." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x4 0.--3. 1. "MKEY1,Mode key to select operation for CPU output compare diagnostic." group.long 0x10++0xB line.long 0x0 "R5FSS_CCMSR3,This register shows the error and self-test status of the inactivity monitor block." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 16. "CMPE3,Compare error for inactivity monitor." "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 8. "STC3,Self-test complete for inactivity monitor." "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 1. "STET3,Self-test error type for inactivity monitor." "0,1" bitfld.long 0x0 0. "STE3,Self-test error for inactivity monitor." "0,1" line.long 0x4 "R5FSS_CCMKEYR3,This register is used to select the operating mode of the inactivity monitor block." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x4 0.--3. 1. "MKEY3,Mode key to select operation for CPU output compare diagnostic." line.long 0x8 "R5FSS_CCMPOLCNTRL,This register is used for polarity inversion of CPU compare signals." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x8 0.--7. 1. "POL_INV,Polarity inversion. This value is used to invert one of the 8 output compare signals from CPU1 to the R5FSS_CCMR5. Inverting any one signal will lead to compare error by the CPU output compare diagnostic." tree.end tree "MCU_R5FSS0_CORE0_ECC_AGGR" base ad:0x40080000 rgroup.long 0x0++0x3 line.long 0x0 "R5FSS_CPU0_REV,Revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "R5FSS_CPU0_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address." bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved." hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "R5FSS_CPU0_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator." group.long 0x3C++0xB line.long 0x0 "R5FSS_CPU0_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 0. "EOI_WR,EOI value." "0,1" line.long 0x4 "R5FSS_CPU0_SEC_STATUS_REG0,SEC interrupt status register 0." bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "R5FSS_CPU0_SEC_STATUS_REG1,SEC interrupt status register 1." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1" bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x80++0x7 line.long 0x0 "R5FSS_CPU0_SEC_ENABLE_SET_REG0,SEC Interrupt enable set register 0." bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU0_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1" bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0xC0++0x7 line.long 0x0 "R5FSS_CPU0_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU0_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1" bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x13C++0xB line.long 0x0 "R5FSS_CPU0_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 0. "EOI_WR,EOI value." "0,1" line.long 0x4 "R5FSS_CPU0_DED_STATUS_REG0,DED interrupt status register 0." bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "R5FSS_CPU0_DED_STATUS_REG1,DED interrupt status register 1." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1" bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x180++0x7 line.long 0x0 "R5FSS_CPU0_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU0_DED_ENABLE_SET_REG1,DED interrupt enable set register 1." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1" bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x1C0++0x7 line.long 0x0 "R5FSS_CPU0_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU0_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1" bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "R5FSS_CPU0_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "R5FSS_CPU0_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "R5FSS_CPU0_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "R5FSS_CPU0_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_R5FSS0_ECC_AGGR" base ad:0x400C0000 rgroup.long 0x0++0x3 line.long 0x0 "R5FSS_CPU1_REV,Revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "R5FSS_CPU1_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address." bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved." hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "R5FSS_CPU1_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x3C++0xB line.long 0x0 "R5FSS_CPU1_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "R5FSS_CPU1_SEC_STATUS_REG0,SEC interrupt status register 0." bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "R5FSS_CPU1_SEC_STATUS_REG1,SEC interrupt status register 1." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x80++0x7 line.long 0x0 "R5FSS_CPU1_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU1_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0xC0++0x7 line.long 0x0 "R5FSS_CPU1_SEC_ENABLE_CLR_REG0,SC interrupt enable clear register 0." bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU1_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x13C++0xB line.long 0x0 "R5FSS_CPU1_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "R5FSS_CPU1_DED_STATUS_REG0,DED interrupt status register 0." bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "R5FSS_CPU1_DED_STATUS_REG1,DED interrupt status register 1." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x180++0x7 line.long 0x0 "R5FSS_CPU1_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU1_DED_ENABLE_SET_REG1,DED interrupt enable set register 1." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x1C0++0x7 line.long 0x0 "R5FSS_CPU1_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU1_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "R5FSS_CPU1_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "R5FSS_CPU1_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "R5FSS_CPU1_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "R5FSS_CPU1_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "MCU_RTI" tree "MCU_RTI0_CFG" base ad:0x40600000 group.long 0x0++0x1B line.long 0x0 "RTI_GCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "COS,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting." "0,1" hexmask.long.word 0x0 2.--14. 1. "RESERVED,Reserved." bitfld.long 0x0 1. "CNT1EN,Counter 1 Enable." "0,1" bitfld.long 0x0 0. "CNT0EN,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0)." "0,1" line.long 0x4 "RTI_TBCTRL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected." "0,1" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0,1" line.long 0x8 "RTI_CAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 1. "CAPCNTR1,Capture Counter 1." "0,1" bitfld.long 0x8 0. "CAPCNTR0,Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0." "0,1" line.long 0xC "RTI_COMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 12. "COMPSEL3,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared." "0,1" rbitfld.long 0xC 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "COMPSEL2,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared." "0,1" rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4. "COMPSEL1,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared." "0,1" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0. "COMPSEL0,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared." "0,1" line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously." hexmask.long 0x10 0.--31. 1. "FRC0,Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously." line.long 0x14 "RTI_UC0" hexmask.long 0x14 0.--31. 1. "UC0,Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,Compare Up Counter 0. This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value." rgroup.long 0x20++0x7 line.long 0x0 "RTI_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the" group.long 0x30++0xB line.long 0x0 "RTI_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously." line.long 0x4 "RTI_UC1" hexmask.long 0x4 0.--31. 1. "UC1,Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,Compare Up Counter 1. This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value." rgroup.long 0x40++0x7 line.long 0x0 "RTI_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the" group.long 0x50++0x1F line.long 0x0 "RTI_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x4 "RTI_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x8 "RTI_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,Compare 1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0xC "RTI_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,Update Compare 1 Register. This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x10 "RTI_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,Compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." hexmask.long 0x14 0.--31. 1. "UDCP2,Update Compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x18 "RTI_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,Compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x1C "RTI_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,Update Compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." rgroup.long 0x70++0x7 line.long 0x0 "RTI_TBLCOMP" hexmask.long 0x0 0.--31. 1. "TBLCOMP,Reserved" line.long 0x4 "RTI_TBHCOMP" hexmask.long 0x4 0.--31. 1. "TBHCOMP,Reserved" group.long 0x80++0xB line.long 0x0 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x0 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read):" "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "SETDMA3,Set Compare DMA Request 3." "0,1" newline bitfld.long 0x0 10. "SETDMA2,Set Compare DMA Request 2." "0,1" bitfld.long 0x0 9. "SETDMA1,Set Compare DMA Request 1." "0,1" bitfld.long 0x0 8. "SETDMA0,Set Compare DMA Request 0." "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "SETINT3,Set Compare Interrupt 3." "0,1" bitfld.long 0x0 2. "SETINT2,Set Compare Interrupt 2." "0,1" newline bitfld.long 0x0 1. "SETINT1,Set Compare Interrupt 1." "0,1" bitfld.long 0x0 0. "SETINT0,Set Compare Interrupt 0." "0,1" line.long 0x4 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see.." hexmask.long.word 0x4 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x4 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x4 16. "CLEARTBINT" "0,1" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 11. "CLEARDMA3,Clear Compare DMA Request 3." "0,1" newline bitfld.long 0x4 10. "CLEARDMA2,Clear Compare DMA Request 2." "0,1" bitfld.long 0x4 9. "CLEARDMA1,Clear Compare DMA Request 1." "0,1" bitfld.long 0x4 8. "CLEARDMA0,Clear Compare DMA Request 0." "0,1" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CLEARINT3,Clear Compare Interrupt 3." "0,1" bitfld.long 0x4 2. "CLEARINT2,Clear Compare Interrupt 2." "0,1" newline bitfld.long 0x4 1. "CLEARINT1,Clear Compare Interrupt 1." "0,1" bitfld.long 0x4 0. "CLEARINT0,Clear Compare Interrupt 0." "0,1" line.long 0x8 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not." hexmask.long.word 0x8 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software." "0,1" hexmask.long.word 0x8 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "INT3,Interrupt Flag 3." "0,1" newline bitfld.long 0x8 2. "INT2,Interrupt Flag 2." "0,1" bitfld.long 0x8 1. "INT1,Interrupt Flag 1." "0,1" bitfld.long 0x8 0. "INT0,Interrupt Flag 0." "0,1" group.long 0x90++0xF line.long 0x0 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be.." hexmask.long 0x0 0.--31. 1. "DWDCTRL,Digital Watchdog Control." line.long 0x4 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value." line.long 0x8 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These.." hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 5. "DWWD_ST,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog." "0,1" bitfld.long 0x8 4. "END,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag." "0,1" bitfld.long 0x8 3. "START,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened." "0,1" bitfld.long 0x8 2. "KEYST,Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the" "0,1" bitfld.long 0x8 1. "DWDST,Digital Watchdog Status. Status flag and is maintained for compatibility reasons." "0,1" newline bitfld.long 0x8 0. "AWDST,Analog Watchdog Status." "0,1" line.long 0xC "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -&gt; Value written to WDKEY -&gt; Result1 -&gt; 0x0A35C -&gt; No Action2 -&gt; 0x0A35C -&gt; No Action3 -&gt; 0x0E51A -&gt; WDKEY is enabled for reset by next 0x0A35C4.." rgroup.long 0xA0++0x3 line.long 0x0 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" hexmask.long 0x0 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 01FFFFFFh. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3 MHz a watchdog reset will be generated in.." group.long 0xA4++0x1B line.long 0x0 "RTI_WWDRXNCTRL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,Digital Windowed Watchdog Reaction." line.long 0x4 "RTI_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,Digital Windowed Watchdog Window Size." line.long 0x8 "RTI_INTCLRENABLE" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt." hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt." hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt." line.long 0xC "RTI_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared." line.long 0x10 "RTI_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared." line.long 0x14 "RTI_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared." line.long 0x18 "RTI_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared." tree.end tree "MCU_RTI1_CFG" base ad:0x40610000 group.long 0x0++0x1B line.long 0x0 "RTI_GCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "COS,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting." "0,1" hexmask.long.word 0x0 2.--14. 1. "RESERVED,Reserved." bitfld.long 0x0 1. "CNT1EN,Counter 1 Enable." "0,1" bitfld.long 0x0 0. "CNT0EN,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0)." "0,1" line.long 0x4 "RTI_TBCTRL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected." "0,1" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0,1" line.long 0x8 "RTI_CAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 1. "CAPCNTR1,Capture Counter 1." "0,1" bitfld.long 0x8 0. "CAPCNTR0,Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0." "0,1" line.long 0xC "RTI_COMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 12. "COMPSEL3,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared." "0,1" rbitfld.long 0xC 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "COMPSEL2,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared." "0,1" rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4. "COMPSEL1,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared." "0,1" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0. "COMPSEL0,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared." "0,1" line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously." hexmask.long 0x10 0.--31. 1. "FRC0,Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously." line.long 0x14 "RTI_UC0" hexmask.long 0x14 0.--31. 1. "UC0,Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,Compare Up Counter 0. This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value." rgroup.long 0x20++0x7 line.long 0x0 "RTI_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the" group.long 0x30++0xB line.long 0x0 "RTI_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously." line.long 0x4 "RTI_UC1" hexmask.long 0x4 0.--31. 1. "UC1,Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,Compare Up Counter 1. This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value." rgroup.long 0x40++0x7 line.long 0x0 "RTI_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the" group.long 0x50++0x1F line.long 0x0 "RTI_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x4 "RTI_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x8 "RTI_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,Compare 1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0xC "RTI_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,Update Compare 1 Register. This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x10 "RTI_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,Compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." hexmask.long 0x14 0.--31. 1. "UDCP2,Update Compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x18 "RTI_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,Compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x1C "RTI_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,Update Compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." rgroup.long 0x70++0x7 line.long 0x0 "RTI_TBLCOMP" hexmask.long 0x0 0.--31. 1. "TBLCOMP,Reserved" line.long 0x4 "RTI_TBHCOMP" hexmask.long 0x4 0.--31. 1. "TBHCOMP,Reserved" group.long 0x80++0xB line.long 0x0 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x0 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read):" "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "SETDMA3,Set Compare DMA Request 3." "0,1" newline bitfld.long 0x0 10. "SETDMA2,Set Compare DMA Request 2." "0,1" bitfld.long 0x0 9. "SETDMA1,Set Compare DMA Request 1." "0,1" bitfld.long 0x0 8. "SETDMA0,Set Compare DMA Request 0." "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "SETINT3,Set Compare Interrupt 3." "0,1" bitfld.long 0x0 2. "SETINT2,Set Compare Interrupt 2." "0,1" newline bitfld.long 0x0 1. "SETINT1,Set Compare Interrupt 1." "0,1" bitfld.long 0x0 0. "SETINT0,Set Compare Interrupt 0." "0,1" line.long 0x4 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see.." hexmask.long.word 0x4 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x4 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x4 16. "CLEARTBINT" "0,1" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 11. "CLEARDMA3,Clear Compare DMA Request 3." "0,1" newline bitfld.long 0x4 10. "CLEARDMA2,Clear Compare DMA Request 2." "0,1" bitfld.long 0x4 9. "CLEARDMA1,Clear Compare DMA Request 1." "0,1" bitfld.long 0x4 8. "CLEARDMA0,Clear Compare DMA Request 0." "0,1" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CLEARINT3,Clear Compare Interrupt 3." "0,1" bitfld.long 0x4 2. "CLEARINT2,Clear Compare Interrupt 2." "0,1" newline bitfld.long 0x4 1. "CLEARINT1,Clear Compare Interrupt 1." "0,1" bitfld.long 0x4 0. "CLEARINT0,Clear Compare Interrupt 0." "0,1" line.long 0x8 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not." hexmask.long.word 0x8 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software." "0,1" hexmask.long.word 0x8 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "INT3,Interrupt Flag 3." "0,1" newline bitfld.long 0x8 2. "INT2,Interrupt Flag 2." "0,1" bitfld.long 0x8 1. "INT1,Interrupt Flag 1." "0,1" bitfld.long 0x8 0. "INT0,Interrupt Flag 0." "0,1" group.long 0x90++0xF line.long 0x0 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be.." hexmask.long 0x0 0.--31. 1. "DWDCTRL,Digital Watchdog Control." line.long 0x4 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value." line.long 0x8 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These.." hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 5. "DWWD_ST,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog." "0,1" bitfld.long 0x8 4. "END,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag." "0,1" bitfld.long 0x8 3. "START,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened." "0,1" bitfld.long 0x8 2. "KEYST,Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the" "0,1" bitfld.long 0x8 1. "DWDST,Digital Watchdog Status. Status flag and is maintained for compatibility reasons." "0,1" newline bitfld.long 0x8 0. "AWDST,Analog Watchdog Status." "0,1" line.long 0xC "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -&gt; Value written to WDKEY -&gt; Result1 -&gt; 0x0A35C -&gt; No Action2 -&gt; 0x0A35C -&gt; No Action3 -&gt; 0x0E51A -&gt; WDKEY is enabled for reset by next 0x0A35C4.." rgroup.long 0xA0++0x3 line.long 0x0 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" hexmask.long 0x0 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 01FFFFFFh. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3 MHz a watchdog reset will be generated in.." group.long 0xA4++0x1B line.long 0x0 "RTI_WWDRXNCTRL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,Digital Windowed Watchdog Reaction." line.long 0x4 "RTI_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,Digital Windowed Watchdog Window Size." line.long 0x8 "RTI_INTCLRENABLE" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt." hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt." hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt." line.long 0xC "RTI_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared." line.long 0x10 "RTI_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared." line.long 0x14 "RTI_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared." line.long 0x18 "RTI_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared." tree.end tree.end tree "MCU_SEC_MMR" tree "MCU_SEC_MMR0_BOOT_CTRL" base ad:0x45A50000 rgroup.long 0x20++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_DEF,Defines the type of the processor cluster." hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16.--18. "CORE_NUM,Number of cores in cluster" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. "DSP_CORE_TYPE,DSP core type configuration 00h - C7x 01h - C6x FFh - Not DSP" hexmask.long.byte 0x0 0.--7. 1. "ARM_CORE_TYPE,ARM core type configuration 00h - A53 01h - A57 10h - R5 FFh - Not ARM" group.long 0x40++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CFG,Configures cluster level characteristics." hexmask.long 0x0 5.--31. 1. "CLSTR_CFG_RSVD,Reserved for future use. Write '0' to ensure compatibility with future devices." bitfld.long 0x0 4. "MEM_INIT_DIS,Disables SRAM initialization (TCM etc) at reset " "0,1" rbitfld.long 0x0 3. "LOCKSTEP_EN,Lockstep enable. Indicates if R5 lockstep operation is supported on the device" "0,1" bitfld.long 0x0 2. "DBG_NO_CLKSTOP,CPU clockstop behavior" "0,1" newline bitfld.long 0x0 1. "TEINIT,Exception handling state at reset:" "0,1" bitfld.long 0x0 0. "LOCKSTEP,When set Core0 and Core1 operate in lockstep mode. Can only be changed if lockstep operation is supported as indicated by CLSTR0_CFG_lockstep_en = 1. If CLSTR0_CFG_lockstep_en = 0 lockstep is not supported this bit will be read only with a.." "0,1" group.long 0x100++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE0_CFG,Configures the TCM and interrupt operation of R5 Core0." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts" "0,1" rbitfld.long 0x0 12.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator" "0,1" newline rbitfld.long 0x0 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "BTCM_EN,Enable Core0 BTCM RAM at reset" "0,1" rbitfld.long 0x0 4.--6. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "ATCM_EN,Enable Core0 ATCM RAM at reset" "0,1" newline rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" group.long 0x110++0x7 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE0_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core0. Bits 6:0 are not used and are always 0." hexmask.long 0x0 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." hexmask.long.byte 0x0 0.--6. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_MCUSEC_CLSTR0_CORE0_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core0." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." group.long 0x120++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE0_PMCTRL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CORE_HALT,Halt Core0.When 0 indicates that Core0 is in the Halt state." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE0_PMSTAT,Shows Cluster Core0 power status." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "CLK_GATE,Core0 Clocked stopped due to WFI or WFE state" "0,1" bitfld.long 0x0 2. "RESERVED,Reserved" "0,1" bitfld.long 0x0 1. "WFE,Core0 WFE" "0,1" newline bitfld.long 0x0 0. "WFI,Core0 WFI" "0,1" group.long 0x180++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE1_CFG,Configures the TCM and interrupt operation of R5 Core1." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts" "0,1" rbitfld.long 0x0 12.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator" "0,1" newline rbitfld.long 0x0 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "BTCM_EN,Enable Core1 BTCM RAM at reset" "0,1" rbitfld.long 0x0 4.--6. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "ATCM_EN,Enable Core1 ATCM RAM at reset" "0,1" newline rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" group.long 0x190++0x7 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE1_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core1. Bits 6:0 are not used and are always 0." hexmask.long 0x0 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." hexmask.long.byte 0x0 0.--6. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_MCUSEC_CLSTR0_CORE1_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core1." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." group.long 0x1A0++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE1_PMCTRL,Configures Cluster Core1 power state." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CORE_HALT,Halt Core1.When 0 indicates that Core1 is in the Halt state." "0,1" rgroup.long 0x1B0++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE1_PMSTAT,Shows Cluster Core1 power status." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "CLK_GATE,Core1 Clocked stopped due to WFI or WFE state" "0,1" bitfld.long 0x0 2. "RESERVED,Reserved" "0,1" bitfld.long 0x0 1. "WFE,Core1 WFE" "0,1" newline bitfld.long 0x0 0. "WFI,Core1 WFI" "0,1" tree.end tree "MCU_SEC_MMR0_DBG_CTRL" base ad:0x45950000 group.long 0x0++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE0_DBG_CFG,Configures debug operation for Cluster Core0." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "DBGEN,Core0 Invasive debug enable." hexmask.long.byte 0x0 8.--11. 1. "NIDEN,Core0 Non-invasive debug enable." hexmask.long.byte 0x0 0.--7. 1. "RESERVED,Reserved" group.long 0x40++0x3 line.long 0x0 "CTRLMMR_MCUSEC_CLSTR0_CORE1_DBG_CFG,Configures debug operation for Cluster Core1." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "DBGEN,Core1 Invasive debug enable." hexmask.long.byte 0x0 8.--11. 1. "NIDEN,Core1 Non-invasive debug enable." hexmask.long.byte 0x0 0.--7. 1. "RESERVED,Reserved" tree.end tree.end tree "MCU_TIMER" tree "MCU_TIMER0_CFG" base ad:0x40400000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER1_CFG" base ad:0x40410000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER2_CFG" base ad:0x40420000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER3_CFG" base ad:0x40430000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER4_CFG" base ad:0x40440000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER5_CFG" base ad:0x40450000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER6_CFG" base ad:0x40460000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER7_CFG" base ad:0x40470000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER8_CFG" base ad:0x40480000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "MCU_TIMER9_CFG" base ad:0x40490000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree.end tree "MCU_UART0" base ad:0x40A00000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree.end tree "MMCSD" base ad:0x0 tree "MMCSD0_CTL_CFG" base ad:0x4F80000 group.word 0x0++0xF line.word 0x0 "MMCSD0_SDMA_SYS_ADDR_LO,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,32-bit Block Count (SDMA System Address) Low When the When the (1) SDMA System Address ( This register contains the system memory address for a SDMA transfer in 32-bit addressing mode. When the Host Controller (HC) stops a SDMA transfer .." line.word 0x2 "MMCSD0_SDMA_SYS_ADDR_HI,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,32-bit Block Count (SDMA System Address) High This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version.." line.word 0x4 "MMCSD0_BLOCK_SIZE,This register is used to configure the number of bytes in a data block." rbitfld.word 0x4 15. "RESERVED,Reserved" "0,1" bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,Host SDMA Buffer Size To perform long DMA transfer System Address register ( These bits shall support when the 0h: 4KB (Detects A11 Carry out) 1h: 8KB (Detects A12 Carry out) 2h: 16KB (Detects A13 Carry out) 3h: 32KB (Detects A14 Carry.." "0,1,2,3,4,5,6,7" hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,Transfer Block Size This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53. It can be accessed only if no transaction is executing (after a transaction has stopped). Read operations during.." line.word 0x6 "MMCSD0_BLOCK_COUNT,This register is used to configure the number of data blocks." hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,16-bit Block Count Host Controller Version 4.10 extends block count to 32-bit. Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: (1) If the (2) If the Use of 16-bit/32-bit Block Count.." line.word 0x8 "MMCSD0_ARGUMENT1_LO,This register contains Lower bits of SD Command Argument." hexmask.word 0x8 0.--15. 1. "CMD_ARG1,Command Argument 1 Low The SD Command Argument is specified as bit 23-8 of Command-Format." line.word 0xA "MMCSD0_ARGUMENT1_HI,This register contains higher bits of SD Command Argument." hexmask.word 0xA 0.--15. 1. "CMD_ARG1,Command Argument 1 High The SD Command Argument is specified as bit 39-24 of Command-Format." line.word 0xC "MMCSD0_TRANSFER_MODE" hexmask.word.byte 0xC 9.--15. 1. "RESERVED,Reserved" bitfld.word 0xC 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0h.." "0,1" bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error this bit is set.." "0,1" newline bitfld.word 0xC 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled ( Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "0,1" bitfld.word 0xC 5. "MULTI_BLK_SEL,Multi/Single Block Select This bit enables multiple block data transfers. 0h: Single Block 1h: Multiple Block" "0,1" bitfld.word 0xC 4. "DATA_XFER_DIR,Data Transfer Direction Select This bit defines the direction of data transfers. 0h: Write (Host to Card) 1h: Read (Card to Host)" "0,1" newline bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,Auto CMD Enable This field determines use of auto command functions. There are three methods to stop Multiple-block read and write operation by CMD23 or CMD12. In the other operations (for example single read/write operation) this field is.." "0,1,2,3" bitfld.word 0xC 1. "BLK_CNT_ENA,Block Count Enable This bit is used to enable the 0h: Disable 1h: Enable" "0,1" bitfld.word 0xC 0. "DMA_ENA,DMA Enable DMA can be enabled only if the 0h: Disable 1h: Enable" "0,1" line.word 0xE "MMCSD0_COMMAND,This register is used to program the Command for host controller." rbitfld.word 0xE 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,Command Index This bit shall be set to the command number (CMD0-63 ACMD0-63)." bitfld.word 0xE 6.--7. "CMD_TYPE,Command Type There are three types of special commands. Suspend Resume and Abort. These bits shall be set to 0h for all other commands. Suspend Command: Resume Command: Abort Command: 0h: Normal 1h: Suspend 2h: Resume 3h: Abort" "0,1,2,3" newline bitfld.word 0xE 5. "DATA_PRESENT,Data Present Select This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line. If is set to 0h for the following: 0h: No Data Present 1h: Data Present" "0,1" bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,Command Index Check Enable If this bit is set to 1h the HC shall check the index field in the response to see if it has the same value as the command index. If it is not it is reported as a Command Index Error. If this bit is set to.." "0,1" bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,Command CRC Check Enable If this bit is set to 1h the HC shall check the CRC field in the response. If an error is detected it is reported as a Command CRC Error. If this bit is set to 0h the CRC field is not checked. 0h: Disable 1h:.." "0,1" newline bitfld.word 0xE 2. "SUB_CMD,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command this bit is set to 0h and when issuing a sub command this bit is set to 1h. Setting of this bit is checked by the.." "0,1" bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select 0h: No Response 1h: Response length 136 2h: Response length 48 3h: Response length 48 check Busy after response" "0,1,2,3" rgroup.word 0x10++0x1 line.word 0x0 "MMCSD0_RESPONSE_0,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.word 0x14++0x1 line.word 0x0 "MMCSD0_RESPONSE_1,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.word 0x18++0x1 line.word 0x0 "MMCSD0_RESPONSE_2,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.word 0x1C++0x1 line.word 0x0 "MMCSD0_RESPONSE_3,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.long 0x20++0x3 line.long 0x0 "MMCSD0_DATA_PORT,This register is used to access internal buffer." hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,Buffer Data The Host Controller Buffer can be accessed through this 32-bit Data Port Register." rgroup.word 0x20++0x1 line.word 0x0 "MMCSD0_RESPONSE_4,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.long 0x24++0x3 line.long 0x0 "MMCSD0_PRESENTSTATE,The Host Driver can get status of the Host Controller from this 32-bit read-only register." bitfld.long 0x0 31. "UHS2_IF_DETECTION,UHS-II IF Detection (UHS-II Only) This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( After UHS-II IF is detected this bit is cleared.." "0,1" bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,Lane Synchronization (UHS-II Only) This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( In case of Version 4.00 this bit.." "0,1" bitfld.long 0x0 29. "UHS2_DORMANT,In Dormant State (UHS-II Only) This status indicates whether UHS-II lanes enter Dormant state. This function is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( RCLK may be stopped in dormant state by.." "0,1" newline bitfld.long 0x0 28. "SUB_COMMAND_STS,Sub Command Status The 1h: Sub Command Status 0h: Main Command Status" "0,1" bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Command Not Issued by Error Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in.." "0,1" bitfld.long 0x0 25.--26. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 24. "SDIF_CMDIN,CMD Line Signal Level (SD Mode Only) This status is used to check CMD line level to recover from errors and for debugging." "0,1" bitfld.long 0x0 23. "SDIF_DAT3IN,DAT[3] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[3]. D23 - DAT[3]" "0,1" bitfld.long 0x0 22. "SDIF_DAT2IN,DAT[2] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[2]. D22 - DAT[2]" "0,1" newline bitfld.long 0x0 21. "SDIF_DAT1IN,DAT[1] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[1]. D21 - DAT[1]" "0,1" bitfld.long 0x0 20. "SDIF_DAT0IN,DAT[0] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. D20 - DAT[0]" "0,1" bitfld.long 0x0 19. "WRITE_PROTECT,Write Protect Switch Pin Level The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin. 0h: Write protected (SDWP# = 1) 1h: Write enabled (SDWP# = 0)" "0,1" newline bitfld.long 0x0 18. "CARD_DETECT,Card Detect Pin Level This bit reflects the inverse value of the SDCD# pin. 0h: No Card present (SDCD# = 1) 1h: Card present (SDCD# = 0)" "0,1" bitfld.long 0x0 17. "CARD_STATE_STABLE,Card State Stable This bit is used for testing. If it is 0h the Card Detect Pin Level is not stable. If this bit is set to 1h it means the Card Detect Pin Level is stable. The 0h: Reset of Debouncing 1h: No Card or Inserted" "0,1" bitfld.long 0x0 16. "CARD_INSERTED,Card Inserted This bit indicates whether a card has been inserted. Changing from 0h to 1h generates a Card Insertion interrupt in the If a Card is removed while its power is on and its clock is oscillating the HC shall clear the 0h: Reset.." "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "BUF_RD_ENA,Buffer Read Enable This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1h readable data exists in the buffer. A change of this bit from 1h to 0h.." "0,1" bitfld.long 0x0 10. "BUF_WR_ENA,Buffer Write Enable This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1h data can be written to the buffer. A change of this bit from 1h to 0h occurs when all.." "0,1" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,Read Transfer Active (SD Mode Only) This status is used for detecting completion of a read transfer. This bit is set to 1h for either of the following conditions: This bit is cleared to 0h for either of the following conditions: 1h:.." "0,1" bitfld.long 0x0 8. "WR_XFER_ACTIVE,Write Transfer Active (SD Mode Only) This status indicates a write transfer is active. If this bit is 0h it means no valid write data exists in the HC. This bit is set in either of the following cases: This bit is cleared in either of the.." "0,1" bitfld.long 0x0 7. "SDIF_DAT7IN,DAT[7] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging. D07 - DAT[7]" "0,1" newline bitfld.long 0x0 6. "SDIF_DAT6IN,DAT[6] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging. D06 - DAT[6]" "0,1" bitfld.long 0x0 5. "SDIF_DAT5IN,DAT[5] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging. D05 - DAT[5]" "0,1" bitfld.long 0x0 4. "SDIF_DAT4IN,DAT[4] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging. D04 - DAT[4]" "0,1" newline bitfld.long 0x0 3. "RETUNING_REQ,Re-Tuning Request (UHS-I Only) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive.." "0,1" bitfld.long 0x0 2. "DATA_LINE_ACTIVE,DAT Line Active (SD Mode Only) This bit indicates whether one of the DAT line on SD bus is in use. 1h: DAT line active 0h: DAT line inactive" "0,1" bitfld.long 0x0 1. "INHIBIT_DAT,Command Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h. If this bit is 0h it indicates the HC can issue the next SD command. Commands with busy signal belong.." "0,1" newline bitfld.long 0x0 0. "INHIBIT_CMD,Command Inhibit (CMD) 1h: Host Controller is not ready to issue a command 0h: Host Controller is ready to issue a command Version 4.10 adds a new control to prevent error statuses from overwriting by receipt of a next command. This status.." "0,1" rgroup.word 0x24++0x1 line.word 0x0 "MMCSD0_RESPONSE_5,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.byte 0x28++0x0 line.byte 0x0 "MMCSD0_HOST_CONTROL1,This register is used to program DMA modes. LED control. data transfer width. High Speed enable. card detect test level and signal selection." bitfld.byte 0x0 7. "CD_SIG_SEL,Card Detect Signal Detection This bit selects source for card detection. 1h: The card detect test level is selected 0h: SDCD# is selected (for normal use)" "0,1" bitfld.byte 0x0 6. "CD_TEST_LEVEL,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal interrupt status enable bit is set. 1h:.." "0,1" bitfld.byte 0x0 5. "EXT_DATA_WIDTH,Extended Data Transfer Width (Embedded and SD Mode Only) This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the This bit is not effective when multiple.." "0,1" newline bitfld.byte 0x0 3.--4. "DMA_SELECT,DMA Select This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the (1) Up to Version 3.00: (2) Version 4.00 or later: Support of 64-bit DMA and 128-bit Descriptor is indicated by the" "0: (2,?,?,?" bitfld.byte 0x0 2. "HIGH_SPEED_ENA,High Speed Enable (SD Mode Only) This bit is optional. Before setting this bit the HD shall check the If the 1h: High Speed Mode 0h: Normal Speed Mode" "0,1" bitfld.byte 0x0 1. "DATA_WIDTH,Data Transfer Width (SD Mode Only) This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode. 1h: 4 bit mode 0h: 1 bit mode" "0,1" newline bitfld.byte 0x0 0. "LED_CONTROL,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands this bit can be set during all transactions. It is not necessary to change.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "MMCSD0_RESPONSE_6,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.byte 0x29++0x2 line.byte 0x0 "MMCSD0_POWER_CONTROL,This register is used to program the SD Bus power and voltage level." bitfld.byte 0x0 5.--7. "UHS2_VOLTAGE,SD Bus Voltage Select for VDD2 (UHS-II Only) This field determines supply voltage range to VDD2. This field can be set to 5h if the 111b: Not used 110b: Not used 101b: 1.8 V 100b: Reserved for 1.2 V 011b – 001b: Reserved 000b: VDD2 Not.." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "UHS2_POWER,SD Bus Power for VDD2 (UHS-II Only) Setting this bit enables providing VDD2. 1h: Power on 0h: Power off" "0,1" bitfld.byte 0x0 1.--3. "SD_BUS_VOLTAGE,SD Bus Voltage Select for VDD1 By setting these bits the HD selects the voltage level for the SD card. Before setting this register the HD shall check the voltage support bits in the 111b: 3.3 V (Flattop.) 110b: 3.0 V (Typ.) 101b: 1.8 V.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "SD_BUS_POWER,SD Bus Power for VDD1 Before setting this bit the SD host driver shall set SD Bus Voltage Select ( If this bit is cleared the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state) and drive SDCLK to low level. If.." "0,1" line.byte 0x1 "MMCSD0_BLOCK_GAP_CONTROL,This register is used to program the block gap request. read wait control and interrupt at block gap." bitfld.byte 0x1 7. "BOOT_ACK_ENA,Boot Acknowledge Check To check for the boot acknowledge in boot operation. 1h: Wait for boot ack from eMMC card 0h: Will not wait for boot ack from eMMC card" "0,1" bitfld.byte 0x1 6. "ALT_BOOT_MODE,Alternative Boot Mode To start boot code access in alternative mode. 1h: To start alternate boot mode access 0h: To stop alternate boot mode access" "0,1" bitfld.byte 0x1 5. "BOOT_ENABLE,Boot Enable To start boot code access. 1h: To start boot code access 0h: To stop boot code access" "0,1" newline rbitfld.byte 0x1 4. "RESERVED,Reserved" "0,1" bitfld.byte 0x1 3. "INTRPT_AT_BLK_GAP,Interrupt At Block Gap (SD Mode Only) This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1h enables interrupt detection at the block gap for a multiple block transfer. If.." "0,1" bitfld.byte 0x1 2. "RDWAIT_CTRL,Read Wait Control (SD Mode Only) The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD.." "0,1" newline bitfld.byte 0x1 1. "CONTINUE,Continue Request This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap set Stop At block Gap Request to 0h ( The Host Controller automatically clears this bit when the.." "0,1" bitfld.byte 0x1 0. "STOP_AT_BLK_GAP,Stop At Block Gap Request This bit is used to stop executing a transaction at the next block gap for non-DMA SDMA and ADMA transfers. Until the transfer complete is set to 1h indicating a transfer completion the HD shall leave this bit.." "0,1" line.byte 0x2 "MMCSD0_WAKEUP_CONTROL,This register is used to program the wakeup functionality. The register is mandatory for the HC. but wakeup functionality depends on the HC system hardware and software. The HD shall maintain voltage on the SD Bus. by setting the.." hexmask.byte 0x2 3.--7. 1. "RESERVED,Reserved" bitfld.byte 0x2 2. "CARD_REMOVAL,Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card removal assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit. 1h: Enable 0h: Disable" "0,1" bitfld.byte 0x2 1. "CARD_INSERTION,Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit. 1h: Enable 0h: Disable" "0,1" newline bitfld.byte 0x2 0. "CARD_INTERRUPT,Wakeup Event Enable On Card Interrupt This bit enables wakeup event via Card Interrupt assertion in the This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h. 1h: Enable 0h: Disable" "0,1" group.word 0x2C++0x1 line.word 0x0 "MMCSD0_CLOCK_CONTROL,This register is used to program the Clock frequency select. Clock generator select. Clock enable. Internal clock state fields. At the initialization of the HC. the HD shall set the SDCLK Frequency Select ([15-8] SDCLK_FRQSEL).." hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,SDCLK/RCLK Frequency Select This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the Capabilities.." bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Upper Bits of SDCLK/RCLK Frequency Select This bit field is assigned to the" "0,1,2,3" bitfld.word 0x0 5. "CLKGEN_SEL,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select ( If the Programmable Clock Mode is supported (non-zero value is set to the This bit depends on the setting of the If If 1h: Programmable.." "0,1" newline rbitfld.word 0x0 4. "RESERVED,Reserved" "0,1" bitfld.word 0x0 3. "PLL_ENA,PLL Enable This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable ( (1) When (2) When 1h: PLL is enabled 0h: PLL is in low power.." "0,1" bitfld.word 0x0 2. "SD_CLK_ENA,SD Clock Enable The HC shall stop SDCLK when writing this bit to 0h. The 1h: Enable providing SDCLK or RCLK 0h: Disable providing SDCLK or RCLK" "0,1" newline rbitfld.word 0x0 1. "INT_CLK_STABLE,Internal Clock Stable This bit is set to 1h when SD clock is stable after writing 1h to (1) Internal Clock Stable (when This bit is set to 1h when internal clock is stable after writing 1h to (2) PLL Clock Stable (when Host Controller.." "0,1" bitfld.word 0x0 0. "INT_CLK_ENA,Internal Clock Enable This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still registers shall be able to be read and written. Clock starts.." "0,1" group.byte 0x2E++0x1 line.byte 0x0 "MMCSD0_TIMEOUT_CONTROL,The register sets the data timeout counter value. At the initialization of the HC. the HD shall set the Data Timeout Counter Value according to the register." hexmask.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,Data Timeout Counter Value This value determines the interval by which DAT line time-outs are detected. Refer to the 1111: Reserved 1110: TMCLK × 2 -------------------- -------------------- 0001: TMCLK × 2 0000: TMCLK × 2" line.byte 0x1 "MMCSD0_SOFTWARE_RESET,This register is used to program the software reset for data. command and for all. A reset pulse is generated when writing 1h to each bit of this register. After completing the reset. the HC shall clear each bit. Because it takes.." hexmask.byte 0x1 3.--7. 1. "RESERVED,Reserved" bitfld.byte 0x1 2. "SWRST_FOR_DAT,Software Reset for DAT Line (SD Mode Only) Only part of data circuit is reset. The following registers and bits are cleared by this bit: 1h: Reset 0h: Work" "0,1" bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset for CMD Line (SD Mode Only) Only part of command circuit is reset to be able to issue a command. From Version 4.10 this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing.." "0,1" newline bitfld.byte 0x1 0. "SWRST_FOR_ALL,Software Reset for All This reset affects the entire HC except for the card detection circuit. Register bits of type ROC RW RW1C RWAC are cleared to 0h. During its initialization the HD shall set this bit to 1h to reset the HC. The HC.." "0,1" group.word 0x30++0xB line.word 0x0 "MMCSD0_NORMAL_INTR_STS,This register gives the status of all the interrupts. The Normal Interrupt Signal Enable (see register) affects read of this register. but Normal Interrupt Signal does not affect these reads. An Interrupt is generated when the.." rbitfld.word 0x0 15. "ERROR_INTR,Error Interrupt If any of the bits in the In UHS-II mode is enabled if any of the bits in the 0h: No Error 1h: Error" "0,1" bitfld.word 0x0 14. "BOOT_COMPLETE,Boot Terminate Interrupt This status is set if the boot operation gets terminated. 0h: Boot operation is not terminated 1h: Boot operation is terminated" "0,1" bitfld.word 0x0 13. "RCV_BOOT_ACK,Boot Acknowledge Receive This status is set if the boot acknowledge is received from device. 0h: Boot acknowledge is not received 1h: Boot acknowledge is received" "0,1" newline rbitfld.word 0x0 12. "RETUNING_EVENT,Re-Tuning Event (UHS-I Only) This status is set if the Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer (not large block count) can be completed without re-tuning. In UHS-II mode this.." "0,1" rbitfld.word 0x0 11. "INTC,int_c (Embedded) This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1" rbitfld.word 0x0 10. "INTB,int_b (Embedded) This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1" newline rbitfld.word 0x0 9. "INTA,int_a (Embedded) This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_A interrupt factor." "0,1" rbitfld.word 0x0 8. "CARD_INTR,Card Interrupt When this status has been set and the Host Driver needs to start this interrupt service the Writing this bit to 1h does not clear this bit. It is cleared by resetting the SD card interrupt factor. (1) DAT[1] Interrupt Input in.." "0,1" bitfld.word 0x0 7. "CARD_REM,Card Removal This status is set if the 0h: Card State Stable or Debouncing 1h: Card Removed" "0,1" newline bitfld.word 0x0 6. "CARD_INS,Card Insertion This status is set if the 0h: Card State Stable or Debouncing 1h: Card Inserted" "0,1" bitfld.word 0x0 5. "BUF_RD_READY,Buffer Read Ready This status is set if the The In UHS-II mode this bit is set at FC (Flow Control) unit basis. 0h: Not Ready to read Buffer 1h: Ready to read Buffer" "0,1" bitfld.word 0x0 4. "BUF_WR_READY,Buffer Write Ready This status is set if the In UHS-II mode this bit is set at FC (Flow Control) unit basis. 0h: Not Ready to Write Buffer 1h: Ready to Write Buffer" "0,1" newline bitfld.word 0x0 3. "DMA_INTERRUPT,DMA Interrupt This status is set if the HC detects the Host DMA Buffer Boundary in the 0h: No DMA Interrupt 1h: DMA Interrupt is Generated" "0,1" bitfld.word 0x0 2. "BLK_GAP_EVENT,Block Gap Event If the Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (see Write Transaction: This bit is set at the falling edge of Write Transfer Active Status (see 0h: No Block Gap Event 1h:.." "0,1" bitfld.word 0x0 1. "XFER_COMPLETE,Transfer Complete This bit is set when a read/write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status ( There are two cases in which the Interrupt is generated. The first is when.." "0,1" newline bitfld.word 0x0 0. "CMD_COMPLETE,Command Complete This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23). Version 4.00 defines response check function for R1 and R5. If the If the If the 0h: No Command Complete 1h: Command Complete" "0,1" line.word 0x2 "MMCSD0_ERROR_INTR_STS,This register gives the status of the error interrupts. Status defined in this register can be enabled by the register. but not by the register. The Interrupt is generated when the register is enabled and at least one of the.." rbitfld.word 0x2 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 12. "HOST,Target Response Error Occurs when detecting ERROR in m_hresp (DMA transaction) 0h: No error 1h: Error" "0,1" bitfld.word 0x2 11. "RESP,Response Error (SD Mode Only) Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If the 0h: No error 1h: Error" "0,1" newline rbitfld.word 0x2 10. "RESERVED,Reserved" "0,1" bitfld.word 0x2 9. "ADMA,ADMA Error This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the 0h: No error 1h: Error" "0,1" bitfld.word 0x2 8. "AUTO_CMD,Auto CMD Error (SD Mode Only) Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that any of the bits D00 to D05 in the 0h: No error 1h: Error" "0,1" newline bitfld.word 0x2 7. "CURR_LIMIT,Current Limit Error By setting the 0h: No error 1h: Power Fail" "0,1" bitfld.word 0x2 6. "DATA_ENDBIT,Data End Bit Error (SD Mode Only) Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status. 0h: No error 1h: Error" "0,1" bitfld.word 0x2 5. "DATA_CRC,Data CRC Error (SD Mode Only) Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 2h. 0h: No error 1h: Error" "0,1" newline bitfld.word 0x2 4. "DATA_TIMEOUT,Data Timeout Error (SD Mode Only) Occurs when detecting one of following timeout conditions: 0h: No error 1h: Timeout" "0,1" bitfld.word 0x2 3. "CMD_INDEX,Command Index Error (SD Mode Only) Occurs if a Command Index error occurs in the Command Response ( 0h: No error 1h: Error" "0,1" bitfld.word 0x2 2. "CMD_ENDBIT,Command End Bit Error (SD Mode Only) Occurs when detecting that the end bit of a command response is 0h. 0h: No error 1h: End Bit Error Generated" "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Command CRC Error (SD Mode Only) Command CRC Error is generated in two cases. 1. If a response is returned and the 2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1.." "0,1" bitfld.word 0x2 0. "CMD_TIMEOUT,Command Timeout Error (SD Mode Only) Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict in which case the 0h: No error 1h: Timeout" "0,1" line.word 0x4 "MMCSD0_NORMAL_INTR_STS_ENA,This register is used to enable the register fields." rbitfld.word 0x4 15. "BIT15_FIXED0,Fixed to 0 The HC shall control error Interrupts using the" "0,1" bitfld.word 0x4 14. "BOOT_COMPLETE,Boot Terminate Interrupt Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 13. "RCV_BOOT_ACK,Boot Acknowledge Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x4 12. "RETUNING_EVENT,Re-Tuning Event Status Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 11. "INTC,INT_C Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to.." "0,1" bitfld.word 0x4 10. "INTB,INT_B Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to.." "0,1" newline bitfld.word 0x4 9. "INTA,INT_A Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to.." "0,1" bitfld.word 0x4 8. "CARD_INTERRUPT,Card Interrupt Status Enable If this bit is set to 0h the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1h. The HD may clear the By.." "0,1" bitfld.word 0x4 7. "CARD_REMOVAL,Card Removal Status Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x4 6. "CARD_INSERTION,Card Insertion Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 5. "BUF_RD_READY,Buffer Read Ready Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 4. "BUF_WR_READY,Buffer Write Ready Status Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x4 3. "DMA_INTERRUPT,DMA Interrupt Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 2. "BLK_GAP_EVENT,Block Gap Event Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 1. "XFER_COMPLETE,Transfer Complete Status Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x4 0. "CMD_COMPLETE,Command Complete Status Enable 0h: Masked 1h: Enabled" "0,1" line.word 0x6 "MMCSD0_ERROR_INTR_STS_ENA,This register is used to enable the register fields." hexmask.word.byte 0x6 12.--15. 1. "VENDOR_SPECIFIC,Vendor Specific Error Status Enable N/A" bitfld.word 0x6 11. "RESP,Response Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 10. "TUNING,Tuning Error Status Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x6 9. "ADMA,ADMA Error Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 8. "AUTO_CMD,Auto CMD Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 7. "CURR_LIMIT,Current Limit Error Status Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x6 6. "DATA_ENDBIT,Data End Bit Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 5. "DATA_CRC,Data CRC Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 4. "DATA_TIMEOUT,Data Timeout Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x6 3. "CMD_INDEX,Command Index Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 2. "CMD_ENDBIT,Command End Bit Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 1. "CMD_CRC,Command CRC Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x6 0. "CMD_TIMEOUT,Command Timeout Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" line.word 0x8 "MMCSD0_NORMAL_INTR_SIG_ENA,Normal Interrupt Signal Enable Register This register is used to select which interrupt status is indicated to the Host System as the Interrupt. These status bits all share the sample 1 bit interrupt line. Setting any of these.." rbitfld.word 0x8 15. "BIT15_FIXED0,Fixed to 0 The HD shall control error Interrupts using the" "0,1" bitfld.word 0x8 14. "BOOT_COMPLETE,Boot Terminate Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 13. "RCV_BOOT_ACK,Boot Acknowledge Receive Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 12. "RETUNING_EVENT,Re-Tuning Event Signal Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 11. "INTC,INT_C Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 10. "INTB,INT_B Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 9. "INTA,INT_A Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 8. "CARD_INTERRUPT,Card Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 7. "CARD_REMOVAL,Card Removal Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 6. "CARD_INSERTION,Card Insertion Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 5. "BUF_RD_READY,Buffer Read Ready Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 4. "BUF_WR_READY,Buffer Write Ready Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 3. "DMA_INTERRUPT,DMA Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 2. "BLK_GAP_EVENT,Block Gap Event Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 1. "XFER_COMPLETE,Transfer Complete Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 0. "CMD_COMPLETE,Command Complete Signal Enable 0h: Masked 1h: Enabled" "0,1" line.word 0xA "MMCSD0_ERROR_INTR_SIG_ENA,Error Interrupt Signal Enable Register This register is used to select which interrupt status is notified to the Host System as the Interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits.." hexmask.word.byte 0xA 12.--15. 1. "VENDOR_SPECIFIC,Vendor Specific Error Signal Enable N/A" bitfld.word 0xA 11. "RESP,Response Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 10. "TUNING,Tuning Error Signal Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0xA 9. "ADMA,ADMA Error Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 8. "AUTO_CMD,Auto CMD Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 7. "CURR_LIMIT,Current Limit Error Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0xA 6. "DATA_ENDBIT,Data End Bit Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 5. "DATA_CRC,Data CRC Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 4. "DATA_TIMEOUT,Data Timeout Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0xA 3. "CMD_INDEX,Command Index Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 2. "CMD_ENDBIT,Command End Bit Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 1. "CMD_CRC,Command CRC Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0xA 0. "CMD_TIMEOUT,Command Timeout Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "MMCSD0_AUTOCMD_ERR_STS,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12/CMD23 errors occur by this register. Auto CMD23 errors are indicated.." hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 7. "CMD_NOT_ISSUED,Command Not Issued By Auto CMD12 Error Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register. This bit is set to 0h when Auto CMD Error is generated by Auto CMD23. 0h: No Error 1h:.." "0,1" bitfld.word 0x0 5.--6. "RESERVED,Reserved" "0,1,2,3" newline bitfld.word 0x0 4. "INDEX,Auto CMD Index Error Occurs if the Command Index error occurs in response to a command. 0h: No Error 1h: Error" "0,1" bitfld.word 0x0 3. "ENDBIT,Auto CMD End Bit Error Occurs when detecting that the end bit of command response is 0h. 0h: No Error 1h: End Bit Error Generated" "0,1" bitfld.word 0x0 2. "CRC,Auto CMD CRC Error Occurs when detecting a CRC error in the command response. 0h: No Error 1h: CRC Error Generated" "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Auto CMD Timeout Error Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1h the other error status bits (D04 - D02) are meaningless. 0h: No Error 1h: Timeout" "0,1" bitfld.word 0x0 0. "ACMD12_NOT_EXEC,Auto CMD12 not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1h means the HC cannot issue Auto CMD12 to stop.." "0,1" group.word 0x3E++0x1 line.word 0x0 "MMCSD0_HOST_CONTROL2,This register is used to program UHS Mode Select. Driver Strength Select. Execute Tuning. Sampling Clock Select. Asynchronous Interrupt Enable and Preset Value Enable." bitfld.word 0x0 15. "PRESET_VALUE_ENA,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host.." "0,1" bitfld.word 0x0 14. "ASYNCH_INTR_ENA,Asynchronous Interrupt Enable This bit can be set to 1h if a card support asynchronous interrupt and the 0h: Disabled 1h: Enabled" "0,1" bitfld.word 0x0 13. "BIT64_ADDRESSING,64-bit Addressing This field is effective when the Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host system. Host Driver sets.." "0,1" newline bitfld.word 0x0 12. "HOST_VER40_ENA,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4.00 mode. In Version 4.00 support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver.." "0,1" bitfld.word 0x0 11. "CMD23_ENA,CMD23 Enable In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 (SCR[33] = 1h) this bit is set to 1h. This bit is used to select Auto CMD23 or Auto.." "0,1" bitfld.word 0x0 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit. 0h: 16-bit Data Length Mode 1h: 26-bit Data Length Mode" "0,1" newline bitfld.word 0x0 9. "DRIVER_STRENGTH2,Driver Strength Select This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value." "0,1" bitfld.word 0x0 8. "UHS2_INTF_ENABLE,UHS-II Interface Enable This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization this bit shall be set to 1h. Before trying to start SD mode initialization this bit shall be set to 0h. This bit is used.." "0,1" bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,Sampling Clock Select (UHS-I Only) This bit is set by tuning procedure when the 0h: Fixed clock is used to sample data 1h: Tuned clock is used to sample data" "0,1" newline bitfld.word 0x0 6. "EXECUTE_TUNING,Execute Tuning (UHS-I Only) This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to the 0h: Not Tuned or Tuning Completed 1h: Execute Tuning" "0,1" bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Driver Strength Select (UHS-I Only) Host Controller output driver in 1.8 V signaling is selected by this bit. In 3.3 V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the If.." "0,1,2,3" bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,1.8 V Signaling Enable (UHS-I Only) This bit controls voltage regulator for I/O cell. 3.3 V is supplied to the card regardless of signaling voltage. Setting this bit from 0h to 1h starts changing signal voltage from 3.3 V to 1.8 V. 1.8 V.." "0,1" newline bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,UHS Mode Select (UHS-I Only) This field is used to select one of UHS-I modes or UHS-II mode. In case of UHS-I mode this field is effective when the If the 0h: SDR12 1h: SDR25 2h: SDR50 3h: SDR104 4h: DDR50 5h: HS400 6h: Reserved 7h:.." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0xF line.quad 0x0 "MMCSD0_CAPABILITIES,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initialization." bitfld.quad 0x0 63. "HS400_SUPPORT,HS400 Support 0h: HS400 is Not Supported 1h: HS400 is Supported" "0,1" bitfld.quad 0x0 61.--62. "RESERVED,Reserved" "0,1,2,3" bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,1.8 V VDD2 Support This bit indicates that support of VDD2 on Host system. 0h: 1.8 V VDD2 is not supported 1h: 1.8 V VDD2 is supported" "0,1" newline bitfld.quad 0x0 59. "ADMA3_SUPPORT,ADMA3 Support This bit indicates that support of ADMA3 on Host Controller. 0h: ADMA3 is not supported 1h: ADMA3 is supported" "0,1" bitfld.quad 0x0 58. "RESERVED,Reserved" "0,1" bitfld.quad 0x0 57. "SPI_BLK_MODE,SPI Block Mode This bit indicates whether SPI Block Mode is supported or not. 0h: Not Supported 1h: Supported" "0,1" newline bitfld.quad 0x0 56. "SPI_SUPPORT,SPI Mode This bit indicates whether SPI Mode is supported or not. 0h: Not Supported 1h: Supported" "0,1" hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to the FFh: Clock Multiplier M = 256 ---- 02h: Clock Multiplier M = 3 01h: Clock Multiplier M = 2 00h: Clock Multiplier is Not Supported" bitfld.quad 0x0 46.--47. "RETUNING_MODES,Re-tuning Modes (UHS-I Only) This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. 0h: Mode 1 1h: Mode 2 2h: Mode 3 3h: Reserved There are two.." "0,1,2,3" newline bitfld.quad 0x0 45. "TUNING_FOR_SDR50,Use Tuning for SDR50 (UHS-I Only) If this bit is set to 1h this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104). 0h: SDR50 does not require tuning 1h: SDR50 requires tuning" "0,1" bitfld.quad 0x0 44. "RESERVED,Reserved" "0,1" hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,Timer Count for Re-Tuning (UHS-I Only) This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ---- n = 2.." newline bitfld.quad 0x0 39. "RESERVED,Reserved" "0,1" bitfld.quad 0x0 38. "DRIVERD_SUPPORT,Driver Type D Support (UHS-I Only) This bit indicates support of Driver Type D for 1.8 Signaling. 0h: Driver Type D is Not Supported 1h: Driver Type D is Supported" "0,1" bitfld.quad 0x0 37. "DRIVERC_SUPPORT,Driver Type C Support (UHS-I Only) This bit indicates support of Driver Type C for 1.8 Signaling. 0h: Driver Type C is Not Supported 1h: Driver Type C is Supported" "0,1" newline bitfld.quad 0x0 36. "DRIVERA_SUPPORT,Driver Type A Support (UHS-I Only) This bit indicates support of Driver Type A for 1.8 Signaling. 0h: Driver Type A is Not Supported 1h: Driver Type A is Supported" "0,1" bitfld.quad 0x0 35. "UHS2_SUPPORT,UHS-II Support (UHS-II Only) This bit indicates whether Host Controller supports UHS-II. If this bit is set to 1h the 0h: UHS-II is Not Supported 1h: UHS-II is Supported" "0,1" bitfld.quad 0x0 34. "DDR50_SUPPORT,DDR50 Support (UHS-I Only) This bit indicates whether DDR50 is supported or not. 0h: DDR50 is Not Supported 1h: DDR50 is Supported" "0,1" newline bitfld.quad 0x0 33. "SDR104_SUPPORT,SDR104 Support (UHS-I Only) This bit indicates whether SDR104 is supported or not. SDR104 requires tuning. 0h: SDR104 is Not Supported 1h: SDR104 is Supported" "0,1" bitfld.quad 0x0 32. "SDR50_SUPPORT,SDR50 Support (UHS-I Only) If SDR104 is supported this bit shall be set to 1h. Bit 40 indicates whether SDR50 requires tuning or not. 0h: SDR50 is Not Supported 1h: SDR50 is Supported" "0,1" bitfld.quad 0x0 30.--31. "SLOT_TYPE,Slot Type This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot). Embedded slot for one device (1h) means that only one non-removable device is connected to a SD bus slot. Shared Bus.." "0,1,2,3" newline bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Asynchronous Interrupt Support (SD Mode Only) Refer to SDIO Specification Version 3.00 about asynchronous interrupt. 0h: Asynchronous Interrupt Not Supported 1h: Asynchronous Interrupt Supported" "0,1" bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,64-bit System Address Support for V3 Meaning of this bit is different depends on Versions. Host Controller Version 3.00 and Version 4.10 use this bit as 64-bit System Address support for V3 mode. Host Controller Version 4.00 uses.." "0,1" bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,64-bit System Address Support for V4 This bit is added from Version 4.10. Setting 1h to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode. When this bit is set to 1h full or a part of.." "0,1" newline bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,Voltage Support 1.8 V This bit indicates whether the HC supports 1.8 V. 0h: 1.8 V Not Supported 1h: 1.8 V Supported" "0,1" bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,Voltage Support 3.0 V This bit indicates whether the HC supports 3.0 V. 0h: 3.0 V Not Supported 1h: 3.0 V Supported" "0,1" bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,Voltage Support 3.3 V This bit indicates whether the HC supports 3.3 V. 0h: 3.3 V Not Supported 1h: 3.3 V Supported" "0,1" newline bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,Suspend/Resume Support This bit indicates whether the HC supports Suspend/Resume functionality. If this bit is 0h the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend/Resume commands. 0h: Not.." "0,1" bitfld.quad 0x0 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. Version 4.10 Host Controller shall support SDMA if ADMA2 is supported. 0h: SDMA Not Supported 1h: SDMA Supported" "0,1" bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC). 0h: High Speed Not Supported 1h: High.." "0,1" newline bitfld.quad 0x0 20. "RESERVED,Reserved" "0,1" bitfld.quad 0x0 19. "ADMA2_SUPPORT,ADMA2 Support 0h: ADMA2 Not support 1h: ADMA2 support" "0,1" bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,8-bit Support for Embedded Device (Embedded) This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when the 0h: 8-bit Bus Width Not Supported 1h: 8-bit Bus Width Supported" "0,1" newline bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,Max Block Length This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below. 0h: 512 byte.." "0,1,2,3" hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,Base Clock Frequency for SD Clock (1) 6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1 MHz. The supported clock range is 10 MHz to.." bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data Timeout Error ( 0h: KHz 1h: MHz" "0,1" newline bitfld.quad 0x0 6. "RESERVED,Reserved" "0,1" hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error ( 0h: Get Information via another method Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz" line.quad 0x8 "MMCSD0_MAX_CURRENT_CAP,This register indicates maximum current capability for each voltage." hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8 V VDD2" hexmask.quad.byte 0x8 24.--31. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8 V VDD1" hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0 V VDD1" hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3 V VDD1" group.word 0x50++0x1 line.word 0x0 "MMCSD0_FORCE_EVNT_ACMD_ERR_STS,This register is not physically implemented. rather it is an address where the register can be written. Writing 1h: set each bit of the register Writing 0h: no effect By setting a bit in this register. the correspondent bit.." hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error 0h: Not Affected 1h: Command Not Issued By Auto CMD12 Error Status is set" "0,1" rbitfld.word 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error 0h: Not Affected 1h: Auto CMD Response Error Status is set" "0,1" bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error 0h: Not Affected 1h: Auto CMD Index Error Status is set" "0,1" bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error 0h: Not Affected 1h: Auto CMD End bit Error Status is set" "0,1" newline bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error 0h: Not Affected 1h: Auto CMD CRC Error Status is set" "0,1" bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error 0h: Not Affected 1h: Auto CMD Timeout Error Status is set" "0,1" bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed 0h: Not Affected 1h: Auto CMD12 Not Executed Status is set" "0,1" wgroup.word 0x52++0x1 line.word 0x0 "MMCSD0_FORCE_EVNT_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written. The register is not a physically implemented register. Rather. it is an address at which the register can be written." hexmask.word.byte 0x0 12.--15. 1. "VEND_SPEC,N/A" bitfld.word 0x0 11. "RESP,Force Event for Response Error 0h: Not Affected 1h: Response Error Status is set" "0,1" bitfld.word 0x0 10. "TUNING,Force Event for Tuning Error 0h: Not Affected 1h: Tuning Error Status is set" "0,1" newline bitfld.word 0x0 9. "ADMA,Force Event for ADMA Error 0h: Not Affected 1h: ADMA Error Status is set" "0,1" bitfld.word 0x0 8. "AUTO_CMD,Force Event for Auto CMD Error 0h: Not Affected 1h: Auto CMD Error Status is set" "0,1" bitfld.word 0x0 7. "CURR_LIM,Force Event for Current Limit Error 0h: Not Affected 1h: Current Limit Error Status is set" "0,1" newline bitfld.word 0x0 6. "DAT_ENDBIT,Force Event for Data End Bit Error 0h: Not Affected 1h: Data End Bit Error Status is set" "0,1" bitfld.word 0x0 5. "DAT_CRC,Force Event for Data CRC Error 0h: Not Affected 1h: CRC Error Status is set" "0,1" bitfld.word 0x0 4. "DAT_TIMEOUT,Force Event for Data Timeout Error 0h: Not Affected 1h: Timeout Error Status is set" "0,1" newline bitfld.word 0x0 3. "CMD_INDEX,Force Event for Command Index Error 0h: Not Affected 1h: Command Index Error Status is set" "0,1" bitfld.word 0x0 2. "CMD_ENDBIT,Force Event for Command End Bit Error 0h: Not Affected 1h: Command End Bit Error Status is set" "0,1" bitfld.word 0x0 1. "CMD_CRC,Force Event for Command CRC Error 0h: Not Affected 1h: Command CRC Error Status is set" "0,1" newline bitfld.word 0x0 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error 0h: Not Affected 1h: Command Timeout Error Status is set" "0,1" rgroup.byte 0x54++0x0 line.byte 0x0 "MMCSD0_ADMA_ERR_STATUS,When the ADMA Error interrupt occur. this register holds the ADMA State ([1-0] ADMA_ERR_STATE) and the register holds address around the error descriptor." hexmask.byte 0x0 3.--7. 1. "RESERVED,Reserved" bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,ADMA Length Mismatch Error This error occurs in the following 2 cases. While the 0h: No Error 1h: Error" "0,1" bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates '2h' because ADMA never stops in this state. D01 - D00: ADMA Error State when error occurred Contents of.." "0,1,2,3" group.quad 0x58++0x7 line.quad 0x0 "MMCSD0_ADMA_SYS_ADDRESS,This register contains the physical address used for ADMA data transfer." hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,ADMA System Address The 32-bit addressing Host Driver uses lower 32-bit of this register (upper 32-bit should be set to 0h) and shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. DMA2/3 ignores.." rgroup.word 0x60++0xF line.word 0x0 "MMCSD0_PRESET_VALUE0,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value. When the [15] PRESET_VALUE_ENA bit is set to 1h. SDCLK/RCLK Frequency Select and Clock Generator Select in.." bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x0 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x0 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x2 "MMCSD0_PRESET_VALUE1,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x2 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x4 "MMCSD0_PRESET_VALUE2,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x4 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x4 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x6 "MMCSD0_PRESET_VALUE3,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x6 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x6 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x8 "MMCSD0_PRESET_VALUE4,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x8 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x8 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0xA "MMCSD0_PRESET_VALUE5,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0xA 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0xA 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0xC "MMCSD0_PRESET_VALUE6,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0xC 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0xC 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0xE "MMCSD0_PRESET_VALUE7,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0xE 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0xE 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" rgroup.word 0x72++0x3 line.word 0x0 "MMCSD0_PRESET_VALUE8,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x0 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x0 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x2 "MMCSD0_PRESET_VALUE10,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x2 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" group.quad 0x78++0x7 line.quad 0x0 "MMCSD0_ADMA3_DESC_ADDRESS,The start address of Integrated DMA Descriptor is set to this register." hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,ADMA3 Integrated Descriptor Address The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and.." group.word 0x80++0x1 line.word 0x0 "MMCSD0_UHS2_BLOCK_SIZE,This register is used to configure the number of bytes in a data block." rbitfld.word 0x0 15. "RESERVED,Reserved" "0,1" bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,UHS-II SDMA Buffer Boundary (SDMA only) When system memory is managed by paging SDMA data transfer is performed in unit of paging. A page size of system memory management is set to this field. Host Controller generates the DMA.." "0,1,2,3,4,5,6,7" hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,UHS-II Block Size This bit field specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Variable block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes." group.long 0x84++0x3 line.long 0x0 "MMCSD0_UHS2_BLOCK_COUNT,This register is used to configure the number of data blocks." hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,UHS-II Block Count This register is effective when the This register should be accessed only when no transaction is executing (after transactions are stopped). During data transfer read operations on this register may return an invalid.." group.byte 0x88++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_0,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x8C++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_1,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x90++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_2,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x94++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_3,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x98++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_4,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x9C++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_5,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.word 0x9C++0x3 line.word 0x0 "MMCSD0_UHS2_XFER_MODE,This register is used to control the operations of data transfers. On issuing a Command Packet. a Command Packet image is set to UHS-II Command Packet register (see - ) but Host Controller does not analyze the setting of UHS-II.." bitfld.word 0x0 15. "DUPLEX_SELECT,Half/Full Select Use of 2 lane half duplex mode is determined by Host Driver. 0h: Full Duplex Mode 1h: 2 Lane Half Duplex Mode" "0,1" bitfld.word 0x0 14. "EBSY_WAIT,EBSY Wait This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer. If this bit is set to 1h Host Controller waits.." "0,1" hexmask.word.byte 0x0 9.--13. 1. "RESERVED,Reserved" newline bitfld.word 0x0 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0h.." "0,1" bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error this bit is set.." "0,1" bitfld.word 0x0 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1: Response Flags Checked in R5:.." "0,1" newline bitfld.word 0x0 5. "BYTE_MODE,Block/Byte Mode This bit specifies whether data transfer is in byte mode or block mode when the 0h: Block Mode 1h: Byte Mode" "0,1" bitfld.word 0x0 4. "DATA_XFER_DIR,Data Transfer Direction This bit specifies direction of data transfer when the 0h: Read (Card to Host) 1h: Write (Host to Card)" "0,1" rbitfld.word 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.word 0x0 1. "BLK_CNT_ENA,Block Count Enable This bit specifies whether data transfer uses the 0h: Block Count Disabled 1h: Block Count Enabled" "0,1" bitfld.word 0x0 0. "DMA_ENA,DMA Enable This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by the 0h: DMA is disabled 1h: DMA is enabled" "0,1" line.word 0x2 "MMCSD0_UHS2_COMMAND,This register is used to program the Command for host controller." rbitfld.word 0x2 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,UHS-II Command Packet Length A command packet length which is set in the UHS-II Command Packet register ( 00011b – 00000b: 3-0 Bytes (Not used) 00100b: 4 Bytes .... .... 10100b: 20 Bytes 11111b – 10101b" bitfld.word 0x2 6.--7. "CMD_TYPE,Command Type This field is used to distinguish a specific command like abort command. If this field is set to 0h the UHS-II RES Packet is stored in UHS-II Response register ( 0h: Normal Command 1h: TRANS_ABORT CCMD 3h: CMD12 or SDIO Abort.." "0,1,2,3" newline bitfld.word 0x2 5. "DATA_PRESENT,Data Present This bit specifies whether the command is accompanied by data packet. 0h: No Data Present 1h: Data Present" "0,1" rbitfld.word 0x2 3.--4. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x2 2. "SUB_COMMAND,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command this bit is set to 0h and when issuing a sub command this bit is set to 1h. Setting of this bit is checked by the.." "0,1" newline rbitfld.word 0x2 0.--1. "RESERVED,Reserved" "0,1,2,3" group.byte 0xA0++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_6,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xA0++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_0,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xA4++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_7,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xA4++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_1,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xA8++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_8,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xA8++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_2,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xAC++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_9,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xAC++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_3,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB0++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_10,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xB0++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_4,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB4++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_11,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0xB4++0x0 line.byte 0x0 "MMCSD0_UHS2_MESSAGE_SELECT,This register is used to access internal buffer." hexmask.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.byte 0x0 0.--1. "MSG_SEL,UHS-II MSG Select Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs can be read from the (assumed for debug usage). 0h: The latest MSG 1h: One MSG before 2h: Two MSGs before 3h: Three MSGs before" "0,1,2,3" rgroup.byte 0xB4++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_5,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB8++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_12,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.long 0xB8++0x3 line.long 0x0 "MMCSD0_UHS2_MESSAGE,This register is used to access internal buffer." hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the" hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the" hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the" rgroup.byte 0xB8++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_6,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xBC++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_13,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.word 0xBC++0x1 line.word 0x0 "MMCSD0_UHS2_DEVICE_INTR_STATUS,This register shows receipt of INT MSG from which device." hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,UHS-II Device Interrupt Status This register shows receipt of INT MSG from which device and is effective when the Writing a bit to 1h clears the status bit (interrupt is treated) and writing a bit to 0h keeps the status value (interrupt is.." rgroup.byte 0xBC++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_7,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xBE++0x0 line.byte 0x0 "MMCSD0_UHS2_DEVICE_SELECT,UHS-II Device Select Register." bitfld.byte 0x0 7. "INT_MSG_ENA,INT MSG Enable (Optional) This bit enables receipt of INT MSG. If this bit is set to 1h receipt of INT MSG is informed by the Support of INT MSG Interrupt is optional. If trying to set this bit to 1h but still this bit is read 0 INT MSG.." "0,1" rbitfld.byte 0x0 4.--6. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "DEV_SEL,UHS-II Device Select Host Controller holds an INT MSG packet per device. One of INT MSGs (up to 15) can be selected by this field and read from the The number of devices implemented in the Host Controller is indicated by the 0h: Unselected.." rgroup.byte 0xBF++0x0 line.byte 0x0 "MMCSD0_UHS2_DEVICE_INT_CODE,This register is effective when the [7] INT_MSG_ENA bit is set to 1h." hexmask.byte 0x0 0.--7. 1. "DEV_INTR,UHS II Device Interrupt This register is effective when the The number of the registers to hold INT MSGs is determined by the" group.byte 0xC0++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_14,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xC0++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_8,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.word 0xC0++0x3 line.word 0x0 "MMCSD0_UHS2_SOFTWARE_RESET,UHS-II Software Reset Register." hexmask.word 0x0 2.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host SD-TRAN Reset Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completion of SD-TRAN reset. If CMD0 is issued SD-TRAN.." "0,1" bitfld.word 0x0 0. "HOST_FULL_RESET,Host Full Reset On issuing FULL_RESET CCMD Host Driver set this bit to 1h to reset Host Controller. This bit is cleared automatically at completion of Host Controller reset. Initialization sequence from PHY Initialization is required to.." "0,1" line.word 0x2 "MMCSD0_UHS2_TIMER_CONTROL,UHS-II Timeout Control Register." hexmask.word.byte 0x2 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,Timeout Counter Value for Deadlock This value determines the deadlock period while host expecting to receive a packet (1 second). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When.." hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,Timeout Counter Value for CMD_RES This value determines the interval between command packet and response packet (5 ms). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this.." group.byte 0xC4++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_15,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.long 0xC4++0x3 line.long 0x0 "MMCSD0_UHS2_ERR_INTR_STS,This register gives the status of all UHS-II interrupts." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor Specific Error Vendor may use this field for vendor specific error status. 0h: Interrupt is not generated 1h: Vendor Specific Error" hexmask.long.word 0x0 18.--26. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout (1 second). Timeout value is determined by the setting of the 0h: Interrupt is not.." "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout (5 ms). Timeout value is determined by the setting of the 0h: Interrupt is not.." "0,1" bitfld.long 0x0 15. "ADMA2_ADMA3,ADMA2/3 Error Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the 0h: Interrupt is not generated 1h: ADMA2/3 Error" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "EBSY,EBSY Error On receiving EBSY packet if the packet indicates an error this bit is set to 1h. Setting of this bit also sets Error Interrupt and Transfer Completer together in the 0h: Interrupt is not generated 1h: EBSY Error (Backend Error)" "0,1" bitfld.long 0x0 7. "UNRECOVERABLE,Unrecoverable Error Setting of this bit means that Unrecoverable Error is set in a packet from a device. 0h: Interrupt is not generated 1h: Device Unrecoverable Error" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 5. "TID,TID Error Setting of this bit means that TID Error occurs. 0h: Interrupt is not generated 1h: TID Error" "0,1" bitfld.long 0x0 4. "FRAMING,Framing Error Setting of this bit means that Framing Error occurs during a packet receiving. 0h: Interrupt is not generated 1h: Framing Error" "0,1" bitfld.long 0x0 3. "CRC,CRC Error Setting of this bit means that CRC Error occurs during a packet receiving. 0h: Interrupt is not generated 1h: CRC Error" "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Retry Expired Setting of this bit means that Retry Counter Expired Error occurs during data transfer. If this bit is set either Framing Error or CRC Error in this register shall be set. 0h: Interrupt is not generated 1h: Retry Expired Error" "0,1" bitfld.long 0x0 1. "RESP_PKT,RES Packet Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If the 0h: Interrupt is not generated 1h: RES Packet Error" "0,1" bitfld.long 0x0 0. "HEADER,Header Error Setting of this bit means that Header Error occurs in a received packet. 0h: Interrupt is not generated 1h: Header Error" "0,1" rgroup.byte 0xC4++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_9,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xC8++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_16,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.long 0xC8++0x3 line.long 0x0 "MMCSD0_UHS2_ERR_INTR_STS_ENA,This register is used to enable the register fields." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC,Vendor Specific Error Setting this bit to 1h enables setting of Vendor Specific Error bit in the 0h: Status is Disabled 1h: Status is Enabled" hexmask.long.word 0x0 18.--26. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables setting of Timeout for Dead lock bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables setting of Timeout for CMD_RES bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables setting of ADMA2/3 Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "EBSY,EBSY Error Setting this bit to 1h enables setting of EBSY Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables setting of Unrecoverable Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 5. "TID,TID Error Setting this bit to 1h enables setting of TID Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 4. "FRAMING,Framing Error Setting this bit to 1h enables setting of Framing Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 3. "CRC,CRC Error Setting this bit to 1h enables setting of CRC Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Retry Expired Setting this bit to 1h enables setting of Retry Expired bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables setting of RES Packet Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 0. "HEADER,Header Error Setting this bit to 1h enables setting of Header Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" rgroup.byte 0xC8++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_10,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xCC++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_17,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.long 0xCC++0x3 line.long 0x0 "MMCSD0_UHS2_ERR_INTR_SIG_ENA,This register is used to generate UHS-II Interrupt signals." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC,Vendor Specific Error Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" hexmask.long.word 0x0 18.--26. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "EBSY,EBSY Error Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 5. "TID,TID Error Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 4. "FRAMING,Framing Error Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 3. "CRC,CRC Error Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED_SIG_ENA,Retry Expired Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 0. "HEADER,Header Error Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" rgroup.byte 0xCC++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_11,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xD0++0x0 line.byte 0x0 "MMCSD0_UHS2_COMMAND_PKT_18,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xD0++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_12,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xD4++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_13,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xD8++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_14,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xDC++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_15,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xE0++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_16,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.word 0xE0++0x3 line.word 0x0 "MMCSD0_UHS2_SETTINGS_PTR,This register is pointer for UHS-II settings." hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register" line.word 0x2 "MMCSD0_UHS2_CAPABILITIES_PTR,This register is pointer for UHS-II Capabilities Register." hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register" rgroup.byte 0xE4++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_17,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.word 0xE4++0x3 line.word 0x0 "MMCSD0_UHS2_TEST_PTR,This register is pointer for UHS-II Test Register." hexmask.word 0x0 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register" line.word 0x2 "MMCSD0_SHARED_BUS_CTRL_PTR,This register is pointer for UHS-II Shared Bus Control Register." hexmask.word 0x2 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register" rgroup.byte 0xE8++0x0 line.byte 0x0 "MMCSD0_UHS2_RESPONSE_18,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.word 0xE8++0x1 line.word 0x0 "MMCSD0_VENDOR_SPECFIC_PTR,This register is pointer for UHS-II Vendor Specific Register." hexmask.word 0x0 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area" group.long 0xF4++0x7 line.long 0x0 "MMCSD0_BOOT_TIMEOUT_CONTROL,This is used to program the boot timeout value counter." hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,Boot Data Timeout Counter Value This value determines the interval by which DAT line timeouts are detected during boot operation for eMMC4.4 card. The value is in number of SD clock." line.long 0x4 "MMCSD0_VENDOR_REGISTER,Vendor register added for Auto Gate SD CLK. CMD11 Power Down Timer. Enhanced Strobe and eMMC Hardware Reset." hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "AUTOGATE_SDCLK,Auto Gate SD CLK If this bit is set SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device. 0h: Disable 1h: Enable" "0,1" hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,CMD11 Power Down Timer Value" newline bitfld.long 0x4 1. "EMMC_HW_RESET,eMMC Hardware Reset Hardware reset signal is generared for eMMC card when this bit is set. 0h: De-sassert hardware reset pin 1h: Drives the hardware reset pin as ZERO (Active LOW to eMMC card)" "0,1" bitfld.long 0x4 0. "ENHANCED_STROBE,Enhanced Strobe This bit enables the enhanced strobe logic of the Host Controller." "0,1" rgroup.word 0xFC++0x3 line.word 0x0 "MMCSD0_SLOT_INT_STS,This register is used to read the interrupt signal for each slot." hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,Interrupt Signal for Slot#0 These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot." line.word 0x2 "MMCSD0_HOST_CONTROLLER_VER,This register is used to read the vendor version number and specification version number." hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,Vendor Version Number The Vendor Version Number is set to 10h (1.0)" hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,Specification Version Number This status indicates the Host Controller Specification Version. The upper and lower 4-bits indicate the version. 0h: SD Host Controller Specification Version 1.00 1h: SD Host Controller Specification Version.." group.long 0x100++0x7 line.long 0x0 "MMCSD0_UHS2_GEN_SETTINGS,Start Address of General settings is pointed by the Register." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,Number of Lanes and Functionalities The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0h: 2 Lanes.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "POWER_MODE,Power Mode This field determines either Fast mode or Low Power mode. Host and all devices connected to the host shall be set to the same mode. 0h: Fast Mode 1h: Low Power Mode" "0,1" line.long 0x4 "MMCSD0_UHS2_PHY_SETTINGS,Start Address of PHY settings is pointed by the Register." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,Host N_LSS_DIR The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h: 8 x 16 LSS 1h: 8 x 1 LSS 2h: 8 x 2 LSS 3h: 8 x 3 LSS .... .... Fh: 8 x 15 LSS" hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,Host N_LSS_SYN The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h - 4 x 3 LSS .... .... Fh: 4 x 15 LSS" newline bitfld.long 0x4 15. "HIBERNATE_ENA,Hibernate Enable After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode VDD1.." "0,1" hexmask.long.byte 0x4 8.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 6.--7. "SPEED_RANGE,Speed Range PLL multiplier is selected by this field. Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. 0h: Range A (Defalt) 1h: Range B 2h: Reserved 3h: Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "RESERVED,Reserved" group.quad 0x108++0x7 line.quad 0x0 "MMCSD0_UHS2_LNK_TRN_SETTINGS,Start Address of LINK/TRAN settings is pointed by the Register." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,Host N_DATA_GAP The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h: No Gap 01h: 1 LSS 02h: 2 LSS 03h: 3 LSS .... .... FFh: 255 LSS" hexmask.quad.word 0x0 18.--31. 1. "RESERVED,Reserved" newline bitfld.quad 0x0 16.--17. "RETRY_COUNT,Retry Count Data Burst retry count is set to this field. 00h: Retry Disabled 01h: 1 time 02h: 2 times 03h: 3 times" "0,1,2,3" hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host N_FCU Host Driver sets the number of blocks in Data Burst (Flow Control) to this field. The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is.." hexmask.quad.byte 0x0 0.--7. 1. "RESERVED,Reserved" rgroup.long 0x110++0x7 line.long 0x0 "MMCSD0_UHS2_GEN_CAP,Start Address of General Capabilities is pointed by the Register." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,Bus Topology This field indicates one of bus topologies configured by a Host system. 0h: P2P Connection 1h: Ring Connection 2h: HUB Connection 3h: HUB is Connected in Ring" "0,1,2,3" hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,Number of Devices Supported This field indicates the maximum number of devices supported by the Host Controller. 0h: Not used 1h: 1 Devices 2h: 2 Devices .... .... Fh: 15 Devices" newline bitfld.long 0x0 16.--17. "DEVICE_TYPE,Removable/Embedded This field indicates device type configured by a Host system. 0h: Removable Card (P2P) 1h: Embedded Devices 2h: Embedded Devices + Removable Card 3h: Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,64-bit Addressing This field indicates support of 64-bit addressing by the Host Controller. 0h: 32-bit Addressing is supported 1h: 32-bit and 64-bit Addressing is supported" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,Number of Lanes and Functionalities This field indicates support of lanes by the Host Controller. 0 mean not supported and 1 means supported. D08: 2L-HD D09: 2D1U-FD D10: 1D2U-FD D11: 2D2U-FD D12: Reserved D13: Reserved" hexmask.long.byte 0x0 4.--7. 1. "GAP,GAP (Group Allocation Power) This field indicates the maximum capability of host power supply for a group configured by a Host system. This field is used to set the argument of DEVICE_INIT CCM. 0h: Not used 1h: 360 mW 2h: 720 mW .... .... Fh: 360 x.." hexmask.long.byte 0x0 0.--3. 1. "DAP,DAP (Device Allocation Power) This field indicates the maximum capability of host power supply for a device configured by a Host system. This field is used to set the argument of DEVICE_INIT CCMD. 0h: 360 mW (Default) 1h: 360 mW 2h: 720 mW .... ...." line.long 0x4 "MMCSD0_UHS2_PHY_CAP,Start Address of PHY Capabilities is pointed by the Register." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,Host N_LSS_DIR This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h: 4 x 3 LSS .... .... Fh: 4 x 15 LSS" hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,Host N_LSS_SYN This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h: 4 x 3 LSS .... .... Fh: 4 x 15 LSS" newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 6.--7. "SPEED_RANGE,Speed Range This field indicates supported Speed Range by the Host Controller. 0h: Range A (Default) 1h: Range A and Range B 2h: Reserved 3h: Reserved" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "RESERVED,Reserved" rgroup.quad 0x118++0x7 line.quad 0x0 "MMCSD0_UHS2_LNK_TRN_CAP,Start Address of LINK/TRAN settings is pointed by the Register." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,Host N_DATA_GAP This field indicates the minimum number of data gap (DIDL) supported by the Host Controller. 00h: No Gap 01h: 1 LSS 02h: 2 LSS 03h: 3 LSS .... .... FFh: 255 LSS" hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,Host Maximum Block Length This field indicates maximum block length by the Host Controller. 000h: Not Used 001h: 1 byte 002h: 2 bytes .... .... 200h: 512 bytes .... .... 800h: 2048 bytes 801h - FFFh: Not Used" newline hexmask.quad.byte 0x0 16.--19. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,Host N_FCU This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller. This value is determined by supported buffer size. 00h: 256 Blocks 01h: 1 Block 02h: 2 Block 03h: 3 Block .... .... FFh: 255 Blocks" hexmask.quad.byte 0x0 0.--7. 1. "RESERVED,Reserved" group.long 0x120++0x3 line.long 0x0 "MMCSD0_FORCE_UHSII_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h: Not Affected 1h: Vendor Specific Error Status is set" hexmask.long.word 0x0 18.--26. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Force Event for Timeout for Deadlock Setting this bit forces the Host Controller to set Timeout for Deadlock in the 0h: Not affected 1h: Timeout for Deadlock Error status is set" "0,1" newline bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Force Event for Timeout for CMD_RES Setting this bit forces the Host Controller to set Timeout for CMD_RES in the 0h: Not affected 1h: Timout for CMD_RES Status is set" "0,1" bitfld.long 0x0 15. "ADMA,Force Event for ADMA Error Setting this bit forces the Host Controller to set ADMA Error in the 0h: Not affected 1h: ADMA Error Status is set" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "EBSY,Force Event for EBSY Error Setting this bit forces the Host Controller to set EBSY Error in the 0h: Not affected 1h: EBSY Error Status is set" "0,1" bitfld.long 0x0 7. "UNRECOVERABLE,Force Event for Unrecoverable Error Setting this bit forces the Host Controller to set Unrecoverable Error in the 0h: Not affected 1h: Unrecoverable Error Status is set" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 5. "TID,Force Event for TID Error Setting this bit forces the Host Controller to set TID Error in the 0h: Not affected 1h: TID Error Status is set" "0,1" bitfld.long 0x0 4. "FRAMING,Force Event for Framing Error Setting this bit forces the Host Controller to set Framing Error in the 0h: Not affected 1h: Framing Error Status is set" "0,1" bitfld.long 0x0 3. "CRC,Force Event for CRC Error Setting this bit forces the Host Controller to set CRC Error in the 0h: Not affected 1h: CRC Error Status is set" "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Force Event for Retry Expired Setting this bit forces the Host Controller to set Retry Expired in the 0h: Not affected 1h: Retry expired error status is set" "0,1" bitfld.long 0x0 1. "RES_PKT,Force Event for RES Packet Error Setting this bit forces the Host Controller to set RES Packet Error in the 0h: Not affected 1h: RES packet error status is set" "0,1" bitfld.long 0x0 0. "HEADER,Force Event for Header Error Setting this bit forces the Host Controller to set Header Error in the 0h: Not affected 1h: Header error status is set" "0,1" rgroup.long 0x200++0x7 line.long 0x0 "MMCSD0_CQ_VERSION,This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1. The following table describes the CQBASE+00h: Command.." hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number (digit left of decimal point) in BCD format" hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number (digit right of decimal point) in BCD format" newline hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix (2nd digit right of decimal point) in BCD format" line.long 0x4 "MMCSD0_CQ_CAPABILITIES,This register is reserved for capability indication." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details ( Field Value Description: 0h: 0.001 MHz 1h: 0.01 MHz 2h: 0.1 MHz 3h: 1 MHz.." bitfld.long 0x4 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0x4 0.--9. 1. "CF_VAL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling. The clock frequency is calculated as ITCFVAL × ITCFMUL. For.." group.long 0x208++0x27 line.long 0x0 "MMCSD0_CQ_CONFIG,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 12. "DCMD_ENA,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot #31 to determine how to decode the.." "0,1" rbitfld.long 0x0 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "TASK_DESC_SIZE,This bit indicates whether the task descriptor size is 128 bits or 64 bits. This bit can only be configured when the Bit Value Description 0h: Task descriptor size is 64 bits 1h: Task descriptor size is 128 bits" "0,1" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CQ_ENABLE,Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE). When this bit is 0h CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller. Before software writes 1h to this.." "0,1" line.long 0x4 "MMCSD0_CQ_CONTROL,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Software shall write 1h to this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state (Halt bit is 1h). When software writes 1h the value of the register is updated to 1h and.." "0,1" hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "HALT_BIT,Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example issuing a Discard Task command (CMDQ_TASK_MGMT). When software writes 1h CQE.." "0,1" line.long 0x8 "MMCSD0_CQ_INTR_STS,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in the register." hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 4. "TASK_ERROR,This bit is asserted when task error is detected due to invalid task descriptor." "0,1" bitfld.long 0x8 3. "TASK_CLEARED,This status bit is asserted (if" "0,1" newline bitfld.long 0x8 2. "RESP_ERR_DET,This status bit is asserted (if Software uses the" "0,1" bitfld.long 0x8 1. "TASK_COMPLETE,This status bit is asserted (if (1) A task is completed and the INT bit is set in its Task Descriptor (2) Interrupt caused by Interrupt Coalescing logic" "0,1" bitfld.long 0x8 0. "HALT_COMPLETE,This status bit is asserted (if" "0,1" line.long 0xC "MMCSD0_CQ_INTR_STS_ENA,This register enables and disables the reporting of the corresponding interrupt to host software in 299 register. When a bit is set (1h) and the corresponding interrupt condition is active. then the 300 bit in the register is.." hexmask.long 0xC 5.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 4. "TASK_ERROR,1h: 0h:" "0,1" bitfld.long 0xC 3. "TASK_CLEARED,1h: 0h:" "0,1" newline bitfld.long 0xC 2. "RESP_ERR_DET,1h: 0h:" "0,1" bitfld.long 0xC 1. "TASK_COMPLETE,1h: 0h:" "0,1" bitfld.long 0xC 0. "HALT_COMPLETE,1h: 0h:" "0,1" line.long 0x10 "MMCSD0_CQ_INTR_SIG_ENA,This register enables and disables the generation of interrupts to host software. When a bit is set 304 (1h) and the corresponding bit in the register is set. then an interrupt is generated. Interrupt sources 305 that are disabled.." hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 4. "TASK_ERROR,When set and the" "0,1" bitfld.long 0x10 3. "TASK_CLEARED,When set and the" "0,1" newline bitfld.long 0x10 2. "RESP_ERR_DET,When set and the" "0,1" bitfld.long 0x10 1. "TASK_COMPLETE,When set and the" "0,1" bitfld.long 0x10 0. "HALT_COMPLETE,When set and the" "0,1" line.long 0x14 "MMCSD0_CQ_INTR_COALESCING,This register controls the interrupt coalescing feature." bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0h by software command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT = 1 in the Task Descriptor. When set to 1h the interrupt coalescing mechanism is enabled and.." "0,1" hexmask.long.word 0x14 21.--30. 1. "RESERVED,Reserved" rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter &gt; 0). Bit Value Description 0h: No task completions have occurred since last.." "0,1" newline hexmask.long.byte 0x14 13.--19. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt. Counter Operation: As data transfer tasks with INT = 0 complete .." rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by software during the interrupt service routine. It starts.." line.long 0x18 "MMCSD0_CQ_TDL_BASE_ADDR,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,This register stores the LSB bits (bits 31-0) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 × (Task Descriptor size + Transfer Descriptor size) as configured by Host.." line.long 0x1C "MMCSD0_CQ_TDL_BASE_ADDR_UPBITS,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,This register stores the MSB bits (bits 63-32) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 × (Task Descriptor size + Transfer Descriptor size) as configured by Host.." line.long 0x20 "MMCSD0_CQ_TASK_DOOR_BELL,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Software shall configure the Writing 1h to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. CQE always processes tasks in-order according to the order submitted to the list by the CQE processes Data.." line.long 0x24 "MMCSD0_CQ_TASK_COMP_NOTIF,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register (at the same time it clears bit n of the When receiving interrupt for task completion software may read this register to know which tasks have finished. After reading this register software may clear the.." rgroup.long 0x230++0x7 line.long 0x0 "MMCSD0_CQ_DEV_QUEUE_STATUS,This register stores the most recent value of the device's queue status." hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register (QSR) from the device it updates this register with the response of status command (the device's queue status)." line.long 0x4 "MMCSD0_CQ_DEV_PENDING_TASKS,This register indicates to software which tasks are queued in the device. awaiting execution." hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task hasnt been executed yet. CQE shall set this bit after receiving a successful response for.." group.long 0x238++0x3 line.long 0x0 "MMCSD0_CQ_TASK_CLEAR,This register is used for removing an outstanding task in the CQE 327. The register should be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1h to bit n of this register orders CQE to clear a task which software has previously issued. This bit can only be written when CQE is in Halt state as indicated in the When software writes 1h to a bit in this register CQE updates the.." group.long 0x240++0x7 line.long 0x0 "MMCSD0_CQ_SEND_STS_CONFIG1,The register controls when the SEND_QUEUE_STATUS commands are sent." hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue. A value of n means CQE shall send status command on the CMD line during the transfer of data block A value of 0h.." hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling. Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "MMCSD0_CQ_SEND_STS_CONFIG2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. CQE shall copy this field to bits 31-16 of the argument when transmitting SEND_QUEUE_STATUS (CMD13) command." rgroup.long 0x248++0x3 line.long 0x0 "MMCSD0_CQ_DCMD_RESPONSE,This register is used for passing the response of a DCMD task to software." hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct command (DCMD) task which was sent. CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit.." rgroup.long 0x250++0x13 line.long 0x0 "MMCSD0_CQ_RESP_ERR_MASK,This register controls the generation of Response Error Detection (RED) interrupt." hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status field which is received in R1/R1b responses. Bit Value Description (for any bit i): 1h: When a R1/R1b response is received with bit i in the device status set a RED interrupt is.." line.long 0x4 "MMCSD0_CQ_TASK_ERR_INFO,This register is updated by CQE when an error occurs on data or command related to a task activity. When such error is detected by CQE or indicated by the eMMC controller CQE stores in the register the task IDs and the command.." bitfld.long 0x4 31. "DATERR_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated the bit is set to 1h. If a no data transfer is in progress when the error is.." "0,1" bitfld.long 0x4 29.--30. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 24.--28. 1. "DATERR_TASK_ID,This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE or indicated by eMMC controller." newline bitfld.long 0x4 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "DATERR_CMD_INDEX,This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK (CMD46) or EXECUTE_WRITE_TASK (CMD47) according to the data direction. The field is.." bitfld.long 0x4 15. "RESP_MODE_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated the bit is set to 1h. If a no command transaction is in progress when the.." "0,1" newline bitfld.long 0x4 13.--14. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 8.--12. 1. "RESP_MODE_TASK_ID,This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE or indicated by eMMC controller." bitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "RESP_MODE_CMD_INDEX,This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE or indicated by eMMC controller." line.long 0x8 "MMCSD0_CQ_CMD_RESP_INDEX,This register stores the index of the last received command response." hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a command response is received." line.long 0xC "MMCSD0_CQ_CMD_RESP_ARG,This register stores the index of the last received command response." hexmask.long 0xC 0.--31. 1. "LAST_CRA,This field stores the argument of the last received command. CQE shall update the value every time a command response is received." line.long 0x10 "MMCSD0_CQ_ERROR_TASK_ID,CQ Error Task ID Register" hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--4. 1. "TERR_ID,Task Error ID" tree.end tree "MMCSD0_ECC_AGGR_RXMEM" base ad:0x2A24000 rgroup.long 0x0++0x3 line.long 0x0 "MMCSD0_RXECC_REV,Aggregator Revision Register Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MMCSD0_RXECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MMCSD0_RXECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator." group.long 0x3C++0x7 line.long 0x0 "MMCSD0_RXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,SEC EOI" "0,1" line.long 0x4 "MMCSD0_RXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "MMCSD0_RXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "MMCSD0_RXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "MMCSD0_RXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,DED EOI" "0,1" line.long 0x4 "MMCSD0_RXECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "MMCSD0_RXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MMCSD0_RXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "MMCSD0_RXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "MMCSD0_RXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "MMCSD0_RXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MMCSD0_RXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD0_ECC_AGGR_TXMEM" base ad:0x2A25000 rgroup.long 0x0++0x3 line.long 0x0 "MMCSD0_TXECC_REV,Aggregator Revision Register Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MMCSD0_TXECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MMCSD0_TXECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator." group.long 0x3C++0x7 line.long 0x0 "MMCSD0_TXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,SEC EOI" "0,1" line.long 0x4 "MMCSD0_TXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "MMCSD0_TXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "MMCSD0_TXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "MMCSD0_TXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,DED EOI" "0,1" line.long 0x4 "MMCSD0_TXECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "MMCSD0_TXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MMCSD0_TXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "MMCSD0_TXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "MMCSD0_TXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "MMCSD0_TXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MMCSD0_TXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD0_SS_CFG" base ad:0x4F88000 rgroup.long 0x0++0x3 line.long 0x0 "MMCSD0_SS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem." hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version" bitfld.long 0x0 8.--10. "MAJ_REV,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor Revision" group.long 0x10++0x37 line.long 0x0 "MMCSD0_SS_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the number of Taps (Phases) of the RX clock that is supported." rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency" line.long 0x4 "MMCSD0_SS_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller. This register sets the LSB fields in the register inside the Host Controller." bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type Should be set based on the final product usage." "0,1,2,3" bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support Suggested Value is 1h (The Core supports monitoring of Asynchronous Interrupt)." "0,1" rbitfld.long 0x4 27.--28. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8 V Support Suggested Value is 1h (The 1.8 Volt Switching is supported by Core)." "0,1" newline bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0 V Support Should be set based on whether 3.0 V is supported on the SD Interface." "0,1" bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3 V Support Suggested Value is 1h as the 3.3 V is the default voltage on the SD Interface." "0,1" bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support Suggested Value is 1h (The Suspend/Resume is supported by Core)." "0,1" bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support Suggested Value is 1h (The SDMA is supported by Core)." "0,1" newline bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support Suggested Value is 1h (The High Speed mode is supported by Core)." "0,1" rbitfld.long 0x4 20. "RESERVED,Reserved" "0,1" bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support Suggested Value is 1h (The ADMA2 is supported by Core)." "0,1" bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device Suggested Value is 1h (The Core supports 8-bit Interface)." "0,1" newline bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length Maximum Block Length supported by the Core/Device." "0,1,2,3" hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock This is the frequency of the FCLK." bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit Suggested Value is 0h (KHz)." "0,1" rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency Suggested Value is 1 KHz." line.long 0x8 "MMCSD0_SS_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller. This register sets the MSB fields in the register inside the Host Controller." bitfld.long 0x8 31. "HS400SUPPORT,HS400 Support Suggested Value is 1h (The Core supports HS400 Mode)." "0,1" rbitfld.long 0x8 29.--30. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8 V VDD2 Support" "0,1" bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support" "0,1" newline rbitfld.long 0x8 24.--26. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator." bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes Should be set to 2h as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3" bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50 This bit should be set if the application wants Tuning be used for SDR50 Modes." "0,1" newline rbitfld.long 0x8 12. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3." bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1" rbitfld.long 0x8 3. "RESERVED,Reserved" "0,1" bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support Suggested Value is 1h (The Core supports DDR50 mode of operation)." "0,1" newline bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support." "0,1" bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support." "0,1" line.long 0xC "MMCSD0_SS_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller. This register sets the LSB fields in the register inside the Host Controller." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current For 1.8 V" hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current For 3.0 V" hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current For 3.3 V" line.long 0x10 "MMCSD0_SS_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller. This register sets the MSB fields in the register inside the Host Controller." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current For 1.8 V (VDD2)" line.long 0x14 "MMCSD0_SS_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for Initialization inside the Host Controller." hexmask.long.tbyte 0x14 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value For Initialization" line.long 0x18 "MMCSD0_SS_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for Default Speed inside the Host Controller." hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value For Default Speed" line.long 0x1C "MMCSD0_SS_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for High Speed inside the Host Controller." hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value For High Speed" line.long 0x20 "MMCSD0_SS_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for SDR12 inside the Host Controller." hexmask.long.tbyte 0x20 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value For SDR12" line.long 0x24 "MMCSD0_SS_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for SDR25 inside the Host Controller." hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value For SDR25" line.long 0x28 "MMCSD0_SS_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for SDR50 inside the Host Controller." hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value For SDR50" line.long 0x2C "MMCSD0_SS_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for SDR104 inside the Host Controller." hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value For SDR104" line.long 0x30 "MMCSD0_SS_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for DDR50 inside the Host Controller." hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value For DDR50" line.long 0x34 "MMCSD0_SS_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for HS400 inside the Host Controller." hexmask.long.tbyte 0x34 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x34 0.--12. 1. "HS400PRESETVAL,Preset Value For HS400" rgroup.long 0x60++0x17 line.long 0x0 "MMCSD0_SS_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller." bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable software to gate off the clocks" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus" line.long 0x4 "MMCSD0_SS_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus" line.long 0x8 "MMCSD0_SS_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus" line.long 0xC "MMCSD0_SS_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)" line.long 0x10 "MMCSD0_SS_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)" line.long 0x14 "MMCSD0_SS_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus" group.long 0x100++0x17 line.long 0x0 "MMCSD0_SS_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY." hexmask.long.word 0x0 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 20.--22. "DR_TY,Drive Source/Sink Impedance Programming 0h: 50 Ohms" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 18.--19. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 17. "RETRIM,Start CALIO Calibration Cycle At positive edge initiates CALIO calibration cycle." "0,1" newline bitfld.long 0x0 16. "EN_RTRIM,CALIO Enable Enables CALIO If enabled CALIO will start calibration cycle at phyctrl_pdb positive edge." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 4.--7. 1. "DLL_TRM_ICP,Analog DLL's Charge Pump Current Trim Programs the analog DLL loop gain." rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "ENDLL,Enable DLL Enables the analog DLL circuits." "0,1" bitfld.long 0x0 0. "PDB,CALIO S/M Power Down Bar SoC asserts after power up sequence is completed." "0,1" line.long 0x4 "MMCSD0_SS_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Host Controller PHY." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 29. "OD_RELEASE_STRB,Disable an internal 4.7 K pull up resistor on STRB line in open drain mode" "0,1" bitfld.long 0x4 28. "OD_RELEASE_CMD,Disable an internal 4.7 K pull up resistor on CMD line in open drain mode" "0,1" hexmask.long.byte 0x4 24.--27. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--23. 1. "OD_RELEASE_DAT,Disable an internal 4.7 K pull up resistor on data lines in open drain mode" rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 13. "ODEN_STRB,Open Drain Enable On STRB Lline" "0,1" bitfld.long 0x4 12. "ODEN_CMD,Open Drain Enable On CMD Line" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "ODEN_DAT,Open Drain Enable On DAT Lines" line.long 0x8 "MMCSD0_SS_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Host Controller PHY." rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 29. "PU_STRB,Enable Pull Up On STRB Line If ren_strb is high week pull up is enabled on STRB line." "0,1" bitfld.long 0x8 28. "PU_CMD,Enable Pull Up On CMD Line If ren_cmd is high week pull up is enabled on CMD line." "0,1" hexmask.long.byte 0x8 24.--27. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "PU_DAT,Enable Pull Up On DAT Lines If ren_dat is high week pull up is enabled on DATA lines." rbitfld.long 0x8 14.--15. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 13. "REN_STRB,Enable Pull Up/Down On The STRB Line If pu_strb is high a week pull up is enabled on STRB line if low week pull down is enabled on STRB line." "0,1" bitfld.long 0x8 12. "REN_CMD,Enable Pull Up/Down On The CMD Line If pu_cmd is high a week pull up is enabled on CMD line if low week pull down is enabled on CMD line." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "REN_DAT,Enable Pull Up/Down On The DAT Lines If pu_dat is high a week pull up is enabled on DATA lines if low week pull down is enabled on DATA lines." line.long 0xC "MMCSD0_SS_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY." hexmask.long.byte 0xC 24.--31. 1. "STRBSEL,Select the Four Taps for each of STRB_90 and STRB_180 Outputs." rbitfld.long 0xC 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 20. "OTAPDLYENA,Output Tap Delay Enable Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1" hexmask.long.byte 0xC 16.--19. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xC 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 9. "ITAPCHGWIN,Input Tap Change Window It gets asserted by the controller while changing the itapdlysel." "0,1" bitfld.long 0xC 8. "ITAPDLYENA,Input Tap Delay Enable This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1" newline rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select Manual control of the RX clock Tap Delay in the non HS200/HS400 modes." line.long 0x10 "MMCSD0_SS_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY." hexmask.long.word 0x10 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 17. "SELDLYTXCLK,Select the Delay chain based txclk." "0,1" bitfld.long 0x10 16. "SELDLYRXCLK,Select the Delay chain based rxclk." "0,1" hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x10 8.--10. "FRQSEL,Select the frequency range of DLL operation:" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 3.--7. 1. "RESERVED,Reserved" bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select." "0,1,2,3,4,5,6,7" line.long 0x14 "MMCSD0_SS_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Host Controller PHY." bitfld.long 0x14 31. "BISTENABLE,Internal BIST Operation Enable Enables the embedded BIST." "0,1" bitfld.long 0x14 30. "BISTSTART,Internal BIST Start Starts the embedded BIST operation." "0,1" rbitfld.long 0x14 28.--29. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "BISTMODE,Internal BIST Mode Select Select the embedded BIST mode of operation." newline hexmask.long.word 0x14 8.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 0.--7. 1. "TESTCTRL,PHY Test Control:" rgroup.long 0x130++0x7 line.long 0x0 "MMCSD0_SS_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Host Controller PHY ports." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 4.--7. 1. "RTRIM,CALIO Calibration Result Holds the content of CALIO Impedance Calibration Result." bitfld.long 0x0 3. "BISTDONE,Internal BIST Completed Test Cycle Indicates that the embedded BIST has completed the test cycle." "0,1" bitfld.long 0x0 2. "EXR_NINST,External Resistor On CALIO Absent Indicates trim cycle started and external resistor is absent." "0,1" newline bitfld.long 0x0 1. "CALDONE,STATUS indicate that CALIO Calibration is completed successfully." "0,1" bitfld.long 0x0 0. "DLLRDY,DLL Ready Indicates that DLL loop is locked." "0,1" line.long 0x4 "MMCSD0_SS_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Host Controller PHY ports." hexmask.long 0x4 0.--31. 1. "BISTSTATUS,Internal BIST Data Compare Results BIST cycle data comparison results." tree.end tree "MMCSD1_CTL_CFG" base ad:0x4FB0000 group.word 0x0++0xF line.word 0x0 "MMCSD1_SDMA_SYS_ADDR_LO,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,32-bit Block Count (SDMA System Address) Low When the When the (1) SDMA System Address ( This register contains the system memory address for a SDMA transfer in 32-bit addressing mode. When the Host Controller (HC) stops a SDMA transfer .." line.word 0x2 "MMCSD1_SDMA_SYS_ADDR_HI,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,32-bit Block Count (SDMA System Address) High This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version.." line.word 0x4 "MMCSD1_BLOCK_SIZE,This register is used to configure the number of bytes in a data block." rbitfld.word 0x4 15. "RESERVED,Reserved" "0,1" bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,Host SDMA Buffer Size To perform long DMA transfer System Address register ( These bits shall support when the 0h: 4KB (Detects A11 Carry out) 1h: 8KB (Detects A12 Carry out) 2h: 16KB (Detects A13 Carry out) 3h: 32KB (Detects A14 Carry.." "0,1,2,3,4,5,6,7" hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,Transfer Block Size This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53. It can be accessed only if no transaction is executing (after a transaction has stopped). Read operations during.." line.word 0x6 "MMCSD1_BLOCK_COUNT,This register is used to configure the number of data blocks." hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,16-bit Block Count Host Controller Version 4.10 extends block count to 32-bit. Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: (1) If the (2) If the Use of 16-bit/32-bit Block Count.." line.word 0x8 "MMCSD1_ARGUMENT1_LO,This register contains Lower bits of SD Command Argument." hexmask.word 0x8 0.--15. 1. "CMD_ARG1,Command Argument 1 Low The SD Command Argument is specified as bit 23-8 of Command-Format." line.word 0xA "MMCSD1_ARGUMENT1_HI,This register contains higher bits of SD Command Argument." hexmask.word 0xA 0.--15. 1. "CMD_ARG1,Command Argument 1 High The SD Command Argument is specified as bit 39-24 of Command-Format." line.word 0xC "MMCSD1_TRANSFER_MODE" hexmask.word.byte 0xC 9.--15. 1. "RESERVED,Reserved" bitfld.word 0xC 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0h.." "0,1" bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error this bit is set.." "0,1" newline bitfld.word 0xC 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled ( Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "0,1" bitfld.word 0xC 5. "MULTI_BLK_SEL,Multi/Single Block Select This bit enables multiple block data transfers. 0h: Single Block 1h: Multiple Block" "0,1" bitfld.word 0xC 4. "DATA_XFER_DIR,Data Transfer Direction Select This bit defines the direction of data transfers. 0h: Write (Host to Card) 1h: Read (Card to Host)" "0,1" newline bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,Auto CMD Enable This field determines use of auto command functions. There are three methods to stop Multiple-block read and write operation by CMD23 or CMD12. In the other operations (for example single read/write operation) this field is.." "0,1,2,3" bitfld.word 0xC 1. "BLK_CNT_ENA,Block Count Enable This bit is used to enable the 0h: Disable 1h: Enable" "0,1" bitfld.word 0xC 0. "DMA_ENA,DMA Enable DMA can be enabled only if the 0h: Disable 1h: Enable" "0,1" line.word 0xE "MMCSD1_COMMAND,This register is used to program the Command for host controller." rbitfld.word 0xE 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,Command Index This bit shall be set to the command number (CMD0-63 ACMD0-63)." bitfld.word 0xE 6.--7. "CMD_TYPE,Command Type There are three types of special commands. Suspend Resume and Abort. These bits shall be set to 0h for all other commands. Suspend Command: Resume Command: Abort Command: 0h: Normal 1h: Suspend 2h: Resume 3h: Abort" "0,1,2,3" newline bitfld.word 0xE 5. "DATA_PRESENT,Data Present Select This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line. If is set to 0h for the following: 0h: No Data Present 1h: Data Present" "0,1" bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,Command Index Check Enable If this bit is set to 1h the HC shall check the index field in the response to see if it has the same value as the command index. If it is not it is reported as a Command Index Error. If this bit is set to.." "0,1" bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,Command CRC Check Enable If this bit is set to 1h the HC shall check the CRC field in the response. If an error is detected it is reported as a Command CRC Error. If this bit is set to 0h the CRC field is not checked. 0h: Disable 1h:.." "0,1" newline bitfld.word 0xE 2. "SUB_CMD,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command this bit is set to 0h and when issuing a sub command this bit is set to 1h. Setting of this bit is checked by the.." "0,1" bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select 0h: No Response 1h: Response length 136 2h: Response length 48 3h: Response length 48 check Busy after response" "0,1,2,3" rgroup.word 0x10++0x1 line.word 0x0 "MMCSD1_RESPONSE_0,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.word 0x14++0x1 line.word 0x0 "MMCSD1_RESPONSE_1,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.word 0x18++0x1 line.word 0x0 "MMCSD1_RESPONSE_2,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.word 0x1C++0x1 line.word 0x0 "MMCSD1_RESPONSE_3,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.long 0x20++0x3 line.long 0x0 "MMCSD1_DATA_PORT,This register is used to access internal buffer." hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,Buffer Data The Host Controller Buffer can be accessed through this 32-bit Data Port Register." rgroup.word 0x20++0x1 line.word 0x0 "MMCSD1_RESPONSE_4,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." rgroup.long 0x24++0x3 line.long 0x0 "MMCSD1_PRESENTSTATE,The Host Driver can get status of the Host Controller from this 32-bit read-only register." bitfld.long 0x0 31. "UHS2_IF_DETECTION,UHS-II IF Detection (UHS-II Only) This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( After UHS-II IF is detected this bit is cleared.." "0,1" bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,Lane Synchronization (UHS-II Only) This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( In case of Version 4.00 this bit.." "0,1" bitfld.long 0x0 29. "UHS2_DORMANT,In Dormant State (UHS-II Only) This status indicates whether UHS-II lanes enter Dormant state. This function is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register ( RCLK may be stopped in dormant state by.." "0,1" newline bitfld.long 0x0 28. "SUB_COMMAND_STS,Sub Command Status The 1h: Sub Command Status 0h: Main Command Status" "0,1" bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Command Not Issued by Error Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in.." "0,1" bitfld.long 0x0 25.--26. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 24. "SDIF_CMDIN,CMD Line Signal Level (SD Mode Only) This status is used to check CMD line level to recover from errors and for debugging." "0,1" bitfld.long 0x0 23. "SDIF_DAT3IN,DAT[3] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[3]. D23 - DAT[3]" "0,1" bitfld.long 0x0 22. "SDIF_DAT2IN,DAT[2] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[2]. D22 - DAT[2]" "0,1" newline bitfld.long 0x0 21. "SDIF_DAT1IN,DAT[1] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[1]. D21 - DAT[1]" "0,1" bitfld.long 0x0 20. "SDIF_DAT0IN,DAT[0] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. D20 - DAT[0]" "0,1" bitfld.long 0x0 19. "WRITE_PROTECT,Write Protect Switch Pin Level The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin. 0h: Write protected (SDWP# = 1) 1h: Write enabled (SDWP# = 0)" "0,1" newline bitfld.long 0x0 18. "CARD_DETECT,Card Detect Pin Level This bit reflects the inverse value of the SDCD# pin. 0h: No Card present (SDCD# = 1) 1h: Card present (SDCD# = 0)" "0,1" bitfld.long 0x0 17. "CARD_STATE_STABLE,Card State Stable This bit is used for testing. If it is 0h the Card Detect Pin Level is not stable. If this bit is set to 1h it means the Card Detect Pin Level is stable. The 0h: Reset of Debouncing 1h: No Card or Inserted" "0,1" bitfld.long 0x0 16. "CARD_INSERTED,Card Inserted This bit indicates whether a card has been inserted. Changing from 0h to 1h generates a Card Insertion interrupt in the If a Card is removed while its power is on and its clock is oscillating the HC shall clear the 0h: Reset.." "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "BUF_RD_ENA,Buffer Read Enable This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1h readable data exists in the buffer. A change of this bit from 1h to 0h.." "0,1" bitfld.long 0x0 10. "BUF_WR_ENA,Buffer Write Enable This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1h data can be written to the buffer. A change of this bit from 1h to 0h occurs when all.." "0,1" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,Read Transfer Active (SD Mode Only) This status is used for detecting completion of a read transfer. This bit is set to 1h for either of the following conditions: This bit is cleared to 0h for either of the following conditions: 1h:.." "0,1" bitfld.long 0x0 8. "WR_XFER_ACTIVE,Write Transfer Active (SD Mode Only) This status indicates a write transfer is active. If this bit is 0h it means no valid write data exists in the HC. This bit is set in either of the following cases: This bit is cleared in either of the.." "0,1" bitfld.long 0x0 7. "SDIF_DAT7IN,DAT[7] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging. D07 - DAT[7]" "0,1" newline bitfld.long 0x0 6. "SDIF_DAT6IN,DAT[6] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging. D06 - DAT[6]" "0,1" bitfld.long 0x0 5. "SDIF_DAT5IN,DAT[5] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging. D05 - DAT[5]" "0,1" bitfld.long 0x0 4. "SDIF_DAT4IN,DAT[4] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging. D04 - DAT[4]" "0,1" newline bitfld.long 0x0 3. "RETUNING_REQ,Re-Tuning Request (UHS-I Only) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive.." "0,1" bitfld.long 0x0 2. "DATA_LINE_ACTIVE,DAT Line Active (SD Mode Only) This bit indicates whether one of the DAT line on SD bus is in use. 1h: DAT line active 0h: DAT line inactive" "0,1" bitfld.long 0x0 1. "INHIBIT_DAT,Command Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h. If this bit is 0h it indicates the HC can issue the next SD command. Commands with busy signal belong.." "0,1" newline bitfld.long 0x0 0. "INHIBIT_CMD,Command Inhibit (CMD) 1h: Host Controller is not ready to issue a command 0h: Host Controller is ready to issue a command Version 4.10 adds a new control to prevent error statuses from overwriting by receipt of a next command. This status.." "0,1" rgroup.word 0x24++0x1 line.word 0x0 "MMCSD1_RESPONSE_5,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.byte 0x28++0x0 line.byte 0x0 "MMCSD1_HOST_CONTROL1,This register is used to program DMA modes. LED control. data transfer width. High Speed enable. card detect test level and signal selection." bitfld.byte 0x0 7. "CD_SIG_SEL,Card Detect Signal Detection This bit selects source for card detection. 1h: The card detect test level is selected 0h: SDCD# is selected (for normal use)" "0,1" bitfld.byte 0x0 6. "CD_TEST_LEVEL,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal interrupt status enable bit is set. 1h:.." "0,1" bitfld.byte 0x0 5. "EXT_DATA_WIDTH,Extended Data Transfer Width (Embedded and SD Mode Only) This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the This bit is not effective when multiple.." "0,1" newline bitfld.byte 0x0 3.--4. "DMA_SELECT,DMA Select This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the (1) Up to Version 3.00: (2) Version 4.00 or later: Support of 64-bit DMA and 128-bit Descriptor is indicated by the" "0: (2,?,?,?" bitfld.byte 0x0 2. "HIGH_SPEED_ENA,High Speed Enable (SD Mode Only) This bit is optional. Before setting this bit the HD shall check the If the 1h: High Speed Mode 0h: Normal Speed Mode" "0,1" bitfld.byte 0x0 1. "DATA_WIDTH,Data Transfer Width (SD Mode Only) This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode. 1h: 4 bit mode 0h: 1 bit mode" "0,1" newline bitfld.byte 0x0 0. "LED_CONTROL,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands this bit can be set during all transactions. It is not necessary to change.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "MMCSD1_RESPONSE_6,This registers is used to store responses from SD Cards." hexmask.word 0x0 0.--15. 1. "CMD_RESP,Command Response R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.byte 0x29++0x2 line.byte 0x0 "MMCSD1_POWER_CONTROL,This register is used to program the SD Bus power and voltage level." bitfld.byte 0x0 5.--7. "UHS2_VOLTAGE,SD Bus Voltage Select for VDD2 (UHS-II Only) This field determines supply voltage range to VDD2. This field can be set to 5h if the 111b: Not used 110b: Not used 101b: 1.8 V 100b: Reserved for 1.2 V 011b – 001b: Reserved 000b: VDD2 Not.." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "UHS2_POWER,SD Bus Power for VDD2 (UHS-II Only) Setting this bit enables providing VDD2. 1h: Power on 0h: Power off" "0,1" bitfld.byte 0x0 1.--3. "SD_BUS_VOLTAGE,SD Bus Voltage Select for VDD1 By setting these bits the HD selects the voltage level for the SD card. Before setting this register the HD shall check the voltage support bits in the 111b: 3.3 V (Flattop.) 110b: 3.0 V (Typ.) 101b: 1.8 V.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "SD_BUS_POWER,SD Bus Power for VDD1 Before setting this bit the SD host driver shall set SD Bus Voltage Select ( If this bit is cleared the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state) and drive SDCLK to low level. If.." "0,1" line.byte 0x1 "MMCSD1_BLOCK_GAP_CONTROL,This register is used to program the block gap request. read wait control and interrupt at block gap." bitfld.byte 0x1 7. "BOOT_ACK_ENA,Boot Acknowledge Check To check for the boot acknowledge in boot operation. 1h: Wait for boot ack from eMMC card 0h: Will not wait for boot ack from eMMC card" "0,1" bitfld.byte 0x1 6. "ALT_BOOT_MODE,Alternative Boot Mode To start boot code access in alternative mode. 1h: To start alternate boot mode access 0h: To stop alternate boot mode access" "0,1" bitfld.byte 0x1 5. "BOOT_ENABLE,Boot Enable To start boot code access. 1h: To start boot code access 0h: To stop boot code access" "0,1" newline rbitfld.byte 0x1 4. "RESERVED,Reserved" "0,1" bitfld.byte 0x1 3. "INTRPT_AT_BLK_GAP,Interrupt At Block Gap (SD Mode Only) This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1h enables interrupt detection at the block gap for a multiple block transfer. If.." "0,1" bitfld.byte 0x1 2. "RDWAIT_CTRL,Read Wait Control (SD Mode Only) The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD.." "0,1" newline bitfld.byte 0x1 1. "CONTINUE,Continue Request This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap set Stop At block Gap Request to 0h ( The Host Controller automatically clears this bit when the.." "0,1" bitfld.byte 0x1 0. "STOP_AT_BLK_GAP,Stop At Block Gap Request This bit is used to stop executing a transaction at the next block gap for non-DMA SDMA and ADMA transfers. Until the transfer complete is set to 1h indicating a transfer completion the HD shall leave this bit.." "0,1" line.byte 0x2 "MMCSD1_WAKEUP_CONTROL,This register is used to program the wakeup functionality. The register is mandatory for the HC. but wakeup functionality depends on the HC system hardware and software. The HD shall maintain voltage on the SD Bus. by setting the.." hexmask.byte 0x2 3.--7. 1. "RESERVED,Reserved" bitfld.byte 0x2 2. "CARD_REMOVAL,Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card removal assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit. 1h: Enable 0h: Disable" "0,1" bitfld.byte 0x2 1. "CARD_INSERTION,Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit. 1h: Enable 0h: Disable" "0,1" newline bitfld.byte 0x2 0. "CARD_INTERRUPT,Wakeup Event Enable On Card Interrupt This bit enables wakeup event via Card Interrupt assertion in the This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h. 1h: Enable 0h: Disable" "0,1" group.word 0x2C++0x1 line.word 0x0 "MMCSD1_CLOCK_CONTROL,This register is used to program the Clock frequency select. Clock generator select. Clock enable. Internal clock state fields. At the initialization of the HC. the HD shall set the SDCLK Frequency Select ([15-8] SDCLK_FRQSEL).." hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,SDCLK/RCLK Frequency Select This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the Capabilities.." bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Upper Bits of SDCLK/RCLK Frequency Select This bit field is assigned to the" "0,1,2,3" bitfld.word 0x0 5. "CLKGEN_SEL,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select ( If the Programmable Clock Mode is supported (non-zero value is set to the This bit depends on the setting of the If If 1h: Programmable.." "0,1" newline rbitfld.word 0x0 4. "RESERVED,Reserved" "0,1" bitfld.word 0x0 3. "PLL_ENA,PLL Enable This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable ( (1) When (2) When 1h: PLL is enabled 0h: PLL is in low power.." "0,1" bitfld.word 0x0 2. "SD_CLK_ENA,SD Clock Enable The HC shall stop SDCLK when writing this bit to 0h. The 1h: Enable providing SDCLK or RCLK 0h: Disable providing SDCLK or RCLK" "0,1" newline rbitfld.word 0x0 1. "INT_CLK_STABLE,Internal Clock Stable This bit is set to 1h when SD clock is stable after writing 1h to (1) Internal Clock Stable (when This bit is set to 1h when internal clock is stable after writing 1h to (2) PLL Clock Stable (when Host Controller.." "0,1" bitfld.word 0x0 0. "INT_CLK_ENA,Internal Clock Enable This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still registers shall be able to be read and written. Clock starts.." "0,1" group.byte 0x2E++0x1 line.byte 0x0 "MMCSD1_TIMEOUT_CONTROL,The register sets the data timeout counter value. At the initialization of the HC. the HD shall set the Data Timeout Counter Value according to the register." hexmask.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,Data Timeout Counter Value This value determines the interval by which DAT line time-outs are detected. Refer to the 1111: Reserved 1110: TMCLK × 2 -------------------- -------------------- 0001: TMCLK × 2 0000: TMCLK × 2" line.byte 0x1 "MMCSD1_SOFTWARE_RESET,This register is used to program the software reset for data. command and for all. A reset pulse is generated when writing 1h to each bit of this register. After completing the reset. the HC shall clear each bit. Because it takes.." hexmask.byte 0x1 3.--7. 1. "RESERVED,Reserved" bitfld.byte 0x1 2. "SWRST_FOR_DAT,Software Reset for DAT Line (SD Mode Only) Only part of data circuit is reset. The following registers and bits are cleared by this bit: 1h: Reset 0h: Work" "0,1" bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset for CMD Line (SD Mode Only) Only part of command circuit is reset to be able to issue a command. From Version 4.10 this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing.." "0,1" newline bitfld.byte 0x1 0. "SWRST_FOR_ALL,Software Reset for All This reset affects the entire HC except for the card detection circuit. Register bits of type ROC RW RW1C RWAC are cleared to 0h. During its initialization the HD shall set this bit to 1h to reset the HC. The HC.." "0,1" group.word 0x30++0xB line.word 0x0 "MMCSD1_NORMAL_INTR_STS,This register gives the status of all the interrupts. The Normal Interrupt Signal Enable (see register) affects read of this register. but Normal Interrupt Signal does not affect these reads. An Interrupt is generated when the.." rbitfld.word 0x0 15. "ERROR_INTR,Error Interrupt If any of the bits in the In UHS-II mode is enabled if any of the bits in the 0h: No Error 1h: Error" "0,1" bitfld.word 0x0 14. "BOOT_COMPLETE,Boot Terminate Interrupt This status is set if the boot operation gets terminated. 0h: Boot operation is not terminated 1h: Boot operation is terminated" "0,1" bitfld.word 0x0 13. "RCV_BOOT_ACK,Boot Acknowledge Receive This status is set if the boot acknowledge is received from device. 0h: Boot acknowledge is not received 1h: Boot acknowledge is received" "0,1" newline rbitfld.word 0x0 12. "RETUNING_EVENT,Re-Tuning Event (UHS-I Only) This status is set if the Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer (not large block count) can be completed without re-tuning. In UHS-II mode this.." "0,1" rbitfld.word 0x0 11. "INTC,int_c (Embedded) This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1" rbitfld.word 0x0 10. "INTB,int_b (Embedded) This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1" newline rbitfld.word 0x0 9. "INTA,int_a (Embedded) This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_A interrupt factor." "0,1" rbitfld.word 0x0 8. "CARD_INTR,Card Interrupt When this status has been set and the Host Driver needs to start this interrupt service the Writing this bit to 1h does not clear this bit. It is cleared by resetting the SD card interrupt factor. (1) DAT[1] Interrupt Input in.." "0,1" bitfld.word 0x0 7. "CARD_REM,Card Removal This status is set if the 0h: Card State Stable or Debouncing 1h: Card Removed" "0,1" newline bitfld.word 0x0 6. "CARD_INS,Card Insertion This status is set if the 0h: Card State Stable or Debouncing 1h: Card Inserted" "0,1" bitfld.word 0x0 5. "BUF_RD_READY,Buffer Read Ready This status is set if the The In UHS-II mode this bit is set at FC (Flow Control) unit basis. 0h: Not Ready to read Buffer 1h: Ready to read Buffer" "0,1" bitfld.word 0x0 4. "BUF_WR_READY,Buffer Write Ready This status is set if the In UHS-II mode this bit is set at FC (Flow Control) unit basis. 0h: Not Ready to Write Buffer 1h: Ready to Write Buffer" "0,1" newline bitfld.word 0x0 3. "DMA_INTERRUPT,DMA Interrupt This status is set if the HC detects the Host DMA Buffer Boundary in the 0h: No DMA Interrupt 1h: DMA Interrupt is Generated" "0,1" bitfld.word 0x0 2. "BLK_GAP_EVENT,Block Gap Event If the Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (see Write Transaction: This bit is set at the falling edge of Write Transfer Active Status (see 0h: No Block Gap Event 1h:.." "0,1" bitfld.word 0x0 1. "XFER_COMPLETE,Transfer Complete This bit is set when a read/write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status ( There are two cases in which the Interrupt is generated. The first is when.." "0,1" newline bitfld.word 0x0 0. "CMD_COMPLETE,Command Complete This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23). Version 4.00 defines response check function for R1 and R5. If the If the If the 0h: No Command Complete 1h: Command Complete" "0,1" line.word 0x2 "MMCSD1_ERROR_INTR_STS,This register gives the status of the error interrupts. Status defined in this register can be enabled by the register. but not by the register. The Interrupt is generated when the register is enabled and at least one of the.." rbitfld.word 0x2 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 12. "HOST,Target Response Error Occurs when detecting ERROR in m_hresp (DMA transaction) 0h: No error 1h: Error" "0,1" bitfld.word 0x2 11. "RESP,Response Error (SD Mode Only) Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If the 0h: No error 1h: Error" "0,1" newline rbitfld.word 0x2 10. "RESERVED,Reserved" "0,1" bitfld.word 0x2 9. "ADMA,ADMA Error This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the 0h: No error 1h: Error" "0,1" bitfld.word 0x2 8. "AUTO_CMD,Auto CMD Error (SD Mode Only) Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that any of the bits D00 to D05 in the 0h: No error 1h: Error" "0,1" newline bitfld.word 0x2 7. "CURR_LIMIT,Current Limit Error By setting the 0h: No error 1h: Power Fail" "0,1" bitfld.word 0x2 6. "DATA_ENDBIT,Data End Bit Error (SD Mode Only) Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status. 0h: No error 1h: Error" "0,1" bitfld.word 0x2 5. "DATA_CRC,Data CRC Error (SD Mode Only) Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 2h. 0h: No error 1h: Error" "0,1" newline bitfld.word 0x2 4. "DATA_TIMEOUT,Data Timeout Error (SD Mode Only) Occurs when detecting one of following timeout conditions: 0h: No error 1h: Timeout" "0,1" bitfld.word 0x2 3. "CMD_INDEX,Command Index Error (SD Mode Only) Occurs if a Command Index error occurs in the Command Response ( 0h: No error 1h: Error" "0,1" bitfld.word 0x2 2. "CMD_ENDBIT,Command End Bit Error (SD Mode Only) Occurs when detecting that the end bit of a command response is 0h. 0h: No error 1h: End Bit Error Generated" "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Command CRC Error (SD Mode Only) Command CRC Error is generated in two cases. 1. If a response is returned and the 2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1.." "0,1" bitfld.word 0x2 0. "CMD_TIMEOUT,Command Timeout Error (SD Mode Only) Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict in which case the 0h: No error 1h: Timeout" "0,1" line.word 0x4 "MMCSD1_NORMAL_INTR_STS_ENA,This register is used to enable the register fields." rbitfld.word 0x4 15. "BIT15_FIXED0,Fixed to 0 The HC shall control error Interrupts using the" "0,1" bitfld.word 0x4 14. "BOOT_COMPLETE,Boot Terminate Interrupt Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 13. "RCV_BOOT_ACK,Boot Acknowledge Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x4 12. "RETUNING_EVENT,Re-Tuning Event Status Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 11. "INTC,INT_C Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to.." "0,1" bitfld.word 0x4 10. "INTB,INT_B Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to.." "0,1" newline bitfld.word 0x4 9. "INTA,INT_A Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to.." "0,1" bitfld.word 0x4 8. "CARD_INTERRUPT,Card Interrupt Status Enable If this bit is set to 0h the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1h. The HD may clear the By.." "0,1" bitfld.word 0x4 7. "CARD_REMOVAL,Card Removal Status Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x4 6. "CARD_INSERTION,Card Insertion Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 5. "BUF_RD_READY,Buffer Read Ready Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 4. "BUF_WR_READY,Buffer Write Ready Status Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x4 3. "DMA_INTERRUPT,DMA Interrupt Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 2. "BLK_GAP_EVENT,Block Gap Event Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x4 1. "XFER_COMPLETE,Transfer Complete Status Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x4 0. "CMD_COMPLETE,Command Complete Status Enable 0h: Masked 1h: Enabled" "0,1" line.word 0x6 "MMCSD1_ERROR_INTR_STS_ENA,This register is used to enable the register fields." hexmask.word.byte 0x6 12.--15. 1. "VENDOR_SPECIFIC,Vendor Specific Error Status Enable N/A" bitfld.word 0x6 11. "RESP,Response Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 10. "TUNING,Tuning Error Status Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x6 9. "ADMA,ADMA Error Status Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 8. "AUTO_CMD,Auto CMD Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 7. "CURR_LIMIT,Current Limit Error Status Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x6 6. "DATA_ENDBIT,Data End Bit Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 5. "DATA_CRC,Data CRC Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 4. "DATA_TIMEOUT,Data Timeout Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x6 3. "CMD_INDEX,Command Index Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 2. "CMD_ENDBIT,Command End Bit Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x6 1. "CMD_CRC,Command CRC Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x6 0. "CMD_TIMEOUT,Command Timeout Error Status Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" line.word 0x8 "MMCSD1_NORMAL_INTR_SIG_ENA,Normal Interrupt Signal Enable Register This register is used to select which interrupt status is indicated to the Host System as the Interrupt. These status bits all share the sample 1 bit interrupt line. Setting any of these.." rbitfld.word 0x8 15. "BIT15_FIXED0,Fixed to 0 The HD shall control error Interrupts using the" "0,1" bitfld.word 0x8 14. "BOOT_COMPLETE,Boot Terminate Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 13. "RCV_BOOT_ACK,Boot Acknowledge Receive Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 12. "RETUNING_EVENT,Re-Tuning Event Signal Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 11. "INTC,INT_C Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 10. "INTB,INT_B Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 9. "INTA,INT_A Signal Enable (Embedded) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 8. "CARD_INTERRUPT,Card Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 7. "CARD_REMOVAL,Card Removal Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 6. "CARD_INSERTION,Card Insertion Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 5. "BUF_RD_READY,Buffer Read Ready Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 4. "BUF_WR_READY,Buffer Write Ready Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 3. "DMA_INTERRUPT,DMA Interrupt Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 2. "BLK_GAP_EVENT,Block Gap Event Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0x8 1. "XFER_COMPLETE,Transfer Complete Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0x8 0. "CMD_COMPLETE,Command Complete Signal Enable 0h: Masked 1h: Enabled" "0,1" line.word 0xA "MMCSD1_ERROR_INTR_SIG_ENA,Error Interrupt Signal Enable Register This register is used to select which interrupt status is notified to the Host System as the Interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits.." hexmask.word.byte 0xA 12.--15. 1. "VENDOR_SPECIFIC,Vendor Specific Error Signal Enable N/A" bitfld.word 0xA 11. "RESP,Response Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 10. "TUNING,Tuning Error Signal Enable (UHS-I Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0xA 9. "ADMA,ADMA Error Signal Enable 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 8. "AUTO_CMD,Auto CMD Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 7. "CURR_LIMIT,Current Limit Error Signal Enable 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0xA 6. "DATA_ENDBIT,Data End Bit Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 5. "DATA_CRC,Data CRC Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 4. "DATA_TIMEOUT,Data Timeout Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0xA 3. "CMD_INDEX,Command Index Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 2. "CMD_ENDBIT,Command End Bit Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" bitfld.word 0xA 1. "CMD_CRC,Command CRC Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" newline bitfld.word 0xA 0. "CMD_TIMEOUT,Command Timeout Error Signal Enable (SD Mode Only) 0h: Masked 1h: Enabled" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "MMCSD1_AUTOCMD_ERR_STS,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12/CMD23 errors occur by this register. Auto CMD23 errors are indicated.." hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 7. "CMD_NOT_ISSUED,Command Not Issued By Auto CMD12 Error Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register. This bit is set to 0h when Auto CMD Error is generated by Auto CMD23. 0h: No Error 1h:.." "0,1" bitfld.word 0x0 5.--6. "RESERVED,Reserved" "0,1,2,3" newline bitfld.word 0x0 4. "INDEX,Auto CMD Index Error Occurs if the Command Index error occurs in response to a command. 0h: No Error 1h: Error" "0,1" bitfld.word 0x0 3. "ENDBIT,Auto CMD End Bit Error Occurs when detecting that the end bit of command response is 0h. 0h: No Error 1h: End Bit Error Generated" "0,1" bitfld.word 0x0 2. "CRC,Auto CMD CRC Error Occurs when detecting a CRC error in the command response. 0h: No Error 1h: CRC Error Generated" "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Auto CMD Timeout Error Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1h the other error status bits (D04 - D02) are meaningless. 0h: No Error 1h: Timeout" "0,1" bitfld.word 0x0 0. "ACMD12_NOT_EXEC,Auto CMD12 not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1h means the HC cannot issue Auto CMD12 to stop.." "0,1" group.word 0x3E++0x1 line.word 0x0 "MMCSD1_HOST_CONTROL2,This register is used to program UHS Mode Select. Driver Strength Select. Execute Tuning. Sampling Clock Select. Asynchronous Interrupt Enable and Preset Value Enable." bitfld.word 0x0 15. "PRESET_VALUE_ENA,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host.." "0,1" bitfld.word 0x0 14. "ASYNCH_INTR_ENA,Asynchronous Interrupt Enable This bit can be set to 1h if a card support asynchronous interrupt and the 0h: Disabled 1h: Enabled" "0,1" bitfld.word 0x0 13. "BIT64_ADDRESSING,64-bit Addressing This field is effective when the Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host system. Host Driver sets.." "0,1" newline bitfld.word 0x0 12. "HOST_VER40_ENA,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4.00 mode. In Version 4.00 support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver.." "0,1" bitfld.word 0x0 11. "CMD23_ENA,CMD23 Enable In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 (SCR[33] = 1h) this bit is set to 1h. This bit is used to select Auto CMD23 or Auto.." "0,1" bitfld.word 0x0 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit. 0h: 16-bit Data Length Mode 1h: 26-bit Data Length Mode" "0,1" newline bitfld.word 0x0 9. "DRIVER_STRENGTH2,Driver Strength Select This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value." "0,1" bitfld.word 0x0 8. "UHS2_INTF_ENABLE,UHS-II Interface Enable This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization this bit shall be set to 1h. Before trying to start SD mode initialization this bit shall be set to 0h. This bit is used.." "0,1" bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,Sampling Clock Select (UHS-I Only) This bit is set by tuning procedure when the 0h: Fixed clock is used to sample data 1h: Tuned clock is used to sample data" "0,1" newline bitfld.word 0x0 6. "EXECUTE_TUNING,Execute Tuning (UHS-I Only) This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to the 0h: Not Tuned or Tuning Completed 1h: Execute Tuning" "0,1" bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Driver Strength Select (UHS-I Only) Host Controller output driver in 1.8 V signaling is selected by this bit. In 3.3 V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the If.." "0,1,2,3" bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,1.8 V Signaling Enable (UHS-I Only) This bit controls voltage regulator for I/O cell. 3.3 V is supplied to the card regardless of signaling voltage. Setting this bit from 0h to 1h starts changing signal voltage from 3.3 V to 1.8 V. 1.8 V.." "0,1" newline bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,UHS Mode Select (UHS-I Only) This field is used to select one of UHS-I modes or UHS-II mode. In case of UHS-I mode this field is effective when the If the 0h: SDR12 1h: SDR25 2h: SDR50 3h: SDR104 4h: DDR50 5h: HS400 6h: Reserved 7h:.." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0xF line.quad 0x0 "MMCSD1_CAPABILITIES,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initialization." bitfld.quad 0x0 63. "HS400_SUPPORT,HS400 Support 0h: HS400 is Not Supported 1h: HS400 is Supported" "0,1" bitfld.quad 0x0 61.--62. "RESERVED,Reserved" "0,1,2,3" bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,1.8 V VDD2 Support This bit indicates that support of VDD2 on Host system. 0h: 1.8 V VDD2 is not supported 1h: 1.8 V VDD2 is supported" "0,1" newline bitfld.quad 0x0 59. "ADMA3_SUPPORT,ADMA3 Support This bit indicates that support of ADMA3 on Host Controller. 0h: ADMA3 is not supported 1h: ADMA3 is supported" "0,1" bitfld.quad 0x0 58. "RESERVED,Reserved" "0,1" bitfld.quad 0x0 57. "SPI_BLK_MODE,SPI Block Mode This bit indicates whether SPI Block Mode is supported or not. 0h: Not Supported 1h: Supported" "0,1" newline bitfld.quad 0x0 56. "SPI_SUPPORT,SPI Mode This bit indicates whether SPI Mode is supported or not. 0h: Not Supported 1h: Supported" "0,1" hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to the FFh: Clock Multiplier M = 256 ---- 02h: Clock Multiplier M = 3 01h: Clock Multiplier M = 2 00h: Clock Multiplier is Not Supported" bitfld.quad 0x0 46.--47. "RETUNING_MODES,Re-tuning Modes (UHS-I Only) This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. 0h: Mode 1 1h: Mode 2 2h: Mode 3 3h: Reserved There are two.." "0,1,2,3" newline bitfld.quad 0x0 45. "TUNING_FOR_SDR50,Use Tuning for SDR50 (UHS-I Only) If this bit is set to 1h this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104). 0h: SDR50 does not require tuning 1h: SDR50 requires tuning" "0,1" bitfld.quad 0x0 44. "RESERVED,Reserved" "0,1" hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,Timer Count for Re-Tuning (UHS-I Only) This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ---- n = 2.." newline bitfld.quad 0x0 39. "RESERVED,Reserved" "0,1" bitfld.quad 0x0 38. "DRIVERD_SUPPORT,Driver Type D Support (UHS-I Only) This bit indicates support of Driver Type D for 1.8 Signaling. 0h: Driver Type D is Not Supported 1h: Driver Type D is Supported" "0,1" bitfld.quad 0x0 37. "DRIVERC_SUPPORT,Driver Type C Support (UHS-I Only) This bit indicates support of Driver Type C for 1.8 Signaling. 0h: Driver Type C is Not Supported 1h: Driver Type C is Supported" "0,1" newline bitfld.quad 0x0 36. "DRIVERA_SUPPORT,Driver Type A Support (UHS-I Only) This bit indicates support of Driver Type A for 1.8 Signaling. 0h: Driver Type A is Not Supported 1h: Driver Type A is Supported" "0,1" bitfld.quad 0x0 35. "UHS2_SUPPORT,UHS-II Support (UHS-II Only) This bit indicates whether Host Controller supports UHS-II. If this bit is set to 1h the 0h: UHS-II is Not Supported 1h: UHS-II is Supported" "0,1" bitfld.quad 0x0 34. "DDR50_SUPPORT,DDR50 Support (UHS-I Only) This bit indicates whether DDR50 is supported or not. 0h: DDR50 is Not Supported 1h: DDR50 is Supported" "0,1" newline bitfld.quad 0x0 33. "SDR104_SUPPORT,SDR104 Support (UHS-I Only) This bit indicates whether SDR104 is supported or not. SDR104 requires tuning. 0h: SDR104 is Not Supported 1h: SDR104 is Supported" "0,1" bitfld.quad 0x0 32. "SDR50_SUPPORT,SDR50 Support (UHS-I Only) If SDR104 is supported this bit shall be set to 1h. Bit 40 indicates whether SDR50 requires tuning or not. 0h: SDR50 is Not Supported 1h: SDR50 is Supported" "0,1" bitfld.quad 0x0 30.--31. "SLOT_TYPE,Slot Type This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot). Embedded slot for one device (1h) means that only one non-removable device is connected to a SD bus slot. Shared Bus.." "0,1,2,3" newline bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Asynchronous Interrupt Support (SD Mode Only) Refer to SDIO Specification Version 3.00 about asynchronous interrupt. 0h: Asynchronous Interrupt Not Supported 1h: Asynchronous Interrupt Supported" "0,1" bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,64-bit System Address Support for V3 Meaning of this bit is different depends on Versions. Host Controller Version 3.00 and Version 4.10 use this bit as 64-bit System Address support for V3 mode. Host Controller Version 4.00 uses.." "0,1" bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,64-bit System Address Support for V4 This bit is added from Version 4.10. Setting 1h to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode. When this bit is set to 1h full or a part of.." "0,1" newline bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,Voltage Support 1.8 V This bit indicates whether the HC supports 1.8 V. 0h: 1.8 V Not Supported 1h: 1.8 V Supported" "0,1" bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,Voltage Support 3.0 V This bit indicates whether the HC supports 3.0 V. 0h: 3.0 V Not Supported 1h: 3.0 V Supported" "0,1" bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,Voltage Support 3.3 V This bit indicates whether the HC supports 3.3 V. 0h: 3.3 V Not Supported 1h: 3.3 V Supported" "0,1" newline bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,Suspend/Resume Support This bit indicates whether the HC supports Suspend/Resume functionality. If this bit is 0h the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend/Resume commands. 0h: Not.." "0,1" bitfld.quad 0x0 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. Version 4.10 Host Controller shall support SDMA if ADMA2 is supported. 0h: SDMA Not Supported 1h: SDMA Supported" "0,1" bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC). 0h: High Speed Not Supported 1h: High.." "0,1" newline bitfld.quad 0x0 20. "RESERVED,Reserved" "0,1" bitfld.quad 0x0 19. "ADMA2_SUPPORT,ADMA2 Support 0h: ADMA2 Not support 1h: ADMA2 support" "0,1" bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,8-bit Support for Embedded Device (Embedded) This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when the 0h: 8-bit Bus Width Not Supported 1h: 8-bit Bus Width Supported" "0,1" newline bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,Max Block Length This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below. 0h: 512 byte.." "0,1,2,3" hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,Base Clock Frequency for SD Clock (1) 6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1 MHz. The supported clock range is 10 MHz to.." bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data Timeout Error ( 0h: KHz 1h: MHz" "0,1" newline bitfld.quad 0x0 6. "RESERVED,Reserved" "0,1" hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error ( 0h: Get Information via another method Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz" line.quad 0x8 "MMCSD1_MAX_CURRENT_CAP,This register indicates maximum current capability for each voltage." hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8 V VDD2" hexmask.quad.byte 0x8 24.--31. 1. "RESERVED,Reserved" newline hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8 V VDD1" hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0 V VDD1" hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3 V VDD1" group.word 0x50++0x1 line.word 0x0 "MMCSD1_FORCE_EVNT_ACMD_ERR_STS,This register is not physically implemented. rather it is an address where the register can be written. Writing 1h: set each bit of the register Writing 0h: no effect By setting a bit in this register. the correspondent bit.." hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error 0h: Not Affected 1h: Command Not Issued By Auto CMD12 Error Status is set" "0,1" rbitfld.word 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error 0h: Not Affected 1h: Auto CMD Response Error Status is set" "0,1" bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error 0h: Not Affected 1h: Auto CMD Index Error Status is set" "0,1" bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error 0h: Not Affected 1h: Auto CMD End bit Error Status is set" "0,1" newline bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error 0h: Not Affected 1h: Auto CMD CRC Error Status is set" "0,1" bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error 0h: Not Affected 1h: Auto CMD Timeout Error Status is set" "0,1" bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed 0h: Not Affected 1h: Auto CMD12 Not Executed Status is set" "0,1" wgroup.word 0x52++0x1 line.word 0x0 "MMCSD1_FORCE_EVNT_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written. The register is not a physically implemented register. Rather. it is an address at which the register can be written." hexmask.word.byte 0x0 12.--15. 1. "VEND_SPEC,N/A" bitfld.word 0x0 11. "RESP,Force Event for Response Error 0h: Not Affected 1h: Response Error Status is set" "0,1" bitfld.word 0x0 10. "TUNING,Force Event for Tuning Error 0h: Not Affected 1h: Tuning Error Status is set" "0,1" newline bitfld.word 0x0 9. "ADMA,Force Event for ADMA Error 0h: Not Affected 1h: ADMA Error Status is set" "0,1" bitfld.word 0x0 8. "AUTO_CMD,Force Event for Auto CMD Error 0h: Not Affected 1h: Auto CMD Error Status is set" "0,1" bitfld.word 0x0 7. "CURR_LIM,Force Event for Current Limit Error 0h: Not Affected 1h: Current Limit Error Status is set" "0,1" newline bitfld.word 0x0 6. "DAT_ENDBIT,Force Event for Data End Bit Error 0h: Not Affected 1h: Data End Bit Error Status is set" "0,1" bitfld.word 0x0 5. "DAT_CRC,Force Event for Data CRC Error 0h: Not Affected 1h: CRC Error Status is set" "0,1" bitfld.word 0x0 4. "DAT_TIMEOUT,Force Event for Data Timeout Error 0h: Not Affected 1h: Timeout Error Status is set" "0,1" newline bitfld.word 0x0 3. "CMD_INDEX,Force Event for Command Index Error 0h: Not Affected 1h: Command Index Error Status is set" "0,1" bitfld.word 0x0 2. "CMD_ENDBIT,Force Event for Command End Bit Error 0h: Not Affected 1h: Command End Bit Error Status is set" "0,1" bitfld.word 0x0 1. "CMD_CRC,Force Event for Command CRC Error 0h: Not Affected 1h: Command CRC Error Status is set" "0,1" newline bitfld.word 0x0 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error 0h: Not Affected 1h: Command Timeout Error Status is set" "0,1" rgroup.byte 0x54++0x0 line.byte 0x0 "MMCSD1_ADMA_ERR_STATUS,When the ADMA Error interrupt occur. this register holds the ADMA State ([1-0] ADMA_ERR_STATE) and the register holds address around the error descriptor." hexmask.byte 0x0 3.--7. 1. "RESERVED,Reserved" bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,ADMA Length Mismatch Error This error occurs in the following 2 cases. While the 0h: No Error 1h: Error" "0,1" bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates '2h' because ADMA never stops in this state. D01 - D00: ADMA Error State when error occurred Contents of.." "0,1,2,3" group.quad 0x58++0x7 line.quad 0x0 "MMCSD1_ADMA_SYS_ADDRESS,This register contains the physical address used for ADMA data transfer." hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,ADMA System Address The 32-bit addressing Host Driver uses lower 32-bit of this register (upper 32-bit should be set to 0h) and shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. DMA2/3 ignores.." rgroup.word 0x60++0xF line.word 0x0 "MMCSD1_PRESET_VALUE0,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value. When the [15] PRESET_VALUE_ENA bit is set to 1h. SDCLK/RCLK Frequency Select and Clock Generator Select in.." bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x0 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x0 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x2 "MMCSD1_PRESET_VALUE1,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x2 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x4 "MMCSD1_PRESET_VALUE2,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x4 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x4 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x6 "MMCSD1_PRESET_VALUE3,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x6 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x6 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x8 "MMCSD1_PRESET_VALUE4,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x8 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x8 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0xA "MMCSD1_PRESET_VALUE5,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0xA 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0xA 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0xC "MMCSD1_PRESET_VALUE6,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0xC 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0xC 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0xE "MMCSD1_PRESET_VALUE7,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0xE 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0xE 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" rgroup.word 0x72++0x3 line.word 0x0 "MMCSD1_PRESET_VALUE8,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x0 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x0 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" line.word 0x2 "MMCSD1_PRESET_VALUE10,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value." bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling. 0h: Driver Type D is Selected 1h: Driver Type C is Selected 2h: Driver Type A is.." "0,1,2,3" bitfld.word 0x2 11.--13. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.word 0x2 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0h: Host Controller Version 2.00 Compatible Clock Generator 1h: Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set the" group.quad 0x78++0x7 line.quad 0x0 "MMCSD1_ADMA3_DESC_ADDRESS,The start address of Integrated DMA Descriptor is set to this register." hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,ADMA3 Integrated Descriptor Address The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and.." group.word 0x80++0x1 line.word 0x0 "MMCSD1_UHS2_BLOCK_SIZE,This register is used to configure the number of bytes in a data block." rbitfld.word 0x0 15. "RESERVED,Reserved" "0,1" bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,UHS-II SDMA Buffer Boundary (SDMA only) When system memory is managed by paging SDMA data transfer is performed in unit of paging. A page size of system memory management is set to this field. Host Controller generates the DMA.." "0,1,2,3,4,5,6,7" hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,UHS-II Block Size This bit field specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Variable block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes." group.long 0x84++0x3 line.long 0x0 "MMCSD1_UHS2_BLOCK_COUNT,This register is used to configure the number of data blocks." hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,UHS-II Block Count This register is effective when the This register should be accessed only when no transaction is executing (after transactions are stopped). During data transfer read operations on this register may return an invalid.." group.byte 0x88++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_0,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x8C++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_1,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x90++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_2,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x94++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_3,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x98++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_4,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0x9C++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_5,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.word 0x9C++0x3 line.word 0x0 "MMCSD1_UHS2_XFER_MODE,This register is used to control the operations of data transfers. On issuing a Command Packet. a Command Packet image is set to UHS-II Command Packet register (see - ) but Host Controller does not analyze the setting of UHS-II.." bitfld.word 0x0 15. "DUPLEX_SELECT,Half/Full Select Use of 2 lane half duplex mode is determined by Host Driver. 0h: Full Duplex Mode 1h: 2 Lane Half Duplex Mode" "0,1" bitfld.word 0x0 14. "EBSY_WAIT,EBSY Wait This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer. If this bit is set to 1h Host Controller waits.." "0,1" hexmask.word.byte 0x0 9.--13. 1. "RESERVED,Reserved" newline bitfld.word 0x0 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0h.." "0,1" bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error this bit is set.." "0,1" bitfld.word 0x0 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1: Response Flags Checked in R5:.." "0,1" newline bitfld.word 0x0 5. "BYTE_MODE,Block/Byte Mode This bit specifies whether data transfer is in byte mode or block mode when the 0h: Block Mode 1h: Byte Mode" "0,1" bitfld.word 0x0 4. "DATA_XFER_DIR,Data Transfer Direction This bit specifies direction of data transfer when the 0h: Read (Card to Host) 1h: Write (Host to Card)" "0,1" rbitfld.word 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.word 0x0 1. "BLK_CNT_ENA,Block Count Enable This bit specifies whether data transfer uses the 0h: Block Count Disabled 1h: Block Count Enabled" "0,1" bitfld.word 0x0 0. "DMA_ENA,DMA Enable This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by the 0h: DMA is disabled 1h: DMA is enabled" "0,1" line.word 0x2 "MMCSD1_UHS2_COMMAND,This register is used to program the Command for host controller." rbitfld.word 0x2 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,UHS-II Command Packet Length A command packet length which is set in the UHS-II Command Packet register ( 00011b – 00000b: 3-0 Bytes (Not used) 00100b: 4 Bytes .... .... 10100b: 20 Bytes 11111b – 10101b" bitfld.word 0x2 6.--7. "CMD_TYPE,Command Type This field is used to distinguish a specific command like abort command. If this field is set to 0h the UHS-II RES Packet is stored in UHS-II Response register ( 0h: Normal Command 1h: TRANS_ABORT CCMD 2h: CMD12 or SDIO Abort.." "0,1,2,3" newline bitfld.word 0x2 5. "DATA_PRESENT,Data Present This bit specifies whether the command is accompanied by data packet. 0h: No Data Present 1h: Data Present" "0,1" rbitfld.word 0x2 3.--4. "RESERVED,Reserved" "0,1,2,3" bitfld.word 0x2 2. "SUB_COMMAND,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command this bit is set to 0h and when issuing a sub command this bit is set to 1h. Setting of this bit is checked by the.." "0,1" newline rbitfld.word 0x2 0.--1. "RESERVED,Reserved" "0,1,2,3" group.byte 0xA0++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_6,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xA0++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_0,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xA4++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_7,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xA4++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_1,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xA8++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_8,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xA8++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_2,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xAC++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_9,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xAC++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_3,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB0++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_10,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xB0++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_4,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB4++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_11,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.byte 0xB4++0x0 line.byte 0x0 "MMCSD1_UHS2_MESSAGE_SELECT,This register is used to access internal buffer." hexmask.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.byte 0x0 0.--1. "MSG_SEL,UHS-II MSG Select Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs can be read from the (assumed for debug usage). 0h: The latest MSG 1h: One MSG before 2h: Two MSGs before 3h: Three MSGs before" "0,1,2,3" rgroup.byte 0xB4++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_5,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB8++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_12,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.long 0xB8++0x3 line.long 0x0 "MMCSD1_UHS2_MESSAGE,This register is used to access internal buffer." hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the" hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the" hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the" rgroup.byte 0xB8++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_6,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xBC++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_13,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.word 0xBC++0x1 line.word 0x0 "MMCSD1_UHS2_DEVICE_INTR_STATUS,This register shows receipt of INT MSG from which device." hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,UHS-II Device Interrupt Status This register shows receipt of INT MSG from which device and is effective when the Writing a bit to 1h clears the status bit (interrupt is treated) and writing a bit to 0h keeps the status value (interrupt is.." rgroup.byte 0xBC++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_7,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xBE++0x0 line.byte 0x0 "MMCSD1_UHS2_DEVICE_SELECT,UHS-II Device Select Register." bitfld.byte 0x0 7. "INT_MSG_ENA,INT MSG Enable (Optional) This bit enables receipt of INT MSG. If this bit is set to 1h receipt of INT MSG is informed by the Support of INT MSG Interrupt is optional. If trying to set this bit to 1h but still this bit is read 0 INT MSG.." "0,1" rbitfld.byte 0x0 4.--6. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "DEV_SEL,UHS-II Device Select Host Controller holds an INT MSG packet per device. One of INT MSGs (up to 15) can be selected by this field and read from the The number of devices implemented in the Host Controller is indicated by the 0h: Unselected.." rgroup.byte 0xBF++0x0 line.byte 0x0 "MMCSD1_UHS2_DEVICE_INT_CODE,This register is effective when the [7] INT_MSG_ENA bit is set to 1h." hexmask.byte 0x0 0.--7. 1. "DEV_INTR,UHS II Device Interrupt This register is effective when the The number of the registers to hold INT MSGs is determined by the" group.byte 0xC0++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_14,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xC0++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_8,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.word 0xC0++0x3 line.word 0x0 "MMCSD1_UHS2_SOFTWARE_RESET,UHS-II Software Reset Register." hexmask.word 0x0 2.--15. 1. "RESERVED,Reserved" bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host SD-TRAN Reset Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completion of SD-TRAN reset. If CMD0 is issued SD-TRAN.." "0,1" bitfld.word 0x0 0. "HOST_FULL_RESET,Host Full Reset On issuing FULL_RESET CCMD Host Driver set this bit to 1h to reset Host Controller. This bit is cleared automatically at completion of Host Controller reset. Initialization sequence from PHY Initialization is required to.." "0,1" line.word 0x2 "MMCSD1_UHS2_TIMER_CONTROL,UHS-II Timeout Control Register." hexmask.word.byte 0x2 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,Timeout Counter Value for Deadlock This value determines the deadlock period while host expecting to receive a packet (1 second). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When.." hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,Timeout Counter Value for CMD_RES This value determines the interval between command packet and response packet (5 ms). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this.." group.byte 0xC4++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_15,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.long 0xC4++0x3 line.long 0x0 "MMCSD1_UHS2_ERR_INTR_STS,This register gives the status of all UHS-II interrupts." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor Specific Error Vendor may use this field for vendor specific error status. 0h: Interrupt is not generated 1h: Vendor Specific Error" hexmask.long.word 0x0 18.--26. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout (1 second). Timeout value is determined by the setting of the 0h: Interrupt is not.." "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout (5 ms). Timeout value is determined by the setting of the 0h: Interrupt is not.." "0,1" bitfld.long 0x0 15. "ADMA2_ADMA3,ADMA2/3 Error Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the 0h: Interrupt is not generated 1h: ADMA2/3 Error" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "EBSY,EBSY Error On receiving EBSY packet if the packet indicates an error this bit is set to 1h. Setting of this bit also sets Error Interrupt and Transfer Completer together in the 0h: Interrupt is not generated 1h: EBSY Error (Backend Error)" "0,1" bitfld.long 0x0 7. "UNRECOVERABLE,Unrecoverable Error Setting of this bit means that Unrecoverable Error is set in a packet from a device. 0h: Interrupt is not generated 1h: Device Unrecoverable Error" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 5. "TID,TID Error Setting of this bit means that TID Error occurs. 0h: Interrupt is not generated 1h: TID Error" "0,1" bitfld.long 0x0 4. "FRAMING,Framing Error Setting of this bit means that Framing Error occurs during a packet receiving. 0h: Interrupt is not generated 1h: Framing Error" "0,1" bitfld.long 0x0 3. "CRC,CRC Error Setting of this bit means that CRC Error occurs during a packet receiving. 0h: Interrupt is not generated 1h: CRC Error" "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Retry Expired Setting of this bit means that Retry Counter Expired Error occurs during data transfer. If this bit is set either Framing Error or CRC Error in this register shall be set. 0h: Interrupt is not generated 1h: Retry Expired Error" "0,1" bitfld.long 0x0 1. "RESP_PKT,RES Packet Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If the 0h: Interrupt is not generated 1h: RES Packet Error" "0,1" bitfld.long 0x0 0. "HEADER,Header Error Setting of this bit means that Header Error occurs in a received packet. 0h: Interrupt is not generated 1h: Header Error" "0,1" rgroup.byte 0xC4++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_9,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xC8++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_16,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.long 0xC8++0x3 line.long 0x0 "MMCSD1_UHS2_ERR_INTR_STS_ENA,This register is used to enable the register fields." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC,Vendor Specific Error Setting this bit to 1h enables setting of Vendor Specific Error bit in the 0h: Status is Disabled 1h: Status is Enabled" hexmask.long.word 0x0 18.--26. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables setting of Timeout for Dead lock bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables setting of Timeout for CMD_RES bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables setting of ADMA2/3 Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "EBSY,EBSY Error Setting this bit to 1h enables setting of EBSY Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables setting of Unrecoverable Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 5. "TID,TID Error Setting this bit to 1h enables setting of TID Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 4. "FRAMING,Framing Error Setting this bit to 1h enables setting of Framing Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 3. "CRC,CRC Error Setting this bit to 1h enables setting of CRC Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Retry Expired Setting this bit to 1h enables setting of Retry Expired bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables setting of RES Packet Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" bitfld.long 0x0 0. "HEADER,Header Error Setting this bit to 1h enables setting of Header Error bit in the 0h: Status is Disabled 1h: Status is Enabled" "0,1" rgroup.byte 0xC8++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_10,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xCC++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_17,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." group.long 0xCC++0x3 line.long 0x0 "MMCSD1_UHS2_ERR_INTR_SIG_ENA,This register is used to generate UHS-II Interrupt signals." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC,Vendor Specific Error Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" hexmask.long.word 0x0 18.--26. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "EBSY,EBSY Error Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 5. "TID,TID Error Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 4. "FRAMING,Framing Error Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 3. "CRC,CRC Error Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED_SIG_ENA,Retry Expired Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" bitfld.long 0x0 0. "HEADER,Header Error Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in the 0h: Interrupt Signal is Disabled 1h: Interrupt Signal is Enabled" "0,1" rgroup.byte 0xCC++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_11,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xD0++0x0 line.byte 0x0 "MMCSD1_UHS2_COMMAND_PKT_18,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see ). The command length varies depends on a Command Packet type. The length is specified by the register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,Command Packet Byte UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type." rgroup.byte 0xD0++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_12,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xD4++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_13,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xD8++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_14,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xDC++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_15,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.byte 0xE0++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_16,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.word 0xE0++0x3 line.word 0x0 "MMCSD1_UHS2_SETTINGS_PTR,This register is pointer for UHS-II settings." hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register" line.word 0x2 "MMCSD1_UHS2_CAPABILITIES_PTR,This register is pointer for UHS-II Capabilities Register." hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register" rgroup.byte 0xE4++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_17,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.word 0xE4++0x3 line.word 0x0 "MMCSD1_UHS2_TEST_PTR,This register is pointer for UHS-II Test Register." hexmask.word 0x0 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register" line.word 0x2 "MMCSD1_SHARED_BUS_CTRL_PTR,This register is pointer for UHS-II Shared Bus Control Register." hexmask.word 0x2 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register" rgroup.byte 0xE8++0x0 line.byte 0x0 "MMCSD1_UHS2_RESPONSE_18,This register is used to store received UHS-II RES Packet image. Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command. which is specified by setting 1h or 2h to the [7-6].." hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Response Packet Byte Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." rgroup.word 0xE8++0x1 line.word 0x0 "MMCSD1_VENDOR_SPECFIC_PTR,This register is pointer for UHS-II Vendor Specific Register." hexmask.word 0x0 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area" group.long 0xF4++0x7 line.long 0x0 "MMCSD1_BOOT_TIMEOUT_CONTROL,This is used to program the boot timeout value counter." hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,Boot Data Timeout Counter Value This value determines the interval by which DAT line timeouts are detected during boot operation for eMMC4.4 card. The value is in number of SD clock." line.long 0x4 "MMCSD1_VENDOR_REGISTER,Vendor register added for Auto Gate SD CLK. CMD11 Power Down Timer. Enhanced Strobe and eMMC Hardware Reset." hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "AUTOGATE_SDCLK,Auto Gate SD CLK If this bit is set SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device. 0h: Disable 1h: Enable" "0,1" hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,CMD11 Power Down Timer Value" newline bitfld.long 0x4 1. "EMMC_HW_RESET,eMMC Hardware Reset Hardware reset signal is generared for eMMC card when this bit is set. 0h: De-sassert hardware reset pin 1h: Drives the hardware reset pin as ZERO (Active LOW to eMMC card)" "0,1" bitfld.long 0x4 0. "ENHANCED_STROBE,Enhanced Strobe This bit enables the enhanced strobe logic of the Host Controller." "0,1" rgroup.word 0xFC++0x3 line.word 0x0 "MMCSD1_SLOT_INT_STS,This register is used to read the interrupt signal for each slot." hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved" hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,Interrupt Signal for Slot#0 These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot." line.word 0x2 "MMCSD1_HOST_CONTROLLER_VER,This register is used to read the vendor version number and specification version number." hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,Vendor Version Number The Vendor Version Number is set to 10h (1.0)" hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,Specification Version Number This status indicates the Host Controller Specification Version. The upper and lower 4-bits indicate the version. 0h: SD Host Controller Specification Version 1.00 1h: SD Host Controller Specification Version.." group.long 0x100++0x7 line.long 0x0 "MMCSD1_UHS2_GEN_SETTINGS,Start Address of General settings is pointed by the Register." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,Number of Lanes and Functionalities The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0h: 2 Lanes.." hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "POWER_MODE,Power Mode This field determines either Fast mode or Low Power mode. Host and all devices connected to the host shall be set to the same mode. 0h: Fast Mode 1h: Low Power Mode" "0,1" line.long 0x4 "MMCSD1_UHS2_PHY_SETTINGS,Start Address of PHY settings is pointed by the Register." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,Host N_LSS_DIR The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h: 8 x 16 LSS 1h: 8 x 1 LSS 2h: 8 x 2 LSS 3h: 8 x 3 LSS .... .... Fh: 8 x 15 LSS" hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,Host N_LSS_SYN The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h - 4 x 3 LSS .... .... Fh: 4 x 15 LSS" newline bitfld.long 0x4 15. "HIBERNATE_ENA,Hibernate Enable After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode VDD1.." "0,1" hexmask.long.byte 0x4 8.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 6.--7. "SPEED_RANGE,Speed Range PLL multiplier is selected by this field. Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. 0h: Range A (Defalt) 1h: Range B 2h: Reserved 3h: Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "RESERVED,Reserved" group.quad 0x108++0x7 line.quad 0x0 "MMCSD1_UHS2_LNK_TRN_SETTINGS,Start Address of LINK/TRAN settings is pointed by the Register." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,Host N_DATA_GAP The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h: No Gap 01h: 1 LSS 02h: 2 LSS 03h: 3 LSS .... .... FFh: 255 LSS" hexmask.quad.word 0x0 18.--31. 1. "RESERVED,Reserved" newline bitfld.quad 0x0 16.--17. "RETRY_COUNT,Retry Count Data Burst retry count is set to this field. 00h: Retry Disabled 01h: 1 time 02h: 2 times 03h: 3 times" "0,1,2,3" hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host N_FCU Host Driver sets the number of blocks in Data Burst (Flow Control) to this field. The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is.." hexmask.quad.byte 0x0 0.--7. 1. "RESERVED,Reserved" rgroup.long 0x110++0x7 line.long 0x0 "MMCSD1_UHS2_GEN_CAP,Start Address of General Capabilities is pointed by the Register." hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,Bus Topology This field indicates one of bus topologies configured by a Host system. 0h: P2P Connection 1h: Ring Connection 2h: HUB Connection 3h: HUB is Connected in Ring" "0,1,2,3" hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,Number of Devices Supported This field indicates the maximum number of devices supported by the Host Controller. 0h: Not used 1h: 1 Devices 2h: 2 Devices .... .... Fh: 15 Devices" newline bitfld.long 0x0 16.--17. "DEVICE_TYPE,Removable/Embedded This field indicates device type configured by a Host system. 0h: Removable Card (P2P) 1h: Embedded Devices 2h: Embedded Devices + Removable Card 3h: Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESERVED,Reserved" "0,1" bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,64-bit Addressing This field indicates support of 64-bit addressing by the Host Controller. 0h: 32-bit Addressing is supported 1h: 32-bit and 64-bit Addressing is supported" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,Number of Lanes and Functionalities This field indicates support of lanes by the Host Controller. 0 mean not supported and 1 means supported. D08: 2L-HD D09: 2D1U-FD D10: 1D2U-FD D11: 2D2U-FD D12: Reserved D13: Reserved" hexmask.long.byte 0x0 4.--7. 1. "GAP,GAP (Group Allocation Power) This field indicates the maximum capability of host power supply for a group configured by a Host system. This field is used to set the argument of DEVICE_INIT CCM. 0h: Not used 1h: 360 mW 2h: 720 mW .... .... Fh: 360 x.." hexmask.long.byte 0x0 0.--3. 1. "DAP,DAP (Device Allocation Power) This field indicates the maximum capability of host power supply for a device configured by a Host system. This field is used to set the argument of DEVICE_INIT CCMD. 0h: 360 mW (Default) 1h: 360 mW 2h: 720 mW .... ...." line.long 0x4 "MMCSD1_UHS2_PHY_CAP,Start Address of PHY Capabilities is pointed by the Register." hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,Host N_LSS_DIR This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h: 4 x 3 LSS .... .... Fh: 4 x 15 LSS" hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,Host N_LSS_SYN This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h: 4 x 16 LSS 1h: 4 x 1 LSS 2h: 4 x 2 LSS 3h: 4 x 3 LSS .... .... Fh: 4 x 15 LSS" newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 6.--7. "SPEED_RANGE,Speed Range This field indicates supported Speed Range by the Host Controller. 0h: Range A (Default) 1h: Range A and Range B 2h: Reserved 3h: Reserved" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "RESERVED,Reserved" rgroup.quad 0x118++0x7 line.quad 0x0 "MMCSD1_UHS2_LNK_TRN_CAP,Start Address of LINK/TRAN settings is pointed by the Register." hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,Host N_DATA_GAP This field indicates the minimum number of data gap (DIDL) supported by the Host Controller. 00h: No Gap 01h: 1 LSS 02h: 2 LSS 03h: 3 LSS .... .... FFh: 255 LSS" hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,Host Maximum Block Length This field indicates maximum block length by the Host Controller. 000h: Not Used 001h: 1 byte 002h: 2 bytes .... .... 200h: 512 bytes .... .... 800h: 2048 bytes 801h - FFFh: Not Used" newline hexmask.quad.byte 0x0 16.--19. 1. "RESERVED,Reserved" hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,Host N_FCU This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller. This value is determined by supported buffer size. 00h: 256 Blocks 01h: 1 Block 02h: 2 Block 03h: 3 Block .... .... FFh: 255 Blocks" hexmask.quad.byte 0x0 0.--7. 1. "RESERVED,Reserved" group.long 0x120++0x3 line.long 0x0 "MMCSD1_FORCE_UHSII_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h: Not Affected 1h: Vendor Specific Error Status is set" hexmask.long.word 0x0 18.--26. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Force Event for Timeout for Deadlock Setting this bit forces the Host Controller to set Timeout for Deadlock in the 0h: Not affected 1h: Timeout for Deadlock Error status is set" "0,1" newline bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Force Event for Timeout for CMD_RES Setting this bit forces the Host Controller to set Timeout for CMD_RES in the 0h: Not affected 1h: Timout for CMD_RES Status is set" "0,1" bitfld.long 0x0 15. "ADMA,Force Event for ADMA Error Setting this bit forces the Host Controller to set ADMA Error in the 0h: Not affected 1h: ADMA Error Status is set" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "EBSY,Force Event for EBSY Error Setting this bit forces the Host Controller to set EBSY Error in the 0h: Not affected 1h: EBSY Error Status is set" "0,1" bitfld.long 0x0 7. "UNRECOVERABLE,Force Event for Unrecoverable Error Setting this bit forces the Host Controller to set Unrecoverable Error in the 0h: Not affected 1h: Unrecoverable Error Status is set" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 5. "TID,Force Event for TID Error Setting this bit forces the Host Controller to set TID Error in the 0h: Not affected 1h: TID Error Status is set" "0,1" bitfld.long 0x0 4. "FRAMING,Force Event for Framing Error Setting this bit forces the Host Controller to set Framing Error in the 0h: Not affected 1h: Framing Error Status is set" "0,1" bitfld.long 0x0 3. "CRC,Force Event for CRC Error Setting this bit forces the Host Controller to set CRC Error in the 0h: Not affected 1h: CRC Error Status is set" "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Force Event for Retry Expired Setting this bit forces the Host Controller to set Retry Expired in the 0h: Not affected 1h: Retry expired error status is set" "0,1" bitfld.long 0x0 1. "RES_PKT,Force Event for RES Packet Error Setting this bit forces the Host Controller to set RES Packet Error in the 0h: Not affected 1h: RES packet error status is set" "0,1" bitfld.long 0x0 0. "HEADER,Force Event for Header Error Setting this bit forces the Host Controller to set Header Error in the 0h: Not affected 1h: Header error status is set" "0,1" rgroup.long 0x200++0x7 line.long 0x0 "MMCSD1_CQ_VERSION,This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1. The following table describes the CQBASE+00h: Command.." hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number (digit left of decimal point) in BCD format" hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number (digit right of decimal point) in BCD format" newline hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix (2nd digit right of decimal point) in BCD format" line.long 0x4 "MMCSD1_CQ_CAPABILITIES,This register is reserved for capability indication." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details ( Field Value Description: 0h: 0.001 MHz 1h: 0.01 MHz 2h: 0.1 MHz 3h: 1 MHz.." bitfld.long 0x4 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0x4 0.--9. 1. "CF_VAL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling. The clock frequency is calculated as ITCFVAL × ITCFMUL. For.." group.long 0x208++0x27 line.long 0x0 "MMCSD1_CQ_CONFIG,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 12. "DCMD_ENA,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot #31 to determine how to decode the.." "0,1" rbitfld.long 0x0 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "TASK_DESC_SIZE,This bit indicates whether the task descriptor size is 128 bits or 64 bits. This bit can only be configured when the Bit Value Description 0h: Task descriptor size is 64 bits 1h: Task descriptor size is 128 bits" "0,1" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CQ_ENABLE,Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE). When this bit is 0h CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller. Before software writes 1h to this.." "0,1" line.long 0x4 "MMCSD1_CQ_CONTROL,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Software shall write 1h to this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state (Halt bit is 1h). When software writes 1h the value of the register is updated to 1h and.." "0,1" hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "HALT_BIT,Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example issuing a Discard Task command (CMDQ_TASK_MGMT). When software writes 1h CQE.." "0,1" line.long 0x8 "MMCSD1_CQ_INTR_STS,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in the register." hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 4. "TASK_ERROR,This bit is asserted when task error is detected due to invalid task descriptor." "0,1" bitfld.long 0x8 3. "TASK_CLEARED,This status bit is asserted (if" "0,1" newline bitfld.long 0x8 2. "RESP_ERR_DET,This status bit is asserted (if Software uses the" "0,1" bitfld.long 0x8 1. "TASK_COMPLETE,This status bit is asserted (if (1) A task is completed and the INT bit is set in its Task Descriptor (2) Interrupt caused by Interrupt Coalescing logic" "0,1" bitfld.long 0x8 0. "HALT_COMPLETE,This status bit is asserted (if" "0,1" line.long 0xC "MMCSD1_CQ_INTR_STS_ENA,This register enables and disables the reporting of the corresponding interrupt to host software in 299 register. When a bit is set (1h) and the corresponding interrupt condition is active. then the 300 bit in the register is.." hexmask.long 0xC 5.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 4. "TASK_ERROR,1h: 0h:" "0,1" bitfld.long 0xC 3. "TASK_CLEARED,1h: 0h:" "0,1" newline bitfld.long 0xC 2. "RESP_ERR_DET,1h: 0h:" "0,1" bitfld.long 0xC 1. "TASK_COMPLETE,1h: 0h:" "0,1" bitfld.long 0xC 0. "HALT_COMPLETE,1h: 0h:" "0,1" line.long 0x10 "MMCSD1_CQ_INTR_SIG_ENA,This register enables and disables the generation of interrupts to host software. When a bit is set 304 (1h) and the corresponding bit in the register is set. then an interrupt is generated. Interrupt sources 305 that are disabled.." hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 4. "TASK_ERROR,When set and the" "0,1" bitfld.long 0x10 3. "TASK_CLEARED,When set and the" "0,1" newline bitfld.long 0x10 2. "RESP_ERR_DET,When set and the" "0,1" bitfld.long 0x10 1. "TASK_COMPLETE,When set and the" "0,1" bitfld.long 0x10 0. "HALT_COMPLETE,When set and the" "0,1" line.long 0x14 "MMCSD1_CQ_INTR_COALESCING,This register controls the interrupt coalescing feature." bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0h by software command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT = 1 in the Task Descriptor. When set to 1h the interrupt coalescing mechanism is enabled and.." "0,1" hexmask.long.word 0x14 21.--30. 1. "RESERVED,Reserved" rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter &gt; 0). Bit Value Description 0h: No task completions have occurred since last.." "0,1" newline hexmask.long.byte 0x14 13.--19. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt. Counter Operation: As data transfer tasks with INT = 0 complete .." rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by software during the interrupt service routine. It starts.." line.long 0x18 "MMCSD1_CQ_TDL_BASE_ADDR,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,This register stores the LSB bits (bits 31-0) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 × (Task Descriptor size + Transfer Descriptor size) as configured by Host.." line.long 0x1C "MMCSD1_CQ_TDL_BASE_ADDR_UPBITS,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,This register stores the MSB bits (bits 63-32) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 × (Task Descriptor size + Transfer Descriptor size) as configured by Host.." line.long 0x20 "MMCSD1_CQ_TASK_DOOR_BELL,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Software shall configure the Writing 1h to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. CQE always processes tasks in-order according to the order submitted to the list by the CQE processes Data.." line.long 0x24 "MMCSD1_CQ_TASK_COMP_NOTIF,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register (at the same time it clears bit n of the When receiving interrupt for task completion software may read this register to know which tasks have finished. After reading this register software may clear the.." rgroup.long 0x230++0x7 line.long 0x0 "MMCSD1_CQ_DEV_QUEUE_STATUS,This register stores the most recent value of the device's queue status." hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register (QSR) from the device it updates this register with the response of status command (the device's queue status)." line.long 0x4 "MMCSD1_CQ_DEV_PENDING_TASKS,This register indicates to software which tasks are queued in the device. awaiting execution." hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task hasnt been executed yet. CQE shall set this bit after receiving a successful response for.." group.long 0x238++0x3 line.long 0x0 "MMCSD1_CQ_TASK_CLEAR,This register is used for removing an outstanding task in the CQE 327. The register should be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1h to bit n of this register orders CQE to clear a task which software has previously issued. This bit can only be written when CQE is in Halt state as indicated in the When software writes 1h to a bit in this register CQE updates the.." group.long 0x240++0x7 line.long 0x0 "MMCSD1_CQ_SEND_STS_CONFIG1,The register controls when the SEND_QUEUE_STATUS commands are sent." hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue. A value of n means CQE shall send status command on the CMD line during the transfer of data block A value of 0h.." hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling. Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "MMCSD1_CQ_SEND_STS_CONFIG2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. CQE shall copy this field to bits 31-16 of the argument when transmitting SEND_QUEUE_STATUS (CMD13) command." rgroup.long 0x248++0x3 line.long 0x0 "MMCSD1_CQ_DCMD_RESPONSE,This register is used for passing the response of a DCMD task to software." hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct command (DCMD) task which was sent. CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit.." rgroup.long 0x250++0x13 line.long 0x0 "MMCSD1_CQ_RESP_ERR_MASK,This register controls the generation of Response Error Detection (RED) interrupt." hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status field which is received in R1/R1b responses. Bit Value Description (for any bit i): 1h: When a R1/R1b response is received with bit i in the device status set a RED interrupt is.." line.long 0x4 "MMCSD1_CQ_TASK_ERR_INFO,This register is updated by CQE when an error occurs on data or command related to a task activity. When such error is detected by CQE or indicated by the eMMC controller CQE stores in the register the task IDs and the command.." bitfld.long 0x4 31. "DATERR_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated the bit is set to 1h. If a no data transfer is in progress when the error is.." "0,1" bitfld.long 0x4 29.--30. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 24.--28. 1. "DATERR_TASK_ID,This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE or indicated by eMMC controller." newline bitfld.long 0x4 22.--23. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 16.--21. 1. "DATERR_CMD_INDEX,This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK (CMD46) or EXECUTE_WRITE_TASK (CMD47) according to the data direction. The field is.." bitfld.long 0x4 15. "RESP_MODE_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated the bit is set to 1h. If a no command transaction is in progress when the.." "0,1" newline bitfld.long 0x4 13.--14. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 8.--12. 1. "RESP_MODE_TASK_ID,This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE or indicated by eMMC controller." bitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "RESP_MODE_CMD_INDEX,This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE or indicated by eMMC controller." line.long 0x8 "MMCSD1_CQ_CMD_RESP_INDEX,This register stores the index of the last received command response." hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a command response is received." line.long 0xC "MMCSD1_CQ_CMD_RESP_ARG,This register stores the index of the last received command response." hexmask.long 0xC 0.--31. 1. "LAST_CRA,This field stores the argument of the last received command. CQE shall update the value every time a command response is received." line.long 0x10 "MMCSD1_CQ_ERROR_TASK_ID,CQ Error Task ID Register" hexmask.long 0x10 5.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--4. 1. "TERR_ID,Task Error ID" tree.end tree "MMCSD1_ECC_AGGR_RXMEM" base ad:0x2A26000 rgroup.long 0x0++0x3 line.long 0x0 "MMCSD1_RXECC_REV,Aggregator Revision Register Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MMCSD1_RXECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MMCSD1_RXECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator." group.long 0x3C++0x7 line.long 0x0 "MMCSD1_RXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,SEC EOI" "0,1" line.long 0x4 "MMCSD1_RXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "MMCSD1_RXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "MMCSD1_RXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "MMCSD1_RXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,DED EOI" "0,1" line.long 0x4 "MMCSD1_RXECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "MMCSD1_RXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MMCSD1_RXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "MMCSD1_RXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "MMCSD1_RXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "MMCSD1_RXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MMCSD1_RXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD1_ECC_AGGR_TXMEM" base ad:0x2A27000 rgroup.long 0x0++0x3 line.long 0x0 "MMCSD1_TXECC_REV,Aggregator Revision Register Revision parameters." bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom Version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Version" group.long 0x8++0x3 line.long 0x0 "MMCSD1_TXECC_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address" bitfld.long 0x0 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "MMCSD1_TXECC_STAT,Misc Status Register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator." group.long 0x3C++0x7 line.long 0x0 "MMCSD1_TXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,SEC EOI" "0,1" line.long 0x4 "MMCSD1_TXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "MMCSD1_TXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "MMCSD1_TXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "MMCSD1_TXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,DED EOI" "0,1" line.long 0x4 "MMCSD1_TXECC_DED_STATUS_REG0,DED Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "MMCSD1_TXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MMCSD1_TXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "MMCSD1_TXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "MMCSD1_TXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "MMCSD1_TXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MMCSD1_TXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD1_SS_CFG" base ad:0x4FB8000 rgroup.long 0x0++0x3 line.long 0x0 "MMCSD1_SS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem." hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version" bitfld.long 0x0 8.--10. "MAJ_REV,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor Revision" group.long 0x10++0x33 line.long 0x0 "MMCSD1_SS_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller." rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the number of Taps (Phases) of the RX clock that is supported." rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency" line.long 0x4 "MMCSD1_SS_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller. This register sets the LSB fields in the register inside the Host Controller." bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type Should be set based on the final product usage." "0,1,2,3" bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support Suggested Value is 1h (The Core supports monitoring of Asynchronous Interrupt)." "0,1" rbitfld.long 0x4 27.--28. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8 V Support Suggested Value is 1h (The 1.8 Volt Switching is supported by Core)." "0,1" newline bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0 V Support Should be set based on whether 3.0 V is supported on the SD Interface." "0,1" bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3 V Support Suggested Value is 1h as the 3.3 V is the default voltage on the SD Interface." "0,1" bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support Suggested Value is 1h (The Suspend/Resume is supported by Core)." "0,1" bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support Suggested Value is 1h (The SDMA is supported by Core)." "0,1" newline bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support Suggested Value is 1h (The High Speed mode is supported by Core)." "0,1" rbitfld.long 0x4 20. "RESERVED,Reserved" "0,1" bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support Suggested Value is 1h (The ADMA2 is supported by Core)." "0,1" bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device Suggested Value is 1h (The Core supports 8-bit Interface)." "0,1" newline bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length Maximum Block Length supported by the Core/Device." "0,1,2,3" hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock This is the frequency of the FCLK." bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit Suggested Value is 0h (KHz)." "0,1" rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency Suggested Value is 1 KHz." line.long 0x8 "MMCSD1_SS_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller. This register sets the MSB fields in the register inside the Host Controller." rbitfld.long 0x8 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8 V VDD2 Support" "0,1" bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support" "0,1" rbitfld.long 0x8 24.--26. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator." bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes Should be set to 2h as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3" bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50 This bit should be set if the application wants Tuning be used for SDR50 Modes." "0,1" rbitfld.long 0x8 12. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3." bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1" rbitfld.long 0x8 3. "RESERVED,Reserved" "0,1" bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support Suggested Value is 1h (The Core supports DDR50 mode of operation)." "0,1" bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support." "0,1" newline bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support." "0,1" line.long 0xC "MMCSD1_SS_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller. This register sets the LSB fields in the register inside the Host Controller." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current For 1.8 V" hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current For 3.0 V" hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current For 3.3 V" line.long 0x10 "MMCSD1_SS_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller. This register sets the MSB fields in the register inside the Host Controller." hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current For 1.8 V (VDD2)" line.long 0x14 "MMCSD1_SS_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for Initialization inside the Host Controller." hexmask.long.tbyte 0x14 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value For Initialization" line.long 0x18 "MMCSD1_SS_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for Default Speed inside the Host Controller." hexmask.long.tbyte 0x18 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value For Default Speed" line.long 0x1C "MMCSD1_SS_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for High Speed inside the Host Controller." hexmask.long.tbyte 0x1C 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value For High Speed" line.long 0x20 "MMCSD1_SS_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for SDR12 inside the Host Controller." hexmask.long.tbyte 0x20 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value For SDR12" line.long 0x24 "MMCSD1_SS_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for SDR25 inside the Host Controller." hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value For SDR25" line.long 0x28 "MMCSD1_SS_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for SDR50 inside the Host Controller." hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value For SDR50" line.long 0x2C "MMCSD1_SS_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for SDR104 inside the Host Controller." hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value For SDR104" line.long 0x30 "MMCSD1_SS_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers ( to ) for DDR50 inside the Host Controller." hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value For DDR50" rgroup.long 0x60++0x17 line.long 0x0 "MMCSD1_SS_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller." bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable software to gate off the clocks" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus" line.long 0x4 "MMCSD1_SS_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus" line.long 0x8 "MMCSD1_SS_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus" line.long 0xC "MMCSD1_SS_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)" line.long 0x10 "MMCSD1_SS_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0x10 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)" line.long 0x14 "MMCSD1_SS_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller." hexmask.long.word 0x14 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus" group.long 0x100++0x3 line.long 0x0 "MMCSD1_SS_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY." bitfld.long 0x0 31. "IOMUX_ENABLE,IO Mux Enable Set 1h for GPIO." "0,1" hexmask.long 0x0 0.--30. 1. "RESERVED,Reserved" group.long 0x10C++0x7 line.long 0x0 "MMCSD1_SS_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY." hexmask.long.word 0x0 21.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 20. "OTAPDLYENA,Output Tap Delay Enable Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1" hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." newline rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 9. "ITAPCHGWIN,Input Tap Change Window It gets asserted by the controller while changing the itapdlysel." "0,1" bitfld.long 0x0 8. "ITAPDLYENA,Input Tap Delay Enable This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select Manual control of the RX clock Tap Delay in the non HS200/HS400 modes." line.long 0x4 "MMCSD1_SS_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--2. "CLKBUFSEL,Clock Delay Buffer Select." "0,1,2,3,4,5,6,7" tree.end tree.end tree "NAV_DDR" base ad:0x0 tree "NAV_DDR0_VIRTID_CFG_MMRS" base ad:0x30A02000 rgroup.long 0x0++0x3 line.long 0x0 "VIRTID_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" group.long 0x10++0x3 line.long 0x0 "VIRTID_WINDOW_y,The VirtID for window y. Offset = 30A02010h + (y * 4h); where y = 0h to Fh" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window y" tree.end tree "NAV_DDR1_VIRTID_CFG_MMRS" base ad:0x30A03000 rgroup.long 0x0++0x3 line.long 0x0 "VIRTID_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" group.long 0x10++0x3 line.long 0x0 "VIRTID_WINDOW_y,The VirtID for window y. Offset = 30A02010h + (y * 4h); where y = 0h to Fh" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window y" tree.end tree.end tree "NAVSS0" base ad:0x0 tree "NAVSS0_CPTS" base ad:0x310D0000 rgroup.long 0x0++0x3 line.long 0x0 "CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x4++0x7 line.long 0x0 "CPTS_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select0000 – TS_SYNC disabled 0001 0001..1111 - TS_SYNC is timestamp counter bits 31 (1111) down to 17 (0001)" hexmask.long.word 0x0 18.--27. 1. "RESERVED" bitfld.long 0x0 17. "TX_GENF_CLR_EN,GENF (and ESTF) Clear Enable. 0 - A TS_GENFn output is not cleared when the associated 1 - A TS_GENFn output is cleared when the associated" "0,1" newline bitfld.long 0x0 16. "TS_RX_NO_EVENT,Timestamp Ethernet Receive produces no events. 0 - Ethernet receive timesync events enabled 1 - Ethernet receive timesync events disabled" "0,1" bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" newline bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" newline bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" newline bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction0 – Increase the time_stamp[63:0] value by the PPM value 1 – Decrease the time_stamp[63:0] value by the PPM value" "0,1" bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode" bitfld.long 0x0 5. "MODE,Timestamp mode 0 – The timestamp is 32-bits with the upper 32-bits forced to zero. 1 – The timestamp is 64-bits." "0,1" newline bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable0 – The timestamp value increments with the selected RFTCLK 1 - The timestamp for received packets is the sequence number of the received packet (first packet is 1 second packet is 2 etc)." "0,1" bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable0 – Timestamps are disabled on received packets to host 1 – Timestamps enabled on received packets to host (cpts_en must be set)" "0,1" bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity0 – TS_COMP is asserted low 1 – TS_COMP is asserted high" "0,1" newline bitfld.long 0x0 1. "INT_TEST,Interrupt testWhen set this bit allows the raw interrupt to be written to facilitate interrupt test." "0,1" bitfld.long 0x0 0. "CPTS_EN,Time sync enableWhen disabled (cleared to zero) the RCLK domain is held in reset." "0,1" line.long 0x4 "CPTS_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long 0x4 5.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select. NOT FUNCTIONAL. See" wgroup.long 0xC++0x3 line.long 0x0 "CPTS_TS_PUSH_REG,Time Stamp Event Push Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PUSH,Time stamp event pushWhen a logic high is written to this bit a time stamp event is pushed onto the event FIFO. The time stamp value is the time of the write of this register not the time of the event read. The time stamp value can then be read.." "0,1" group.long 0x10++0x3 line.long 0x0 "CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low valueWriting the ts_load_en bit causes ts_load[63:0] to be written into the time stamp. The time stamp value is read by initiating a time stamp push event not by reading this register. When reading this register the.." wgroup.long 0x14++0x3 line.long 0x0 "CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enableWriting a one to this bit enables the time stamp value to be written with the value in ts_load[63:0]. This bit is write only and will be cleared by the hardware after one clock. The upper 32-bits of the timestamp are.." "0,1" group.long 0x18++0xB line.long 0x0 "CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low valueWriting a non-zero value to the TS_Comp_Length[31:0] register causes a pulse of TS_Comp_Length RCLK periods on the TS_COMP output and a comparison event when the time_stamp counter value is equivalent to.." line.long 0x4 "CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison lengthWriting a non-zero value to this field enables the time stamp comparison event and output. This value should be zero when the TS_Comp_Low and TS_Comp_High registers are written." line.long 0x8 "CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)Writable when int_test = 1. A one in this bit indicates that there are one or more events in the event FIFO." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" group.long 0x28++0x7 line.long 0x0 "CPTS_INT_ENABLE_REG,Interrupt Enable Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amountOnly a single high or low time is adjusted and the ts_comp_nudge value is cleared to zero when the nudge has occurred." wgroup.long 0x30++0x3 line.long 0x0 "CPTS_EVENT_POP_REG,Event Pop Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EVENT_POP,Event popWhen a logic high is written to this bit an event is popped off the event FIFO. The event FIFO pop occurs as part of the interrupt process after the event has been read from the Event_0-3 registers. Popping an event discards the event.." "0,1" rgroup.long 0x34++0xF line.long 0x0 "CPTS_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time StampThe timestamp is valid for transmit receive and time stamp push event types. The timestamp value is not valid for counter roll event types." line.long 0x4 "CPTS_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 30.--31. "RESERVED" "0,1,2,3" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE0 – The packet was received/transmitted on the express queue. 1 – The packet was received/transmitted on the prempt queue." "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port numberindicates the port number (encoded) of an Ethernet event or the encoded hardware timestamp number." newline hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type0000 – Time Stamp Push Event 0001 – Time Stamp Rollover Event 0010 – Time Stamp Half Rollover Event 0011 – Hardware Time Stamp Push Event 0100 – Ethernet Receive Event 0101 – Ethernet Transmit Event 0110 – Time Stamp.." hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message typeThe message type value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events." hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence IDThe 16-bit sequence id is the value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events." line.long 0x8 "CPTS_EVENT_2_REG,Event 2 Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,DomainThe 8-bit domain is the value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events." line.long 0xC "CPTS_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time StampThe timestamp upper 32-bits are valid for transmit receive and time stamp push event types. This value is zero in 32-bit mode." group.long 0x44++0x17 line.long 0x0 "CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high valueWriting the ts_load_en bit causes the value contained in this register (and the ts_load[63:0]) to be written into the time stamp. The time stamp value is read by initiating a time stamp push event not by reading.." line.long 0x4 "CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high valueWriting a non-zero value to the TS_Comp_Length[31:0] register causes a pulse of TS_Comp_Length RCLK periods on the TS_COMP output and a comparison event when the time_stamp counter value is equivalent to.." line.long 0x8 "CPTS_TS_ADD_VAL_REG,TS Add Value Register" hexmask.long 0x8 3.--31. 1. "RESERVED" bitfld.long 0x8 0.--2. "ADD_VAL,Add ValueAdd Value is added to 1 to comprise the timestamp increment value. The timestamp increment value is added to the current timestamp (time_stamp[63:0]) on each RCLK. The timestamp increment value can be adjusted by nudge and ppm also. The.." "0,1,2,3,4,5,6,7" line.long 0xC "CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low valueThe 64-bit PPM value takes effect when this low value is written. The high value should be written first. Note: There should be at least 10 clocks in between writes to the low register to ensure that the previous.." line.long 0x10 "CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High valueThis value should be written first (before the low value is written). The minimum value of the ts_ppm is 0x400 (all 42 bits)." line.long 0x14 "CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge valueThis two’s complement number is added to the time_stamp[63:0] value to increase or decrease the timestamp value by the ts_nudge amount. The ts_nudge value is cleared to zero when the nudge has occurred." group.long 0xE0++0x1B line.long 0x0 "CPTS_TS_GENF_COMP_LOW_REG_j,Time Stamp Generate Function Comparison Low Value Offset = E0h + (j * 20h); where j = 0h to 5h" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low ValueThis value should be written after the upper 32-bits. The ts_GENFn_comp high and low should only be written when the ts_GENFn_length value is zero." line.long 0x4 "CPTS_TS_GENF_COMP_HIGH_REG_j,Time Stamp Generate Function Comparison high Value Offset = E4h + (j * 20h); where j = 0h to 5h" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High ValueThis value should be written before the lower 32-bits are written. The ts_GENFn_comp high and low should only be written when the ts_GENFn_length value is zero." line.long 0x8 "CPTS_TS_GENF_CONTROL_REG_j,Time Stamp Generate Function Control Offset = E8h + (j * 20h); where j = 0h to 5h" hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert0 – The output TS_GENFn signal asserts high 1 – The output TS_GENFn signal asserts low" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction0 – A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount. 1 – A single RCLK is subtracted from.." "0,1" line.long 0xC "CPTS_TS_GENF_LENGTH_REG_j,Time Stamp Generate Function Length Value Offset = ECh + (j * 20h); where j = 0h to 5h" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length ValueThe minimum value is decimal 5" line.long 0x10 "CPTS_TS_GENF_PPM_LOW_REG_j,Time Stamp Generate Function PPM Low Value Offset = F0h + (j * 20h); where j = 0h to 5h" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low ValueThe 64-bit PPM value takes effect when this low value is written. The high value should be written first" line.long 0x14 "CPTS_TS_GENF_PPM_HIGH_REG_j,Time Stamp Generate Function PPM High Value Offset = F4h + (j * 20h); where j = 0h to 5h" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High ValueThis value should be written first (before the low value is written)." line.long 0x18 "CPTS_TS_GENF_NUDGE_REG_j,Time Stamp Generate Function Nudge Value Offset = F8h + (j * 20h); where j = 0h to 5h" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge ValueThis two’s complement number is added to the generate counter value to increase or decrease the length by the ts_genfN_nudge amount. Only a single high or low time is adjusted and the ts_genfN_nudge value.." group.long 0x200++0x1B line.long 0x0 "CPTS_TS_ESTF_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low ValueThis value should be written after the upper 32-bits. The ts_ESTFn_comp high and low should only be written when the ts_ESTFn_length value is zero." line.long 0x4 "CPTS_TS_ESTF_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High ValueThis value should be written before the lower 32-bits are written. The ts_ESTFn_comp high and low should only be written when the ts_ESTFn_length value is zero" line.long 0x8 "CPTS_TS_ESTF_CONTROL_REG,Time Stamp ESTF Generate Function Control" hexmask.long 0x8 2.--31. 1. "RESERVED" bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert 0 – The output TS_ESTFn signal asserts low 1 – The output TS_ESTFn signal asserts high" "0,1" bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction 0 – A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount. 1 – A single RCLK is subtracted.." "0,1" line.long 0xC "CPTS_TS_ESTF_LENGTH_REG,Time Stamp ESTF Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value" line.long 0x10 "CPTS_TS_ESTF_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low ValueThe 64-bit PPM value takes effect when this low value is written. The high value should be written first." line.long 0x14 "CPTS_TS_ESTF_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High ValueThis value should be written first (before the low value is written)." line.long 0x18 "CPTS_TS_ESTF_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge ValueThis two’s complement number is added to the generate counter value to increase or decrease the length by the ts_estfN_nudge amount. Only a single high or low time is adjusted and the ts_estfN_nudge.." tree.end tree "NAVSS0_DMA_PVU0_CFG" base ad:0x30F81000 rgroup.long 0x0++0x7 line.long 0x0 "PVU_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.Fh in this device." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PVU_CONFIG,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" newline hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs40h in this device" group.long 0x10++0xB line.long 0x0 "PVU_ENABLE,The Enable Register enables the PVU." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = PVU disabled 1 = PVU enabled" "0: PVU disabled,1: PVU enabled" line.long 0x4 "PVU_VIRTID_MAP1,The Map Register 1 defines the virtid mapping for the PVU." hexmask.long.byte 0x4 24.--31. 1. "RESERVED" bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" hexmask.long.byte 0x4 12.--15. 1. "RESERVED" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "PVU_VIRTID_MAP2,The Map Register 2 defines the virtid mapping for the PVU." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." group.long 0x30++0x3 line.long 0x0 "PVU_EXCEPTION_LOGGING_DISABLE,The Exception Logging Disable Register defines which types of faults are disabled for logging." hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" newline bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" newline bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" newline bitfld.long 0x0 1. "RESERVED" "0,1" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" group.long 0x104++0x3 line.long 0x0 "PVU_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x120++0x3 line.long 0x0 "PVU_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" newline bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "PVU_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "PVU_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." newline hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "PVU_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "PVU_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "PVU_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." newline bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "PVU_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x140++0x13 line.long 0x0 "PVU_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "PVU_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "PVU_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "PVU_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "PVU_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "NAVSS0_INTR0_INTR_ROUTER_CFG" base ad:0x310E0000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version 10h - NAVSS0 Fh - MCU_NAVSS0" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_MUXCNTL_y,Interrupt mux control register Offset = 4h + (y * 4); where y = 0h to 1FFh for NAVSS0 Offset = 4h + (y * 4); where y = 0h to 3Fh for MCU_NAVSS0" hexmask.long.word 0x0 17.--31. 1. "RESERVED" bitfld.long 0x0 16. "INT_ENABLE,Interrupt output enable for interrupt y" "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "MUX_CONTROL,Mux control for interrupt y Avoid programming the mux control when input interrutps are enabled via INT_ENABLE." tree.end tree "NAVSS0_IO_PVU0_CFG" base ad:0x30F80000 rgroup.long 0x0++0x7 line.long 0x0 "PVU_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.Fh in this device." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PVU_CONFIG,The Config Register contains the configuration values for the module." hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel" newline hexmask.long.word 0x4 0.--15. 1. "TLBS,Number of TLBs40h in this device" group.long 0x10++0xB line.long 0x0 "PVU_ENABLE,The Enable Register enables the PVU." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EN,PVU Enable bit. 0 = PVU disabled 1 = PVU enabled" "0: PVU disabled,1: PVU enabled" line.long 0x4 "PVU_VIRTID_MAP1,The Map Register 1 defines the virtid mapping for the PVU." hexmask.long.byte 0x4 24.--31. 1. "RESERVED" bitfld.long 0x4 22.--23. "DMA_CL3,Map for DMA sub-class 3. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 20.--21. "DMA_CL2,Map for DMA sub-class 2. Value is the final sub-class and selects TLB+n." "0,1,2,3" bitfld.long 0x4 18.--19. "DMA_CL1,Map for DMA sub-class 1. Value is the final sub-class and selects TLB+n." "0,1,2,3" newline bitfld.long 0x4 16.--17. "DMA_CL0,Map for DMA sub-class 0. Value is the final sub-class and selects TLB+n." "0,1,2,3" hexmask.long.byte 0x4 12.--15. 1. "RESERVED" newline hexmask.long.word 0x4 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes." line.long 0x8 "PVU_VIRTID_MAP2,The Map Register 2 defines the virtid mapping for the PVU." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--11. 1. "MAX_CNT,VirtID maximum for PVU." group.long 0x30++0x3 line.long 0x0 "PVU_EXCEPTION_LOGGING_DISABLE,The Exception Logging Disable Register defines which types of faults are disabled for logging." hexmask.long 0x0 7.--31. 1. "RESERVED" bitfld.long 0x0 6. "MISS_DIS,Disable for PVU miss fault logging. 0 = enable miss fault logging. 1 = disable miss fault logging." "0: enable miss fault logging,1: disable miss fault logging" newline bitfld.long 0x0 5. "PREF_DIS,Disable for prefetch permissions fault logging. 0 = enable prefetch fault logging. 1 = disable prefetch fault logging." "0: enable prefetch fault logging,1: disable prefetch fault logging" bitfld.long 0x0 4. "EXEC_DIS,Disable for execute permissions fault logging. 0 = enable execute fault logging. 1 = disable execute fault logging." "0: enable execute fault logging,1: disable execute fault logging" newline bitfld.long 0x0 3. "WRITE_DIS,Disable for write permissions fault logging. 0 = enable write fault logging. 1 = disable write fault logging." "0: enable write fault logging,1: disable write fault logging" bitfld.long 0x0 2. "READ_DIS,Disable for read permissions fault logging. 0 = enable read fault logging. 1 = disable read fault logging." "0: enable read fault logging,1: disable read fault logging" newline bitfld.long 0x0 1. "RESERVED" "0,1" bitfld.long 0x0 0. "VIRTID_DIS,Disable for virtID permission fault logging. 0 = enable virtID fault logging. 1 = disable virtID fault logging." "0: enable virtID fault logging,1: disable virtID fault logging" group.long 0x104++0x3 line.long 0x0 "PVU_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x120++0x3 line.long 0x0 "PVU_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_INTR,Disables logging interrupt when set. This will not disable logging so if cleared the current log should also be cleared to guarantee the next log generates the interrupt." "0,1" newline bitfld.long 0x0 0. "DISABLE_F,Disables logging when set. This will also disable interrupts." "0,1" rgroup.long 0x124++0x17 line.long 0x0 "PVU_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 6 = PVU." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." newline hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "PVU_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = PVU miss. 1 = Max virtid violation. 2 = reserved. 3 = read permission violation. 4 = write permission violation. 5 = execute permission violation. 6 = prefetch permission violation." newline hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "PVU_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Input virtual address lower 32 bits." line.long 0xC "PVU_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits." line.long 0x10 "PVU_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." newline bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" newline bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" newline bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "PVU_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data. Reading this register will clear the error pending bit except when emudbg is set." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x140++0x13 line.long 0x0 "PVU_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "PVU_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" line.long 0x8 "PVU_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal." hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal." "0,1" line.long 0xC "PVU_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal." hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal." "0,1" line.long 0x10 "PVU_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register" tree.end tree "NAVSS0_IO_PVU0_CFG_TLBIF" base ad:0x36000000 group.long 0x0++0x3 line.long 0x0 "PVU_CHAIN_j,The TLB chain points to another TLB. The j is the TLB number. Offset = 0h + (j * 1000h); where j = 0h to 3Fh" bitfld.long 0x0 31. "EN,Enable for the TLB. 0 = disable TLB. 1 = enable TLB." "0: disable TLB,1: enable TLB" bitfld.long 0x0 30. "LOG_DIS,Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging." "0: enable fault logging,1: disable fault logging" newline bitfld.long 0x0 29. "FAULT,A fault has been detected from this TLB that could not be logged. Will be set by hardware and can be cleared by software." "0,1" hexmask.long.tbyte 0x0 12.--28. 1. "RESERVED" newline hexmask.long.word 0x0 0.--11. 1. "CHAIN,Chain to another TLB. 0 = no chain. &gt;0 = chain to that TLB number." group.long 0x20++0xB line.long 0x0 "PVU_ENTRY0_j_k,The TLB Entry. The j is the TLB number. and the k is the entry number within a TLB. The address must be aligned to the page size. Offset = 20h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh. k = 0h to 7h" hexmask.long 0x0 0.--31. 1. "VBASE_L,Virtual Base Address bits 31 to 0.The address must be aligned to the page size." line.long 0x4 "PVU_ENTRY1_j_k,The TLB Entry. The j is the TLB number. and the k is the entry number within a TLB. The address must be aligned to the page size. Offset = 24h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh. k = 0h to 7h" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32.The address must be aligned to the page size." line.long 0x8 "PVU_ENTRY2_j_k,The TLB Entry. The j is the TLB number. and the k is the entry number within a TLB. Offset = 28h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh. k = 0h to 7h" bitfld.long 0x8 30.--31. "MODE,Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use." "0: invalid,1: reserved,2: valid,3: reserved" bitfld.long 0x8 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU." "0: Secure Transactions are not affected,1: Secure Transactions that match the entry is.." newline hexmask.long.byte 0x8 22.--28. 1. "RESERVED" bitfld.long 0x8 21. "PSECURE,LPAE Field for Secure Page" "0,1" newline bitfld.long 0x8 20. "RESERVED" "0,1" hexmask.long.byte 0x8 16.--19. 1. "PSIZE,LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G." newline hexmask.long.byte 0x8 10.--15. 1. "PPERM,LPAE Field for Page Permissions. Bit 0 = enable user read access UR. Bit 1 = enable user write access UW. Bit 2 = enable user execute access UX. Bit 3 = enable supervisor read access SR. Bit 4 = enable supervisor write access SW. Bit 5 = enable.." bitfld.long 0x8 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through." "0: device,1: write back,2: write through,?" newline bitfld.long 0x8 7. "RESERVED" "0,1" bitfld.long 0x8 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1" newline bitfld.long 0x8 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1" bitfld.long 0x8 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1" newline bitfld.long 0x8 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" bitfld.long 0x8 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate." "0: no allocate,1: write allocate,2: read allocate,3: read and write allocate" group.long 0x30++0xB line.long 0x0 "PVU_ENTRY4_j_k,The TLB Entry. The j is the TLB number. and the k is the entry number within a TLB. The address must be aligned to the page size. Offset = 30h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh. k = 0h to 7h" hexmask.long 0x0 0.--31. 1. "PBASE_L,Physical Base Address bits 31 to 0.The address must be aligned to the page size." line.long 0x4 "PVU_ENTRY5_j_k,The TLB Entry. The j is the TLB number. and the k is the entry number within a TLB. The address must be aligned to the page size. Offset = 34h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh. k = 0h to 7h" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32.The address must be aligned to the page size." line.long 0x8 "PVU_ENTRY6_j_k,The TLB Entry. The j is the TLB number. and the k is the entry number within a TLB. Offset = 38h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh. k = 0h to 7h" hexmask.long 0x8 5.--31. 1. "RESERVED" bitfld.long 0x8 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the ORDERID field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source.." "0: bypass and use the orderid from the source..,1: use the ORDERID field value for the destination.." newline hexmask.long.byte 0x8 0.--3. 1. "ORDERID,Defines the bus orderid value for this entry if hit." tree.end base ad:0x0 tree "NAVSS0_MAILBOX" tree "NAVSS0_MAILBOX0_REGS0" base ad:0x31F80000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS1" base ad:0x31F81000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS2" base ad:0x31F82000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS3" base ad:0x31F83000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS4" base ad:0x31F84000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS5" base ad:0x31F85000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS6" base ad:0x31F86000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS7" base ad:0x31F87000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS8" base ad:0x31F88000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS9" base ad:0x31F89000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS10" base ad:0x31F8A000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree "NAVSS0_MAILBOX0_REGS11" base ad:0x31F8B000 rgroup.long 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FC 7100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox. Read: Reads the next available message. Write: Add a message to this mailbox queue. Offset = 40h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 0.--31. 1. "VALUE,Message in Mailbox y" rgroup.long 0x80++0x3 line.long 0x0 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "FULL,Full flag for Mailbox y" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7" group.long 0x100++0xF line.long 0x0 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user . Software may also write 1 to a given bit to set this bit to test interrupt.." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" newline bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" newline bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" newline bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" newline bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" newline bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a.." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt source. Write 1 to a bit enables an interrupt source." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 no action." "0,1" line.long 0xC "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j. Read value is the current enable bits for each interrupt sourc. Write 1 to a bit disables an interrupt source." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" newline bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 no action." "0,1" wgroup.long 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt.." hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" tree.end tree.end tree "NAVSS0_MCRC" base ad:0x31F70000 group.long 0x0++0x3 line.long 0x0 "MCRC_CRC_CTRL0,CRC Global Control Register 0" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" newline bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" group.long 0x8++0x3 line.long 0x0 "MCRC_CRC_CTRL1,CRC Global Control Register 1" hexmask.long 0x0 1.--31. 1. "RESERVED" newline bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" group.long 0x10++0x3 line.long 0x0 "MCRC_CRC_CTRL2,Channel Mode Control Register" hexmask.long.byte 0x0 26.--31. 1. "RESERVED" newline bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 2.--3. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" group.long 0x18++0x3 line.long 0x0 "MCRC_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIME_OUT_ENS,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt enable" group.long 0x20++0x3 line.long 0x0 "MCRC_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 =.." "0: Has no effect,1: Compression Complete Interrupt disable" group.long 0x28++0x3 line.long 0x0 "MCRC_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 21.--23. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode. 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode. 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "MCRC_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "MCRC_CRC_BUSY,CRC Busy Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" newline bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" group.long 0x40++0x7 line.long 0x0 "MCRC_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.word 0x0 20.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "MCRC_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0x4C++0x7 line.long 0x0 "MCRC_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." group.long 0x60++0xF line.long 0x0 "MCRC_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "MCRC_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "MCRC_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "MCRC_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "MCRC_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "MCRC_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "MCRC_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x80++0x7 line.long 0x0 "MCRC_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.word 0x0 20.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "MCRC_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0x8C++0x7 line.long 0x0 "MCRC_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0xA0++0xF line.long 0x0 "MCRC_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "MCRC_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "MCRC_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "MCRC_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "MCRC_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "MCRC_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "MCRC_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0xC0++0x7 line.long 0x0 "MCRC_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.word 0x0 20.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "MCRC_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0xCC++0x7 line.long 0x0 "MCRC_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0xE0++0xF line.long 0x0 "MCRC_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "MCRC_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "MCRC_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "MCRC_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "MCRC_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "MCRC_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "MCRC_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x100++0x7 line.long 0x0 "MCRC_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.word 0x0 20.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "MCRC_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." group.long 0x10C++0x7 line.long 0x0 "MCRC_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.byte 0x0 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" newline hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0x120++0xF line.long 0x0 "MCRC_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "MCRC_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "MCRC_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "MCRC_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "MCRC_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "MCRC_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "MCRC_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x140++0x3 line.long 0x0 "MCRC_BUS_SEL,Data bus tracing selection" hexmask.long 0x0 3.--31. 1. "RESERVED" newline bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." wgroup.long 0x200++0x3 line.long 0x0 "MCRC_I0_PSA_SIGREG1_CPY_Y,Channel 1 PSA signature block region Offset = 200h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." wgroup.long 0x280++0x3 line.long 0x0 "MCRC_I0_PSA_SIGREG2_CPY_Y,Channel 2 PSA signature block region Offset = 280h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." wgroup.long 0x300++0x3 line.long 0x0 "MCRC_I0_PSA_SIGREG3_CPY_Y,Channel 3 PSA signature block region Offset = 300h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." wgroup.long 0x380++0x3 line.long 0x0 "MCRC_I0_PSA_SIGREG4_CPY_Y,Channel 4 PSA signature block region Offset = 380h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end base ad:0x0 tree "NAVSS0_MODSS" tree "NAVSS0_MODSS_INTA0_CFG" base ad:0x30800000 rgroup.quad 0x0++0x17 line.quad 0x0 "INTA_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.long 0x0 32.--63. 1. "RESERVED" hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL Revision." bitfld.quad 0x0 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" line.quad 0x8 "INTA_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.long 0x8 32.--63. 1. "RESERVED" hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "INTA_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "RESERVED" hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end tree "NAVSS0_MODSS_INTA0_CFG_IMAP" base ad:0x30900000 group.quad 0x0++0x7 line.quad 0x0 "INTA_IMAP_j,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto. Offset = 0h + (j * 8h); where j = 0h to 3FFh" hexmask.quad 0x0 17.--63. 1. "RESERVED" hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." bitfld.quad 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end tree "NAVSS0_MODSS_INTA0_CFG_INTR" base ad:0x33C00000 group.quad 0x0++0x1F line.quad 0x0 "INTA_ENABLE_SET_j,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output. Offset = 0h.." hexmask.quad 0x0 0.--63. 1. "ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "INTA_ENABLE_CLEAR_j,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output." hexmask.quad 0x8 0.--63. 1. "ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "INTA_STATUS_SET_j,The Interrupt Status register is read by software to determine the cause of an interrupt. Offset = 10h + (j * 1000h); where j = 0h to 3Fh" hexmask.quad 0x10 0.--63. 1. "STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "INTA_STATUS_CLEAR_j,The Interrupt Status register is read by software to determine the cause of an interrupt. Offset = 18h + (j * 1000h); where j = 0h to 3Fh" hexmask.quad 0x18 0.--63. 1. "STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" rgroup.quad 0x20++0x7 line.quad 0x0 "INTA_STATUSM_j,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt. Offset = 20h + (j * 1000h); where j = 0h to 3Fh" hexmask.quad 0x0 0.--63. 1. "STATUS,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end tree "NAVSS0_MODSS_INTA1_CFG" base ad:0x30801000 rgroup.quad 0x0++0x17 line.quad 0x0 "INTA_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.long 0x0 32.--63. 1. "RESERVED" hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL Revision." bitfld.quad 0x0 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" line.quad 0x8 "INTA_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.long 0x8 32.--63. 1. "RESERVED" hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "INTA_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "RESERVED" hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end tree "NAVSS0_MODSS_INTA1_CFG_IMAP" base ad:0x30908000 group.quad 0x0++0x7 line.quad 0x0 "INTA_IMAP_j,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto. Offset = 0h + (j * 8h); where j = 0h to 3FFh" hexmask.quad 0x0 17.--63. 1. "RESERVED" hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." bitfld.quad 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end tree "NAVSS0_MODSS_INTA1_CFG_INTR" base ad:0x33C40000 group.quad 0x0++0x1F line.quad 0x0 "INTA_ENABLE_SET_j,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output. Offset = 0h.." hexmask.quad 0x0 0.--63. 1. "ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "INTA_ENABLE_CLEAR_j,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output." hexmask.quad 0x8 0.--63. 1. "ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "INTA_STATUS_SET_j,The Interrupt Status register is read by software to determine the cause of an interrupt. Offset = 10h + (j * 1000h); where j = 0h to 3Fh" hexmask.quad 0x10 0.--63. 1. "STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "INTA_STATUS_CLEAR_j,The Interrupt Status register is read by software to determine the cause of an interrupt. Offset = 18h + (j * 1000h); where j = 0h to 3Fh" hexmask.quad 0x18 0.--63. 1. "STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" rgroup.quad 0x20++0x7 line.quad 0x0 "INTA_STATUSM_j,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt. Offset = 20h + (j * 1000h); where j = 0h to 3Fh" hexmask.quad 0x0 0.--63. 1. "STATUS,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end tree.end tree "NAVSS0_NBSS" tree "NAVSS0_NBSS_CFG_REGS0_MMRS" base ad:0x3800000 rgroup.long 0x0++0x3 line.long 0x0 "NBSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end tree "NAVSS0_NBSS_NB0_CFG_MMRS" base ad:0x3802000 rgroup.long 0x0++0x3 line.long 0x0 "NB_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "NB_THREADMAP,The Thread Map Register defines the VBUSM.C thread for each VBUSM source." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "THREADMAP,Thread map each bit is for each VBUSM source. Bit [0] maps orderid 0-7 to VBUSM.C thread number. Bit [1] maps orderid 8-15 to VBUSM.C thread number. 0: VBUSM.C thread 0 (non-real time traffic) 1: VBUSM.C thread 2 (real-time traffic)" "0: VBUSM,1: VBUSM,?,?" tree.end tree "NAVSS0_NBSS_NB0_MEM_ATTR0_CFG" base ad:0x3820000 group.long 0x0++0x3 line.long 0x0 "NB_MEMATTR64K_y,The Memory Attribute register contains the attributes for all the 64K mapped regions. Offset = 0h + (y * 4h); where y = 0h to 1FFFh" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "MEMTYPE,This defines the type for the memory. 0h = Device 1h = Writeback 2h = Writethrough 3h = Non-cacheable" "0,1,2,3" bitfld.long 0x0 4.--5. "SDOMAIN,This defines the shareability domain of the memory. 0h = Non-shared 1h = Inner shared 2h = Outer shared 3h = System shared" "0,1,2,3" bitfld.long 0x0 2.--3. "OUTER,This defines the outer allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" bitfld.long 0x0 0.--1. "INNER,This defines the inner allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" tree.end tree "NAVSS0_NBSS_NB0_MEM_ATTR1_CFG" base ad:0x3828000 group.long 0x0++0x3 line.long 0x0 "NB_MEMATTR64K_y,The Memory Attribute register contains the attributes for all the 64K mapped regions. Offset = 0h + (y * 4h); where y = 0h to 1FFFh" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "MEMTYPE,This defines the type for the memory. 0h = Device 1h = Writeback 2h = Writethrough 3h = Non-cacheable" "0,1,2,3" bitfld.long 0x0 4.--5. "SDOMAIN,This defines the shareability domain of the memory. 0h = Non-shared 1h = Inner shared 2h = Outer shared 3h = System shared" "0,1,2,3" bitfld.long 0x0 2.--3. "OUTER,This defines the outer allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" bitfld.long 0x0 0.--1. "INNER,This defines the inner allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" tree.end tree "NAVSS0_NBSS_NB1_MEM_ATTR0_CFG" base ad:0x3840000 group.long 0x0++0x3 line.long 0x0 "NB_MEMATTR16M0_y,The Memory Attribute register contains the attributes for all the first 16M mapped regions. Offset = 0h + (y * 4h); where y = 0h to 7Fh" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "MEMTYPE,This defines the type for the memory. 0h = Device 1h = Writeback 2h = Writethrough 3h = Non-cacheable" "0,1,2,3" bitfld.long 0x0 4.--5. "SDOMAIN,This defines the shareability domain of the memory. 0h = Non-shared 1h = Inner shared 2h = Outer shared 3h = System shared" "0,1,2,3" bitfld.long 0x0 2.--3. "OUTER,This defines the outer allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" bitfld.long 0x0 0.--1. "INNER,This defines the inner allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" group.long 0x200++0x3 line.long 0x0 "NB_MEMATTR16M1_y,The Memory Attribute register contains the attributes for all the second 16M mapped regions. Offset = 200h + (y * 4h); where y = 0h to 1FFFh" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "MEMTYPE,This defines the type for the memory. 0h = Device 1h = Writeback 2h = Writethrough 3h = Non-cacheable" "0,1,2,3" bitfld.long 0x0 4.--5. "SDOMAIN,This defines the shareability domain of the memory. 0h = Non-shared 1h = Inner shared 2h = Outer shared 3h = System shared" "0,1,2,3" bitfld.long 0x0 2.--3. "OUTER,This defines the outer allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" bitfld.long 0x0 0.--1. "INNER,This defines the inner allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" tree.end tree "NAVSS0_NBSS_NB1_MEM_ATTR1_CFG" base ad:0x3850000 group.long 0x0++0x3 line.long 0x0 "NB_MEMATTR16M0_y,The Memory Attribute register contains the attributes for all the first 16M mapped regions. Offset = 0h + (y * 4h); where y = 0h to 7Fh" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "MEMTYPE,This defines the type for the memory. 0h = Device 1h = Writeback 2h = Writethrough 3h = Non-cacheable" "0,1,2,3" bitfld.long 0x0 4.--5. "SDOMAIN,This defines the shareability domain of the memory. 0h = Non-shared 1h = Inner shared 2h = Outer shared 3h = System shared" "0,1,2,3" bitfld.long 0x0 2.--3. "OUTER,This defines the outer allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" bitfld.long 0x0 0.--1. "INNER,This defines the inner allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" group.long 0x200++0x3 line.long 0x0 "NB_MEMATTR16M1_y,The Memory Attribute register contains the attributes for all the second 16M mapped regions. Offset = 200h + (y * 4h); where y = 0h to 1FFFh" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "MEMTYPE,This defines the type for the memory. 0h = Device 1h = Writeback 2h = Writethrough 3h = Non-cacheable" "0,1,2,3" bitfld.long 0x0 4.--5. "SDOMAIN,This defines the shareability domain of the memory. 0h = Non-shared 1h = Inner shared 2h = Outer shared 3h = System shared" "0,1,2,3" bitfld.long 0x0 2.--3. "OUTER,This defines the outer allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" bitfld.long 0x0 0.--1. "INNER,This defines the inner allocatability of the memory. 0h = Non-allocatable 1h = Writes allocate reads do not 2h = Reads allocate writes do not 3h = Reads and writes allocate" "0,1,2,3" tree.end tree.end tree "NAVSS0_PROXY" tree "NAVSS0_PROXY0_BUF_CFG" base ad:0x33400000 group.long 0x0++0x3 line.long 0x0 "PROXY_EVT_REG_j,The Proxy Event for the proxy Offset = 0h + (j * 1000h); where j = 0h to 3Fh" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Proxy Error Event" tree.end tree "NAVSS0_PROXY0_CFG_BUF_CFG" base ad:0x31120000 rgroup.long 0x0++0x7 line.long 0x0 "PROXY_PID,The Revision Register contains the major and minor revisions for the module. Reset = 66349100h" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.12h in this device." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PROXY_CONFIG,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." group.long 0x14++0x3 line.long 0x0 "PROXY_GLB_EVT,The Global Event Register defines the event to send for a global error." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "ERR_EVENT,Global error event destination. 0xFFFF disables the event" tree.end tree "NAVSS0_PROXY_BUF" base ad:0x31130000 group.long 0x0++0x3 line.long 0x0 "PROXY_DATA_y,The Proxy Buffer for the proxy Offset = 0h + (y * 4h); where y = 0h to FFFh" hexmask.long 0x0 0.--31. 1. "VAL,Proxy Buffer Data" tree.end tree "NAVSS0_PROXY_TARGET0_DATA" base ad:0x33000000 group.long 0x0++0x7 line.long 0x0 "PROXY_CTL_j,The Proxy Control for the proxy. NOTE: This register must be written only via 32-bit accesses. 64-bit writes are not supported and may result in data loss. Offset = 0h + (j * 1000h); where j = 0h to 3Fh" hexmask.long.byte 0x0 27.--31. 1. "RESERVED" bitfld.long 0x0 24.--26. "ELSIZE,Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes" "0: 4 bytes,1: 8 bytes,2: 16 bytes,3: 32 bytes,4: 64 bytes,5: 128 bytes,6: 256 bytes,7: 512 bytes" hexmask.long.byte 0x0 18.--23. 1. "RESERVED" bitfld.long 0x0 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue. 0h = access the head of the queue 1h = access the tail of the queue 2h = peek access the head of the queue 3h = peek access the tail of the queue. NOT SUPPORTED" "0,1,2,3" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Proxy Queue" line.long 0x4 "PROXY_STATUS_j,The Proxy Status for the proxy. NOTE: This register must be written only via 32-bit accesses. 64-bit writes are not supported and may result in data loss. Offset = 4h + (j * 1000h); where j = 0h to 3Fh" bitfld.long 0x4 31. "ERROR,Proxy Error status" "0,1" hexmask.long 0x4 0.--30. 1. "RESERVED" group.long 0x200++0x3 line.long 0x0 "PROXY_DATA_j_y,The Proxy Data for the proxy. target and channel Offset = 200h + (j * 1000h) + (y * 4h); where j = 0h to 3Fh. y = 0h to 7Fh" hexmask.long 0x0 0.--31. 1. "VAL,Proxy Data" tree.end tree.end tree "NAVSS0_SEC_PROXY" tree "NAVSS0_SEC_PROXY0_CFG_MMRS" base ad:0x31140000 rgroup.long 0x0++0x7 line.long 0x0 "SEC_PROXY_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "SEC_PROXY_CONFIG,The Config Register shows configured params." hexmask.long.word 0x4 16.--31. 1. "MSG_SIZE,Supported message size in bytes." hexmask.long.word 0x4 0.--15. 1. "THREADS,Number of proxy threads supported." tree.end tree "NAVSS0_SEC_PROXY0_CFG_RT" base ad:0x32400000 group.long 0x0++0x7 line.long 0x0 "SEC_PROXY_STATUS_j,The Status Register gives status for proxy thread j. Offset =0h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_RT j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_RT" bitfld.long 0x0 31. "ERROR,Error detected on proxy thread. The error will also use the err_evt field to generate an error event which can generate an interrupt. While in error a proxy thread will not process any operations. Write a 0 to clear the error and reset the proxy.." "0,1" hexmask.long.byte 0x0 0.--7. 1. "CUR_CNT,Current message count for the proxy thread. For an inbound proxy this is the number of available messages. For an outbound proxy this is the number of free messages that can be written." line.long 0x4 "SEC_PROXY_THR_j,The Threshold Register controls the threshold for proxy thread j events. Offset =4h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_RT j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_RT" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events. For an outbound proxy this will be the number of free messages to cause an event. For an inbound proxy this will be the number of available messages to cause an event." tree.end tree "NAVSS0_SEC_PROXY0_CFG_SCFG" base ad:0x32800000 group.long 0x0++0x13 line.long 0x0 "SEC_PROXY_BUFFER_L,The Buffer Register defines the pointer for the external buffer." hexmask.long 0x0 0.--31. 1. "BASE_L,The base address for the external buffer lower 32 bits." line.long 0x4 "SEC_PROXY_BUFFER_H,The Buffer Register defines the pointer for the external buffer." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits." line.long 0x8 "SEC_PROXY_TARGET_L,The Target Register defines the pointer for the external target." hexmask.long 0x8 0.--31. 1. "BASE_L,The base address for the external target lower 32 bits." line.long 0xC "SEC_PROXY_TARGET_H,The Target Register defines the pointer for the external target." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits." line.long 0x10 "SEC_PROXY_ORDERID,The Buffer OrderID Register contains the bus value for the buffer memory access." hexmask.long 0x10 5.--31. 1. "RESERVED" bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus OrderID value for the buffer access with the ORDERID register field. 0 = bypass and use the OrderID from the source transaction for the destination transaction. 1 = use the ORDERID register field value for the.." "0: bypass and use the OrderID from the source..,1: use the ORDERID register field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus OrderID value for the buffer access." group.long 0x1000++0xB line.long 0x0 "SEC_PROXY_CTL_j,The Control Register defines controls for proxy thread a. Offset = 1000h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" bitfld.long 0x0 31. "DIR,Direction for the proxy thread. 0 = outbound write only. 1 = inbound read only." "0: outbound,1: inbound" hexmask.long.byte 0x0 24.--30. 1. "RESERVED" hexmask.long.byte 0x0 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread. Is not used otherwise." hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue." line.long 0x4 "SEC_PROXY_EVT_MAP_j,The Event Map Register defines the event numbers for proxy thread a. Offset = 1004h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" hexmask.long.word 0x4 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread." hexmask.long.word 0x4 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread." line.long 0x8 "SEC_PROXY_DST_j,The Destination Register defines the destination proxy thread for outbound proxy thread a. Offset = 1008h + (j * 1000h); where j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers. This is ignored for inbound proxy threads." tree.end tree "NAVSS0_SEC_PROXY0_SRC_TARGET_DATA" base ad:0x32C00000 rgroup.long 0x0++0x3 line.long 0x0 "SEC_PROXY_DATA_j,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored. Reads are allowed to know the source thread of the message. Offset = 0h + (j * 1000h); where j = 0h to 9Fh for.." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "SRC_THR,Proxy source thread of message." group.long 0x4++0x3 line.long 0x0 "SEC_PROXY_MESSAGE_j_y,The Message Data for proxy thread a. The word with index b = 14 contains the completion final byte. Offset = 4h + (j * 1000h) + (y * 4h); where j = 0h to 9Fh. y = 0h to Eh for NAVSS0_SEC_PROXY0_SRC_TARGET_DATA j = 0h to 59h. y = 0h.." hexmask.long 0x0 0.--31. 1. "DATA,Proxy Message Data" tree.end tree.end tree "NAVSS0_SPINLOCK" base ad:0x30E00000 rgroup.long 0x0++0x3 line.long 0x0 "SPINLOCK_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66FA 5100h" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module family." hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version." newline bitfld.long 0x0 8.--10. "X_MAJOR,Major revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision." group.long 0x10++0x3 line.long 0x0 "SPINLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "SOFTRESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the locks" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPINLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUMLOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" hexmask.long.word 0x0 8.--23. 1. "RESERVED" newline bitfld.long 0x0 7. "IU7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224 -.." "0: All lock registers 224,1: At least one of the lock registers 224" bitfld.long 0x0 6. "IU6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192 -.." "0: All lock registers 192,1: At least one of the lock registers 192" newline bitfld.long 0x0 5. "IU5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160 -.." "0: All lock registers 160,1: At least one of the lock registers 160" bitfld.long 0x0 4. "IU4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128 -.." "0: All lock registers 128,1: At least one of the lock registers 128" newline bitfld.long 0x0 3. "IU3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 - 127.." "0: All lock registers 96,1: At least one of the lock registers 96" bitfld.long 0x0 2. "IU2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95 are.." "0: All lock registers 64,1: At least one of the lock registers 64" newline bitfld.long 0x0 1. "IU1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63 are.." "0: All lock registers 32,1: At least one of the lock registers 32" bitfld.long 0x0 0. "IU0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31 are in.." "0: All lock registers 0,1: At least one of the lock registers 0" group.long 0x800++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_y,The LOCK_REG_y register is read and written to perform lock and unlock operations on lock 'y' Offset = 30E00800h + (y * 4h); where y = 0h to FFh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end base ad:0x0 tree "NAVSS0_TIMERMGR" tree "NAVSS0_TIMERMGR0_CFG" base ad:0x30E80000 rgroup.long 0x0++0x3 line.long 0x0 "TIMERMGR_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66F8 B100h" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version number" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision number" group.long 0x4++0x3 line.long 0x0 "TIMERMGR_CNTL,This register controls the overall behavior of the timer manager module" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the MAX_TIMER will be enabled. Useful for initial programming to not need to loop over every TIMERMGR_CONTROL_j_k register to enable every timer if many or all are.." "0,1" bitfld.long 0x0 11. "RESERVED" "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" newline bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count 0h = Timer Manager is disabled 1h = Timer Manager is enabled" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "TIMERMGR_COUNTER,This register contains the current value" hexmask.long 0x0 0.--31. 1. "VAL,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "TIMERMGR_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is the only register that needs.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED" bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers &gt; 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "TIMERMGR_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all 1024 timers." hexmask.long.byte 0x4 24.--31. 1. "RESERVED" bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "TIMERMGR_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which banks contain expired timers." hexmask.long 0x8 0.--31. 1. "VAL,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "TIMERMGR_STATUS_y,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out Offset = 100h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "VAL,Each bit is the timeout status for an individual timer" tree.end tree "NAVSS0_TIMERMGR0_CFG_OES" base ad:0x30F00000 group.long 0x0++0x3 line.long 0x0 "TIMERMGR_EVENTIDX_y,This programs the event index for a given timer Offset = 0h + (y * 4h); where y = 0h to 3FFh" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "VAL,The event index for a given timer to be used on the output event interface" tree.end tree "NAVSS0_TIMERMGR0_CFG_TIMERS" base ad:0x32200000 group.long 0x0++0x7 line.long 0x0 "TIMERMGR_SETUP_j_k,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via and Offset = 0h + (j * 1000h) + (k *.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "TIMERMGR_CONTROL_j_k,Modifies the behavior of timer N with control signals below Offset = 4h + (j * 1000h) + (k * 100h); where j = 0h to 3Fh. k = 0h to Fh" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "AUTORESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" hexmask.long.byte 0x4 3.--7. 1. "RESERVED" rbitfld.long 0x4 2. "EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMERMGR_SETUP_j_k register. Will always read 0" "0,1" bitfld.long 0x4 0. "ENABLE,Write 1 to enable 0 to disable the timer." "0,1" tree.end tree "NAVSS0_TIMERMGR1_CFG" base ad:0x30E81000 rgroup.long 0x0++0x3 line.long 0x0 "TIMERMGR_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space Reset = 66F8 B100h" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version number" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision number" group.long 0x4++0x3 line.long 0x0 "TIMERMGR_CNTL,This register controls the overall behavior of the timer manager module" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED" bitfld.long 0x0 12. "MASS_ENABLE,Always reads zero. When a 1 is written to this bit all timers from 0 to the MAX_TIMER will be enabled. Useful for initial programming to not need to loop over every TIMERMGR_CONTROL_j_k register to enable every timer if many or all are.." "0,1" bitfld.long 0x0 11. "RESERVED" "0,1" hexmask.long.word 0x0 1.--10. 1. "MAX_TIMER,The maximum timer that will be checked - e.g. if only using 512 timers set this to 511. All timers above this number will be ignored. Should be set once during initialization" newline bitfld.long 0x0 0. "ENABLE,Enables the timer manager. When this bit is zero the timers will all be halted and will not count 0h = Timer Manager is disabled 1h = Timer Manager is enabled" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "TIMERMGR_COUNTER,This register contains the current value" hexmask.long 0x0 0.--31. 1. "VAL,The current timer_counter value in the timebase being used by all timers in this module" rgroup.long 0xA0++0xB line.long 0x0 "TIMERMGR_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires. It indicates the total number of timers that have expired and the ID of the first timer to expire. If NUM_EXPIRED_TIMERS is 1. this is the only register that needs.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED" bitfld.long 0x0 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer. If num_expired_timers &gt; 0 this should always be a 1" "0,1" hexmask.long.word 0x0 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire" hexmask.long.word 0x0 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers" line.long 0x4 "TIMERMGR_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire. It is indended as a more efficient way of finding the first few timers to expire rather than needing to read the status of all 1024 timers." hexmask.long.byte 0x4 24.--31. 1. "RESERVED" bitfld.long 0x4 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1" hexmask.long.word 0x4 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire" bitfld.long 0x4 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire" line.long 0x8 "TIMERMGR_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0. When servicing the timer interrupt. if the num_expired_timers bit is greater than 3. this register may be read to see which banks contain expired timers." hexmask.long 0x8 0.--31. 1. "VAL,A 1 in bit N indicates that the corresponding bank has expired timers" rgroup.long 0x100++0x3 line.long 0x0 "TIMERMGR_STATUS_y,Each bit is the timeout status for an individual timer. 0 = timer has not timed out or is disabled. 1 = timer has timed out Offset = 100h + (y * 4h); where y = 0h to 1Fh" hexmask.long 0x0 0.--31. 1. "VAL,Each bit is the timeout status for an individual timer" tree.end tree "NAVSS0_TIMERMGR1_CFG_OES" base ad:0x30F01000 group.long 0x0++0x3 line.long 0x0 "TIMERMGR_EVENTIDX_y,This programs the event index for a given timer Offset = 0h + (y * 4h); where y = 0h to 3FFh" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "VAL,The event index for a given timer to be used on the output event interface" tree.end tree "NAVSS0_TIMERMGR1_CFG_TIMERS" base ad:0x32240000 group.long 0x0++0x7 line.long 0x0 "TIMERMGR_SETUP_j_k,This reprograms timer N with the written value. This number will be the number of ticks of the timer_clock before the timer expires. if timer N and the timer manager itself are both enabled via and Offset = 0h + (j * 1000h) + (k *.." hexmask.long 0x0 0.--31. 1. "COUNT,The number of ticks of the timer_clock before this timer would expire when reprogrammed" line.long 0x4 "TIMERMGR_CONTROL_j_k,Modifies the behavior of timer N with control signals below Offset = 4h + (j * 1000h) + (k * 100h); where j = 0h to 3Fh. k = 0h to Fh" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED" bitfld.long 0x4 8. "AUTORESET,Automatically reset the timer when it expires. Provides the option of a periodic timer rather than one that needs to be cleared after each expiration. Added for hardware usage of the timers so the expirations can occur regularly without.." "0,1" hexmask.long.byte 0x4 3.--7. 1. "RESERVED" rbitfld.long 0x4 2. "EXPIRED,The status of the current timer. 1 = expired" "?,1: expired" bitfld.long 0x4 1. "SET,This may be used to touch/set a timer. When a 1 is written the corresponding timer will be refreshed with the current value in its TIMERMGR_SETUP_j_k register. Will always read 0" "0,1" bitfld.long 0x4 0. "ENABLE,Write 1 to enable 0 to disable the timer." "0,1" tree.end tree.end tree "NAVSS0_UDMASS" tree "NAVSS0_UDMASS_INTA0_CFG" base ad:0x30802000 rgroup.quad 0x0++0x17 line.quad 0x0 "UDMA_INTA_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.long 0x0 32.--63. 1. "RESERVED" hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revisioн" bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "UDMA_INTA_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.long 0x8 32.--63. 1. "RESERVED" hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers. NOTE: This value is 600h for MCU_NAVSS0_UDMASS_INTR_AGGR0" line.quad 0x10 "UDMA_INTA_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "RESERVED" hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers NOTE: This value is 100h for MCU_NAVSS0_UDMASS_INTR_AGGR0" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers NOTE: This value is 80h for MCU_NAVSS0_UDMASS_INTR_AGGR0" tree.end tree "NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" base ad:0x31040000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_MAP_j,The Global Event Mapping register controls the egress global event index for this event count. Offset =0h + (j * 20h); where j = 0h to 1FFh for NAVSS0_UDMASS_INTA0_CFG_GCNTCFG j = 0h to FFh for MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" hexmask.quad 0x0 16.--63. 1. "RESERVED" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end tree "NAVSS0_UDMASS_INTA0_CFG_GCNTRTI" base ad:0x33800000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_COUNT_j,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a count has been processed by the.." hexmask.quad.long 0x0 32.--63. 1. "RESERVED" hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end tree "NAVSS0_UDMASS_INTA0_CFG_IMAP" base ad:0x30940000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_IMAP_j,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto. Offset = 0h + (j * 8h); where j = 0h to 11FFh for NAVSS0_UDMASS_INTA0_CFG_IMAP j = 0h to 5FFh for.." hexmask.quad 0x0 17.--63. 1. "RESERVED" hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." bitfld.quad 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end tree "NAVSS0_UDMASS_INTA0_CFG_INTR" base ad:0x33D00000 group.quad 0x0++0x1F line.quad 0x0 "UDMA_INTA_ENABLE_SET_j,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output. Offset.." hexmask.quad 0x0 0.--63. 1. "ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "UDMA_INTA_ENABLE_CLEAR_j,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output." hexmask.quad 0x8 0.--63. 1. "ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "UDMA_INTA_STATUS_SET_j,The Interrupt Status register is read by software to determine the cause of an interrupt. Offset = 10h + (j * 1000h); where j = 0h to FFh" hexmask.quad 0x10 0.--63. 1. "STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "UDMA_INTA_STATUS_CLEAR_j,The Interrupt Status register is read by software to determine the cause of an interrupt. Offset = 18h + (j * 1000h); where j = 0h to FFh" hexmask.quad 0x18 0.--63. 1. "STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" rgroup.quad 0x20++0x7 line.quad 0x0 "UDMA_INTA_STATUSM_j,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt. Offset = 20h + (j * 1000h); where j = 0h to FFh" hexmask.quad 0x0 0.--63. 1. "STATUS,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end tree "NAVSS0_UDMASS_INTA0_CFG_L2G" base ad:0x31100000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_MAP_j,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event count is determined by.." hexmask.quad.long 0x0 32.--63. 1. "RESERVED" bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 16.--30. 1. "RESERVED" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end tree "NAVSS0_UDMASS_INTA0_CFG_MCAST" base ad:0x31110000 group.quad 0x0++0x7 line.quad 0x0 "UDMA_INTA_MCMAP_j,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this register. which is selected.." hexmask.quad.word 0x0 48.--63. 1. "RESERVED" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." hexmask.quad.word 0x0 16.--31. 1. "RESERVED" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end tree "NAVSS0_UDMASS_PSILCFG0_CFG_PROXY" base ad:0x31F78000 rgroup.long 0x0++0x3 line.long 0x0 "PSIL_CFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x10++0x3 line.long 0x0 "PSIL_CFG_PROXY_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a configuration access. Once set this bit is persistent until manually cleared." "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a configuration read or write transaction and asserting the TOUT bit" group.long 0x100++0xB line.long 0x0 "PSIL_CFG_PROXY_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "BUSY,Indication that a configuration read or write is in progress 0h = No transaction is in progress 1h = Transaction is in progress" "0,1" bitfld.long 0x0 30. "DIR,Direction of configuration transaction 0h = Write transaction 1h = Read transaction" "0,1" bitfld.long 0x0 29. "TO,Indication that a timeout occurred. This bit should be written to 0h on each new transaction. 0h = Transaction completed normally 1h = Timeout occurred" "0,1" hexmask.long.word 0x0 16.--28. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "THREAD_ID,Thread ID to which configuration read or write is being sent. The thread ID mapping is shown in" line.long 0x4 "PSIL_CFG_PROXY_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 16.--27. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "ADDRESS,Word (32-bit) address within thread configuration space for transaction 0h = Peer thread ID register ( 1h = Peer credit register ( 2h = Enable register ( 40h = Capabilities register ( 400h = Static TR register" line.long 0x8 "PSIL_CFG_PROXY_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "WDATA,Configuration data word to be written" group.long 0x140++0x3 line.long 0x0 "PSIL_CFG_PROXY_RDATA,The Read Data Register contains the data which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "RDATA,Configuration data word that was read" tree.end tree "NAVSS0_UDMASS_RINGACC0_CFG" base ad:0x31080000 group.long 0x40++0x13 line.long 0x0 "RINGACC_BA_LO_J,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or to.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "RINGACC_BA_HI_j,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or to.." hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "RINGACC_SIZE_j,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue. 0h = exposed ring mode for SW direct access 1h = messaging mode when all operations are through bus accesses allowing multiple producers or consumers. 2h = credentials mode is message mode plus stores.." "0,1,2,3" bitfld.long 0x8 27.--29. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "0: 4 bytes,1: 8 bytes,2: 16 bytes,3: 32 bytes,4: 64 bytes,5: 128 bytes,6: 256 bytes,7: RESERVED" hexmask.long.byte 0x8 20.--23. 1. "RESERVED" newline hexmask.long.tbyte 0x8 0.--19. 1. "ELCNT,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "RINGACC_EVENT_j,The Ring Event Register contains the event number for the ring for when it is active or empty. Offset = 4Ch + (j * 100h); where j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "EVENT,Defines the event for this ring or queue." line.long 0x10 "RINGACC_ORDERID_j,The Ring OrderID Register contains the bus orderid value for the ring memory access. Offset = 50h + (j * 100h); where j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG j = 0h to 11Dh for MCU_NAVSS0_UDMASS_RINGACC0_CFG" hexmask.long 0x10 5.--31. 1. "RESERVED" bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end tree "NAVSS0_UDMASS_RINGACC0_CFG_MON" base ad:0x32000000 group.long 0x0++0xF line.long 0x0 "RINGACC_CONTROL_j,Monitor Control Register Offset = 0h + (j * 1000h); where j = 0h to 1Fh" hexmask.long.word 0x0 16.--31. 1. "EVT,Event to produce." hexmask.long.byte 0x0 12.--15. 1. "RESERVED" hexmask.long.byte 0x0 8.--11. 1. "SOURCE,Monitor source selection. 0 = element count 1 = reserved 2 = reseved" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" bitfld.long 0x0 0.--2. "MODE,Monitor Mode. 0 = disabled. 1 = push/pop statistics capture. 2 = low/high threshold checks. 3 = low/high watermarking. 4 = starvation counting." "0: disabled,1: push/pop statistics capture,2: low/high threshold checks,3: low/high watermarking,4: starvation counting,?,?,?" line.long 0x4 "RINGACC_QUEUE_j,Monitor Queue Register Offset = 4h + (j * 1000h); where j = 0h to 1Fh" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VAL,Queue to monitor." line.long 0x8 "RINGACC_DATA0_j,Monitor Data Register Offset = 8h + (j * 1000h); where j = 0h to 1Fh" hexmask.long 0x8 0.--31. 1. "VAL,Monitor Data. For mode 1 this is read-only and number of pushes. For mode 2 this is read-write and the low threshold value. For mode 3 this is read only and the low watermark. For mode 4 this is read only and the starvation count." line.long 0xC "RINGACC_DATA1_j,Monitor Data Register Offset = Ch + (j * 1000h); where j = 0h to 1Fh" hexmask.long 0xC 0.--31. 1. "VAL,Monitor Data. For mode 1 this is read-only and number of pops. For mode 2 this is read-write and the high threshold value. For mode 3 this is read only and the high watermark. For mode 4 this is not used." tree.end tree "NAVSS0_UDMASS_RINGACC0_CFG_RT" base ad:0x3C000000 wgroup.long 0x10++0x3 line.long 0x0 "RINGACC_DB_j,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation. Offset = 10h + (j *.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ absolute.." rgroup.long 0x18++0xF line.long 0x0 "RINGACC_OCC_j,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be used for.." hexmask.long.word 0x0 21.--31. 1. "RESERVED" hexmask.long.tbyte 0x0 0.--20. 1. "CNT,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "RINGACC_INDX_j,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel. Offset = 1Ch + (j * 1000h); where j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT j = 0h to.." hexmask.long.word 0x4 20.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--19. 1. "IDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "RINGACC_HWOCC_j,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the.." hexmask.long.word 0x8 21.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--20. 1. "CNT,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "RINGACC_HWINDX_j,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel. Offset = 24h + (j * 1000h); where j = 0h to 331h for NAVSS0_UDMASS_RINGACC0_CFG_RT j = 0h.." hexmask.long.word 0xC 20.--31. 1. "RESERVED" hexmask.long.tbyte 0xC 0.--19. 1. "IDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end tree "NAVSS0_UDMASS_RINGACC0_GCFG" base ad:0x31160000 rgroup.long 0x0++0x3 line.long 0x0 "RINGACC_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision - for this device." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x10++0x3 line.long 0x0 "RINGACC_TRACE_CTL,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" hexmask.long.word 0x0 16.--28. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." group.long 0x20++0x3 line.long 0x0 "RINGACC_OVRFLOW,Overflow Queue Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages." group.long 0x40++0x3 line.long 0x0 "RINGACC_ERROR_EVT,Error Event Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "RINGACC_ERROR_LOG,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event is pending." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 16.--30. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end tree "NAVSS0_UDMASS_RINGACC0_SRC_FIFOS" base ad:0x38000000 group.long 0x0++0x3 line.long 0x0 "RINGACC_RINGHEADDATA_j_y,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head. These registers are virtual and non-static (i.e. they are just address locations that are used to access the ring.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head element data" group.long 0x200++0x3 line.long 0x0 "RINGACC_RINGTAILDATA_j_y,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail. These registers are virtual and non-static (i.e. they are just address locations that are used to access the ring.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring tail element data" group.long 0x400++0x3 line.long 0x0 "RINGACC_PEEKHEADDATA_j_y,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are used to.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring head element data. Not supported in ring mode." group.long 0x600++0x3 line.long 0x0 "RINGACC_PEEKTAILDATA_j_y,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element. These registers are virtual and non-static (i.e. they are just address locations that are used to.." hexmask.long 0x0 0.--31. 1. "DATA,Block of ring tail element data. Not supported in ring mode." tree.end tree "NAVSS0_UDMASS_UDMAP0_CFG" base ad:0x31150000 rgroup.long 0x0++0x3 line.long 0x0 "UDMA_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision" bitfld.long 0x0 8.--10. "REVMAJ,Major" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor" group.long 0x4++0x7 line.long 0x0 "UDMA_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1.." line.long 0x4 "UDMA_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" group.long 0x10++0x3 line.long 0x0 "UDMA_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" group.long 0x1C++0x3 line.long 0x0 "UDMA_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs ." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC" rgroup.long 0x20++0xB line.long 0x0 "UDMA_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports." hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" newline bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" newline bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" newline bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" newline bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "UDMA_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports." hexmask.long 0x4 4.--31. 1. "RESERVED" bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "UDMA_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports." hexmask.long.byte 0x8 27.--31. 1. "RESERVED" hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x8 9.--17. 1. "ECHAN_CNT,Tx external channel count" hexmask.long.word 0x8 0.--8. 1. "TCHAN_CNT,Tx internal channel count" rgroup.word 0x2C++0x1 line.word 0x0 "UDMA_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports." hexmask.word 0x0 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" group.long 0x80++0x3 line.long 0x0 "UDMA_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" group.long 0x88++0x3 line.long 0x0 "UDMA_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected until the pend bit is.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" bitfld.long 0x0 30. "RESERVED" "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.byte 0x0 9.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end tree "NAVSS0_UDMASS_UDMAP0_CFG_RCHAN" base ad:0x30C00000 group.long 0x0++0x3 line.long 0x0 "UDMA_RCFG_j,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0). Offset = 0h + (j * 100h); where.." bitfld.long 0x0 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." hexmask.long.byte 0x0 26.--30. 1. "RESERVED" newline bitfld.long 0x0 24.--25. "ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate to.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" hexmask.long.byte 0x0 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x0 16.--19. 1. "CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED 1 =.." bitfld.long 0x0 15. "IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Short packets are treated as.." "0: Short packets are treated as exceptions and..,1: Short packets are ignored and the TR will.." newline bitfld.long 0x0 14. "IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." hexmask.long.byte 0x0 0.--6. 1. "FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." group.long 0x14++0x3 line.long 0x0 "UDMA_RCQ_j,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode. This register may only be written when the channel is disabled.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." group.long 0x20++0x3 line.long 0x0 "UDMA_ROES_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" group.long 0x60++0xB line.long 0x0 "UDMA_REOES_j,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the corresponding register will be.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "UDMA_RPRI_CTRL_j,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface. Offset = 64h + (j * 100h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN j = 0h to 2Fh for.." bitfld.long 0x4 31. "RESERVED" "0,1" bitfld.long 0x4 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 19.--27. 1. "RESERVED" bitfld.long 0x4 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 4.--15. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "UDMA_THREAD_j,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register. Offset = 68h.." hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." group.long 0x80++0x3 line.long 0x0 "UDMA_RST_SCHED_j,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this register.." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority 3.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." group.long 0xF0++0x3 line.long 0x0 "UDMA_RFLOW_RNG_j,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel. Offset = F0h + (j * 100h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHAN j =.." bitfld.long 0x0 31. "RESERVED" "0,1" hexmask.long.word 0x0 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel. A value of 0 indicates that no flow IDs other than the default are allowed for the channel.." newline bitfld.long 0x0 14.--15. "RESERVED" "0,1,2,3" hexmask.long.word 0x0 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range.." tree.end tree "NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT" base ad:0x34000000 group.long 0x0++0x3 line.long 0x0 "UDMA_RRT_CTL_j,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation. Offset = 0h + (j * 1000h); where j = 0h.." bitfld.long 0x0 31. "EN,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the attached.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "FTDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set teh implementation may choose to bypass data transfers and event generation. This bit is a modifier to the normal rx_teardown.." "0,1" newline hexmask.long 0x0 1.--27. 1. "RESERVED" rbitfld.long 0x0 0. "ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" wgroup.long 0x8++0x3 line.long 0x0 "UDMA_RRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the rx_chan_type is configured as a Third Party DMA channel. This register has no.." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" group.long 0x80++0x3 line.long 0x0 "UDMA_RRT_STDATA_j_y,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the channel." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" group.long 0x200++0x3F line.long 0x0 "UDMA_RRT_PEER0_j,This register provides access to the remote peer's realtime register at 0x400. Offset = 200h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "UDMA_RRT_PEER1_j,This register provides access to the remote peer's realtime register at 0x401. Offset = 204h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "UDMA_RRT_PEER2_j,This register provides access to the remote peer's realtime register at 0x402. Offset = 208h + (j * 1000h); where j = 0h to 95h j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "UDMA_RRT_PEER3_j,This register provides access to the remote peer's realtime register at 0x403. Offset = 20Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "UDMA_RRT_PEER4_j,This register provides access to the remote peer's realtime register at 0x404. Offset = 210h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "UDMA_RRT_PEER5_j,This register provides access to the remote peer's realtime register at 0x405. Offset = 214h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "UDMA_RRT_PEER6_j,This register provides access to the remote peer's realtime register at 0x406. Offset = 218h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "UDMA_RRT_PEER7_j,This register provides access to the remote peer's realtime register at 0x407. Offset = 21Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "UDMA_RRT_PEER8_j,This register provides access to the remote peer's realtime register at 0x408. Offset = 220h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "UDMA_RRT_PEER9_j,This register provides access to the remote peer's realtime register at 0x409. Offset = 224h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "UDMA_RRT_PEER10_j,This register provides access to the remote peer's realtime register at 0x40A. Offset = 228h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "UDMA_RRT_PEER11_j,This register provides access to the remote peer's realtime register at 0x40B. Offset = 22Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "UDMA_RRT_PEER12_j,This register provides access to the remote peer's realtime register at 0x40C. Offset = 230h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "UDMA_RRT_PEER13_j,This register provides access to the remote peer's realtime register at 0x40D. Offset = 234h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "UDMA_RRT_PEER14_j,This register provides access to the remote peer's realtime register at 0x40E. Offset = 238h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "UDMA_RRT_PEER15_j,This register provides access to the remote peer's realtime register at 0x40F. Offset = 23Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." group.long 0x400++0x3 line.long 0x0 "UDMA_RRT_PCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 400h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." group.long 0x408++0x3 line.long 0x0 "UDMA_RRT_BCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 408h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "UDMA_RRT_SBCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 410h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree "NAVSS0_UDMASS_UDMAP0_CFG_RFLOW" base ad:0x30D00000 group.long 0x0++0x1F line.long 0x0 "UDMA_RFA_j,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." bitfld.long 0x0 31. "RESERVED" "0,1" bitfld.long 0x0 30. "EINFO,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in the PD and.." "0,1" newline bitfld.long 0x0 29. "PSINFO,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words that are.." "0,1" bitfld.long 0x0 28. "ERR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs): 0 = Starvation errors result in dropping packet and reclaiming any used.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in subsequent re-try of.." newline bitfld.long 0x0 26.--27. "DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use: 0 = Host 1 = RESERVED 2 = Monolithic 3 = RESERVED" "0: Host,1: RESERVED,2: Monolithic,3: RESERVED" bitfld.long 0x0 25. "PS_LOC,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure. If this bit is cleared the DMA will clear the Protocol Specific Region Location bit in the PD and will place the.." "0,1" newline hexmask.long.word 0x0 16.--24. 1. "SOP_OFF,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the minimum.." hexmask.long.word 0x0 0.--15. 1. "DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto." line.long 0x4 "UDMA_RFB_j,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." hexmask.long.byte 0x4 24.--31. 1. "SRCTAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1." hexmask.long.byte 0x4 16.--23. 1. "SRCTAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1." newline hexmask.long.byte 0x4 8.--15. 1. "DSTTAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1." hexmask.long.byte 0x4 0.--7. 1. "DSTTAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1." line.long 0x8 "UDMA_RFC_j,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." bitfld.long 0x8 31. "RESERVED" "0,1" bitfld.long 0x8 28.--30. "SRCTAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,7: 0 of the source tag field in Word 3 of the.." newline bitfld.long 0x8 27. "RESERVED" "0,1" bitfld.long 0x8 24.--26. "SRCTAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in.." "0: do not overwrite,1: overwrite with value given in rx_src_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with src_tag[7:0] from back end..,?,?,7: 0 of the source tag field in Word 3 of the.." newline bitfld.long 0x8 23. "RESERVED" "0,1" bitfld.long 0x8 20.--22. "DSTTAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_hi,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,?" newline bitfld.long 0x8 19. "RESERVED" "0,1" bitfld.long 0x8 16.--18. "DSTTAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given.." "0: do not overwrite,1: overwrite with value given in rx_dest_tag_lo,2: overwrite with flow_id[7:0] from back end..,3: RESERVED,4: overwrite with dest_tag[7:0] from back end..,5: overwrite with dest_tag[15:8] from back end..,?,7: 0 of the destination tag field in word 3 of the.." newline hexmask.long.word 0x8 3.--15. 1. "RESERVED" bitfld.long 0x8 0.--2. "SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the SOP.." "0: Do not use the threshold,1: Use the thresholds to select between the 4..,?,?,?,?,?,?" line.long 0xC "UDMA_RFD_j,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." hexmask.long.word 0xC 16.--31. 1. "FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size 0: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value." hexmask.long.word 0xC 0.--15. 1. "FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet" line.long 0x10 "UDMA_RFE_j,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in this.." hexmask.long.word 0x10 16.--31. 1. "FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet" hexmask.long.word 0x10 0.--15. 1. "FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet" line.long 0x14 "UDMA_RFF_j,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is.." hexmask.long.word 0x14 16.--31. 1. "SIZE_THRESH0,Rx Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the.." hexmask.long.word 0x14 0.--15. 1. "SIZE_THRESH1,Rx Packet Size Threshold 1: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the.." line.long 0x18 "UDMA_RFG_j,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is.." hexmask.long.word 0x18 16.--31. 1. "SIZE_THRESH2,Rx Packet Size Threshold 2: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the.." hexmask.long.word 0x18 0.--15. 1. "FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size 1: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value. This field is optional." line.long 0x1C "UDMA_RFH_j,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. This register is.." hexmask.long.word 0x1C 16.--31. 1. "FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size 2: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size1 value. This field is optional." hexmask.long.word 0x1C 0.--15. 1. "FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size 3: This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value. This field is optional." tree.end tree "NAVSS0_UDMASS_UDMAP0_CFG_TCHAN" base ad:0x30B00000 group.long 0x0++0x7 line.long 0x0 "UDMA_TCFG_j,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0). Offset = 0h + (j * 100h); where.." bitfld.long 0x0 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." bitfld.long 0x0 30. "FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended packet.." "0: DMA controller will pass extended packet info..,1: DMA controller will filter extended packet info.." newline bitfld.long 0x0 29. "FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,1: DMA controller will filter PS words" bitfld.long 0x0 26.--28. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--25. "ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate to.." "0: Pointers are physical addresses,1: Pointers are intermediate addresses which..,2: Pointers are virtual addresses which require..,?" hexmask.long.byte 0x0 20.--23. 1. "RESERVED" newline hexmask.long.byte 0x0 16.--19. 1. "CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED 1 =.." bitfld.long 0x0 8. "NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" newline bitfld.long 0x0 7. "RESERVED" "0,1" hexmask.long.byte 0x0 0.--6. 1. "FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type." line.long 0x4 "UDMA_TCREDIT_j,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This field should not be changed.." hexmask.long 0x4 3.--31. 1. "RESERVED" bitfld.long 0x4 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received." "0,1,2,3,4,5,6,7" group.long 0x14++0x3 line.long 0x0 "UDMA_TCQ_j,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel is disabled (tx_enable in.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to." group.long 0x20++0x3 line.long 0x0 "UDMA_TOES_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" group.long 0x60++0xB line.long 0x0 "UDMA_TEOES_j,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the corresponding register will be.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated" line.long 0x4 "UDMA_TPRI_CTRL_j,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface. Offset = 64h + (j * 100h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN j = 0h to 2Fh for.." bitfld.long 0x4 31. "RESERVED" "0,1" bitfld.long 0x4 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 19.--27. 1. "RESERVED" bitfld.long 0x4 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 4.--15. 1. "RESERVED" hexmask.long.byte 0x4 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x8 "UDMA_THREAD_j,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register. Offset = 68h.." hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." group.long 0x70++0x3 line.long 0x0 "UDMA_TFIFO_DEPTH_j,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be artificially reduced in.." group.long 0x80++0x3 line.long 0x0 "UDMA_TST_SCHED_j,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this register.." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority 3.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end tree "NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT" base ad:0x35000000 group.long 0x0++0x3 line.long 0x0 "UDMA_TRT_CTL_j,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation. Offset = 0h + (j * 1000h); where j = 0h.." bitfld.long 0x0 31. "EN,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the attached.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 28. "FTDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the normal tx_teardown.." "0,1" newline hexmask.long 0x0 1.--27. 1. "RESERVED" rbitfld.long 0x0 0. "ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" wgroup.long 0x8++0x3 line.long 0x0 "UDMA_TRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register has no.." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "UDMA_TRT_STDATA_j_Y,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the channel." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" group.long 0x200++0x3F line.long 0x0 "UDMA_TRT_PEER0_j,This register provides access to the remote peer's realtime register at 0x400. Offset = 200h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "UDMA_TRT_PEER1_j,This register provides access to the remote peer's realtime register at 0x401. Offset = 204h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "UDMA_TRT_PEER2_j,This register provides access to the remote peer's realtime register at 0x402. Offset = 208h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "UDMA_TRT_PEER3_j,This register provides access to the remote peer's realtime register at 0x403. Offset = 20Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "UDMA_TRT_PEER4_j,This register provides access to the remote peer's realtime register at 0x404. Offset = 210h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "UDMA_TRT_PEER5_j,This register provides access to the remote peer's realtime register at 0x405. Offset = 214h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "UDMA_TRT_PEER6_j,This register provides access to the remote peer's realtime register at 0x406. Offset = 218h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "UDMA_TRT_PEER7_j,This register provides access to the remote peer's realtime register at 0x407. Offset = 21Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "UDMA_TRT_PEER8_j,This register provides access to the remote peer's realtime register at 0x408. Offset = 220h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "UDMA_TRT_PEER9_j,This register provides access to the remote peer's realtime register at 0x409. Offset = 224h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "UDMA_TRT_PEER10_j,This register provides access to the remote peer's realtime register at 0x40A. Offset = 228h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "UDMA_TRT_PEER11_j,This register provides access to the remote peer's realtime register at 0x40B. Offset = 22Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "UDMA_TRT_PEER12_j,This register provides access to the remote peer's realtime register at 0x40C. Offset = 230h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "UDMA_TRT_PEER13_j,This register provides access to the remote peer's realtime register at 0x40D. Offset = 234h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "UDMA_TRT_PEER14_j,This register provides access to the remote peer's realtime register at 0x40E. Offset = 238h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "UDMA_TRT_PEER15_j,This register provides access to the remote peer's realtime register at 0x40F. Offset = 23Ch + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." group.long 0x400++0x3 line.long 0x0 "UDMA_TRT_PCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 400h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." group.long 0x408++0x3 line.long 0x0 "UDMA_TRT_BCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 408h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "UDMA_TRT_SBCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel. Offset = 410h + (j * 1000h); where j = 0h to for NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT j = 0h to 2Fh for.." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree.end tree.end tree "NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS" base ad:0x3810000 rgroup.long 0x0++0x3 line.long 0x0 "VIRTID_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" group.long 0x10++0x3 line.long 0x0 "VIRTID_WINDOW_y,The VirtID for window y. Offset = 30A02010h + (y * 4h); where y = 0h to Fh" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--11. 1. "VIRTID,VirtID for window y" tree.end tree "PCIE" base ad:0x0 tree "PCIE1_CORE_CPTS_CFG_CPTS_VBUSP" base ad:0x2916000 rgroup.long 0x0++0x3 line.long 0x0 "PCIE_CPTS_IDVER_REG,Identification and Version Register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x8++0x3 line.long 0x0 "PCIE_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register" hexmask.long 0x0 5.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "RFTCLK_SEL,Reference clock select" wgroup.long 0xC++0x3 line.long 0x0 "PCIE_CPTS_TS_PUSH_REG,Time Stamp Event Push Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1" group.long 0x10++0x3 line.long 0x0 "PCIE_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value" wgroup.long 0x14++0x3 line.long 0x0 "PCIE_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1" group.long 0x18++0xB line.long 0x0 "PCIE_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register" hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value" line.long 0x4 "PCIE_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length" line.long 0x8 "PCIE_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "PCIE_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" group.long 0x28++0x7 line.long 0x0 "PCIE_CPTS_INT_ENABLE_REG,Interrupt Enable Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" line.long 0x4 "PCIE_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount" wgroup.long 0x30++0x3 line.long 0x0 "PCIE_CPTS_EVENT_POP_REG,Event Pop Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1" rgroup.long 0x34++0xF line.long 0x0 "PCIE_CPTS_EVENT_0_REG,Event 0 Register" hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp" line.long 0x4 "PCIE_CPTS_EVENT_1_REG,Event 1 Register" bitfld.long 0x4 30.--31. "RESERVED" "0,1,2,3" bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1" hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number" hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type" newline hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type" hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID" line.long 0x8 "PCIE_CPTS_EVENT_2_REG,Event 2 Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain" line.long 0xC "PCIE_CPTS_EVENT_3_REG,Event 3 Register" hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp" group.long 0x44++0x17 line.long 0x0 "PCIE_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register" hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value" line.long 0x4 "PCIE_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register" hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value" line.long 0x8 "PCIE_CPTS_TS_ADD_VAL_REG,TS Add Value Register" hexmask.long 0x8 3.--31. 1. "RESERVED" bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7" line.long 0xC "PCIE_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register" hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value" line.long 0x10 "PCIE_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value" line.long 0x14 "PCIE_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value" group.long 0x200++0x1B line.long 0x0 "PCIE_CPTS_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value" hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value" line.long 0x4 "PCIE_CPTS_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value" hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value" line.long 0x8 "PCIE_CPTS_CONTROL_REG,Time Sync Control Register" hexmask.long.byte 0x8 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" hexmask.long.word 0x8 18.--27. 1. "RESERVED" bitfld.long 0x8 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1" bitfld.long 0x8 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1" newline bitfld.long 0x8 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1" bitfld.long 0x8 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1" bitfld.long 0x8 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1" bitfld.long 0x8 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1" newline bitfld.long 0x8 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" bitfld.long 0x8 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x8 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" bitfld.long 0x8 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" newline bitfld.long 0x8 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1" bitfld.long 0x8 6. "TS_COMP_TOG,Timestamp Compare Toggle mode:" "0,1" bitfld.long 0x8 5. "MODE,Timestamp mode" "0,1" bitfld.long 0x8 4. "SEQUENCE_EN,Sequence Enable" "0,1" newline bitfld.long 0x8 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1" bitfld.long 0x8 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1" bitfld.long 0x8 1. "INT_TEST,Interrupt test" "0,1" bitfld.long 0x8 0. "CPTS_EN,Time sync enable" "0,1" line.long 0xC "PCIE_CPTS_LENGTH_REG,Time Stamp Generate Function Length Value" hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value" line.long 0x10 "PCIE_CPTS_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value" hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value" line.long 0x14 "PCIE_CPTS_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value" line.long 0x18 "PCIE_CPTS_NUDGE_REG,Time Stamp Generate Function Nudge Value" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value" tree.end tree "PCIE1_CORE_DBN_CFG_PCIE_CORE" base ad:0xD800000 group.long 0x400000++0xF line.long 0x0 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to the . Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through Offset = 400000h + (i * 20h); where i = 0h to 1Fh" hexmask.long.tbyte 0x0 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N" rbitfld.long 0x0 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x4 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to the . Provides bits 63:32 of the PCIe address Offset = 400004h + (i * 20h); where i = 0h to 1Fh" hexmask.long 0x4 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x8 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to the . Provides bits 31:0 of the Outbound PCIe Descriptor Offset = 400008h + (i * 20h); where i = 0h to 1Fh" hexmask.long 0x8 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0xC "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to the . Provides bits 63:32 of the PCIe Descriptor Offset = 40000Ch + (i * 20h); where i = 0h to 1Fh" hexmask.long 0xC 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" group.long 0x400014++0xB line.long 0x0 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to the . Provides PASID Value and The present bit Offset = 400014h + (i * 20h); where i = 0h to 1Fh" hexmask.long.word 0x0 23.--31. 1. "RSVD,reserved" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to the . holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability Offset = 400018h + (i * 20h); where i = 0h to 1Fh" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region" bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to the . holds the base address [63:32] of this region. Offset = 40001Ch + (i * 20h); where i = 0h to 1Fh" hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" group.long 0x400400++0xF line.long 0x0 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to the . Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through Offset = 400400h + (i * 20h); where i = 0h to 1Fh" hexmask.long.tbyte 0x0 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N" rbitfld.long 0x0 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" line.long 0x4 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to the . Provides bits 63:32 of the PCIe address Offset = 400404h + (i * 20h); where i = 0h to 1Fh" hexmask.long 0x4 0.--31. 1. "DATA,Bits [63:32] of PCIe Address Register for region N" line.long 0x8 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to the . Provides bits 31:0 of the Outbound PCIe Descriptor Offset = 400408h + (i * 20h); where i = 0h to 1Fh" hexmask.long 0x8 0.--31. 1. "DATA,Lowest 32-bits of PCIe Descriptor Register for region N" line.long 0xC "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to the . Provides bits 63:32 of the PCIe Descriptor Offset = 40040Ch + (i * 20h); where i = 0h to 1Fh" hexmask.long 0xC 0.--31. 1. "DATA,Lower middle 32-bits of PCIe Descriptor Register for region N" group.long 0x400414++0xB line.long 0x0 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to the . Provides PASID Value and The present bit Offset = 400414h + (i * 20h); where i = 0h to 1Fh" hexmask.long.word 0x0 23.--31. 1. "RSVD,reserved" hexmask.long.tbyte 0x0 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}" line.long 0x4 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to the . Holds the base address [31:8] of this region. Lower [5:0] is used for region size programmability Offset = 400418h + (i * 20h); where i = 0h to 1Fh" hexmask.long.tbyte 0x4 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region" bitfld.long 0x4 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "REGION_SIZE,the value programmed in this field + 1 gives the region size" line.long 0x8 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to the . holds the base address [63:32] of this region. Offset = 40041Ch + (i * 20h); where i = 0h to 1Fh" hexmask.long 0x8 0.--31. 1. "DATA,Bits [63:32] of AXI outbound Base Address Register used to decode the region" group.long 0x400800++0x7 line.long 0x0 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to the . Provides bits 31:8 of the AXI Address and the number of PCIE address bits passed through Offset = 400800h + (k * 8h); where k = 0h to 2h" hexmask.long.tbyte 0x0 8.--31. 1. "DATA,Bits [31:8] of AXI Address Register for BAR N" rbitfld.long 0x0 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" line.long 0x4 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to the . Provides bits 63:32 of the AXI Address Offset = 400804h + (k * 8h); where k = 0h to 2h" hexmask.long 0x4 0.--31. 1. "DATA,Bits [63:32] of AXI Address Register for BAR N" group.long 0x400820++0x7 line.long 0x0 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to the . N/A" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.byte 0x0 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper" hexmask.long.word 0x0 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper" line.long 0x4 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to the . N/A" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1" group.long 0x400840++0x7 line.long 0x0 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to the . Provides bits 31:0 of the AXI address Offset = 400840h + (m * 40h) + (n * 8h); where m = 0 to 15h. n = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Bits [31:0] of Address Register for BAR N" line.long 0x4 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to the . Provides bits 63:32 of the AXI address Offset = 400844h + (m * 40h) + (n * 8h); where m = 0 to 15h. n = 0h to 7h" hexmask.long 0x4 0.--31. 1. "DATA,Bits [63:32] of AXI Address Register for BAR N" tree.end tree "PCIE1_CORE_ECC_AGGR0" base ad:0x2A02000 rgroup.long 0x0++0x3 line.long 0x0 "PCIE_ECC0_REV,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "PCIE_ECC0_VECTOR,ECC Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "PCIE_ECC0_STAT,Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "PCIE_ECC0_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "PCIE_ECC0_SEC_EOI_REG,EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PCIE_ECC0_SEC_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 5.--31. 1. "RESERVED" bitfld.long 0x4 4. "AXI2VBUSM_MST_PEND,Interrupt Pending Status for axi2vbusm_mst_pend" "0,1" bitfld.long 0x4 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1" bitfld.long 0x4 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "PCIE_ECC0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED" bitfld.long 0x0 4. "AXI2VBUSM_MST_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_pend" "0,1" bitfld.long 0x0 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1" bitfld.long 0x0 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "PCIE_ECC0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED" bitfld.long 0x0 4. "AXI2VBUSM_MST_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_pend" "0,1" bitfld.long 0x0 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1" bitfld.long 0x0 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "PCIE_ECC0_DED_EOI_REG,EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PCIE_ECC0_DED_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 5.--31. 1. "RESERVED" bitfld.long 0x4 4. "AXI2VBUSM_MST_PEND,Interrupt Pending Status for axi2vbusm_mst_pend" "0,1" bitfld.long 0x4 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1" bitfld.long 0x4 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "PCIE_ECC0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED" bitfld.long 0x0 4. "AXI2VBUSM_MST_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_pend" "0,1" bitfld.long 0x0 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1" bitfld.long 0x0 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "PCIE_ECC0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED" bitfld.long 0x0 4. "AXI2VBUSM_MST_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_pend" "0,1" bitfld.long 0x0 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1" bitfld.long 0x0 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1" group.long 0x200++0xF line.long 0x0 "PCIE_ECC0_AGGR_ENABLE_SET,AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "PCIE_ECC0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "PCIE_ECC0_AGGR_STATUS_SET,AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "PCIE_ECC0_AGGR_STATUS_CLR,AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PCIE1_CORE_ECC_AGGR1" base ad:0x2A03000 rgroup.long 0x0++0x3 line.long 0x0 "PCIE_ECC1_REV,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "PCIE_ECC1_VECTOR,ECC Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "PCIE_ECC1_STAT,Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "PCIE_ECC1_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "PCIE_ECC1_SEC_EOI_REG,EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PCIE_ECC1_SEC_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 4.--31. 1. "RESERVED" bitfld.long 0x4 3. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "PCIE_ECC1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "PCIE_ECC1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "PCIE_ECC1_DED_EOI_REG,EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "PCIE_ECC1_DED_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 4.--31. 1. "RESERVED" bitfld.long 0x4 3. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "PCIE_ECC1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "PCIE_ECC1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "PCIE_ECC1_AGGR_ENABLE_SET,AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "PCIE_ECC1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "PCIE_ECC1_AGGR_STATUS_SET,AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "PCIE_ECC1_AGGR_STATUS_CLR,AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG" base ad:0x2910000 rgroup.long 0x0++0x3 line.long 0x0 "PCIE_INTD_REVISION,Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor" group.long 0x10++0x3 line.long 0x0 "PCIE_INTD_EOI_REG,End of Interrupt Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "PCIE_INTD_INTR_VECTOR_REG,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" group.long 0x100++0xB line.long 0x0 "PCIE_INTD_ENABLE_REG_SYS_0,Enable Register 0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 5. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5,Enable Set for sys_en_pcie_downstream_5" "0,1" newline bitfld.long 0x0 4. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4,Enable Set for sys_en_pcie_downstream_4" "0,1" bitfld.long 0x0 3. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3,Enable Set for sys_en_pcie_downstream_3" "0,1" newline bitfld.long 0x0 2. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2,Enable Set for sys_en_pcie_downstream_2" "0,1" bitfld.long 0x0 1. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1,Enable Set for sys_en_pcie_downstream_1" "0,1" newline bitfld.long 0x0 0. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0,Enable Set for sys_en_pcie_downstream_0" "0,1" line.long 0x4 "PCIE_INTD_ENABLE_REG_SYS_1,Enable Register 1" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 26. "ENABLE_SYS_EN_PCIE_PWR_STATE,Enable Set for sys_en_pcie_pwr_state" "0,1" newline bitfld.long 0x4 25. "ENABLE_SYS_EN_PCIE_LEGACY_3,Enable Set for sys_en_pcie_legacy_3" "0,1" bitfld.long 0x4 24. "ENABLE_SYS_EN_PCIE_LEGACY_2,Enable Set for sys_en_pcie_legacy_2" "0,1" newline bitfld.long 0x4 23. "ENABLE_SYS_EN_PCIE_LEGACY_1,Enable Set for sys_en_pcie_legacy_1" "0,1" bitfld.long 0x4 22. "ENABLE_SYS_EN_PCIE_LEGACY_0,Enable Set for sys_en_pcie_legacy_0" "0,1" newline bitfld.long 0x4 21. "ENABLE_SYS_EN_PCIE_FLR_21,Enable Set for sys_en_pcie_flr_21" "0,1" bitfld.long 0x4 20. "ENABLE_SYS_EN_PCIE_FLR_20,Enable Set for sys_en_pcie_flr_20" "0,1" newline bitfld.long 0x4 19. "ENABLE_SYS_EN_PCIE_FLR_19,Enable Set for sys_en_pcie_flr_19" "0,1" bitfld.long 0x4 18. "ENABLE_SYS_EN_PCIE_FLR_18,Enable Set for sys_en_pcie_flr_18" "0,1" newline bitfld.long 0x4 17. "ENABLE_SYS_EN_PCIE_FLR_17,Enable Set for sys_en_pcie_flr_17" "0,1" bitfld.long 0x4 16. "ENABLE_SYS_EN_PCIE_FLR_16,Enable Set for sys_en_pcie_flr_16" "0,1" newline bitfld.long 0x4 15. "ENABLE_SYS_EN_PCIE_FLR_15,Enable Set for sys_en_pcie_flr_15" "0,1" bitfld.long 0x4 14. "ENABLE_SYS_EN_PCIE_FLR_14,Enable Set for sys_en_pcie_flr_14" "0,1" newline bitfld.long 0x4 13. "ENABLE_SYS_EN_PCIE_FLR_13,Enable Set for sys_en_pcie_flr_13" "0,1" bitfld.long 0x4 12. "ENABLE_SYS_EN_PCIE_FLR_12,Enable Set for sys_en_pcie_flr_12" "0,1" newline bitfld.long 0x4 11. "ENABLE_SYS_EN_PCIE_FLR_11,Enable Set for sys_en_pcie_flr_11" "0,1" bitfld.long 0x4 10. "ENABLE_SYS_EN_PCIE_FLR_10,Enable Set for sys_en_pcie_flr_10" "0,1" newline bitfld.long 0x4 9. "ENABLE_SYS_EN_PCIE_FLR_9,Enable Set for sys_en_pcie_flr_9" "0,1" bitfld.long 0x4 8. "ENABLE_SYS_EN_PCIE_FLR_8,Enable Set for sys_en_pcie_flr_8" "0,1" newline bitfld.long 0x4 7. "ENABLE_SYS_EN_PCIE_FLR_7,Enable Set for sys_en_pcie_flr_7" "0,1" bitfld.long 0x4 6. "ENABLE_SYS_EN_PCIE_FLR_6,Enable Set for sys_en_pcie_flr_6" "0,1" newline bitfld.long 0x4 5. "ENABLE_SYS_EN_PCIE_FLR_5,Enable Set for sys_en_pcie_flr_5" "0,1" bitfld.long 0x4 4. "ENABLE_SYS_EN_PCIE_FLR_4,Enable Set for sys_en_pcie_flr_4" "0,1" newline bitfld.long 0x4 3. "ENABLE_SYS_EN_PCIE_FLR_3,Enable Set for sys_en_pcie_flr_3" "0,1" bitfld.long 0x4 2. "ENABLE_SYS_EN_PCIE_FLR_2,Enable Set for sys_en_pcie_flr_2" "0,1" newline bitfld.long 0x4 1. "ENABLE_SYS_EN_PCIE_FLR_1,Enable Set for sys_en_pcie_flr_1" "0,1" bitfld.long 0x4 0. "ENABLE_SYS_EN_PCIE_FLR_0,Enable Set for sys_en_pcie_flr_0" "0,1" line.long 0x8 "PCIE_INTD_ENABLE_REG_SYS_2,Enable Register 2" hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 11. "ENABLE_SYS_EN_PCIE_PTM,Enable Set for sys_en_pcie_ptm" "0,1" newline bitfld.long 0x8 10. "ENABLE_SYS_EN_PCIE_LINK_STATE,Enable Set for sys_en_pcie_link_state" "0,1" bitfld.long 0x8 9. "ENABLE_SYS_EN_PCIE_HOT_RESET,Enable Set for sys_en_pcie_hot_reset" "0,1" newline bitfld.long 0x8 8. "ENABLE_SYS_EN_PCIE_ERROR_2,Enable Set for sys_en_pcie_error_2" "0,1" bitfld.long 0x8 7. "ENABLE_SYS_EN_PCIE_ERROR_1,Enable Set for sys_en_pcie_error_1" "0,1" newline bitfld.long 0x8 6. "ENABLE_SYS_EN_PCIE_ERROR_0,Enable Set for sys_en_pcie_error_0" "0,1" bitfld.long 0x8 5. "ENABLE_SYS_EN_PCIE_DPA_5,Enable Set for sys_en_pcie_dpa_5" "0,1" newline bitfld.long 0x8 4. "ENABLE_SYS_EN_PCIE_DPA_4,Enable Set for sys_en_pcie_dpa_4" "0,1" bitfld.long 0x8 3. "ENABLE_SYS_EN_PCIE_DPA_3,Enable Set for sys_en_pcie_dpa_3" "0,1" newline bitfld.long 0x8 2. "ENABLE_SYS_EN_PCIE_DPA_2,Enable Set for sys_en_pcie_dpa_2" "0,1" bitfld.long 0x8 1. "ENABLE_SYS_EN_PCIE_DPA_1,Enable Set for sys_en_pcie_dpa_1" "0,1" newline bitfld.long 0x8 0. "ENABLE_SYS_EN_PCIE_DPA_0,Enable Set for sys_en_pcie_dpa_0" "0,1" group.long 0x300++0xB line.long 0x0 "PCIE_INTD_ENABLE_CLR_REG_SYS_0,Enable Clear Register 0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 5. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5_CLR,Enable Clear for sys_en_pcie_downstream_5" "0,1" newline bitfld.long 0x0 4. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4_CLR,Enable Clear for sys_en_pcie_downstream_4" "0,1" bitfld.long 0x0 3. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3_CLR,Enable Clear for sys_en_pcie_downstream_3" "0,1" newline bitfld.long 0x0 2. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2_CLR,Enable Clear for sys_en_pcie_downstream_2" "0,1" bitfld.long 0x0 1. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1_CLR,Enable Clear for sys_en_pcie_downstream_1" "0,1" newline bitfld.long 0x0 0. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0_CLR,Enable Clear for sys_en_pcie_downstream_0" "0,1" line.long 0x4 "PCIE_INTD_ENABLE_CLR_REG_SYS_1,Enable Clear Register 1" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 26. "ENABLE_SYS_EN_PCIE_PWR_STATE_CLR,Enable Clear for sys_en_pcie_pwr_state" "0,1" newline bitfld.long 0x4 25. "ENABLE_SYS_EN_PCIE_LEGACY_3_CLR,Enable Clear for sys_en_pcie_legacy_3" "0,1" bitfld.long 0x4 24. "ENABLE_SYS_EN_PCIE_LEGACY_2_CLR,Enable Clear for sys_en_pcie_legacy_2" "0,1" newline bitfld.long 0x4 23. "ENABLE_SYS_EN_PCIE_LEGACY_1_CLR,Enable Clear for sys_en_pcie_legacy_1" "0,1" bitfld.long 0x4 22. "ENABLE_SYS_EN_PCIE_LEGACY_0_CLR,Enable Clear for sys_en_pcie_legacy_0" "0,1" newline bitfld.long 0x4 21. "ENABLE_SYS_EN_PCIE_FLR_21_CLR,Enable Clear for sys_en_pcie_flr_21" "0,1" bitfld.long 0x4 20. "ENABLE_SYS_EN_PCIE_FLR_20_CLR,Enable Clear for sys_en_pcie_flr_20" "0,1" newline bitfld.long 0x4 19. "ENABLE_SYS_EN_PCIE_FLR_19_CLR,Enable Clear for sys_en_pcie_flr_19" "0,1" bitfld.long 0x4 18. "ENABLE_SYS_EN_PCIE_FLR_18_CLR,Enable Clear for sys_en_pcie_flr_18" "0,1" newline bitfld.long 0x4 17. "ENABLE_SYS_EN_PCIE_FLR_17_CLR,Enable Clear for sys_en_pcie_flr_17" "0,1" bitfld.long 0x4 16. "ENABLE_SYS_EN_PCIE_FLR_16_CLR,Enable Clear for sys_en_pcie_flr_16" "0,1" newline bitfld.long 0x4 15. "ENABLE_SYS_EN_PCIE_FLR_15_CLR,Enable Clear for sys_en_pcie_flr_15" "0,1" bitfld.long 0x4 14. "ENABLE_SYS_EN_PCIE_FLR_14_CLR,Enable Clear for sys_en_pcie_flr_14" "0,1" newline bitfld.long 0x4 13. "ENABLE_SYS_EN_PCIE_FLR_13_CLR,Enable Clear for sys_en_pcie_flr_13" "0,1" bitfld.long 0x4 12. "ENABLE_SYS_EN_PCIE_FLR_12_CLR,Enable Clear for sys_en_pcie_flr_12" "0,1" newline bitfld.long 0x4 11. "ENABLE_SYS_EN_PCIE_FLR_11_CLR,Enable Clear for sys_en_pcie_flr_11" "0,1" bitfld.long 0x4 10. "ENABLE_SYS_EN_PCIE_FLR_10_CLR,Enable Clear for sys_en_pcie_flr_10" "0,1" newline bitfld.long 0x4 9. "ENABLE_SYS_EN_PCIE_FLR_9_CLR,Enable Clear for sys_en_pcie_flr_9" "0,1" bitfld.long 0x4 8. "ENABLE_SYS_EN_PCIE_FLR_8_CLR,Enable Clear for sys_en_pcie_flr_8" "0,1" newline bitfld.long 0x4 7. "ENABLE_SYS_EN_PCIE_FLR_7_CLR,Enable Clear for sys_en_pcie_flr_7" "0,1" bitfld.long 0x4 6. "ENABLE_SYS_EN_PCIE_FLR_6_CLR,Enable Clear for sys_en_pcie_flr_6" "0,1" newline bitfld.long 0x4 5. "ENABLE_SYS_EN_PCIE_FLR_5_CLR,Enable Clear for sys_en_pcie_flr_5" "0,1" bitfld.long 0x4 4. "ENABLE_SYS_EN_PCIE_FLR_4_CLR,Enable Clear for sys_en_pcie_flr_4" "0,1" newline bitfld.long 0x4 3. "ENABLE_SYS_EN_PCIE_FLR_3_CLR,Enable Clear for sys_en_pcie_flr_3" "0,1" bitfld.long 0x4 2. "ENABLE_SYS_EN_PCIE_FLR_2_CLR,Enable Clear for sys_en_pcie_flr_2" "0,1" newline bitfld.long 0x4 1. "ENABLE_SYS_EN_PCIE_FLR_1_CLR,Enable Clear for sys_en_pcie_flr_1" "0,1" bitfld.long 0x4 0. "ENABLE_SYS_EN_PCIE_FLR_0_CLR,Enable Clear for sys_en_pcie_flr_0" "0,1" line.long 0x8 "PCIE_INTD_ENABLE_CLR_REG_SYS_2,Enable Clear Register 2" hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 11. "ENABLE_SYS_EN_PCIE_PTM_CLR,Enable Clear for sys_en_pcie_ptm" "0,1" newline bitfld.long 0x8 10. "ENABLE_SYS_EN_PCIE_LINK_STATE_CLR,Enable Clear for sys_en_pcie_link_state" "0,1" bitfld.long 0x8 9. "ENABLE_SYS_EN_PCIE_HOT_RESET_CLR,Enable Clear for sys_en_pcie_hot_reset" "0,1" newline bitfld.long 0x8 8. "ENABLE_SYS_EN_PCIE_ERROR_2_CLR,Enable Clear for sys_en_pcie_error_2" "0,1" bitfld.long 0x8 7. "ENABLE_SYS_EN_PCIE_ERROR_1_CLR,Enable Clear for sys_en_pcie_error_1" "0,1" newline bitfld.long 0x8 6. "ENABLE_SYS_EN_PCIE_ERROR_0_CLR,Enable Clear for sys_en_pcie_error_0" "0,1" bitfld.long 0x8 5. "ENABLE_SYS_EN_PCIE_DPA_5_CLR,Enable Clear for sys_en_pcie_dpa_5" "0,1" newline bitfld.long 0x8 4. "ENABLE_SYS_EN_PCIE_DPA_4_CLR,Enable Clear for sys_en_pcie_dpa_4" "0,1" bitfld.long 0x8 3. "ENABLE_SYS_EN_PCIE_DPA_3_CLR,Enable Clear for sys_en_pcie_dpa_3" "0,1" newline bitfld.long 0x8 2. "ENABLE_SYS_EN_PCIE_DPA_2_CLR,Enable Clear for sys_en_pcie_dpa_2" "0,1" bitfld.long 0x8 1. "ENABLE_SYS_EN_PCIE_DPA_1_CLR,Enable Clear for sys_en_pcie_dpa_1" "0,1" newline bitfld.long 0x8 0. "ENABLE_SYS_EN_PCIE_DPA_0_CLR,Enable Clear for sys_en_pcie_dpa_0" "0,1" rgroup.long 0x500++0x7 line.long 0x0 "PCIE_INTD_STATUS_REG_SYS_0,Status Register 0" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 5. "STATUS_SYS_PCIE_DOWNSTREAM_5,Status for sys_en_pcie_downstream_5" "0,1" newline bitfld.long 0x0 4. "STATUS_SYS_PCIE_DOWNSTREAM_4,Status for sys_en_pcie_downstream_4" "0,1" bitfld.long 0x0 3. "STATUS_SYS_PCIE_DOWNSTREAM_3,Status for sys_en_pcie_downstream_3" "0,1" newline bitfld.long 0x0 2. "STATUS_SYS_PCIE_DOWNSTREAM_2,Status for sys_en_pcie_downstream_2" "0,1" bitfld.long 0x0 1. "STATUS_SYS_PCIE_DOWNSTREAM_1,Status for sys_en_pcie_downstream_1" "0,1" newline bitfld.long 0x0 0. "STATUS_SYS_PCIE_DOWNSTREAM_0,Status for sys_en_pcie_downstream_0" "0,1" line.long 0x4 "PCIE_INTD_STATUS_REG_SYS_1,Status Register 1" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 26. "STATUS_SYS_PCIE_PWR_STATE,Status for sys_en_pcie_pwr_state" "0,1" newline bitfld.long 0x4 25. "STATUS_SYS_PCIE_LEGACY_3,Status for sys_en_pcie_legacy_3" "0,1" bitfld.long 0x4 24. "STATUS_SYS_PCIE_LEGACY_2,Status for sys_en_pcie_legacy_2" "0,1" newline bitfld.long 0x4 23. "STATUS_SYS_PCIE_LEGACY_1,Status for sys_en_pcie_legacy_1" "0,1" bitfld.long 0x4 22. "STATUS_SYS_PCIE_LEGACY_0,Status for sys_en_pcie_legacy_0" "0,1" newline bitfld.long 0x4 21. "STATUS_SYS_PCIE_FLR_21,Status for sys_en_pcie_flr_21" "0,1" bitfld.long 0x4 20. "STATUS_SYS_PCIE_FLR_20,Status for sys_en_pcie_flr_20" "0,1" newline bitfld.long 0x4 19. "STATUS_SYS_PCIE_FLR_19,Status for sys_en_pcie_flr_19" "0,1" bitfld.long 0x4 18. "STATUS_SYS_PCIE_FLR_18,Status for sys_en_pcie_flr_18" "0,1" newline bitfld.long 0x4 17. "STATUS_SYS_PCIE_FLR_17,Status for sys_en_pcie_flr_17" "0,1" bitfld.long 0x4 16. "STATUS_SYS_PCIE_FLR_16,Status for sys_en_pcie_flr_16" "0,1" newline bitfld.long 0x4 15. "STATUS_SYS_PCIE_FLR_15,Status for sys_en_pcie_flr_15" "0,1" bitfld.long 0x4 14. "STATUS_SYS_PCIE_FLR_14,Status for sys_en_pcie_flr_14" "0,1" newline bitfld.long 0x4 13. "STATUS_SYS_PCIE_FLR_13,Status for sys_en_pcie_flr_13" "0,1" bitfld.long 0x4 12. "STATUS_SYS_PCIE_FLR_12,Status for sys_en_pcie_flr_12" "0,1" newline bitfld.long 0x4 11. "STATUS_SYS_PCIE_FLR_11,Status for sys_en_pcie_flr_11" "0,1" bitfld.long 0x4 10. "STATUS_SYS_PCIE_FLR_10,Status for sys_en_pcie_flr_10" "0,1" newline bitfld.long 0x4 9. "STATUS_SYS_PCIE_FLR_9,Status for sys_en_pcie_flr_9" "0,1" bitfld.long 0x4 8. "STATUS_SYS_PCIE_FLR_8,Status for sys_en_pcie_flr_8" "0,1" newline bitfld.long 0x4 7. "STATUS_SYS_PCIE_FLR_7,Status for sys_en_pcie_flr_7" "0,1" bitfld.long 0x4 6. "STATUS_SYS_PCIE_FLR_6,Status for sys_en_pcie_flr_6" "0,1" newline bitfld.long 0x4 5. "STATUS_SYS_PCIE_FLR_5,Status for sys_en_pcie_flr_5" "0,1" bitfld.long 0x4 4. "STATUS_SYS_PCIE_FLR_4,Status for sys_en_pcie_flr_4" "0,1" newline bitfld.long 0x4 3. "STATUS_SYS_PCIE_FLR_3,Status for sys_en_pcie_flr_3" "0,1" bitfld.long 0x4 2. "STATUS_SYS_PCIE_FLR_2,Status for sys_en_pcie_flr_2" "0,1" newline bitfld.long 0x4 1. "STATUS_SYS_PCIE_FLR_1,Status for sys_en_pcie_flr_1" "0,1" bitfld.long 0x4 0. "STATUS_SYS_PCIE_FLR_0,Status for sys_en_pcie_flr_0" "0,1" group.long 0x508++0x3 line.long 0x0 "PCIE_INTD_STATUS_REG_SYS_2,Status Register 2" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "STATUS_SYS_PCIE_PTM,Status write 1 to set for sys_en_pcie_ptm" "0,1" newline bitfld.long 0x0 10. "STATUS_SYS_PCIE_LINK_STATE,Status write 1 to set for sys_en_pcie_link_state" "0,1" bitfld.long 0x0 9. "STATUS_SYS_PCIE_HOT_RESET,Status write 1 to set for sys_en_pcie_hot_reset" "0,1" newline bitfld.long 0x0 8. "STATUS_SYS_PCIE_ERROR_2,Status write 1 to set for sys_en_pcie_error_2" "0,1" bitfld.long 0x0 7. "STATUS_SYS_PCIE_ERROR_1,Status write 1 to set for sys_en_pcie_error_1" "0,1" newline bitfld.long 0x0 6. "STATUS_SYS_PCIE_ERROR_0,Status write 1 to set for sys_en_pcie_error_0" "0,1" bitfld.long 0x0 5. "STATUS_SYS_PCIE_DPA_5,Status write 1 to set for sys_en_pcie_dpa_5" "0,1" newline bitfld.long 0x0 4. "STATUS_SYS_PCIE_DPA_4,Status write 1 to set for sys_en_pcie_dpa_4" "0,1" bitfld.long 0x0 3. "STATUS_SYS_PCIE_DPA_3,Status write 1 to set for sys_en_pcie_dpa_3" "0,1" newline bitfld.long 0x0 2. "STATUS_SYS_PCIE_DPA_2,Status write 1 to set for sys_en_pcie_dpa_2" "0,1" bitfld.long 0x0 1. "STATUS_SYS_PCIE_DPA_1,Status write 1 to set for sys_en_pcie_dpa_1" "0,1" newline bitfld.long 0x0 0. "STATUS_SYS_PCIE_DPA_0,Status write 1 to set for sys_en_pcie_dpa_0" "0,1" group.long 0x708++0x3 line.long 0x0 "PCIE_INTD_STATUS_CLR_REG_SYS_2,Status Clear Register 2" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "STATUS_SYS_PCIE_PTM_CLR,Status write 1 to clear for sys_en_pcie_ptm" "0,1" newline bitfld.long 0x0 10. "STATUS_SYS_PCIE_LINK_STATE_CLR,Status write 1 to clear for sys_en_pcie_link_state" "0,1" bitfld.long 0x0 9. "STATUS_SYS_PCIE_HOT_RESET_CLR,Status write 1 to clear for sys_en_pcie_hot_reset" "0,1" newline bitfld.long 0x0 8. "STATUS_SYS_PCIE_ERROR_2_CLR,Status write 1 to clear for sys_en_pcie_error_2" "0,1" bitfld.long 0x0 7. "STATUS_SYS_PCIE_ERROR_1_CLR,Status write 1 to clear for sys_en_pcie_error_1" "0,1" newline bitfld.long 0x0 6. "STATUS_SYS_PCIE_ERROR_0_CLR,Status write 1 to clear for sys_en_pcie_error_0" "0,1" bitfld.long 0x0 5. "STATUS_SYS_PCIE_DPA_5_CLR,Status write 1 to clear for sys_en_pcie_dpa_5" "0,1" newline bitfld.long 0x0 4. "STATUS_SYS_PCIE_DPA_4_CLR,Status write 1 to clear for sys_en_pcie_dpa_4" "0,1" bitfld.long 0x0 3. "STATUS_SYS_PCIE_DPA_3_CLR,Status write 1 to clear for sys_en_pcie_dpa_3" "0,1" newline bitfld.long 0x0 2. "STATUS_SYS_PCIE_DPA_2_CLR,Status write 1 to clear for sys_en_pcie_dpa_2" "0,1" bitfld.long 0x0 1. "STATUS_SYS_PCIE_DPA_1_CLR,Status write 1 to clear for sys_en_pcie_dpa_1" "0,1" newline bitfld.long 0x0 0. "STATUS_SYS_PCIE_DPA_0_CLR,Status write 1 to clear for sys_en_pcie_dpa_0" "0,1" rgroup.long 0xA80++0x3 line.long 0x0 "PCIE_INTD_INTR_VECTOR_REG_SYS,Interrupt Vector for sys" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_SYS,Interrupt Vector" tree.end tree "PCIE1_CORE_USER_CFG_USER_CFG" base ad:0x2917000 rgroup.long 0x0++0x3 line.long 0x0 "PCIE_USER_REVID,Module ID register" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x4++0xF line.long 0x0 "PCIE_USER_CMD_STATUS,Command Status register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "LINK_TRAINING_ENABLE,This bit must be set to 1 to enable the LTSSM to bring up the link." "0,1" line.long 0x4 "PCIE_USER_RSTCMD,Reset Command and Status register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "INIT_HOT_RESET,When this bit is set to 1'b1 in the RP mode the core initiates a Hot Reset sequence on the PCIe link." "0,1" line.long 0x8 "PCIE_USER_INITCFG,Initialization configuration register" hexmask.long.byte 0x8 25.--31. 1. "RESERVED" bitfld.long 0x8 24. "CONFIG_ENABLE,When this bit is set to 0 in the EP mode the Controller will generate a CRS Completion in response to Configuration Requests." "0,1" bitfld.long 0x8 22.--23. "VC_COUNT,Number of VCs configured." "0,1,2,3" newline hexmask.long.byte 0x8 15.--21. 1. "MAX_EVAL_ITERATION,Denotes the maximum number of iterations to be performed during the DirectionChange Feedback Link Equalization in case the direction change feedback does not converge to 00." bitfld.long 0x8 14. "BYPASS_PHASE23,This MMR should be programmed during system boot or initialization." "0,1" bitfld.long 0x8 13. "BYPASS_REMOTE_TX_EQUALIZATION,This MMR should be programmed during system boot or initialization." "0,1" newline hexmask.long.word 0x8 2.--12. 1. "SUPPORTED_PRESET,This MMR should be programmed during system boot or initialization." bitfld.long 0x8 1. "DISABLE_GEN3_DC_BALANCE,This bit it is used to disable the transmission of special DC Balance symbols in TS1 training sequences for improving the DC balance of the bit stream at 8.0 GT/s or higher speed." "0,1" bitfld.long 0x8 0. "SRIS_ENABLE,Should be set as per the System Reference Clocking Implementation." "0,1" line.long 0xC "PCIE_USER_PMCMD,Power Management command register" hexmask.long 0xC 3.--31. 1. "RESERVED" bitfld.long 0xC 2. "POWER_STATE_CHANGE_ACK,Software must assert this bit for a minimum of one cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT when it is ready to transition to the low-power state requested by the configuration write request." "0,1" bitfld.long 0xC 1. "CLIENT_REQ_EXIT_L1_SUBSTATE,Client logic can trigger an explicit L" "0,1" newline bitfld.long 0xC 0. "CLIENT_REQ_EXIT_L1,Client logic can trigger an explicit L1 exit by setting this bit." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "PCIE_USER_LINKSTATUS,Link Status register" bitfld.long 0x0 30.--31. "RESERVED" "0,1,2,3" hexmask.long.byte 0x0 24.--29. 1. "LTSSM_STATE,Current state of the Link Training and Status State Machine within the core." hexmask.long.byte 0x0 16.--23. 1. "POWER_STATE_CHANGE_FUNCTION_NUM,Function number of the function for which a power state change occurred." newline bitfld.long 0x0 15. "RESERVED" "0,1" bitfld.long 0x0 12.--14. "L1_PM_SUBSTATE,This register provides the current state of the L1 PM substates state machine." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "LINK_POWER_STATE,Current power state of the PCIe link." newline bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" bitfld.long 0x0 4.--5. "NEGOTIATED_SPEED,Current operating speed of the link is as follows:" "0,1,2,3" bitfld.long 0x0 2.--3. "NEGOTIATED_LINK_WIDTH,Current link width are as follows:" "0,1,2,3" newline bitfld.long 0x0 0.--1. "LINK_STATUS,Status of the PCI Express link." "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "PCIE_USER_LEGACY_INTR_SET,Legacy interrupt set register" hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "INTD_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express." "0,1" bitfld.long 0x0 2. "INTC_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express." "0,1" newline bitfld.long 0x0 1. "INTB_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express." "0,1" bitfld.long 0x0 0. "INTA_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express." "0,1" line.long 0x4 "PCIE_USER_LEGACY_INT_PENDING,Legacy interrupt pending set register" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "INT_ACK,When using legacy interrupts this bit indicates that the core has sent an INTx Assert or Deassert message in response to a change in the state of one of the INTx inputs." "0,1" rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "INT_PENDING_STATUS,When using legacy interrupts this input is used to indicate the interrupt pending status of the Physical Functions. The bit i must be set when an interrupt is pending in Function i." rgroup.long 0x20++0x1F line.long 0x0 "PCIE_USER_MSI_STAT,MSI status register" hexmask.long 0x0 6.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--5. 1. "MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Physical Functions." line.long 0x4 "PCIE_USER_MSI_VECTOR,MSI vector register" hexmask.long.word 0x4 18.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--17. 1. "MSI_VECTOR_COUNT,When the core is configured in the EndPoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Physical Functions." line.long 0x8 "PCIE_USER_MSI_MASK_PF0,PF0 MSI mask register" hexmask.long 0x8 0.--31. 1. "MSI_MASK_PF0,These bits provide the setting of the MSI Mask registers of the Physical Function0." line.long 0xC "PCIE_USER_MSI_MASK_PF1,PF1 MSI mask register" hexmask.long 0xC 0.--31. 1. "MSI_MASK_PF1,These bits provide the setting of the MSI Mask registers of the Physical Function1." line.long 0x10 "PCIE_USER_MSI_MASK_PF2,PF2 MSI mask register" hexmask.long 0x10 0.--31. 1. "MSI_MASK_PF2,These bits provide the setting of the MSI Mask registers of the Physical Function2." line.long 0x14 "PCIE_USER_MSI_MASK_PF3,PF3 MSI mask register" hexmask.long 0x14 0.--31. 1. "MSI_MASK_PF3,These bits provide the setting of the MSI Mask registers of the Physical Function3." line.long 0x18 "PCIE_USER_MSI_MASK_PF4,PF4 MSI mask register" hexmask.long 0x18 0.--31. 1. "MSI_MASK_PF4,These bits provide the setting of the MSI Mask registers of the Physical Function4." line.long 0x1C "PCIE_USER_MSI_MASK_PF5,PF5 MSI mask register" hexmask.long 0x1C 0.--31. 1. "MSI_MASK_PF5,These bits provide the setting of the MSI Mask registers of the Physical Function5." group.long 0x40++0x17 line.long 0x0 "PCIE_USER_MSI_PENDING_STATUS_PF0,PF0 MSI pending status input register" hexmask.long 0x0 0.--31. 1. "MSI_PENDING_STATUS_PF0,These inputs provide the status of the MSI pending interrupts for the Physical Function0 from the client to the core." line.long 0x4 "PCIE_USER_MSI_PENDING_STATUS_PF1,PF1 MSI pending status input register" hexmask.long 0x4 0.--31. 1. "MSI_PENDING_STATUS_PF1,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0x8 "PCIE_USER_MSI_PENDING_STATUS_PF2,PF2 MSI pending status input register" hexmask.long 0x8 0.--31. 1. "MSI_PENDING_STATUS_PF2,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0xC "PCIE_USER_MSI_PENDING_STATUS_PF3,PF3 MSI pending status input register" hexmask.long 0xC 0.--31. 1. "MSI_PENDING_STATUS_PF3,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0x10 "PCIE_USER_MSI_PENDING_STATUS_PF4,PF4 MSI pending status input register" hexmask.long 0x10 0.--31. 1. "MSI_PENDING_STATUS_PF4,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." line.long 0x14 "PCIE_USER_MSI_PENDING_STATUS_PF5,PF5 MSI pending status input register" hexmask.long 0x14 0.--31. 1. "MSI_PENDING_STATUS_PF5,These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management the.." rgroup.long 0x58++0x5B line.long 0x0 "PCIE_USER_MSI_STAT_VF,MSI_VF status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "VF_MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Virtual Functions." line.long 0x4 "PCIE_USER_MSI_VECTOR0_VF,MSI_VF vector count register0" hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x4 0.--23. 1. "VF_MSI_VECTOR_COUNT0,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function0 thru Virtual Function7." line.long 0x8 "PCIE_USER_MSI_VECTOR1_VF,MSI_VF vector count register1" hexmask.long.byte 0x8 24.--31. 1. "RESERVED" hexmask.long.tbyte 0x8 0.--23. 1. "VF_MSI_VECTOR_COUNT1,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function8 thru Virtual Function15." line.long 0xC "PCIE_USER_MSI_MASK_VF0,VF0MSI mask register" hexmask.long 0xC 0.--31. 1. "MSI_MASK_VF0,These bits provide the setting of the MSI Mask registers of the Virtual Function0." line.long 0x10 "PCIE_USER_MSI_MASK_VF1,VF1MSI mask register" hexmask.long 0x10 0.--31. 1. "MSI_MASK_VF1,These bits provide the setting of the MSI Mask registers of the Virtual Function1." line.long 0x14 "PCIE_USER_MSI_MASK_VF2,VF2MSI mask register" hexmask.long 0x14 0.--31. 1. "MSI_MASK_VF2,These bits provide the setting of the MSI Mask registers of the Virtual Function2." line.long 0x18 "PCIE_USER_MSI_MASK_VF3,VF3MSI mask register" hexmask.long 0x18 0.--31. 1. "MSI_MASK_VF3,These bits provide the setting of the MSI Mask registers of the Virtual Function3." line.long 0x1C "PCIE_USER_MSI_MASK_VF4,VF4MSI mask register" hexmask.long 0x1C 0.--31. 1. "MSI_MASK_VF4,These bits provide the setting of the MSI Mask registers of the Virtual Function4." line.long 0x20 "PCIE_USER_MSI_MASK_VF5,VF5MSI mask register" hexmask.long 0x20 0.--31. 1. "MSI_MASK_VF5,These bits provide the setting of the MSI Mask registers of the Virtual Function5." line.long 0x24 "PCIE_USER_MSI_MASK_VF6,VF6MSI mask register" hexmask.long 0x24 0.--31. 1. "MSI_MASK_VF6,These bits provide the setting of the MSI Mask registers of the Virtual Function6." line.long 0x28 "PCIE_USER_MSI_MASK_VF7,VF7MSI mask register" hexmask.long 0x28 0.--31. 1. "MSI_MASK_VF7,These bits provide the setting of the MSI Mask registers of the Virtual Function7." line.long 0x2C "PCIE_USER_MSI_MASK_VF8,VF8MSI mask register" hexmask.long 0x2C 0.--31. 1. "MSI_MASK_VF8,These bits provide the setting of the MSI Mask registers of the Virtual Function8." line.long 0x30 "PCIE_USER_MSI_MASK_VF9,VF9MSI mask register" hexmask.long 0x30 0.--31. 1. "MSI_MASK_VF9,These bits provide the setting of the MSI Mask registers of the Virtual Function9." line.long 0x34 "PCIE_USER_MSI_MASK_VF10,VF10MSI mask register" hexmask.long 0x34 0.--31. 1. "MSI_MASK_VF10,These bits provide the setting of the MSI Mask registers of the Virtual Function10." line.long 0x38 "PCIE_USER_MSI_MASK_VF11,VF11MSI mask register" hexmask.long 0x38 0.--31. 1. "MSI_MASK_VF11,These bits provide the setting of the MSI Mask registers of the Virtual Function11." line.long 0x3C "PCIE_USER_MSI_MASK_VF12,VF12MSI mask register" hexmask.long 0x3C 0.--31. 1. "MSI_MASK_VF12,These bits provide the setting of the MSI Mask registers of the Virtual Function12." line.long 0x40 "PCIE_USER_MSI_MASK_VF13,VF13MSI mask register" hexmask.long 0x40 0.--31. 1. "MSI_MASK_VF13,These bits provide the setting of the MSI Mask registers of the Virtual Function13." line.long 0x44 "PCIE_USER_MSI_MASK_VF14,VF14MSI mask register" hexmask.long 0x44 0.--31. 1. "MSI_MASK_VF14,These bits provide the setting of the MSI Mask registers of the Virtual Function14." line.long 0x48 "PCIE_USER_MSI_MASK_VF15,VF15MSI mask register" hexmask.long 0x48 0.--31. 1. "MSI_MASK_VF15,These bits provide the setting of the MSI Mask registers of the Virtual Function15." line.long 0x4C "PCIE_USER_MSIX_STAT,MSIX status register" hexmask.long 0x4C 6.--31. 1. "RESERVED" hexmask.long.byte 0x4C 0.--5. 1. "MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of Physical Functions.Bit0 represents the MSIX Enable for Physical Function0 and Bit1 represents the MSIX Enable for Physical Function 1" line.long 0x50 "PCIE_USER_MSIX_MASK,MSIX mask register" hexmask.long 0x50 6.--31. 1. "RESERVED" hexmask.long.byte 0x50 0.--5. 1. "MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Physical Functions." line.long 0x54 "PCIE_USER_MSIX_STAT_VF,Virtual Function MSIX status register" hexmask.long.word 0x54 16.--31. 1. "RESERVED" hexmask.long.word 0x54 0.--15. 1. "VF_MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of virtual Functions.Bit0 represents the MSIX Enable for Virtual Function0 Bit1 represents the MSIX Enable for Virtual Function 1 and so on" line.long 0x58 "PCIE_USER_MSIX_MASK_VF,Virtual Function MSIX mask register" hexmask.long.word 0x58 16.--31. 1. "RESERVED" hexmask.long.word 0x58 0.--15. 1. "VF_MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Virtual Functions." wgroup.long 0xB4++0x7 line.long 0x0 "PCIE_USER_FLR_DONE,Physical Function-Level Reset Done register" hexmask.long 0x0 6.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--5. 1. "FLR_DONE,These bits are connected to the" line.long 0x4 "PCIE_USER_VF_FLR_DONE,Virtual Function-Level Reset Done register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "VF_FLR_DONE,These bits are connected to the" group.long 0xBC++0x3 line.long 0x0 "PCIE_USER_PTM_CFG,Return to the . PTM Timestamp configuration register" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--10. "PTM_EP_TIMER_ADJ,PTM EP Timer tick adjust value. 1 will increment ptm_ep_timer by 1 each clock cycle 2 will increment the timer by 2 .. 7 will increment the timer by 7. The adjust value should be set prior to enabling PTM operation in the PCIe controller." "0,1,2,3,4,5,6,7" rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "PTM_CLK_SEL,Select CPTS HW1 push input. 0 will select ptm_local_timer[0] 1 will select ptm_local_timer[1] ... 63 will select ptm_local_timer[63] and 64 will select ptm_local_timer_out_valid. The values 65 to 127 are unused. The PTM clock select bit.." rgroup.long 0xC0++0x7 line.long 0x0 "PCIE_USER_PTM_TIMER_LOW,PTM timer value lower 32-bits" hexmask.long 0x0 0.--31. 1. "PTM_TIMER_OUT_LOW,ptm_timer_out[31:0] value from PCIe core." line.long 0x4 "PCIE_USER_PTM_TIMER_HIGH,PTM timer value upper 32-bits" hexmask.long 0x4 0.--31. 1. "PTM_TIMER_OUT_HIGH,ptm_timer_out[63:32] value from PCIe core." group.long 0xC8++0x3 line.long 0x0 "PCIE_USER_EOI_VECTOR,Return to the . EOI vector for re-triggering interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,EOI vector for level interrupts. Writing the EOI value as specfied to this register will re-trigger a pending interrupt. 0 - Downstream interrupt 1 - FLR interrupt 2 - Legacy interrupt 3 - Power state interrupt" tree.end tree "PCIE1_CORE_VMAP_MMRS" base ad:0x2914000 group.long 0x0++0xB line.long 0x0 "PCIE_VMAP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EN,ID enable" "0,1" line.long 0x4 "PCIE_VMAP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh" hexmask.long.word 0x4 16.--31. 1. "MASK,RequesterID mask" hexmask.long.word 0x4 0.--15. 1. "RID,RequesterID" line.long 0x8 "PCIE_VMAP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh" hexmask.long.word 0x8 18.--31. 1. "RESERVED" bitfld.long 0x8 16.--17. "ATYPE,Address type attribute." "0,1,2,3" hexmask.long.byte 0x8 12.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--11. 1. "VID,Match ID" group.long 0x200++0x3 line.long 0x0 "PCIE_VMAP_DEFMAP,virtID default value register" hexmask.long.word 0x0 21.--31. 1. "RESERVED" bitfld.long 0x0 20. "ATS_DIS,ATS mode." "0,1" bitfld.long 0x0 19. "BDF_MODE,Bus default mode." "0,1" bitfld.long 0x0 18. "RESERVED" "0,1" bitfld.long 0x0 16.--17. "DEF_ATYPE,Default address type attribute." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--11. 1. "DEF_VID,Default match ID" group.long 0x300++0x3 line.long 0x0 "PCIE_VMAP_DESC_j,Return to the . Outbound ASEL non-zero descriptor register Offset = 300h + (j * 4h); where j = 0h to 1Fh" bitfld.long 0x0 29.--31. "TRAFFIC_CLASS,PCIe Traffic Class (TC) associated with the non-zero ASEL request." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 17.--28. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BD_EN,External bus and device number enable.This bit enables the client to supply the bus and device numbers to be used in the requester ID. If this bit is 0 the core uses the captured values of the bus and device numbers to form the Requester ID. If.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "BUS_NUM,PCI Bus Number associated with the request.When descriptor bit[16] is set this field must specify the bus number to be used for the Requester ID. Otherwise this field is ignored by the core." hexmask.long.byte 0x0 0.--7. 1. "DEV_FUNC_NUM,PCI Function and Device Number associated with the request.In ARI mode all 8 bits are used to indicate the requesting function number. In legacy mode only bits[3:0] are used to specify function number and bits[7:4] are used to specify the.." group.long 0x400++0x3 line.long 0x0 "PCIE_VMAP_OB_VIRTID_MATCH,Return to the . Outbound virtid match register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 5.--11. 1. "VAL,Outbound virtid [11:5] match value.When outbound VBUSM slave interface virtid [11:5] matches the value in this register and the ASEL value is non-zero the PCIe controller address translation unit (ATU) is bypassed. The PCIe TLP descriptor values are.." hexmask.long.byte 0x0 0.--4. 1. "RESERVED,Reserved" tree.end tree "PCIE1_DAT0" base ad:0x18000000 group.long 0x0++0x3 line.long 0x0 "PCIE_DATA_MEM_y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh" hexmask.long 0x0 0.--31. 1. "PCIE_DATA,PCIE data region0" tree.end tree "PCIE1_DAT1" base ad:0x4100000000 group.long 0x0++0x3 line.long 0x0 "PCIE_DATA_MEM_y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh" hexmask.long 0x0 0.--31. 1. "PCIE_DATA,PCIE data region1" tree.end tree.end tree "PDMA" base ad:0x0 tree "PDMA5_REGS" base ad:0x27E0000 rgroup.long 0x0++0x3 line.long 0x0 "PDMA5_ECC_REV,IP revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "PDMA5_ECC_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "PDMA5_ECC_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator" group.long 0x3C++0x7 line.long 0x0 "PDMA5_ECC_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "PDMA5_ECC_SEC_STATUS_REG0,SEC interrupt status register 0." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt pending status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt pending status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt pending status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt pending status for tpcf0_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "PDMA5_ECC_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf0_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "PDMA5_ECC_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf0_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "PDMA5_ECC_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "PDMA5_ECC_DED_STATUS_REG0,DED interrupt status register 0." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt pending status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt pending status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt pending status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt pending status for tpcf0_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "PDMA5_ECC_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf0_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "PDMA5_ECC_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf0_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "PDMA5_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "PDMA5_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "PDMA5_ECC_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "PDMA5_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PDMA9_REGS" base ad:0x27E1000 rgroup.long 0x0++0x3 line.long 0x0 "PDMA9_ECC_REV,IP revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "PDMA9_ECC_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "PDMA9_ECC_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator" group.long 0x3C++0x7 line.long 0x0 "PDMA9_ECC_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "PDMA9_ECC_SEC_STATUS_REG0,SEC interrupt status register 0." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt pending status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt pending status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt pending status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt pending status for tpcf0_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "PDMA9_ECC_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf0_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "PDMA9_ECC_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf0_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "PDMA9_ECC_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "PDMA9_ECC_DED_STATUS_REG0,DED interrupt status register 0." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt pending status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt pending status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt pending status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt pending status for tpcf0_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "PDMA9_ECC_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf0_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "PDMA9_ECC_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf0_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "PDMA9_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "PDMA9_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "PDMA9_ECC_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "PDMA9_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PDMA10_REGS" base ad:0x27E2000 rgroup.long 0x0++0x3 line.long 0x0 "PDMA10_ECC_REV,IP revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "PDMA10_ECC_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "PDMA10_ECC_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator" group.long 0x3C++0x7 line.long 0x0 "PDMA10_ECC_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "PDMA10_ECC_SEC_STATUS_REG0,SEC interrupt status register 0." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt pending status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt pending status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt pending status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt pending status for tpcf0_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "PDMA10_ECC_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf0_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "PDMA10_ECC_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf0_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "PDMA10_ECC_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "PDMA10_ECC_DED_STATUS_REG0,DED interrupt status register 0." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt pending status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt pending status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt pending status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt pending status for tpcf0_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "PDMA10_ECC_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf0_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "PDMA10_ECC_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf0_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "PDMA10_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "PDMA10_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "PDMA10_ECC_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3" line.long 0xC "PDMA10_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "PLL0_CFG" base ad:0x680000 rgroup.long 0x0++0x3 line.long 0x0 "PLL0_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8++0x3 line.long 0x0 "PLL0_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x10++0x7 line.long 0x0 "PLL0_LOCKKEY0,Return to the . PLL0 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL0_LOCKKEY1,Return to the . PLL0 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" group.long 0x20++0x3 line.long 0x0 "PLL0_CTRL,Return to the . PLL0 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "PLL0_STAT,Return to the . PLL0 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x30++0xB line.long 0x0 "PLL0_FREQ_CTRL0,Return to the . PLL0 Frequency Control 0 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL0_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL0_DIV_CTRL,Return to the . PLL0 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x40++0x7 line.long 0x0 "PLL0_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL0" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL0_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL0" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x80++0x1F line.long 0x0 "PLL0_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL0" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "PLL0_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL0" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "PLL0_HSDIV_CTRL2,Return to the . HSDIV_CTRL2 register for PLL0" bitfld.long 0x8 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x8 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x8 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x8 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "PLL0_HSDIV_CTRL3,Return to the . HSDIV_CTRL3 register for PLL0" bitfld.long 0xC 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0xC 16.--30. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0xC 9.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0xC 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "PLL0_HSDIV_CTRL4,Return to the . HSDIV_CTRL4 register for PLL0" bitfld.long 0x10 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x10 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x10 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "PLL0_HSDIV_CTRL5,Return to the . HSDIV_CTRL5 register for PLL0" bitfld.long 0x14 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x14 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x14 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x18 "PLL0_HSDIV_CTRL6,Return to the . HSDIV_CTRL6 register for PLL0" bitfld.long 0x18 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x18 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x18 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x18 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x1C "PLL0_HSDIV_CTRL7,Return to the . HSDIV_CTRL7 register for PLL0" bitfld.long 0x1C 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x1C 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x1C 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x1C 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x1000++0x3 line.long 0x0 "PLL1_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x1008++0x3 line.long 0x0 "PLL1_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x1010++0x7 line.long 0x0 "PLL1_LOCKKEY0,Return to the . PLL1 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL1_LOCKKEY1,Return to the . PLL1 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers" group.long 0x1020++0x3 line.long 0x0 "PLL1_CTRL,Return to the . PLL1 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x1024++0x3 line.long 0x0 "PLL1_STAT,Return to the . PLL1 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x1030++0xB line.long 0x0 "PLL1_FREQ_CTRL0,Return to the . PLL1 Frequency Control 1 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL1_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL1_DIV_CTRL,Return to the . PLL1 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x1040++0x7 line.long 0x0 "PLL1_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL1" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL1_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL1" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x1080++0x17 line.long 0x0 "PLL1_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL1" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "PLL1_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL1" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "PLL1_HSDIV_CTRL2,Return to the . HSDIV_CTRL2 register for PLL1" bitfld.long 0x8 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x8 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x8 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x8 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "PLL1_HSDIV_CTRL3,Return to the . HSDIV_CTRL3 register for PLL1" bitfld.long 0xC 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0xC 16.--30. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0xC 9.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0xC 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "PLL1_HSDIV_CTRL4,Return to the . HSDIV_CTRL4 register for PLL1" bitfld.long 0x10 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x10 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x10 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "PLL1_HSDIV_CTRL5,Return to the . HSDIV_CTRL5 register for PLL1" bitfld.long 0x14 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x14 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x14 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" group.long 0x109C++0x3 line.long 0x0 "PLL1_HSDIV_CTRL7,Return to the . HSDIV_CTRL7 register for PLL1" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x2000++0x3 line.long 0x0 "PLL2_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x2008++0x3 line.long 0x0 "PLL2_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x2010++0x7 line.long 0x0 "PLL2_LOCKKEY0,Return to the . PLL2 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL2_LOCKKEY1,Return to the . PLL2 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers" group.long 0x2020++0x3 line.long 0x0 "PLL2_CTRL,Return to the . PLL2 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x2024++0x3 line.long 0x0 "PLL2_STAT,Return to the . PLL2 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x2030++0xB line.long 0x0 "PLL2_FREQ_CTRL0,Return to the . PLL2 Frequency Control 2 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL2_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL2_DIV_CTRL,Return to the . PLL2 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x2040++0x7 line.long 0x0 "PLL2_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL2" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL2_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL2" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x2080++0x13 line.long 0x0 "PLL2_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL2" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "PLL2_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL2" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "PLL2_HSDIV_CTRL2,Return to the . HSDIV_CTRL2 register for PLL2" bitfld.long 0x8 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x8 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x8 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x8 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "PLL2_HSDIV_CTRL3,Return to the . HSDIV_CTRL3 register for PLL2" bitfld.long 0xC 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0xC 16.--30. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0xC 9.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0xC 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "PLL2_HSDIV_CTRL4,Return to the . HSDIV_CTRL4 register for PLL2" bitfld.long 0x10 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x10 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x10 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" group.long 0x2098++0x3 line.long 0x0 "PLL2_HSDIV_CTRL6,Return to the . HSDIV_CTRL6 register for PLL2" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x3000++0x3 line.long 0x0 "PLL3_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x3008++0x3 line.long 0x0 "PLL3_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x3010++0x7 line.long 0x0 "PLL3_LOCKKEY0,Return to the . PLL3 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL3_LOCKKEY1,Return to the . PLL3 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers" group.long 0x3020++0x3 line.long 0x0 "PLL3_CTRL,Return to the . PLL3 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x3024++0x3 line.long 0x0 "PLL3_STAT,Return to the . PLL3 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x3030++0xB line.long 0x0 "PLL3_FREQ_CTRL0,Return to the . PLL3 Frequency Control 3 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL3_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL3_DIV_CTRL,Return to the . PLL3 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x3040++0x7 line.long 0x0 "PLL3_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL3" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL3_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL3" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x3080++0x13 line.long 0x0 "PLL3_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL3" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "PLL3_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL3" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "PLL3_HSDIV_CTRL2,Return to the . HSDIV_CTRL2 register for PLL3" bitfld.long 0x8 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x8 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x8 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x8 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "PLL3_HSDIV_CTRL3,Return to the . HSDIV_CTRL3 register for PLL3" bitfld.long 0xC 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0xC 16.--30. 1. "RESERVED,Reserved" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0xC 9.--14. 1. "RESERVED,Reserved" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0xC 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "PLL3_HSDIV_CTRL4,Return to the . HSDIV_CTRL4 register for PLL3" bitfld.long 0x10 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x10 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x10 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x10 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x4000++0x3 line.long 0x0 "PLL4_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x4008++0x3 line.long 0x0 "PLL4_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x4010++0x7 line.long 0x0 "PLL4_LOCKKEY0,Return to the . PLL4 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL4_LOCKKEY1,Return to the . PLL4 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition4 registers" group.long 0x4020++0x3 line.long 0x0 "PLL4_CTRL,Return to the . PLL4 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x4024++0x3 line.long 0x0 "PLL4_STAT,Return to the . PLL4 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x4030++0xB line.long 0x0 "PLL4_FREQ_CTRL0,Return to the . PLL4 Frequency Control 4 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL4_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL4_DIV_CTRL,Return to the . PLL4 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x4040++0x7 line.long 0x0 "PLL4_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL4" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL4_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL4" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x4080++0xB line.long 0x0 "PLL4_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL4" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "PLL4_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL4" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "PLL4_HSDIV_CTRL2,Return to the . HSDIV_CTRL2 register for PLL4" bitfld.long 0x8 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x8 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x8 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x8 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x7000++0x3 line.long 0x0 "PLL7_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x7008++0x3 line.long 0x0 "PLL7_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x7010++0x7 line.long 0x0 "PLL7_LOCKKEY0,Return to the . PLL7 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL7_LOCKKEY1,Return to the . PLL7 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers" group.long 0x7020++0x3 line.long 0x0 "PLL7_CTRL,Return to the . PLL7 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x7024++0x3 line.long 0x0 "PLL7_STAT,Return to the . PLL7 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x7030++0xB line.long 0x0 "PLL7_FREQ_CTRL0,Return to the . PLL7 Frequency Control 7 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL7_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL7_DIV_CTRL,Return to the . PLL7 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x7040++0x7 line.long 0x0 "PLL7_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL7" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL7_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL7" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x7060++0x3 line.long 0x0 "PLL7_CAL_CTRL,Return to the . PLL7 Calibration Control Register" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" hexmask.long.word 0x0 21.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" rbitfld.long 0x0 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter.Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" rbitfld.long 0x0 12.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration.When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x7064++0x3 line.long 0x0 "PLL7_CAL_STAT,Return to the . PLL7 Calibration Status Register" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.word 0x0 20.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0.If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x7080++0x3 line.long 0x0 "PLL7_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL7" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x8000++0x3 line.long 0x0 "PLL8_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8008++0x3 line.long 0x0 "PLL8_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x8010++0x7 line.long 0x0 "PLL8_LOCKKEY0,Return to the . PLL8 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition8 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL8_LOCKKEY1,Return to the . PLL8 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition8 registers" group.long 0x8020++0x3 line.long 0x0 "PLL8_CTRL,Return to the . PLL8 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0x8024++0x3 line.long 0x0 "PLL8_STAT,Return to the . PLL8 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x8030++0xB line.long 0x0 "PLL8_FREQ_CTRL0,Return to the . PLL8 Frequency Control 8 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL8_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL8_DIV_CTRL,Return to the . PLL8 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x8040++0x7 line.long 0x0 "PLL8_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL8" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL8_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL8" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x8060++0x3 line.long 0x0 "PLL8_CAL_CTRL,Return to the . PLL8 Calibration Control Register" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" hexmask.long.word 0x0 21.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" rbitfld.long 0x0 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter.Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" rbitfld.long 0x0 12.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration.When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x8064++0x3 line.long 0x0 "PLL8_CAL_STAT,Return to the . PLL8 Calibration Status Register" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.word 0x0 20.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0.If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x8080++0x3 line.long 0x0 "PLL8_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL8" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0xC000++0x3 line.long 0x0 "PLL12_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0xC008++0x3 line.long 0x0 "PLL12_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0xC010++0x7 line.long 0x0 "PLL12_LOCKKEY0,Return to the . PLL12 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition12 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL12_LOCKKEY1,Return to the . PLL12 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition12 registers" group.long 0xC020++0x3 line.long 0x0 "PLL12_CTRL,Return to the . PLL12 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0xC024++0x3 line.long 0x0 "PLL12_STAT,Return to the . PLL12 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0xC030++0xB line.long 0x0 "PLL12_FREQ_CTRL0,Return to the . PLL12 Frequency Control 12 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL12_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL12_DIV_CTRL,Return to the . PLL12 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0xC040++0x7 line.long 0x0 "PLL12_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL12" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL12_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL12" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0xC060++0x3 line.long 0x0 "PLL12_CAL_CTRL,Return to the . PLL12 Calibration Control Register" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" hexmask.long.word 0x0 21.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" rbitfld.long 0x0 19. "RESERVED,Reserved" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter.Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CAL_BYP,Calibration bypass1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" rbitfld.long 0x0 12.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration.When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0xC064++0x3 line.long 0x0 "PLL12_CAL_STAT,Return to the . PLL12 Calibration Status Register" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.word 0x0 20.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0.If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0xC080++0x3 line.long 0x0 "PLL12_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL12" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0xE000++0x3 line.long 0x0 "PLL14_PID,Return to the . Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral Identification Register Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0xE008++0x3 line.long 0x0 "PLL14_CFG,Return to the . PLL MMR Configuration" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved):2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved):2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0xE010++0x7 line.long 0x0 "PLL14_LOCKKEY0,Return to the . PLL14 Lock Key 0 Register" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition14 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "PLL14_LOCKKEY1,Return to the . PLL14 Lock Key 1 RegisterAddr" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition14 registers" group.long 0xE020++0x3 line.long 0x0 "PLL14_CTRL,Return to the . PLL14 Control" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference.." "0,1" hexmask.long.word 0x0 17.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator.This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-phase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide.." "0,1" rgroup.long 0xE024++0x3 line.long 0x0 "PLL14_STAT,Return to the . PLL14 Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0xE030++0xB line.long 0x0 "PLL14_FREQ_CTRL0,Return to the . PLL14 Frequency Control 14 Register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by.." line.long 0x4 "PLL14_FREQ_CTRL1,Return to the . PLL0 Frequency Control 1 Register" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395.The total feedback divide value is (fb_div_int + fb_div_frac / (2)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2)) 24'h000002 - .000000119209 (2/(2)) :.." line.long 0x8 "PLL14_DIV_CTRL,Return to the . PLL14 Output Clock Divider Register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1.." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 6.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider.Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0xE040++0x7 line.long 0x0 "PLL14_SS_CTRL,Return to the . PLL_SS_CTRL register for PLL14" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator.1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 26.--30. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" rbitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 15. "RESET,SSM reset.When set to 1 the SSM modulator is in reset" "0,1" newline hexmask.long.word 0x0 5.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved):1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "PLL14_SS_SPREAD,Return to the . PLL_SS_SPREAD register for PLL14" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider.This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.word 0x4 5.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0xE080++0x7 line.long 0x0 "PLL14_HSDIV_CTRL0,Return to the . HSDIV_CTRL0 register for PLL14" bitfld.long 0x0 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x0 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x0 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "PLL14_HSDIV_CTRL1,Return to the . HSDIV_CTRL1 register for PLL14" bitfld.long 0x4 31. "RESET,SSM reset.When set to 1 the SSM modulator is in resetl" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Reserved" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" hexmask.long.byte 0x4 9.--14. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" tree.end tree "PLLCTRL0" base ad:0x410000 rgroup.long 0x0++0x3 line.long 0x0 "PID,Return to the . Peripheral identification register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral identification register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.Will vary depending on release" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x100++0x3 line.long 0x0 "PLLCTL,Return to the . PLL control register" hexmask.long.tbyte 0x0 10.--31. 1. "RSVD2,Reserved" bitfld.long 0x0 9. "EXCLKSRC,Selects between using bypass clock or an external clock source. 0=bypass clock 1=external clock source" "0: bypass clock,1: external clock source" newline bitfld.long 0x0 8. "CLKMODE,Reference Clock Selection. 1 = clkin_pi is the reference clock 0 = oscin_pi is the reference clock This bit is only applicable when d_clkmodesrc_pi = 1. It is otherwise don't care." "0: oscin_pi is the reference clock This bit is only..,1: clkin_pi is the reference clock" bitfld.long 0x0 7. "PLLSELB,Selects PLL A versus PLL B. 1 = PLL B is selected. PLL A is put in power down (pll_a_pwrdn_po = 1) 0 = PLL A is selected. PLL B is put in power down. (pll_b_pwrdn_po = 1)" "0: PLL A is selected,1: PLL B is selected" newline bitfld.long 0x0 6. "RSVD1,Reserved" "0,1" bitfld.long 0x0 5. "PLLENSRC,PLLEN Mux Control Source 1 = PLLEN Mux is controlled by input pllen_pi. PLLCTL.PLLEN is don't care 0 = PLLEN Mux is controlled by PLLCTL.PLLEN. pllen_pi is don't care" "0: PLLEN Mux is controlled by PLLCTL,1: PLLEN Mux is controlled by input pllen_pi" newline bitfld.long 0x0 4. "PLLDIS,Asserts DISABLE to PLL if Supported 1 = PLL Controller output pll_disable_po = 1. 0 = PLL Controller output pll_disable_po = 0. Chip team must pay attention to the disable signal polarity of the PLL they use. Some PLLs may require PLLDIS=1 to.." "0: PLL Controller output pll_disable_po = 0,1: PLL Controller output pll_disable_po = 1" bitfld.long 0x0 3. "PLLRST,Asserts RESET to PLL if Supported.Controls output pll_reset_po. 1= PLL Controller output pll_reset_po = 1. 0= PLL Controller output pll_reset_po=0. Chip team must pay attention to the reset signal polarity of the PLL they use. Some PLLs require.." "0: PLL Controller output pll_reset_po=0,1: PLL Controller output pll_reset_po = 1" newline bitfld.long 0x0 2. "RSVD,Reserved" "0,1" bitfld.long 0x0 1. "PLLPWRDN,Selects PLL Power Down for the PLL selected by PLLSELB.The PLL not selected by PLLSELB is NOT controlled by PLLPWRDN bit. The not-selected PLL will stay in power down regardless of PLLPWRDN value. 0 = Selected PLL Operational. If PLLSELB=0 (PLLA.." "0: Selected PLL Operational,1: Selected PLL Placed In Power Down State" newline bitfld.long 0x0 0. "PLLEN,PLL Mode Enable This bit controls the multiplexer before the SYSCLK dividers D1 to Dn. 0 = Bypass Mode PreDiv PLL and PostDiv are bypassed. SYSCLK divided down directly from input reference clock refclk. 1 = PLL Mode PLL is used. SYSCLK divided.." "0: Bypass Mode PreDiv,1: PLL Mode PLL is used" group.long 0x118++0x7 line.long 0x0 "PLLDIV1,Return to the . PLL controller divider1 control register" hexmask.long.word 0x0 16.--31. 1. "RSVD1,Reserved" bitfld.long 0x0 15. "DN_EN,Divider Dn Enable 0 = Divider n Disabled. SYSCLKn is also gated before and after divider Dn. 1 = Divider n Enabled" "0: Divider n Disabled,1: Divider n Enabled" newline bitfld.long 0x0 14. "HALF_RATIO,Ratio is in half steps.Example 1: if RATIO = 00000 and HALFRATIO=1 the divider will be /1.5. Example 2: RATIO=10111 and HALFRATIO=1 divider will be /24.5. Example 3: if RATIO=00011 and HALFRATIO=0 divider will be /4. THE HALF RATIO DIVIDER IS.." "?,1: if RATIO = 00000 and HALFRATIO=1 the divider.." hexmask.long.byte 0x0 8.--13. 1. "RSVD,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "RATIO,Divider Dn Ratio (SYSCLKn divider) 00000=/1 00001=/2 00010=/3 00011=/4 00100=/5 00101=/6 00110=/7 00111=/8 01000=/9 01001=/10 01010=/11 01011=/12 01100=/13 01101=/14 01110=/15 01111=/16 10000=/17 10001=/18 10010=/19 10011=/20 10100=/21 10101=/22.." line.long 0x4 "PLLDIV2,Return to the . PLL controller divider2 control register" hexmask.long.word 0x4 16.--31. 1. "RSVD1,Reserved" bitfld.long 0x4 15. "DN_EN,Divider Dn Enable 0 = Divider n Disabled. SYSCLKn is also gated before and after divider Dn. 1 = Divider n Enabled" "0: Divider n Disabled,1: Divider n Enabled" newline bitfld.long 0x4 14. "HALF_RATIO,Ratio is in half steps.Example 1: if RATIO = 00000 and HALFRATIO=1 the divider will be /1.5. Example 2: RATIO=10111 and HALFRATIO=1 divider will be /24.5. Example 3: if RATIO=00011 and HALFRATIO=0 divider will be /4. THE HALF RATIO DIVIDER IS.." "?,1: if RATIO = 00000 and HALFRATIO=1 the divider.." hexmask.long.byte 0x4 8.--13. 1. "RSVD,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "RATIO,Divider Dn Ratio (SYSCLKn divider) 00000=/1 00001=/2 00010=/3 00011=/4 00100=/5 00101=/6 00110=/7 00111=/8 01000=/9 01001=/10 01010=/11 01011=/12 01100=/13 01101=/14 01110=/15 01111=/16 10000=/17 10001=/18 10010=/19 10011=/20 10100=/21 10101=/22.." group.long 0x138++0xF line.long 0x0 "PLLCMD,Return to the . PLL Controller command register" hexmask.long 0x0 2.--31. 1. "RSVD,Reserved" bitfld.long 0x0 1. "OSCPWRDN,iOscillator Power Down Command 1: A write of 1 (doesn't need to be a transition from 0 to 1) to this bit initiates oscillator power down command. 0: A write of 0 to this bit clears the bit to zero but causes no effect. Read from this field.." "0: A write of 0 to this bit clears the bit to zero..,1: A write of 1" newline bitfld.long 0x0 0. "GOSET,GO bit for SYSCLKx phase alignment. GOSET = 1: A write of 1 to this bit signifies that the new divide ratios in PLLDIV[1:n] are taken into account at the nearest possible rising edge to phase align the clocks. The actual SYSCLKx to be aligned are.." "0: A write of 0 to this bit clears the bit to zero..,1: A write of 1 to this bit signifies that the new.." line.long 0x4 "PLLSTAT,Return to the . PLL Controller status register" hexmask.long 0x4 3.--31. 1. "RSVD,Reserved" rbitfld.long 0x4 2. "STABLE,OSCIN Stable This bit shows the status of the rstclk_cnt_done_po signal. It indicates if the rstclk counter has finished counting implying that the OSCIN/CLKIN is stable. The d_rstclk_cnt_pi must be set properly to allow rstclk counter to count.." "0: rstclk counter not done counting,1: OSCIN/CLKIN is assumed to be stable" newline rbitfld.long 0x4 1. "LOCK,PLL Core STATUS This bit returns the lock status of the selected PLL core (if supported by PLL core). For example if PLLSELB=0 (PLLA selected) it reflects the status of pll_a_lock_i. If PLLSELB-1 (PLLB selected) it reflects the status of.." "0: PLL core not locked,1: PLL core locked" rbitfld.long 0x4 0. "GOSET,Reflects the status of GO transition.Read from this register returns the status of the GO operation. Writes to the register are ignored. GOSTAT = 1: This bit goes to 1 as soon as GOSET in PLLCMD is written to. It remains a 1 when GO operation.." "0: No GO operation in progress,1: This bit goes to 1 as soon as GOSET in PLLCMD is.." line.long 0x8 "ALNCTL,Return to the . PLL Controller clock align control register" hexmask.long.word 0x8 16.--31. 1. "RSVD,Reserved" hexmask.long.word 0x8 1.--15. 1. "ALN,SYSCLKx needs to be aligned with other clocks selected in this register. ALNx = 0: Do not need to align SYSCLKx to other clocks. SYSCLKx is left free-running. ALNx = 1: Align SYSCLKx to other clocks selected in this register Software note: This bit.." newline bitfld.long 0x8 0. "ALN1,SYSCLK1 needs to be aligned with other clocks selected in this register. ALN1 = 0: Do not need to align SYSCLK1 to other clocks. SYSCLK1 is left free-running. ALN1 = 1: Align SYSCLK1 to other clocks selected in this register Software note: This bit.." "0: Do not need to align SYSCLK1 to other clocks,1: Align SYSCLK1 to other clocks selected in this.." line.long 0xC "DCHANGE,Return to the . PLLDIV ratio change register" hexmask.long.word 0xC 16.--31. 1. "RSVD,Reserved" hexmask.long.word 0xC 1.--15. 1. "SYS,SYSCLKx divide ratio has been modified.SYSCLKx ratio will be changed during GO operation. SYSx = 0: SYSCLKx ratio has not been modified. When GOSET is set SYSCLKx will not be affected. SYSx = 1: SYSCLKx ratio has been modified. When GOSET is set .." newline rbitfld.long 0xC 0. "SYS1,SYSCLK1 divide ratio has been modified.SYSCLK1 ratio will be changed during GO operation. SYS1 = 0: SYSCLK1 ratio has not been modified. When GOSET is set SYSCLK1 will not be affected. SYS1 = 1: SYSCLK1 ratio has been modified. When GOSET is set .." "0: SYSCLK1 ratio has not been modified,1: SYSCLK1 ratio has been modified" tree.end tree "PSC0" base ad:0x400000 rgroup.long 0x0++0x3 line.long 0x0 "PSC0_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module. The PSC0_PID stores version information used to identify the module. All bits within this register are read-only (writes.." bitfld.long 0x0 30.--31. "SCHEME,PSC0_PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x7 line.long 0x0 "PSC0_GBLCTL,This register contains global control to PSC." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control." hexmask.long.byte 0x0 0.--7. 1. "RESERVED" line.long 0x4 "PSC0_GBLSTAT,This register shows the PSC global status." hexmask.long.byte 0x4 28.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits" hexmask.long.word 0x4 1.--15. 1. "RESERVED" bitfld.long 0x4 0. "OVRIDE,PSC Override Status" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "PSC0_INTEVAL,This register has no storage. Read from this register returns 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "GOSET,GOSTAT Interrupt Set" "0,1" bitfld.long 0x0 18. "EPCSET,External Power Control Interrupt Set" "0,1" bitfld.long 0x0 17. "ERRSET,Combined Interrupt Set" "0,1" hexmask.long.word 0x0 3.--16. 1. "RESERVED" bitfld.long 0x0 2. "EPCEV,External Power Control Interrupt Set" "0,1" newline bitfld.long 0x0 1. "ERREV,Re_evaluate Error Interrupt" "0,1" bitfld.long 0x0 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "PSC0_MERRPR_y,This register records pending error conditions for all modules. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.). Offset = 40h + (y * 4h); where y = 0h to 3h" hexmask.long 0x0 0.--31. 1. "M,Records pending error conditions." group.long 0x50++0x3 line.long 0x0 "PSC0_MERRCR_y,This register has no storage. Read from this register returns 0. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.). Offset = 50h + (y * 4h); where y = 0h to 3h" hexmask.long 0x0 0.--31. 1. "M,Write of 1 clears the corresponding MERRPR bit." rgroup.long 0x60++0x3 line.long 0x0 "PSC0_PERRPR,This register records pending error conditions for each power domain. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "P,Power Domain n Error Condition." group.long 0x68++0x3 line.long 0x0 "PSC0_PERRCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "P,Write of 1 clears the corresponding PSC0_PERRPR bit." rgroup.long 0x70++0x3 line.long 0x0 "PSC0_EPCPR,This register records pending external power control conditions. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "EPC,External Power Control Intervention Request for Power Domain n" group.long 0x78++0x3 line.long 0x0 "PSC0_EPCCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "EPC,Write of 1 clears the corresponding PSC0_EPCPR bit" rgroup.long 0x100++0x3 line.long 0x0 "PSC0_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor." bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC" hexmask.long.word 0x0 8.--23. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RAILCNT,Indicates the current rail counter value" group.long 0x104++0x7 line.long 0x0 "PSC0_RAILCTL,This register is user programmable. It holds the counter values for rail counter. User can select one of the two counter values to be used for each power domain (see PSC0_RAILSEL register)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 8.--15. 1. "RAILCTR1,Rail Counter Value 1" hexmask.long.byte 0x0 0.--7. 1. "RAILCTR0,Rail Counter Value 0" line.long 0x4 "PSC0_RAILSEL,User can use this register to select the counter value (PSC0_RAILCTL) for each power domain." hexmask.long 0x4 0.--31. 1. "P,Rail Counter Select for Power Domain" group.long 0x120++0x3 line.long 0x0 "PSC0_PTCMD,This is a pseudo-command register with no actual storage. Reads return 0. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "GO,Power Domain n GO Transition" rgroup.long 0x128++0x3 line.long 0x0 "PSC0_PTSTAT,This is a status register. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "GOSTAT,Power Domain n Transition Command Status" rgroup.long 0x200++0x3 line.long 0x0 "PSC0_PDSTAT_y,This is a status register. One register per power domain. Each register contains the status for the given power domain. Offset = 200h + (y * 4h); where y = 0h to 1Dh" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" bitfld.long 0x0 11. "EMUIHB,Emulation Alters Domain State" "0,1" bitfld.long 0x0 10. "PWRBAD,Power Bad error" "0,1" bitfld.long 0x0 9. "PORDONE,POR Done Input Status" "0,1" bitfld.long 0x0 8. "PORZ,PORz output actual status" "0,1" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "STATE,Current Power Domain State" group.long 0x300++0x3 line.long 0x0 "PSC0_PDCTL_y,This is a control register. One register per power domain. Offset = 300h + (y * 4h); where y = 0h to 1Dh" bitfld.long 0x0 31. "FORCE,Force Bit" "0,1" bitfld.long 0x0 30. "RESERVED" "0,1" bitfld.long 0x0 29. "PWRSW,Power shorting Switch Control" "0,1" bitfld.long 0x0 28. "ISO,Isolation Cell control" "0,1" hexmask.long.byte 0x0 24.--27. 1. "RESERVED" hexmask.long.byte 0x0 16.--23. 1. "WAKECNT,RAM wake count delay value" newline bitfld.long 0x0 15. "RESERVED" "0,1" bitfld.long 0x0 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10.--11. "RESERVED" "0,1,2,3" bitfld.long 0x0 9. "EMUIHBIE,Emulation alters domain state" "0,1" bitfld.long 0x0 8. "EPCGOOD,External Power Control Power Good Indication" "0,1" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "NEXT,User_Desired Next Power Domain State" "0,1" rgroup.long 0x400++0x3 line.long 0x0 "PSC0_PDCFG_y,This is a status register. It shows PSC settings for easy debug. Offset = 400h + (y * 4h); where y = 0h to 1Dh" hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "ICEPICK,Icepick support" "0,1" bitfld.long 0x0 2. "RESERVED" "0,1" bitfld.long 0x0 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1" bitfld.long 0x0 0. "ALWAYSON,Always on power domain" "0,1" rgroup.long 0x600++0x3 line.long 0x0 "PSC0_MDCFG_y,This is a constant register showing some PSC settings for easy debug. This register is read only. Offset = 600h + (y * 4h); where y = 0h to 6Bh" hexmask.long.word 0x0 21.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--20. 1. "PWRDOM,Indicates which power domain this module belongs to" bitfld.long 0x0 15. "AUTOONLY" "0,1" bitfld.long 0x0 14. "RESETISO" "0,1" bitfld.long 0x0 13. "NEXTLOCK" "0,1" bitfld.long 0x0 12. "ASYNC,Async Lpsc" "0,1" newline bitfld.long 0x0 11. "ICEPICK,IcePick support" "0,1" bitfld.long 0x0 10. "PERMDIS,Permanently disable" "0,1" bitfld.long 0x0 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1" bitfld.long 0x0 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7" rgroup.long 0x800++0x3 line.long 0x0 "PSC0_MDSTAT_y,This register shows the status of each module. Requires one register per module on the device. Offset = 800h + (y * 4h); where y = 0h to 6Bh" hexmask.long.word 0x0 18.--31. 1. "RESERVED" bitfld.long 0x0 17. "EMUIHB,Emulation Alters Module State." "0,1" bitfld.long 0x0 16. "EMURST,Emulation Alters Reset" "0,1" bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "MCKOUT,Actual modclk output to module" "0,1" bitfld.long 0x0 11. "MRSTDONE,Module reset initialization done status" "0,1" newline bitfld.long 0x0 10. "MRSTZ,Module reset actual status" "0,1" bitfld.long 0x0 9. "LRSTDONE,Module local reset initialization done status" "0,1" bitfld.long 0x0 8. "LRSTZ,Module local reset actual status" "0,1" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "STATE,These bits indicate the current module state" group.long 0xA00++0x3 line.long 0x0 "PSC0_MDCTL_y,This register provides specific control for the individual module. One register per module on the device. Offset = A00h + (y * 4h); where y = 0h to 6Bh" bitfld.long 0x0 31. "FORCE,Force Bit" "0,1" hexmask.long.tbyte 0x0 13.--30. 1. "RESERVED" bitfld.long 0x0 12. "RESETISO,Reset Isolation" "0,1" bitfld.long 0x0 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1" bitfld.long 0x0 10. "EMUIHBIE,Emulation Alters Module State." "0,1" bitfld.long 0x0 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "LRSTZ,Module local reset control" "0,1" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "NEXT,Module Next State" tree.end tree "R5FSS" base ad:0x0 tree "R5FSS0" base ad:0x2A2D000 group.long 0x0++0x3 line.long 0x0 "R5FSS_DISABLE_CR,Return to the . This register contains config bits to enable or disable change requests added to the IP." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "COMBINE_TCM_LOCKSTEP_MODE,This bit disables the CR logic to combine TCM in lockstep mode" "0,1" rgroup.long 0x4++0x13 line.long 0x0 "R5FSS_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS,Return to the . Status bits showing the R5FSS CPU0 EVNT BUS single-bit error counters." hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16.--17. "EVNT_BUS8,Status bits showing the R5FSS CPU0 EVNT 8 single-bit error counter" "0,1,2,3" bitfld.long 0x0 14.--15. "EVNT_BUS7,Status bits showing the R5FSS CPU0 EVNT 7 single-bit error counter" "0,1,2,3" newline bitfld.long 0x0 12.--13. "EVNT_BUS6,Status bits showing the R5FSS CPU0 EVNT 6 single-bit error counter" "0,1,2,3" bitfld.long 0x0 10.--11. "EVNT_BUS5,Status bits showing the R5FSS CPU0 EVNT 5 single-bit error counter" "0,1,2,3" bitfld.long 0x0 8.--9. "EVNT_BUS4,Status bits showing the R5FSS CPU0 EVNT 4 single-bit error counter" "0,1,2,3" newline bitfld.long 0x0 6.--7. "EVNT_BUS3,Status bits showing the R5FSS CPU0 EVNT 3 single-bit error counter" "0,1,2,3" bitfld.long 0x0 4.--5. "EVNT_BUS2,Status bits showing the R5FSS CPU0 EVNT 2 single-bit error counter" "0,1,2,3" bitfld.long 0x0 2.--3. "EVNT_BUS1,Status bits showing the R5FSS CPU0 EVNT 1 single-bit error counter" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EVNT_BUS0,Status bits showing the R5FSS CPU0 EVNT 0 single-bit error counter" "0,1,2,3" line.long 0x4 "R5FSS_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS,Return to the . Status bits showing the R5FSS CPU1 EVNT BUS single-bit error counters." hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16.--17. "EVNT_BUS8,Status bits showing the R5FSS CPU1 EVNT 8 single-bit error counter" "0,1,2,3" bitfld.long 0x4 14.--15. "EVNT_BUS7,Status bits showing the R5FSS CPU1 EVNT 7 single-bit error counter" "0,1,2,3" newline bitfld.long 0x4 12.--13. "EVNT_BUS6,Status bits showing the R5FSS CPU1 EVNT 6 single-bit error counter" "0,1,2,3" bitfld.long 0x4 10.--11. "EVNT_BUS5,Status bits showing the R5FSS CPU1 EVNT 5 single-bit error counter" "0,1,2,3" bitfld.long 0x4 8.--9. "EVNT_BUS4,Status bits showing the R5FSS CPU1 EVNT 4 single-bit error counter" "0,1,2,3" newline bitfld.long 0x4 6.--7. "EVNT_BUS3,Status bits showing the R5FSS CPU1 EVNT 3 single-bit error counter" "0,1,2,3" bitfld.long 0x4 4.--5. "EVNT_BUS2,Status bits showing the R5FSS CPU1 EVNT 2 single-bit error counter" "0,1,2,3" bitfld.long 0x4 2.--3. "EVNT_BUS1,Status bits showing the R5FSS CPU1 EVNT 1 single-bit error counter" "0,1,2,3" newline bitfld.long 0x4 0.--1. "EVNT_BUS0,Status bits showing the R5FSS CPU1 EVNT 0 single-bit error counter" "0,1,2,3" line.long 0x8 "R5FSS_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS,Return to the . Status bits showing the R5FSS CPU0 EVNT BUS multi-bit error counters." hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 12.--13. "EVNT_BUS6,Status bits showing the R5FSS CPU0 EVNT 6 multi-bit error counter" "0,1,2,3" bitfld.long 0x8 10.--11. "EVNT_BUS5,Status bits showing the R5FSS CPU0 EVNT 5 multi-bit error counter" "0,1,2,3" newline bitfld.long 0x8 8.--9. "EVNT_BUS4,Status bits showing the R5FSS CPU0 EVNT 4 multi-bit error counter" "0,1,2,3" bitfld.long 0x8 6.--7. "EVNT_BUS3,Status bits showing the R5FSS CPU0 EVNT 3 multi-bit error counter" "0,1,2,3" bitfld.long 0x8 4.--5. "EVNT_BUS2,Status bits showing the R5FSS CPU0 EVNT 2 multi-bit error counter" "0,1,2,3" newline bitfld.long 0x8 2.--3. "EVNT_BUS1,Status bits showing the R5FSS CPU0 EVNT 1 multi-bit error counter" "0,1,2,3" bitfld.long 0x8 0.--1. "EVNT_BUS0,Status bits showing the R5FSS CPU0 EVNT 0 multi-bit error counter" "0,1,2,3" line.long 0xC "R5FSS_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS,Return to the . Status bits showing the R5FSS CPU1 EVNT BUS multi-bit error counters." hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 12.--13. "EVNT_BUS6,Status bits showing the R5FSS CPU1 EVNT 6 multi-bit error counter" "0,1,2,3" bitfld.long 0xC 10.--11. "EVNT_BUS5,Status bits showing the R5FSS CPU1 EVNT 5 multi-bit error counter" "0,1,2,3" newline bitfld.long 0xC 8.--9. "EVNT_BUS4,Status bits showing the R5FSS CPU1 EVNT 4 multi-bit error counter" "0,1,2,3" bitfld.long 0xC 6.--7. "EVNT_BUS3,Status bits showing the R5FSS CPU1 EVNT 3 multi-bit error counter" "0,1,2,3" bitfld.long 0xC 4.--5. "EVNT_BUS2,Status bits showing the R5FSS CPU1 EVNT 2 multi-bit error counter" "0,1,2,3" newline bitfld.long 0xC 2.--3. "EVNT_BUS1,Status bits showing the R5FSS CPU1 EVNT 1 multi-bit error counter" "0,1,2,3" bitfld.long 0xC 0.--1. "EVNT_BUS0,Status bits showing the R5FSS CPU1 EVNT 0 multi-bit error counter" "0,1,2,3" line.long 0x10 "R5FSS_EVNT_BUS_ESM_STATUS,Return to the . ESM status bits for the R5FSS EVNT BUS." hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 3. "CPU1_MULTIPLE_BIT_ERROR,ESM status of CPU1 multi-bit errors on EVNT BUS" "0,1" bitfld.long 0x10 2. "CPU1_SINGLE_BIT_ERROR,ESM status of CPU1 single-bit errors on EVNT BUS" "0,1" newline bitfld.long 0x10 1. "CPU0_MULTIPLE_BIT_ERROR,ESM status of CPU0 multi-bit errors on EVNT BUS" "0,1" bitfld.long 0x10 0. "CPU0_SINGLE_BIT_ERROR,ESM status of CPU0 single-bit errors on EVNT BUS" "0,1" group.long 0x18++0xF line.long 0x0 "R5FSS_EVNT_BUS_ESM_SET,Return to the . Set the R5FSS EVNT BUS ESM events." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "CPU1_MULTIPLE_BIT_ERROR,Set CPU1 multi-bit errors ESM event" "0,1" bitfld.long 0x0 2. "CPU1_SINGLE_BIT_ERROR,Set CPU1 single-bit errors ESM event" "0,1" newline bitfld.long 0x0 1. "CPU0_MULTIPLE_BIT_ERROR,Set CPU0 multi-bit error ESM event" "0,1" bitfld.long 0x0 0. "CPU0_SINGLE_BIT_ERROR,Set CPU0 single-bit error ESM event" "0,1" line.long 0x4 "R5FSS_EVNT_BUS_ESM_CLR,Return to the . RESET the R5FSS EVNT BUS ESM events." bitfld.long 0x4 31. "CPU1_EB6_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 31 multi-bit error counter" "0,1" bitfld.long 0x4 30. "CPU1_EB5_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 30 multi-bit error counter" "0,1" bitfld.long 0x4 29. "CPU1_EB4_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 29 multi-bit error counter" "0,1" newline bitfld.long 0x4 28. "CPU1_EB3_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 28 multi-bit error counter" "0,1" bitfld.long 0x4 27. "CPU1_EB2_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 27 multi-bit error counter" "0,1" bitfld.long 0x4 26. "CPU1_EB1_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 26 multi-bit error counter" "0,1" newline bitfld.long 0x4 25. "CPU1_EB0_MULTIPLE_BIT_ERROR,Decrement CPU1 EVNT BUS 25 multi-bit error counter" "0,1" bitfld.long 0x4 24. "CPU1_EB8_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 24 single-bit error counter" "0,1" bitfld.long 0x4 23. "CPU1_EB7_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 23 single-bit error counter" "0,1" newline bitfld.long 0x4 22. "CPU1_EB6_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 22 single-bit error counter" "0,1" bitfld.long 0x4 21. "CPU1_EB5_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 21 single-bit error counter" "0,1" bitfld.long 0x4 20. "CPU1_EB4_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 20 single-bit error counter" "0,1" newline bitfld.long 0x4 19. "CPU1_EB3_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 19 single-bit error counter" "0,1" bitfld.long 0x4 18. "CPU1_EB2_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 18 single-bit error counter" "0,1" bitfld.long 0x4 17. "CPU1_EB1_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 17 single-bit error counter" "0,1" newline bitfld.long 0x4 16. "CPU1_EB0_SINGLE_BIT_ERROR,Decrement CPU1 EVNT BUS 16 single-bit error counter" "0,1" bitfld.long 0x4 15. "CPU0_EB6_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 15 multi-bit error counter" "0,1" bitfld.long 0x4 14. "CPU0_EB5_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 14 multi-bit error counter" "0,1" newline bitfld.long 0x4 13. "CPU0_EB4_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 13 multi-bit error counter" "0,1" bitfld.long 0x4 12. "CPU0_EB3_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 12 multi-bit error counter" "0,1" bitfld.long 0x4 11. "CPU0_EB2_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 11 multi-bit error counter" "0,1" newline bitfld.long 0x4 10. "CPU0_EB1_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 10 multi-bit error counter" "0,1" bitfld.long 0x4 9. "CPU0_EB0_MULTIPLE_BIT_ERROR,Decrement CPU0 EVNT BUS 9 multi-bit error counter" "0,1" bitfld.long 0x4 8. "CPU0_EB8_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 8 single-bit error counter" "0,1" newline bitfld.long 0x4 7. "CPU0_EB7_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 7 single-bit error counter" "0,1" bitfld.long 0x4 6. "CPU0_EB6_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 6 single-bit error counter" "0,1" bitfld.long 0x4 5. "CPU0_EB5_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 5 single-bit error counter" "0,1" newline bitfld.long 0x4 4. "CPU0_EB4_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 4 single-bit error counter" "0,1" bitfld.long 0x4 3. "CPU0_EB3_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 3 single-bit error counter" "0,1" bitfld.long 0x4 2. "CPU0_EB2_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 2 single-bit error counter" "0,1" newline bitfld.long 0x4 1. "CPU0_EB1_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 1 single-bit error counter" "0,1" bitfld.long 0x4 0. "CPU0_EB0_SINGLE_BIT_ERROR,Decrement CPU0 EVNT BUS 0 single-bit error counter" "0,1" line.long 0x8 "R5FSS_EVNT_BUS_MASK_ESM_SET,Return to the . Mask the R5FSS EVNT BUS ESM events." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "CPU1_MULTIPLE_BIT_ERROR,Mask CPU1 multi-bit errors ESM event" "0,1" bitfld.long 0x8 2. "CPU1_SINGLE_BIT_ERROR,Mask CPU1 single-bit errors ESM event" "0,1" newline bitfld.long 0x8 1. "CPU0_MULTIPLE_BIT_ERROR,Mask CPU0 multi-bit error ESM event" "0,1" bitfld.long 0x8 0. "CPU0_SINGLE_BIT_ERROR,Mask CPU0 single-bit error ESM event" "0,1" line.long 0xC "R5FSS_EVNT_BUS_MASK_ESM_CLR,Return to the . Unmask the R5FSS EVNT BUS ESM events." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 3. "CPU1_MULTIPLE_BIT_ERROR,Unmask CPU1 multi-bit errors ESM event" "0,1" bitfld.long 0xC 2. "CPU1_SINGLE_BIT_ERROR,Unmask CPU1 single-bit errors ESM event" "0,1" newline bitfld.long 0xC 1. "CPU0_MULTIPLE_BIT_ERROR,Unmask CPU0 multi-bit error ESM event" "0,1" bitfld.long 0xC 0. "CPU0_SINGLE_BIT_ERROR,Unmask CPU0 single-bit error ESM event" "0,1" tree.end tree "R5FSS0_COMPARE_CFG" base ad:0x5B00000 group.long 0x0++0x7 line.long 0x0 "R5FSS_CCMSR1,This register shows the error and self-test status of the CPU output compare block." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 16. "CMPE1,Compare error for CPU output compare diagnostic." "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 8. "STC1,Self-test complete for CPU output compare diagnostic." "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 1. "STET1,Self-test error type for CPU output compare diagnostic." "0,1" bitfld.long 0x0 0. "STE1,Self-test error for CPU output compare diagnostic." "0,1" line.long 0x4 "R5FSS_CCMKEYR1,This register is used to select the operating mode of the CPU output compare block." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x4 0.--3. 1. "MKEY1,Mode key to select operation for CPU output compare diagnostic." group.long 0x10++0xB line.long 0x0 "R5FSS_CCMSR3,This register shows the error and self-test status of the inactivity monitor block." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 16. "CMPE3,Compare error for inactivity monitor." "0,1" hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 8. "STC3,Self-test complete for inactivity monitor." "0,1" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." bitfld.long 0x0 1. "STET3,Self-test error type for inactivity monitor." "0,1" bitfld.long 0x0 0. "STE3,Self-test error for inactivity monitor." "0,1" line.long 0x4 "R5FSS_CCMKEYR3,This register is used to select the operating mode of the inactivity monitor block." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x4 0.--3. 1. "MKEY3,Mode key to select operation for CPU output compare diagnostic." line.long 0x8 "R5FSS_CCMPOLCNTRL,This register is used for polarity inversion of CPU compare signals." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Reserved. Reads return 0. Writes have no effect." hexmask.long.byte 0x8 0.--7. 1. "POL_INV,Polarity inversion. This value is used to invert one of the 8 output compare signals from CPU1 to the R5FSS_CCMR5. Inverting any one signal will lead to compare error by the CPU output compare diagnostic." tree.end tree "R5FSS0_CORE0_ECC_AGGR" base ad:0x2A68000 rgroup.long 0x0++0x3 line.long 0x0 "R5FSS_CPU0_REV,Revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "R5FSS_CPU0_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address." bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved." hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "R5FSS_CPU0_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved." hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator." group.long 0x3C++0xB line.long 0x0 "R5FSS_CPU0_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 0. "EOI_WR,EOI value." "0,1" line.long 0x4 "R5FSS_CPU0_SEC_STATUS_REG0,SEC interrupt status register 0." bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "R5FSS_CPU0_SEC_STATUS_REG1,SEC interrupt status register 1." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1" bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x80++0x7 line.long 0x0 "R5FSS_CPU0_SEC_ENABLE_SET_REG0,SEC Interrupt enable set register 0." bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU0_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1" bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0xC0++0x7 line.long 0x0 "R5FSS_CPU0_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0." bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU0_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1" bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x13C++0xB line.long 0x0 "R5FSS_CPU0_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 0. "EOI_WR,EOI value." "0,1" line.long 0x4 "R5FSS_CPU0_DED_STATUS_REG0,DED interrupt status register 0." bitfld.long 0x4 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x4 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x4 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x4 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1" line.long 0x8 "R5FSS_CPU0_DED_STATUS_REG1,DED interrupt status register 1." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1" bitfld.long 0x8 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x8 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x180++0x7 line.long 0x0 "R5FSS_CPU0_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU0_DED_ENABLE_SET_REG1,DED interrupt enable set register 1." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1" bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x1C0++0x7 line.long 0x0 "R5FSS_CPU0_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." bitfld.long 0x0 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU0_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1." hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1" bitfld.long 0x4 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "R5FSS_CPU0_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "R5FSS_CPU0_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "R5FSS_CPU0_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "R5FSS_CPU0_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "R5FSS0_ECC_AGGR" base ad:0x5B10000 rgroup.long 0x0++0x3 line.long 0x0 "R5FSS_CPU1_REV,Revision register." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x8++0x3 line.long 0x0 "R5FSS_CPU1_VECTOR,ECC vector register." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved." bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address." bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS." "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved." hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status." rgroup.long 0xC++0x3 line.long 0x0 "R5FSS_CPU1_STAT,Misc status register." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x3C++0xB line.long 0x0 "R5FSS_CPU1_SEC_EOI_REG,SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "R5FSS_CPU1_SEC_STATUS_REG0,SEC interrupt status register 0." bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "R5FSS_CPU1_SEC_STATUS_REG1,SEC interrupt status register 1." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x80++0x7 line.long 0x0 "R5FSS_CPU1_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0." bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU1_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0xC0++0x7 line.long 0x0 "R5FSS_CPU1_SEC_ENABLE_CLR_REG0,SC interrupt enable clear register 0." bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU1_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x13C++0xB line.long 0x0 "R5FSS_CPU1_DED_EOI_REG,DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "EOI_WR,EOI value" "0,1" line.long 0x4 "R5FSS_CPU1_DED_STATUS_REG0,DED interrupt status register 0." bitfld.long 0x4 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x4 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x4 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x4 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1" line.long 0x8 "R5FSS_CPU1_DED_STATUS_REG1,DED interrupt status register 1." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x8 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x8 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x180++0x7 line.long 0x0 "R5FSS_CPU1_DED_ENABLE_SET_REG0,DED interrupt enable set register 0." bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU1_DED_ENABLE_SET_REG1,DED interrupt enable set register 1." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x1C0++0x7 line.long 0x0 "R5FSS_CPU1_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0." bitfld.long 0x0 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1" bitfld.long 0x0 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1" newline bitfld.long 0x0 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1" bitfld.long 0x0 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1" newline bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1" line.long 0x4 "R5FSS_CPU1_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1" bitfld.long 0x4 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "R5FSS_CPU1_AGGR_ENABLE_SET,AGGR interrupt enable set register." hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,Interrupt enable set for parity errors" "0,1" line.long 0x4 "R5FSS_CPU1_AGGR_ENABLE_CLR,AGGR interrupt enable clear register." hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,Interrupt enable clear for parity errors" "0,1" line.long 0x8 "R5FSS_CPU1_AGGR_STATUS_SET,AGGR interrupt status set register." hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "R5FSS_CPU1_AGGR_STATUS_CLR,AGGR interrupt status clear register." hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "RTI" base ad:0x0 tree "RTI0_CFG" base ad:0x2200000 group.long 0x0++0x1B line.long 0x0 "RTI_GCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "COS,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting." "0,1" hexmask.long.word 0x0 2.--14. 1. "RESERVED,Reserved." bitfld.long 0x0 1. "CNT1EN,Counter 1 Enable." "0,1" bitfld.long 0x0 0. "CNT0EN,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0)." "0,1" line.long 0x4 "RTI_TBCTRL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected." "0,1" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0,1" line.long 0x8 "RTI_CAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 1. "CAPCNTR1,Capture Counter 1." "0,1" bitfld.long 0x8 0. "CAPCNTR0,Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0." "0,1" line.long 0xC "RTI_COMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 12. "COMPSEL3,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared." "0,1" rbitfld.long 0xC 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "COMPSEL2,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared." "0,1" rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4. "COMPSEL1,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared." "0,1" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0. "COMPSEL0,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared." "0,1" line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously." hexmask.long 0x10 0.--31. 1. "FRC0,Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously." line.long 0x14 "RTI_UC0" hexmask.long 0x14 0.--31. 1. "UC0,Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,Compare Up Counter 0. This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value." rgroup.long 0x20++0x7 line.long 0x0 "RTI_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the" group.long 0x30++0xB line.long 0x0 "RTI_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously." line.long 0x4 "RTI_UC1" hexmask.long 0x4 0.--31. 1. "UC1,Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,Compare Up Counter 1. This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value." rgroup.long 0x40++0x7 line.long 0x0 "RTI_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the" group.long 0x50++0x1F line.long 0x0 "RTI_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x4 "RTI_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x8 "RTI_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,Compare 1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0xC "RTI_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,Update Compare 1 Register. This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x10 "RTI_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,Compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." hexmask.long 0x14 0.--31. 1. "UDCP2,Update Compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x18 "RTI_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,Compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x1C "RTI_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,Update Compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." rgroup.long 0x70++0x7 line.long 0x0 "RTI_TBLCOMP" hexmask.long 0x0 0.--31. 1. "TBLCOMP,Reserved" line.long 0x4 "RTI_TBHCOMP" hexmask.long 0x4 0.--31. 1. "TBHCOMP,Reserved" group.long 0x80++0xB line.long 0x0 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x0 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read):" "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "SETDMA3,Set Compare DMA Request 3." "0,1" newline bitfld.long 0x0 10. "SETDMA2,Set Compare DMA Request 2." "0,1" bitfld.long 0x0 9. "SETDMA1,Set Compare DMA Request 1." "0,1" bitfld.long 0x0 8. "SETDMA0,Set Compare DMA Request 0." "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "SETINT3,Set Compare Interrupt 3." "0,1" bitfld.long 0x0 2. "SETINT2,Set Compare Interrupt 2." "0,1" newline bitfld.long 0x0 1. "SETINT1,Set Compare Interrupt 1." "0,1" bitfld.long 0x0 0. "SETINT0,Set Compare Interrupt 0." "0,1" line.long 0x4 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see.." hexmask.long.word 0x4 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x4 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x4 16. "CLEARTBINT" "0,1" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 11. "CLEARDMA3,Clear Compare DMA Request 3." "0,1" newline bitfld.long 0x4 10. "CLEARDMA2,Clear Compare DMA Request 2." "0,1" bitfld.long 0x4 9. "CLEARDMA1,Clear Compare DMA Request 1." "0,1" bitfld.long 0x4 8. "CLEARDMA0,Clear Compare DMA Request 0." "0,1" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CLEARINT3,Clear Compare Interrupt 3." "0,1" bitfld.long 0x4 2. "CLEARINT2,Clear Compare Interrupt 2." "0,1" newline bitfld.long 0x4 1. "CLEARINT1,Clear Compare Interrupt 1." "0,1" bitfld.long 0x4 0. "CLEARINT0,Clear Compare Interrupt 0." "0,1" line.long 0x8 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not." hexmask.long.word 0x8 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software." "0,1" hexmask.long.word 0x8 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "INT3,Interrupt Flag 3." "0,1" newline bitfld.long 0x8 2. "INT2,Interrupt Flag 2." "0,1" bitfld.long 0x8 1. "INT1,Interrupt Flag 1." "0,1" bitfld.long 0x8 0. "INT0,Interrupt Flag 0." "0,1" group.long 0x90++0xF line.long 0x0 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be.." hexmask.long 0x0 0.--31. 1. "DWDCTRL,Digital Watchdog Control." line.long 0x4 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value." line.long 0x8 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These.." hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 5. "DWWD_ST,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog." "0,1" bitfld.long 0x8 4. "END,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag." "0,1" bitfld.long 0x8 3. "START,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened." "0,1" bitfld.long 0x8 2. "KEYST,Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the" "0,1" bitfld.long 0x8 1. "DWDST,Digital Watchdog Status. Status flag and is maintained for compatibility reasons." "0,1" newline bitfld.long 0x8 0. "AWDST,Analog Watchdog Status." "0,1" line.long 0xC "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -&gt; Value written to WDKEY -&gt; Result1 -&gt; 0x0A35C -&gt; No Action2 -&gt; 0x0A35C -&gt; No Action3 -&gt; 0x0E51A -&gt; WDKEY is enabled for reset by next 0x0A35C4.." rgroup.long 0xA0++0x3 line.long 0x0 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" hexmask.long 0x0 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 01FFFFFFh. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3 MHz a watchdog reset will be generated in.." group.long 0xA4++0x1B line.long 0x0 "RTI_WWDRXNCTRL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,Digital Windowed Watchdog Reaction." line.long 0x4 "RTI_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,Digital Windowed Watchdog Window Size." line.long 0x8 "RTI_INTCLRENABLE" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt." hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt." hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt." line.long 0xC "RTI_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared." line.long 0x10 "RTI_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared." line.long 0x14 "RTI_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared." line.long 0x18 "RTI_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared." tree.end tree "RTI1_CFG" base ad:0x2210000 group.long 0x0++0x1B line.long 0x0 "RTI_GCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "COS,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting." "0,1" hexmask.long.word 0x0 2.--14. 1. "RESERVED,Reserved." bitfld.long 0x0 1. "CNT1EN,Counter 1 Enable." "0,1" bitfld.long 0x0 0. "CNT0EN,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0)." "0,1" line.long 0x4 "RTI_TBCTRL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected." "0,1" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0,1" line.long 0x8 "RTI_CAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 1. "CAPCNTR1,Capture Counter 1." "0,1" bitfld.long 0x8 0. "CAPCNTR0,Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0." "0,1" line.long 0xC "RTI_COMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 12. "COMPSEL3,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared." "0,1" rbitfld.long 0xC 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "COMPSEL2,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared." "0,1" rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4. "COMPSEL1,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared." "0,1" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0. "COMPSEL0,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared." "0,1" line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously." hexmask.long 0x10 0.--31. 1. "FRC0,Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously." line.long 0x14 "RTI_UC0" hexmask.long 0x14 0.--31. 1. "UC0,Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,Compare Up Counter 0. This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value." rgroup.long 0x20++0x7 line.long 0x0 "RTI_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the" group.long 0x30++0xB line.long 0x0 "RTI_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously." line.long 0x4 "RTI_UC1" hexmask.long 0x4 0.--31. 1. "UC1,Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,Compare Up Counter 1. This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value." rgroup.long 0x40++0x7 line.long 0x0 "RTI_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the" group.long 0x50++0x1F line.long 0x0 "RTI_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x4 "RTI_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x8 "RTI_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,Compare 1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0xC "RTI_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,Update Compare 1 Register. This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x10 "RTI_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,Compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." hexmask.long 0x14 0.--31. 1. "UDCP2,Update Compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x18 "RTI_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,Compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x1C "RTI_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,Update Compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." rgroup.long 0x70++0x7 line.long 0x0 "RTI_TBLCOMP" hexmask.long 0x0 0.--31. 1. "TBLCOMP,Reserved" line.long 0x4 "RTI_TBHCOMP" hexmask.long 0x4 0.--31. 1. "TBHCOMP,Reserved" group.long 0x80++0xB line.long 0x0 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x0 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read):" "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "SETDMA3,Set Compare DMA Request 3." "0,1" newline bitfld.long 0x0 10. "SETDMA2,Set Compare DMA Request 2." "0,1" bitfld.long 0x0 9. "SETDMA1,Set Compare DMA Request 1." "0,1" bitfld.long 0x0 8. "SETDMA0,Set Compare DMA Request 0." "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "SETINT3,Set Compare Interrupt 3." "0,1" bitfld.long 0x0 2. "SETINT2,Set Compare Interrupt 2." "0,1" newline bitfld.long 0x0 1. "SETINT1,Set Compare Interrupt 1." "0,1" bitfld.long 0x0 0. "SETINT0,Set Compare Interrupt 0." "0,1" line.long 0x4 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see.." hexmask.long.word 0x4 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x4 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x4 16. "CLEARTBINT" "0,1" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 11. "CLEARDMA3,Clear Compare DMA Request 3." "0,1" newline bitfld.long 0x4 10. "CLEARDMA2,Clear Compare DMA Request 2." "0,1" bitfld.long 0x4 9. "CLEARDMA1,Clear Compare DMA Request 1." "0,1" bitfld.long 0x4 8. "CLEARDMA0,Clear Compare DMA Request 0." "0,1" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CLEARINT3,Clear Compare Interrupt 3." "0,1" bitfld.long 0x4 2. "CLEARINT2,Clear Compare Interrupt 2." "0,1" newline bitfld.long 0x4 1. "CLEARINT1,Clear Compare Interrupt 1." "0,1" bitfld.long 0x4 0. "CLEARINT0,Clear Compare Interrupt 0." "0,1" line.long 0x8 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not." hexmask.long.word 0x8 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software." "0,1" hexmask.long.word 0x8 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "INT3,Interrupt Flag 3." "0,1" newline bitfld.long 0x8 2. "INT2,Interrupt Flag 2." "0,1" bitfld.long 0x8 1. "INT1,Interrupt Flag 1." "0,1" bitfld.long 0x8 0. "INT0,Interrupt Flag 0." "0,1" group.long 0x90++0xF line.long 0x0 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be.." hexmask.long 0x0 0.--31. 1. "DWDCTRL,Digital Watchdog Control." line.long 0x4 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value." line.long 0x8 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These.." hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 5. "DWWD_ST,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog." "0,1" bitfld.long 0x8 4. "END,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag." "0,1" bitfld.long 0x8 3. "START,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened." "0,1" bitfld.long 0x8 2. "KEYST,Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the" "0,1" bitfld.long 0x8 1. "DWDST,Digital Watchdog Status. Status flag and is maintained for compatibility reasons." "0,1" newline bitfld.long 0x8 0. "AWDST,Analog Watchdog Status." "0,1" line.long 0xC "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -&gt; Value written to WDKEY -&gt; Result1 -&gt; 0x0A35C -&gt; No Action2 -&gt; 0x0A35C -&gt; No Action3 -&gt; 0x0E51A -&gt; WDKEY is enabled for reset by next 0x0A35C4.." rgroup.long 0xA0++0x3 line.long 0x0 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" hexmask.long 0x0 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 01FFFFFFh. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3 MHz a watchdog reset will be generated in.." group.long 0xA4++0x1B line.long 0x0 "RTI_WWDRXNCTRL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,Digital Windowed Watchdog Reaction." line.long 0x4 "RTI_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,Digital Windowed Watchdog Window Size." line.long 0x8 "RTI_INTCLRENABLE" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt." hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt." hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt." line.long 0xC "RTI_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared." line.long 0x10 "RTI_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared." line.long 0x14 "RTI_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared." line.long 0x18 "RTI_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared." tree.end tree "RTI28_CFG" base ad:0x23C0000 group.long 0x0++0x1B line.long 0x0 "RTI_GCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "COS,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting." "0,1" hexmask.long.word 0x0 2.--14. 1. "RESERVED,Reserved." bitfld.long 0x0 1. "CNT1EN,Counter 1 Enable." "0,1" bitfld.long 0x0 0. "CNT0EN,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0)." "0,1" line.long 0x4 "RTI_TBCTRL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected." "0,1" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0,1" line.long 0x8 "RTI_CAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 1. "CAPCNTR1,Capture Counter 1." "0,1" bitfld.long 0x8 0. "CAPCNTR0,Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0." "0,1" line.long 0xC "RTI_COMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 12. "COMPSEL3,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared." "0,1" rbitfld.long 0xC 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "COMPSEL2,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared." "0,1" rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4. "COMPSEL1,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared." "0,1" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0. "COMPSEL0,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared." "0,1" line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously." hexmask.long 0x10 0.--31. 1. "FRC0,Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously." line.long 0x14 "RTI_UC0" hexmask.long 0x14 0.--31. 1. "UC0,Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,Compare Up Counter 0. This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value." rgroup.long 0x20++0x7 line.long 0x0 "RTI_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the" group.long 0x30++0xB line.long 0x0 "RTI_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously." line.long 0x4 "RTI_UC1" hexmask.long 0x4 0.--31. 1. "UC1,Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,Compare Up Counter 1. This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value." rgroup.long 0x40++0x7 line.long 0x0 "RTI_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the" group.long 0x50++0x1F line.long 0x0 "RTI_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x4 "RTI_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x8 "RTI_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,Compare 1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0xC "RTI_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,Update Compare 1 Register. This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x10 "RTI_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,Compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." hexmask.long 0x14 0.--31. 1. "UDCP2,Update Compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x18 "RTI_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,Compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x1C "RTI_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,Update Compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." rgroup.long 0x70++0x7 line.long 0x0 "RTI_TBLCOMP" hexmask.long 0x0 0.--31. 1. "TBLCOMP,Reserved" line.long 0x4 "RTI_TBHCOMP" hexmask.long 0x4 0.--31. 1. "TBHCOMP,Reserved" group.long 0x80++0xB line.long 0x0 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x0 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read):" "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "SETDMA3,Set Compare DMA Request 3." "0,1" newline bitfld.long 0x0 10. "SETDMA2,Set Compare DMA Request 2." "0,1" bitfld.long 0x0 9. "SETDMA1,Set Compare DMA Request 1." "0,1" bitfld.long 0x0 8. "SETDMA0,Set Compare DMA Request 0." "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "SETINT3,Set Compare Interrupt 3." "0,1" bitfld.long 0x0 2. "SETINT2,Set Compare Interrupt 2." "0,1" newline bitfld.long 0x0 1. "SETINT1,Set Compare Interrupt 1." "0,1" bitfld.long 0x0 0. "SETINT0,Set Compare Interrupt 0." "0,1" line.long 0x4 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see.." hexmask.long.word 0x4 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x4 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x4 16. "CLEARTBINT" "0,1" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 11. "CLEARDMA3,Clear Compare DMA Request 3." "0,1" newline bitfld.long 0x4 10. "CLEARDMA2,Clear Compare DMA Request 2." "0,1" bitfld.long 0x4 9. "CLEARDMA1,Clear Compare DMA Request 1." "0,1" bitfld.long 0x4 8. "CLEARDMA0,Clear Compare DMA Request 0." "0,1" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CLEARINT3,Clear Compare Interrupt 3." "0,1" bitfld.long 0x4 2. "CLEARINT2,Clear Compare Interrupt 2." "0,1" newline bitfld.long 0x4 1. "CLEARINT1,Clear Compare Interrupt 1." "0,1" bitfld.long 0x4 0. "CLEARINT0,Clear Compare Interrupt 0." "0,1" line.long 0x8 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not." hexmask.long.word 0x8 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software." "0,1" hexmask.long.word 0x8 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "INT3,Interrupt Flag 3." "0,1" newline bitfld.long 0x8 2. "INT2,Interrupt Flag 2." "0,1" bitfld.long 0x8 1. "INT1,Interrupt Flag 1." "0,1" bitfld.long 0x8 0. "INT0,Interrupt Flag 0." "0,1" group.long 0x90++0xF line.long 0x0 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be.." hexmask.long 0x0 0.--31. 1. "DWDCTRL,Digital Watchdog Control." line.long 0x4 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value." line.long 0x8 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These.." hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 5. "DWWD_ST,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog." "0,1" bitfld.long 0x8 4. "END,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag." "0,1" bitfld.long 0x8 3. "START,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened." "0,1" bitfld.long 0x8 2. "KEYST,Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the" "0,1" bitfld.long 0x8 1. "DWDST,Digital Watchdog Status. Status flag and is maintained for compatibility reasons." "0,1" newline bitfld.long 0x8 0. "AWDST,Analog Watchdog Status." "0,1" line.long 0xC "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -&gt; Value written to WDKEY -&gt; Result1 -&gt; 0x0A35C -&gt; No Action2 -&gt; 0x0A35C -&gt; No Action3 -&gt; 0x0E51A -&gt; WDKEY is enabled for reset by next 0x0A35C4.." rgroup.long 0xA0++0x3 line.long 0x0 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" hexmask.long 0x0 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 01FFFFFFh. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3 MHz a watchdog reset will be generated in.." group.long 0xA4++0x1B line.long 0x0 "RTI_WWDRXNCTRL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,Digital Windowed Watchdog Reaction." line.long 0x4 "RTI_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,Digital Windowed Watchdog Window Size." line.long 0x8 "RTI_INTCLRENABLE" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt." hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt." hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt." line.long 0xC "RTI_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared." line.long 0x10 "RTI_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared." line.long 0x14 "RTI_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared." line.long 0x18 "RTI_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared." tree.end tree "RTI29_CFG" base ad:0x23D0000 group.long 0x0++0x1B line.long 0x0 "RTI_GCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "COS,Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting." "0,1" hexmask.long.word 0x0 2.--14. 1. "RESERVED,Reserved." bitfld.long 0x0 1. "CNT1EN,Counter 1 Enable." "0,1" bitfld.long 0x0 0. "CNT0EN,Counter 0 Enable. The CNT0EN bit starts and stops the operation of counter block0 (UC0 and FRC0)." "0,1" line.long 0x4 "RTI_TBCTRL" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected." "0,1" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0,1" line.long 0x8 "RTI_CAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 1. "CAPCNTR1,Capture Counter 1." "0,1" bitfld.long 0x8 0. "CAPCNTR0,Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0." "0,1" line.long 0xC "RTI_COMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 12. "COMPSEL3,Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared." "0,1" rbitfld.long 0xC 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8. "COMPSEL2,Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared." "0,1" rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 4. "COMPSEL1,Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared." "0,1" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0. "COMPSEL0,Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared." "0,1" line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously." hexmask.long 0x10 0.--31. 1. "FRC0,Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously." line.long 0x14 "RTI_UC0" hexmask.long 0x14 0.--31. 1. "UC0,Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,Compare Up Counter 0. This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value." rgroup.long 0x20++0x7 line.long 0x0 "RTI_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the" group.long 0x30++0xB line.long 0x0 "RTI_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously." line.long 0x4 "RTI_UC1" hexmask.long 0x4 0.--31. 1. "UC1,Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,Compare Up Counter 1. This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value." rgroup.long 0x40++0x7 line.long 0x0 "RTI_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when an event occurs controlled by the external capture control block." line.long 0x4 "RTI_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when an event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the" group.long 0x50++0x1F line.long 0x0 "RTI_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x4 "RTI_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x8 "RTI_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,Compare 1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0xC "RTI_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,Update Compare 1 Register. This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x10 "RTI_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,Compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." hexmask.long 0x14 0.--31. 1. "UDCP2,Update Compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." line.long 0x18 "RTI_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,Compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to.." line.long 0x1C "RTI_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,Update Compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention." rgroup.long 0x70++0x7 line.long 0x0 "RTI_TBLCOMP" hexmask.long 0x0 0.--31. 1. "TBLCOMP,Reserved" line.long 0x4 "RTI_TBHCOMP" hexmask.long 0x4 0.--31. 1. "TBHCOMP,Reserved" group.long 0x80++0xB line.long 0x0 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see ..." hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x0 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read):" "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 11. "SETDMA3,Set Compare DMA Request 3." "0,1" newline bitfld.long 0x0 10. "SETDMA2,Set Compare DMA Request 2." "0,1" bitfld.long 0x0 9. "SETDMA1,Set Compare DMA Request 1." "0,1" bitfld.long 0x0 8. "SETDMA0,Set Compare DMA Request 0." "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "SETINT3,Set Compare Interrupt 3." "0,1" bitfld.long 0x0 2. "SETINT2,Set Compare Interrupt 2." "0,1" newline bitfld.long 0x0 1. "SETINT1,Set Compare Interrupt 1." "0,1" bitfld.long 0x0 0. "SETINT0,Set Compare Interrupt 0." "0,1" line.long 0x4 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled. Some of the RTI features described in this section may not be supported on this family of devices. For more information. see.." hexmask.long.word 0x4 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt." "0,1" bitfld.long 0x4 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt." "0,1" bitfld.long 0x4 16. "CLEARTBINT" "0,1" hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 11. "CLEARDMA3,Clear Compare DMA Request 3." "0,1" newline bitfld.long 0x4 10. "CLEARDMA2,Clear Compare DMA Request 2." "0,1" bitfld.long 0x4 9. "CLEARDMA1,Clear Compare DMA Request 1." "0,1" bitfld.long 0x4 8. "CLEARDMA0,Clear Compare DMA Request 0." "0,1" hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x4 3. "CLEARINT3,Clear Compare Interrupt 3." "0,1" bitfld.long 0x4 2. "CLEARINT2,Clear Compare Interrupt 2." "0,1" newline bitfld.long 0x4 1. "CLEARINT1,Clear Compare Interrupt 1." "0,1" bitfld.long 0x4 0. "CLEARINT0,Clear Compare Interrupt 0." "0,1" line.long 0x8 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not." hexmask.long.word 0x8 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag." "0,1" bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software." "0,1" hexmask.long.word 0x8 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "INT3,Interrupt Flag 3." "0,1" newline bitfld.long 0x8 2. "INT2,Interrupt Flag 2." "0,1" bitfld.long 0x8 1. "INT1,Interrupt Flag 1." "0,1" bitfld.long 0x8 0. "INT0,Interrupt Flag 0." "0,1" group.long 0x90++0xF line.long 0x0 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. This register's functionality is dependent on whether the DWD is implemented to be.." hexmask.long 0x0 0.--31. 1. "DWDCTRL,Digital Watchdog Control." line.long 0x4 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value." line.long 0x8 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features. The values of the following status bits will not be affected by a system reset. These.." hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 5. "DWWD_ST,Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog." "0,1" bitfld.long 0x8 4. "END,Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag." "0,1" bitfld.long 0x8 3. "START,Windowed Watchdog End Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened." "0,1" bitfld.long 0x8 2. "KEYST,Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the" "0,1" bitfld.long 0x8 1. "DWDST,Digital Watchdog Status. Status flag and is maintained for compatibility reasons." "0,1" newline bitfld.long 0x8 0. "AWDST,Analog Watchdog Status." "0,1" line.long 0xC "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.word 0xC 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0xC 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -&gt; Value written to WDKEY -&gt; Result1 -&gt; 0x0A35C -&gt; No Action2 -&gt; 0x0A35C -&gt; No Action3 -&gt; 0x0E51A -&gt; WDKEY is enabled for reset by next 0x0A35C4.." rgroup.long 0xA0++0x3 line.long 0x0 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices. For more information. see . RTI Not Supported Features." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" hexmask.long 0x0 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 01FFFFFFh. When the DWD is enabled and the DWD counter starts counting down from this value with an RTI_FCLK time base of 3 MHz a watchdog reset will be generated in.." group.long 0xA4++0x1B line.long 0x0 "RTI_WWDRXNCTRL" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,Digital Windowed Watchdog Reaction." line.long 0x4 "RTI_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,Digital Windowed Watchdog Window Size." line.long 0x8 "RTI_INTCLRENABLE" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt." hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt." hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt." line.long 0xC "RTI_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared." line.long 0x10 "RTI_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared." line.long 0x14 "RTI_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared." line.long 0x18 "RTI_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared." tree.end tree.end tree "SEC_MMR" base ad:0x0 tree "SEC_MMR0_BOOT_CTRL" base ad:0x45A40000 rgroup.long 0x20++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_DEF,Defines the type of the processor cluster." hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16.--18. "CORE_NUM,Number of cores in cluster" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. "DSP_CORE_TYPE,DSP core type configuration 00h - C7x 01h - C6x FFh - Not DSP" hexmask.long.byte 0x0 0.--7. 1. "ARM_CORE_TYPE,ARM core type configuration 00h - A53 01h - A57 10h - R5 FFh - Not ARM" group.long 0x40++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CFG,Configures cluster level characteristics." hexmask.long 0x0 5.--31. 1. "CLSTR_CFG_RSVD,Reserved for future use. Write '0' to ensure compatibility with future devices." bitfld.long 0x0 4. "MEM_INIT_DIS,Disables SRAM initialization (TCM Cache Tags etc) at reset" "0,1" rbitfld.long 0x0 3. "LOCKSTEP_EN,Lockstep enable. Indicates if R5 lockstep operation is supported on the device" "0,1" bitfld.long 0x0 2. "DBG_NO_CLKSTOP,CPU clockstop behavior" "0,1" newline bitfld.long 0x0 1. "TEINIT,Exception handling state at reset:" "0,1" bitfld.long 0x0 0. "LOCKSTEP,When set Core0 and Core1 operate in lockstep mode. Can only be changed if lockstep operation is supported as indicated by CLSTR0_CFG_lockstep_en = 1. If CLSTR0_CFG_lockstep_en = 0 lockstep is not supported this bit will be read only with a.." "0,1" group.long 0x100++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE0_CFG,Configures the TCM and interrupt operation of R5 Core0." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts when set" "0,1" rbitfld.long 0x0 12.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator" "0,1" newline rbitfld.long 0x0 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "BTCM_EN,Enable Core0 BTCM RAM at reset when set" "0,1" rbitfld.long 0x0 4.--6. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "ATCM_EN,Enable Core0 ATCM RAM at reset when set" "0,1" newline rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" group.long 0x110++0x7 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core0. Bits 4:0 are not used and are always 0." hexmask.long 0x0 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." hexmask.long.byte 0x0 0.--6. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core0." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." group.long 0x120++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE0_PMCTRL,Configures Cluster Core0 power state." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CORE_HALT,Halt Core0.When 0 indicates that Core0 is in the Halt state." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE0_PMSTAT,Shows Cluster Core0 power status." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "CLK_GATE,Core0 Clocked stoppedWhen 0 indicates clock stopped due to WFI or WFE state" "0,1" bitfld.long 0x0 2. "RESERVED,Reserved" "0,1" bitfld.long 0x0 1. "WFE,Core0 WFE" "0,1" newline bitfld.long 0x0 0. "WFI,Core0 WFI" "0,1" group.long 0x180++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE1_CFG,Configures the TCM and interrupt operation of R5 Core1." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 15. "NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts when set" "0,1" rbitfld.long 0x0 12.--14. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator" "0,1" newline rbitfld.long 0x0 8.--10. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "BTCM_EN,Enable Core1 BTCM RAM at reset when set" "0,1" rbitfld.long 0x0 4.--6. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "ATCM_EN,Enable Core1 ATCM RAM at reset when set" "0,1" newline rbitfld.long 0x0 0.--2. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" group.long 0x190++0x7 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE1_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core1. Bits 4:0 are not used and are always 0." hexmask.long 0x0 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0." hexmask.long.byte 0x0 0.--6. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_SEC_CLSTR0_CORE1_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core1." hexmask.long.word 0x4 16.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]." group.long 0x1A0++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE1_PMCTRL,Configures Cluster Core1 power state." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CORE_HALT,Halt Core1.When 0 indicates that Core1 is in the Halt state." "0,1" rgroup.long 0x1B0++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE1_PMSTAT,Shows Cluster Core1 power status." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "CLK_GATE,Core1 Clocked stoppedWhen 0 indicates clock stopped due to WFI or WFE state" "0,1" bitfld.long 0x0 2. "RESERVED,Reserved" "0,1" bitfld.long 0x0 1. "WFE,Core1 WFE" "0,1" newline bitfld.long 0x0 0. "WFI,Core1 WFI" "0,1" tree.end tree "SEC_MMR0_DBG_CTRL" base ad:0x45944000 group.long 0x0++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE0_DBG_CFG,Configures debug operation for Cluster Core0." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "DBGEN,Core0 Invasive debug enable." hexmask.long.byte 0x0 8.--11. 1. "NIDEN,Core0 Non-invasive debug enable." hexmask.long.byte 0x0 0.--7. 1. "RESERVED,Reserved" group.long 0x40++0x3 line.long 0x0 "CTRLMMR_SEC_CLSTR0_CORE1_DBG_CFG,Configures debug operation for Cluster Core1." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 12.--15. 1. "DBGEN,Core1 Invasive debug enable." hexmask.long.byte 0x0 8.--11. 1. "NIDEN,Core1 Non-invasive debug enable." hexmask.long.byte 0x0 0.--7. 1. "RESERVED,Reserved" tree.end tree.end tree "SERDES_10G0" base ad:0x5060000 rgroup.long 0x0++0xB line.long 0x0 "CMN_PID_TYPE,Product type ID register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "CMN_PID_TYPE_15_0,Product type : This field contains the ASCII codes that represent the product type sd for SerDes." line.long 0x4 "CMN_PID_NUM,Product number ID register" hexmask.long.word 0x4 16.--31. 1. "CMN_PID_NUM_15_0,Product number : This field contains the binary coded decimal numbers that represent the product number." newline hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CMN_PID_REV,Product revision ID register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" newline hexmask.long.word 0x8 0.--15. 1. "CMN_PID_REV_15_0,Product revision : This field contains the binary coded decimal numbers that represent the product revision." rgroup.long 0x10++0xB line.long 0x0 "CMN_PID_NODE__CMN_PID_MFG,Product technology manufacturer ID register" hexmask.long.word 0x0 16.--31. 1. "CMN_PID_NODE_15_0,Product technology process node : This field contains the binary coded decimal numbers that represent the product technology node" newline hexmask.long.word 0x0 0.--15. 1. "CMN_PID_MFG_15_0,Product technology manufacturer : This field contains the ASCII codes that represent the product technology manufacturer t for TSMC." line.long 0x4 "CMN_PID_FLV1__CMN_PID_FLV0,Product technology process flavor ID register 0" hexmask.long.word 0x4 16.--31. 1. "CMN_PID_FLV1_15_0,Product technology flavor : This field contains the ASCII codes that represent the second two characters of the product technology flavor." newline hexmask.long.word 0x4 0.--15. 1. "CMN_PID_FLV0_15_0,Product technology flavor : This field contains the ASCII codes that represent the first two characters of the product technology flavor." line.long 0x8 "CMN_PID_LANES__CMN_PID_IOV,Product I/O voltage ID register" hexmask.long.byte 0x8 24.--31. 1. "CMN_PID_LANES_15_8,Product SerDes lanes left of common : This field contains the binary coded decimal numbers that represent the number of lanes implemented in this SerDes product on the left side of the common module." newline hexmask.long.byte 0x8 16.--23. 1. "CMN_PID_LANES_7_0,Product SerDes lanes right of common : This field contains the binary coded decimal numbers that represent the number of lanes implemented in this SerDes product on the right side of the common module." newline hexmask.long.word 0x8 0.--15. 1. "CMN_PID_IOV_15_0,Product I/O voltage : This field contains the binary coded decimal numbers that represent the product I/O voltage." rgroup.long 0x20++0xB line.long 0x0 "CMN_PID_METAL1__CMN_PID_METAL0,Product metal layers ID register 0" hexmask.long.byte 0x0 28.--31. 1. "CMN_PID_METAL1_15_12,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "CMN_PID_METAL1_11_8,Reserved" newline hexmask.long.byte 0x0 20.--23. 1. "CMN_PID_METAL1_7_4,Product xy metal layers : This field contains the binary coded decimal number that represent the number of xy metal layers used for this product." newline hexmask.long.byte 0x0 16.--19. 1. "CMN_PID_METAL1_3_0,Product xe metal layers : This field contains the binary coded decimal number that represent the number of xe metal layers used for this product." newline hexmask.long.byte 0x0 12.--15. 1. "CMN_PID_METAL0_15_12,Product xd metal layers : This field contains the binary coded decimal number that represent the number of xd metal layers used for this product." newline hexmask.long.byte 0x0 8.--11. 1. "CMN_PID_METAL0_11_8,Product xc metal layers : This field contains the binary coded decimal number that represent the number of xc metal layers used for this product." newline hexmask.long.byte 0x0 4.--7. 1. "CMN_PID_METAL0_7_4,Product xa metal layers : This field contains the binary coded decimal number that represent the number of xa metal layers used for this product." newline hexmask.long.byte 0x0 0.--3. 1. "CMN_PID_METAL0_3_0,Product x metal layers : This field contains the binary coded decimal number that represent the number of x metal layers used for this product." line.long 0x4 "CMN_PID_METAL3__CMN_PID_METAL2,Product metal layers ID register 2" hexmask.long.byte 0x4 28.--31. 1. "CMN_PID_METAL3_15_12,Product yz metal layers : This field contains the binary coded decimal number that represent the number of yz metal layers used for this product." newline hexmask.long.byte 0x4 24.--27. 1. "CMN_PID_METAL3_11_8,Product u metal layers : This field contains the binary coded decimal number that represent the number of u metal layers used for this product." newline hexmask.long.byte 0x4 20.--23. 1. "CMN_PID_METAL3_7_4,Product r metal layers : This field contains the binary coded decimal number that represent the number of r metal layers used for this product." newline hexmask.long.byte 0x4 16.--19. 1. "CMN_PID_METAL3_3_0,Product z metal layers : This field contains the binary coded decimal number that represent the number of z metal layers used for this product." newline hexmask.long.byte 0x4 12.--15. 1. "CMN_PID_METAL2_15_12,Product yz metal layers : This field contains the binary coded decimal number that represent the number of yz metal layers used for this product." newline hexmask.long.byte 0x4 8.--11. 1. "CMN_PID_METAL2_11_8,Product yy metal layers : This field contains the binary coded decimal number that represent the number of yy metal layers used for this product." newline hexmask.long.byte 0x4 4.--7. 1. "CMN_PID_METAL2_7_4,Product ya metal layers : This field contains the binary coded decimal number that represent the number of ya metal layers used for this product." newline hexmask.long.byte 0x4 0.--3. 1. "CMN_PID_METAL2_3_0,Product y metal layers : This field contains the binary coded decimal number that represent the number of y metal layers used for this product." line.long 0x8 "CMN_PID_METALD,Product metal layer direction ID register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" newline bitfld.long 0x8 15. "CMN_PID_METALD_15,Reserved" "0,1" newline bitfld.long 0x8 14. "CMN_PID_METALD_14,Reserved" "0,1" newline bitfld.long 0x8 13. "CMN_PID_METALD_13,Reserved" "0,1" newline bitfld.long 0x8 12. "CMN_PID_METALD_12,Reserved" "0,1" newline bitfld.long 0x8 11. "CMN_PID_METALD_11,Metal 11 direction (when used) :" "0,1" newline bitfld.long 0x8 10. "CMN_PID_METALD_10,Metal 10 direction (when used) :" "0,1" newline bitfld.long 0x8 9. "CMN_PID_METALD_9,Metal 9 direction (when used) :" "0,1" newline bitfld.long 0x8 8. "CMN_PID_METALD_8,Metal 8 direction :" "0,1" newline bitfld.long 0x8 7. "CMN_PID_METALD_7,Metal 7 direction :" "0,1" newline bitfld.long 0x8 6. "CMN_PID_METALD_6,Metal 6 direction :" "0,1" newline bitfld.long 0x8 5. "CMN_PID_METALD_5,Metal 5 direction :" "0,1" newline bitfld.long 0x8 4. "CMN_PID_METALD_4,Metal 4 direction :" "0,1" newline bitfld.long 0x8 3. "CMN_PID_METALD_3,Metal 3 direction :" "0,1" newline bitfld.long 0x8 2. "CMN_PID_METALD_2,Metal 2 direction :" "0,1" newline bitfld.long 0x8 1. "CMN_PID_METALD_1,Metal 1 direction :" "0,1" newline bitfld.long 0x8 0. "CMN_PID_METALD_0,Metal 0 direction : This layer does not have a direction associated with it." "0,1" group.long 0x40++0x7 line.long 0x0 "CMN_SSM_BANDGAP_TMR__CMN_SSM_SM_CTRL,Startup state machine control register" hexmask.long.word 0x0 21.--31. 1. "CMN_SSM_BANDGAP_TMR_15_5,Reserved" newline hexmask.long.byte 0x0 16.--20. 1. "CMN_SSM_BANDGAP_TMR_4_0,Bandgap enable state timer value : Value used for the timer when the startup state machine is in the bandgap enable state." newline hexmask.long.byte 0x0 8.--15. 1. "CMN_SSM_SM_CTRL_15_8,Reserved" newline bitfld.long 0x0 7. "CMN_SSM_SM_CTRL_7,Bandgap enable override enable : When active (1'b1) the bandgap enable override bit in this register will drive the ssmda_bandgap_en pin from the SSM directly." "0,1" newline bitfld.long 0x0 6. "CMN_SSM_SM_CTRL_6,Bandgap enable override : When enabled by the bandgap enable override enable bit in this register this bit will drive the ssmda_bandgap_en pin from the SSM directly." "0,1" newline bitfld.long 0x0 5. "CMN_SSM_SM_CTRL_5,Bias enable override enable : When active (1'b1) the bias enable override bit in this register will drive the ssmda_bias_en pin from the SSM directly." "0,1" newline bitfld.long 0x0 4. "CMN_SSM_SM_CTRL_4,Bias enable override : When enabled by the bias enable override enable bit in this register this bit will drive the ssmda_bias_en pin from the SSM directly." "0,1" newline rbitfld.long 0x0 2.--3. "CMN_SSM_SM_CTRL_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "CMN_SSM_SM_CTRL_1,Skip post bandgap enable re-calibration : When this bit is active (1'b1) the post bandgap enable calibration state will be skipped if it was previously run unless the macro is disabled or reset." "0,1" newline bitfld.long 0x0 0. "CMN_SSM_SM_CTRL_0,Skip auto re-calibration : When this bit is active (1'b1) the auto calibration state will be skipped if it was previously run unless the macro is disabled or reset." "0,1" line.long 0x4 "CMN_SSM_BIAS_TMR,Bias enable timer register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.word 0x4 7.--15. 1. "CMN_SSM_BIAS_TMR_15_7,Reserved" newline hexmask.long.byte 0x4 0.--6. 1. "CMN_SSM_BIAS_TMR_6_0,Bias enable state timer value : Value used for the timer when the startup state machine is in the bias enable state." group.long 0x4C++0x23 line.long 0x0 "CMN_SSM_USER_DEF_CTRL,Startup state machine user defined control register" hexmask.long.byte 0x0 24.--31. 1. "CMN_SSM_USER_DEF_CTRL_15_8,Reserved" newline hexmask.long.byte 0x0 18.--23. 1. "CMN_SSM_USER_DEF_CTRL_7_2,Reserved - spare" newline bitfld.long 0x0 17. "CMN_SSM_USER_DEF_CTRL_1,Force SSM gated clock on: Setting this bit to 1'b1 will force the SSM gated clock on independent of the internal SSM state machine clock gate controls." "0,1" newline bitfld.long 0x0 16. "CMN_SSM_USER_DEF_CTRL_0,Bandgap enable hold enable: This bit enables the bandgap enable hold function which holds the bandgap enable active in the common suspend state until the signal detect function is switched off." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED" line.long 0x4 "CMN_PLLSM0_PLLEN_TMR__CMN_PLLSM0_SM_CTRL,PLL 0 control state machine control register" hexmask.long.word 0x4 20.--31. 1. "CMN_PLLSM0_PLLEN_TMR_15_4,Reserved" newline hexmask.long.byte 0x4 16.--19. 1. "CMN_PLLSM0_PLLEN_TMR_3_0,PLL enable state timer value : Value used for the timer when the startup state machine is in the PLL enable state." newline hexmask.long.byte 0x4 10.--15. 1. "CMN_PLLSM0_SM_CTRL_15_10,Reserved" newline bitfld.long 0x4 9. "CMN_PLLSM0_SM_CTRL_9,PLL enable override enable : When active (1'b1) the PLL enable override bit in this register will drive the pllsmda_pll_en pin from the PLLSM directly." "0,1" newline bitfld.long 0x4 8. "CMN_PLLSM0_SM_CTRL_8,PLL enable override : When enabled by the PLL enable override enable bit in this register this bit will drive the pllsmda_pll_en pin from the PLLSM directly." "0,1" newline bitfld.long 0x4 7. "CMN_PLLSM0_SM_CTRL_7,PLL reset override enable : When active (1'b1) the PLL reset override bit in this register will drive the" "0,1" newline bitfld.long 0x4 6. "CMN_PLLSM0_SM_CTRL_6,PLL reset override : When enabled by the PLL reset override enable bit in this register this bit will drive the pllsmda_pll_rst_n pin from the PLLSM directly." "0,1" newline bitfld.long 0x4 5. "CMN_PLLSM0_SM_CTRL_5,PLL pre charge override enable : When active (1'b1) the PLL pre charge override bit in this register will drive the pllsmda_pll_pre_charge pin from the PLLSM directly." "0,1" newline bitfld.long 0x4 4. "CMN_PLLSM0_SM_CTRL_4,PLL pre charge override : When enabled by the PLL pre charge override enable bit in this register this bit will drive the pllsmda_pll_pre_charge pin from the PLLSM directly." "0,1" newline rbitfld.long 0x4 1.--3. "CMN_PLLSM0_SM_CTRL_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CMN_PLLSM0_SM_CTRL_0,Skip PLL re-calibration : When this bit is active (1'b1) the PLL calibration state will be skipped if it was previously run unless the PLL is disabled or resetting the state machine." "0,1" line.long 0x8 "CMN_PLLSM0_PLLVREF_TMR__CMN_PLLSM0_PLLPRE_TMR,PLL 0 pre-charge timer register" hexmask.long.word 0x8 20.--31. 1. "CMN_PLLSM0_PLLVREF_TMR_15_4,Reserved" newline hexmask.long.byte 0x8 16.--19. 1. "CMN_PLLSM0_PLLVREF_TMR_3_0,PLL VREF delay state timer value : Value used for the timer when the startup state machine is in the PLL VREF delay state." newline hexmask.long.byte 0x8 8.--15. 1. "CMN_PLLSM0_PLLPRE_TMR_15_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "CMN_PLLSM0_PLLPRE_TMR_7_0,PLL pre-charge state timer value : Value used for the timer when the startup state machine is in the PLL pre-charge state." line.long 0xC "CMN_PLLSM0_PLLCLKDIS_TMR__CMN_PLLSM0_PLLLOCK_TMR,PLL 0 lock delay timer register" hexmask.long.word 0xC 18.--31. 1. "CMN_PLLSM0_PLLCLKDIS_TMR_15_2,Reserved" newline bitfld.long 0xC 16.--17. "CMN_PLLSM0_PLLCLKDIS_TMR_1_0,PLL clock disable delay state timer value : Value used for the timer when the startup state machine is in the PLL clock disable delay state." "0,1,2,3" newline hexmask.long.byte 0xC 10.--15. 1. "CMN_PLLSM0_PLLLOCK_TMR_15_10,Reserved" newline hexmask.long.word 0xC 0.--9. 1. "CMN_PLLSM0_PLLLOCK_TMR_9_0,PLL lock delay state timer value : Value used for the timer when the startup state machine is in the PLL lock delay state." line.long 0x10 "CMN_PLLSM0_USER_DEF_CTRL,PLL 0 control state machine user defined control register" hexmask.long.byte 0x10 24.--31. 1. "CMN_PLLSM0_USER_DEF_CTRL_15_8,Reserved" newline hexmask.long.byte 0x10 17.--23. 1. "CMN_PLLSM0_USER_DEF_CTRL_7_1,Reserved - spare" newline bitfld.long 0x10 16. "CMN_PLLSM0_USER_DEF_CTRL_0,PLL lock override: When active (1'b1) this bit will force the PLL lock indication active." "0,1" newline hexmask.long.word 0x10 0.--15. 1. "RESERVED" line.long 0x14 "CMN_PLLSM1_PLLEN_TMR__CMN_PLLSM1_SM_CTRL,PLL 1 control state machine control register" hexmask.long.word 0x14 20.--31. 1. "CMN_PLLSM1_PLLEN_TMR_15_4,Reserved" newline hexmask.long.byte 0x14 16.--19. 1. "CMN_PLLSM1_PLLEN_TMR_3_0,PLL enable state timer value : Value used for the timer when the startup state machine is in the PLL enable state." newline hexmask.long.byte 0x14 10.--15. 1. "CMN_PLLSM1_SM_CTRL_15_10,Reserved" newline bitfld.long 0x14 9. "CMN_PLLSM1_SM_CTRL_9,PLL enable override enable : When active (1'b1) the PLL enable override bit in this register will drive the pllsmda_pll_en pin from the PLLSM directly." "0,1" newline bitfld.long 0x14 8. "CMN_PLLSM1_SM_CTRL_8,PLL enable override : When enabled by the PLL enable override enable bit in this register this bit will drive the pllsmda_pll_en pin from the PLLSM directly." "0,1" newline bitfld.long 0x14 7. "CMN_PLLSM1_SM_CTRL_7,PLL reset override enable : When active (1'b1) the PLL reset override bit in this register will drive the" "0,1" newline bitfld.long 0x14 6. "CMN_PLLSM1_SM_CTRL_6,PLL reset override : When enabled by the PLL reset override enable bit in this register this bit will drive the pllsmda_pll_rst_n pin from the PLLSM directly." "0,1" newline bitfld.long 0x14 5. "CMN_PLLSM1_SM_CTRL_5,PLL pre charge override enable : When active (1'b1) the PLL pre charge override bit in this register will drive the pllsmda_pll_pre_charge pin from the PLLSM directly." "0,1" newline bitfld.long 0x14 4. "CMN_PLLSM1_SM_CTRL_4,PLL pre charge override : When enabled by the PLL pre charge override enable bit in this register this bit will drive the pllsmda_pll_pre_charge pin from the PLLSM directly." "0,1" newline rbitfld.long 0x14 1.--3. "CMN_PLLSM1_SM_CTRL_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0. "CMN_PLLSM1_SM_CTRL_0,Skip PLL re-calibration : When this bit is active (1'b1) the PLL calibration state will be skipped if it was previously run unless the PLL is disabled or resetting the state machine." "0,1" line.long 0x18 "CMN_PLLSM1_PLLVREF_TMR__CMN_PLLSM1_PLLPRE_TMR,PLL 1 pre-charge timer register" hexmask.long.word 0x18 20.--31. 1. "CMN_PLLSM1_PLLVREF_TMR_15_4,Reserved" newline hexmask.long.byte 0x18 16.--19. 1. "CMN_PLLSM1_PLLVREF_TMR_3_0,PLL VREF delay state timer value : Value used for the timer when the startup state machine is in the PLL VREF delay state." newline hexmask.long.byte 0x18 8.--15. 1. "CMN_PLLSM1_PLLPRE_TMR_15_8,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "CMN_PLLSM1_PLLPRE_TMR_7_0,PLL pre-charge state timer value : Value used for the timer when the startup state machine is in the PLL pre-charge state." line.long 0x1C "CMN_PLLSM1_PLLCLKDIS_TMR__CMN_PLLSM1_PLLLOCK_TMR,PLL 1 lock delay timer register" hexmask.long.word 0x1C 18.--31. 1. "CMN_PLLSM1_PLLCLKDIS_TMR_15_2,Reserved" newline bitfld.long 0x1C 16.--17. "CMN_PLLSM1_PLLCLKDIS_TMR_1_0,PLL clock disable delay state timer value : Value used for the timer when the startup state machine is in the PLL clock disable delay state." "0,1,2,3" newline hexmask.long.byte 0x1C 10.--15. 1. "CMN_PLLSM1_PLLLOCK_TMR_15_10,Reserved" newline hexmask.long.word 0x1C 0.--9. 1. "CMN_PLLSM1_PLLLOCK_TMR_9_0,PLL lock delay state timer value : Value used for the timer when the startup state machine is in the PLL lock delay state." line.long 0x20 "CMN_PLLSM1_USER_DEF_CTRL,PLL 1 control state machine user defined control register" hexmask.long.byte 0x20 24.--31. 1. "CMN_PLLSM1_USER_DEF_CTRL_15_8,Reserved" newline hexmask.long.byte 0x20 17.--23. 1. "CMN_PLLSM1_USER_DEF_CTRL_7_1,Reserved - spare" newline bitfld.long 0x20 16. "CMN_PLLSM1_USER_DEF_CTRL_0,PLL lock override: When active (1'b1) this bit will force the PLL lock indication active." "0,1" newline hexmask.long.word 0x20 0.--15. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "CMN_CDIAG_CDB_PWRI_OVRD__CMN_CDIAG_PWRI_TMR,Common power island control timer register" bitfld.long 0x0 31. "CMN_CDIAG_CDB_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1" newline bitfld.long 0x0 30. "CMN_CDIAG_CDB_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0,1" newline rbitfld.long 0x0 28.--29. "CMN_CDIAG_CDB_PWRI_OVRD_13_12,Reserved" "0,1,2,3" newline bitfld.long 0x0 27. "CMN_CDIAG_CDB_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine." "0,1" newline rbitfld.long 0x0 26. "CMN_CDIAG_CDB_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine." "0,1" newline bitfld.long 0x0 25. "CMN_CDIAG_CDB_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine." "0,1" newline rbitfld.long 0x0 24. "CMN_CDIAG_CDB_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "CMN_CDIAG_CDB_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine." newline hexmask.long.byte 0x0 11.--15. 1. "CMN_CDIAG_PWRI_TMR_15_11,Reserved" newline bitfld.long 0x0 8.--10. "CMN_CDIAG_PWRI_TMR_10_8,Power enable phase 2 timer value: This specifies the number of reference clock cycles the power island control state machines in common will wait in the power phase 2 enable states in order to allow enough time for the second.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "CMN_CDIAG_PWRI_TMR_7_3,Reserved" newline bitfld.long 0x0 0.--2. "CMN_CDIAG_PWRI_TMR_2_0,Power enable phase 1 timer value: This specifies the number of reference clock cycles the power island control state machines in common will wait in the power phase 1 enable states in order to allow enough time for the first phase.." "0,1,2,3,4,5,6,7" line.long 0x4 "CMN_CDIAG_PLLC_PWRI_OVRD__CMN_CDIAG_CDB_PWRI_STAT,Common CDB power island control status register" bitfld.long 0x4 31. "CMN_CDIAG_PLLC_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1" newline bitfld.long 0x4 30. "CMN_CDIAG_PLLC_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control.." "0,1" newline rbitfld.long 0x4 28.--29. "CMN_CDIAG_PLLC_PWRI_OVRD_13_12,Reserved" "0,1,2,3" newline bitfld.long 0x4 27. "CMN_CDIAG_PLLC_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine." "0,1" newline rbitfld.long 0x4 26. "CMN_CDIAG_PLLC_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine." "0,1" newline bitfld.long 0x4 25. "CMN_CDIAG_PLLC_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine." "0,1" newline rbitfld.long 0x4 24. "CMN_CDIAG_PLLC_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "CMN_CDIAG_PLLC_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine." newline hexmask.long.byte 0x4 8.--15. 1. "CMN_CDIAG_CDB_PWRI_STAT_15_8,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "CMN_CDIAG_CDB_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine." line.long 0x8 "CMN_CDIAG_CCAL_PWRI_OVRD__CMN_CDIAG_PLLC_PWRI_STAT,Common PLL controller power island control status register" bitfld.long 0x8 31. "CMN_CDIAG_CCAL_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1" newline bitfld.long 0x8 30. "CMN_CDIAG_CCAL_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control.." "0,1" newline rbitfld.long 0x8 28.--29. "CMN_CDIAG_CCAL_PWRI_OVRD_13_12,Reserved" "0,1,2,3" newline bitfld.long 0x8 27. "CMN_CDIAG_CCAL_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine." "0,1" newline rbitfld.long 0x8 26. "CMN_CDIAG_CCAL_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine." "0,1" newline bitfld.long 0x8 25. "CMN_CDIAG_CCAL_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine." "0,1" newline rbitfld.long 0x8 24. "CMN_CDIAG_CCAL_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "CMN_CDIAG_CCAL_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine." newline hexmask.long.byte 0x8 8.--15. 1. "CMN_CDIAG_PLLC_PWRI_STAT_15_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "CMN_CDIAG_PLLC_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine." line.long 0xC "CMN_CDIAG_XCVRC_PWRI_OVRD__CMN_CDIAG_CCAL_PWRI_STAT,Common common calibration power island control status register" bitfld.long 0xC 31. "CMN_CDIAG_XCVRC_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control.." "0,1" newline bitfld.long 0xC 30. "CMN_CDIAG_XCVRC_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control.." "0,1" newline rbitfld.long 0xC 28.--29. "CMN_CDIAG_XCVRC_PWRI_OVRD_13_12,Reserved" "0,1,2,3" newline bitfld.long 0xC 27. "CMN_CDIAG_XCVRC_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine." "0,1" newline rbitfld.long 0xC 26. "CMN_CDIAG_XCVRC_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine." "0,1" newline bitfld.long 0xC 25. "CMN_CDIAG_XCVRC_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine." "0,1" newline rbitfld.long 0xC 24. "CMN_CDIAG_XCVRC_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine." "0,1" newline hexmask.long.byte 0xC 16.--23. 1. "CMN_CDIAG_XCVRC_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine." newline hexmask.long.byte 0xC 8.--15. 1. "CMN_CDIAG_CCAL_PWRI_STAT_15_8,Reserved" newline hexmask.long.byte 0xC 0.--7. 1. "CMN_CDIAG_CCAL_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine." line.long 0x10 "CMN_CDIAG_DIAG_PWRI_OVRD__CMN_CDIAG_XCVRC_PWRI_STAT,Common transceiver controller power island control status register" bitfld.long 0x10 31. "CMN_CDIAG_DIAG_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1" newline bitfld.long 0x10 30. "CMN_CDIAG_DIAG_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control.." "0,1" newline rbitfld.long 0x10 28.--29. "CMN_CDIAG_DIAG_PWRI_OVRD_13_12,Reserved" "0,1,2,3" newline bitfld.long 0x10 27. "CMN_CDIAG_DIAG_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine." "0,1" newline rbitfld.long 0x10 26. "CMN_CDIAG_DIAG_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine." "0,1" newline bitfld.long 0x10 25. "CMN_CDIAG_DIAG_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine." "0,1" newline rbitfld.long 0x10 24. "CMN_CDIAG_DIAG_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine." "0,1" newline hexmask.long.byte 0x10 16.--23. 1. "CMN_CDIAG_DIAG_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine." newline hexmask.long.byte 0x10 8.--15. 1. "CMN_CDIAG_XCVRC_PWRI_STAT_15_8,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "CMN_CDIAG_XCVRC_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine." line.long 0x14 "CMN_CDIAG_PRATECLK_CTRL__CMN_CDIAG_DIAG_PWRI_STAT,Common diagnostic power island control status register" hexmask.long.word 0x14 18.--31. 1. "CMN_CDIAG_PRATECLK_CTRL_15_2,Reserved" newline bitfld.long 0x14 17. "CMN_CDIAG_PRATECLK_CTRL_1,Common PLL 1 full rate and data rate source clock select: Selects the PLL source clock to use when generating the cmn_pll1_clk_fullrt cmn_pll1_clk_datart0 and cmn_pll1_clk_datart1 clocks." "0,1" newline bitfld.long 0x14 16. "CMN_CDIAG_PRATECLK_CTRL_0,Common PLL 0 full rate and data rate source clock select: Selects the PLL source clock to use when generating the cmn_pll0_clk_fullrt cmn_pll0_clk_datart0 and cmn_pll0_clk_datart1 clocks." "0,1" newline hexmask.long.byte 0x14 8.--15. 1. "CMN_CDIAG_DIAG_PWRI_STAT_15_8,Reserved" newline hexmask.long.byte 0x14 0.--7. 1. "CMN_CDIAG_DIAG_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine." line.long 0x18 "CMN_CDIAG_REFCLK_TEST__CMN_CDIAG_REFCLK_OVRD,Reference clock receiver override register" hexmask.long.byte 0x18 26.--31. 1. "CMN_CDIAG_REFCLK_TEST_15_10,Reserved" newline bitfld.long 0x18 24.--25. "CMN_CDIAG_REFCLK_TEST_9_8,Reserved - spare" "0,1,2,3" newline rbitfld.long 0x18 22.--23. "CMN_CDIAG_REFCLK_TEST_7_6,Reserved" "0,1,2,3" newline bitfld.long 0x18 21. "CMN_CDIAG_REFCLK_TEST_5,Reference clock driver 0 test mode enable: Enables the reference clock driver DC test mode by controlling the cmnda_ref_clk0_drv_test_en signal going into the analog." "0,1" newline bitfld.long 0x18 20. "CMN_CDIAG_REFCLK_TEST_4,Reference clock driver 0 test mode value: When enabled by the reference clock driver 0 test mode enable bit in this register the value in this bit will be driven by the reference clock driver by controlling the.." "0,1" newline rbitfld.long 0x18 19. "CMN_CDIAG_REFCLK_TEST_3,Reserved" "0,1" newline bitfld.long 0x18 18. "CMN_CDIAG_REFCLK_TEST_2,Reference clock receiver test mode enable: Enables the reference clock receiver DC test mode by controlling the cmnda_ref_clk_rcv_test_en signal going into the analog." "0,1" newline rbitfld.long 0x18 17. "CMN_CDIAG_REFCLK_TEST_1,Reference clock receiver test mode PLL value: When enabled by the reference clock receiver test mode enable bit in this register the value in this bit will be the value present on the PLL reference clock receiver." "0,1" newline rbitfld.long 0x18 16. "CMN_CDIAG_REFCLK_TEST_0,Reference clock receiver test mode digital value: When enabled by the reference clock receiver test mode enable bit in this register the value in this bit will be the value present on the digital reference clock receiver." "0,1" newline rbitfld.long 0x18 13.--15. "CMN_CDIAG_REFCLK_OVRD_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12. "CMN_CDIAG_REFCLK_OVRD_12,Derived reference clock source select: Selects which PLL is the source for the derived reference clock by driving the cmnda_ref_clk_der_src_sel signal to the analog." "0,1" newline rbitfld.long 0x18 10.--11. "CMN_CDIAG_REFCLK_OVRD_11_10,Reserved" "0,1,2,3" newline bitfld.long 0x18 8.--9. "CMN_CDIAG_REFCLK_OVRD_9_8,Digital reference clock receiver hysteresis adjust: Control the amount of hysteresis used for the digital reference clock receiver by driving the cmnda_ref_clk_dig_hyst_adj signal to the analog." "0,1,2,3" newline rbitfld.long 0x18 7. "CMN_CDIAG_REFCLK_OVRD_7,Reserved" "0,1" newline bitfld.long 0x18 6. "CMN_CDIAG_REFCLK_OVRD_6,Analog reference clock enable override: This bit can be used to force the cmnda_ref_clk_en signal going to the analog to the active state." "0,1" newline bitfld.long 0x18 5. "CMN_CDIAG_REFCLK_OVRD_5,Reference clock AC coupling cap bypass: Controls the bypassing of the AC coupling caps in the differential receiver." "0,1" newline bitfld.long 0x18 4. "CMN_CDIAG_REFCLK_OVRD_4,Derived reference clock enable: Enables the derived reference clock function by driving the cmnda_ref_clk_der_en signal to the analog." "0,1" newline bitfld.long 0x18 2.--3. "CMN_CDIAG_REFCLK_OVRD_3_2,Reference clock high pass filter control: Controls the cutoff frequency of the high pass filter in the reference clock receiver input." "0,1,2,3" newline rbitfld.long 0x18 1. "CMN_CDIAG_REFCLK_OVRD_1,Reserved" "0,1" newline bitfld.long 0x18 0. "CMN_CDIAG_REFCLK_OVRD_0,Reference clock receiver circuit clock control:" "0,1" line.long 0x1C "CMN_CDIAG_SDOSC_CTRL__CMN_CDIAG_PSMCLK_CTRL,Power state machine clock receiver control register" hexmask.long.word 0x1C 18.--31. 1. "CMN_CDIAG_SDOSC_CTRL_15_2,Reserved" newline bitfld.long 0x1C 17. "CMN_CDIAG_SDOSC_CTRL_1,Oscillator Enable Override Enable: This bit enables the oscillator enable override bit in this register to directly control the signal detect oscillator." "0,1" newline bitfld.long 0x1C 16. "CMN_CDIAG_SDOSC_CTRL_0,Oscillator Enable Override: When enabled by the oscillator enable override enable bit in this register this bit can be used to directly control the enable of the signal detect oscillator." "0,1" newline hexmask.long.word 0x1C 4.--15. 1. "CMN_CDIAG_PSMCLK_CTRL_15_4,Reserved" newline hexmask.long.byte 0x1C 0.--3. 1. "CMN_CDIAG_PSMCLK_CTRL_3_0,PSM clock divider value: The value of this field is used to control the divider setting of the PSM clock divider." line.long 0x20 "CMN_CDIAG_REFCLK_DRV0_CTRL,Reference clock bump driver 0 control register" hexmask.long.word 0x20 16.--31. 1. "RESERVED" newline hexmask.long.byte 0x20 10.--15. 1. "CMN_CDIAG_REFCLK_DRV0_CTRL_15_10,Reserved" newline bitfld.long 0x20 8.--9. "CMN_CDIAG_REFCLK_DRV0_CTRL_9_8,Clock driver drive current tune: Controls the amplitude of the reference clock driver by controlling the cmnda_ref_clk0_itune signal going to the analog." "0,1,2,3" newline rbitfld.long 0x20 7. "CMN_CDIAG_REFCLK_DRV0_CTRL_7,Reserved" "0,1" newline bitfld.long 0x20 6. "CMN_CDIAG_REFCLK_DRV0_CTRL_6,Reference clock driver high Z: When the reference clock driver is disabled this controls if the driver outputs are high Z or pulled low by controlling the cmnda_ref_clk0_drv_highz signal going to the analog." "0,1" newline bitfld.long 0x20 5. "CMN_CDIAG_REFCLK_DRV0_CTRL_5,Clock driver termination: Enables the termination in the reference clock driver by controlling the cmnda_ref_clk0_termination signal going to the analog." "0,1" newline bitfld.long 0x20 4. "CMN_CDIAG_REFCLK_DRV0_CTRL_4,Clock select: Selects which reference clock that will be driven by the reference clock driver by controlling the cmnda_ref_clk0_clk_select signal going to the analog." "0,1" newline bitfld.long 0x20 3. "CMN_CDIAG_REFCLK_DRV0_CTRL_3,Clock gate enable override enable: This bit enables the clock gate enable override bit in this register to override the clock gate of the reference clock driver." "0,1" newline bitfld.long 0x20 2. "CMN_CDIAG_REFCLK_DRV0_CTRL_2,Clock gate enable override: When enabled by the clock gate enable override enable bit in this register this bit can be used to directly control the clock gate enable of the reference clock driver by controlling the.." "0,1" newline bitfld.long 0x20 1. "CMN_CDIAG_REFCLK_DRV0_CTRL_1,Driver enable override enable: This bit enables the driver enable override bit in this register to override the enable of the reference clock driver." "0,1" newline bitfld.long 0x20 0. "CMN_CDIAG_REFCLK_DRV0_CTRL_0,Driver enable override: When enabled by the driver enable override enable bit in this register this bit can be used to directly control the enable of the reference clock driver by controlling the cmnda_ref_clk0_drv_en signal.." "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "CMN_CDIAG_RST_DIAG__CMN_CDIAG_CDB_DIAG,Common control CDB diagnostic register" hexmask.long.word 0x0 18.--31. 1. "CMN_CDIAG_RST_DIAG_15_2,Reserved" newline bitfld.long 0x0 17. "CMN_CDIAG_RST_DIAG_1,Current state of the cdb_isl_ctrl_sm_reset_n reset." "0,1" newline bitfld.long 0x0 16. "CMN_CDIAG_RST_DIAG_0,Current state of the cmn_reset_sync_n reset." "0,1" newline hexmask.long.word 0x0 1.--15. 1. "CMN_CDIAG_CDB_DIAG_15_1,Reserved" newline bitfld.long 0x0 0. "CMN_CDIAG_CDB_DIAG_0,CDB bus error: This bit will be set when the internal CDB watchdog timer expires." "0,1" group.long 0xBC++0xF line.long 0x0 "CMN_CDIAG_DCYA,Common control cover your alternatives register" hexmask.long.byte 0x0 24.--31. 1. "CMN_CDIAG_DCYA_15_8,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "CMN_CDIAG_DCYA_7_0,Reserved - spare" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED" line.long 0x4 "CMN_BGCAL_OVRD__CMN_BGCAL_CTRL,Bandgap calibration control register" bitfld.long 0x4 31. "CMN_BGCAL_OVRD_15,Bandgap code override enable: Activation (1'b1) of this register bit allows the bandgap codes determined during the automatic calibration process to be overridden." "0,1" newline bitfld.long 0x4 30. "CMN_BGCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_bias_bgcal_en enable." "0,1" newline hexmask.long.byte 0x4 22.--29. 1. "CMN_BGCAL_OVRD_13_6,Reserved" newline hexmask.long.byte 0x4 16.--21. 1. "CMN_BGCAL_OVRD_5_0,Bandgap code override value: These bits are used to override the bandgap code determined during the automatic calibration process." newline bitfld.long 0x4 15. "CMN_BGCAL_CTRL_15,Start bandgap calibration: Activating (1'b1) this bit will start the bandgap calibration process." "0,1" newline rbitfld.long 0x4 14. "CMN_BGCAL_CTRL_14,Bandgap calibration process done: This bit will be set to 1'b1 when the bandgap calibration process is complete." "0,1" newline rbitfld.long 0x4 13. "CMN_BGCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1" newline rbitfld.long 0x4 12. "CMN_BGCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_bias_bgcal_comp)." "0,1" newline hexmask.long.byte 0x4 6.--11. 1. "CMN_BGCAL_CTRL_11_6,Reserved" newline hexmask.long.byte 0x4 0.--5. 1. "CMN_BGCAL_CTRL_5_0,Bandgap calibration code: This is the calibration code that was determined by the bandgap calibration process." line.long 0x8 "CMN_BGCAL_TUNE__CMN_BGCAL_START,Bandgap calibration start register" hexmask.long.word 0x8 22.--31. 1. "CMN_BGCAL_TUNE_15_6,Reserved" newline hexmask.long.byte 0x8 16.--21. 1. "CMN_BGCAL_TUNE_5_0,Bandgap calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled." newline bitfld.long 0x8 15. "CMN_BGCAL_START_15,Bandgap calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in." "0,1" newline hexmask.long.word 0x8 6.--14. 1. "CMN_BGCAL_START_14_6,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "CMN_BGCAL_START_5_0,Start bandgap calibration code: This is the calibration code that the calibration process starts with when automatic calibration is run." line.long 0xC "CMN_BGCAL_ITER_TMR__CMN_BGCAL_INIT_TMR,Bandgap calibration initialization timer register" hexmask.long.byte 0xC 25.--31. 1. "CMN_BGCAL_ITER_TMR_15_9,Reserved" newline hexmask.long.word 0xC 16.--24. 1. "CMN_BGCAL_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the bandgap calibration signals going to the analog and when the comparator value coming from the analog circuits can.." newline hexmask.long.byte 0xC 9.--15. 1. "CMN_BGCAL_INIT_TMR_15_9,Reserved" newline hexmask.long.word 0xC 0.--8. 1. "CMN_BGCAL_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog bandgap calibration circuits are enabled and when the first values are placed on the bandgap calibration signals going to.." group.long 0xE0++0xB line.long 0x0 "CMN_IBCAL_OVRD__CMN_IBCAL_CTRL,External bias current calibration control register" bitfld.long 0x0 31. "CMN_IBCAL_OVRD_15,Calibration code override enable: Activation (1'b1) of this register bit allows the calibration code determined during the automatic resistor calibration process to be overridden." "0,1" newline bitfld.long 0x0 30. "CMN_IBCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_ibiascal_en enable and the cmnda_ibiascal_clk clock." "0,1" newline hexmask.long.byte 0x0 23.--29. 1. "CMN_IBCAL_OVRD_13_7,Reserved" newline hexmask.long.byte 0x0 16.--22. 1. "CMN_IBCAL_OVRD_6_0,Calibration code override value: These bits are used to override the calibration code determined during the automatic resistor calibration process." newline bitfld.long 0x0 15. "CMN_IBCAL_CTRL_15,Start calibration: Activating (1'b1) this bit will start the calibration process." "0,1" newline rbitfld.long 0x0 14. "CMN_IBCAL_CTRL_14,Calibration process done: This bit will be set to 1'b1 when the calibration process is complete." "0,1" newline rbitfld.long 0x0 13. "CMN_IBCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1" newline rbitfld.long 0x0 12. "CMN_IBCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_ibiascal_comp)." "0,1" newline hexmask.long.byte 0x0 7.--11. 1. "CMN_IBCAL_CTRL_11_7,Reserved" newline hexmask.long.byte 0x0 0.--6. 1. "CMN_IBCAL_CTRL_6_0,Calibration code: This is the calibration code that was determined by the calibration process." line.long 0x4 "CMN_IBCAL_TUNE__CMN_IBCAL_START,External bias current calibration start register" hexmask.long.word 0x4 23.--31. 1. "CMN_IBCAL_TUNE_15_7,Reserved" newline hexmask.long.byte 0x4 16.--22. 1. "CMN_IBCAL_TUNE_6_0,Calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled." newline bitfld.long 0x4 15. "CMN_IBCAL_START_15,Calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in." "0,1" newline hexmask.long.byte 0x4 7.--14. 1. "CMN_IBCAL_START_14_7,Reserved" newline hexmask.long.byte 0x4 0.--6. 1. "CMN_IBCAL_START_6_0,Start resistor calibration code: This is the calibration code that the resistor calibration process starts with when automatic calibration is run." line.long 0x8 "CMN_IBCAL_ITER_TMR__CMN_IBCAL_INIT_TMR,External bias current calibration initialization timer register" hexmask.long.word 0x8 23.--31. 1. "CMN_IBCAL_ITER_TMR_15_7,Reserved" newline hexmask.long.byte 0x8 16.--22. 1. "CMN_IBCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration selection bus going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.word 0x8 7.--15. 1. "CMN_IBCAL_INIT_TMR_15_7,Reserved" newline hexmask.long.byte 0x8 0.--6. 1. "CMN_IBCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first calibration selection value is placed on the calibration code bus going.." group.long 0x100++0x13 line.long 0x0 "CMN_PLL0_VCOCAL_START__CMN_PLL0_VCOCAL_CTRL,PLL 0 VCO calibration control register" rbitfld.long 0x0 31. "CMN_PLL0_VCOCAL_START_15,Reserved" "0,1" newline bitfld.long 0x0 28.--30. "CMN_PLL0_VCOCAL_START_14_12,VCO calibration initial step size control: This field specifies the initial step size for the VCO calibration state machine." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "CMN_PLL0_VCOCAL_START_11_8,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "CMN_PLL0_VCOCAL_START_7_0,VCO calibration code starting point value: This field specifies the starting VCO code that is used by the VCO calibration state machine." newline bitfld.long 0x0 15. "CMN_PLL0_VCOCAL_CTRL_15,Start VCO calibration: Activating (1'b1) this bit will start a VCO calibration process." "0,1" newline rbitfld.long 0x0 14. "CMN_PLL0_VCOCAL_CTRL_14,VCO calibration process done: This bit will be set to 1'b1 when the VCO calibration process is complete." "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "CMN_PLL0_VCOCAL_CTRL_13_8,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "CMN_PLL0_VCOCAL_CTRL_7_0,VCO calibration code: This is the calibration code that was determined by the VCO calibration process." line.long 0x4 "CMN_PLL0_VCOCAL_OVRD__CMN_PLL0_VCOCAL_TCTRL,PLL 0 VCO calibration timer control register" bitfld.long 0x4 31. "CMN_PLL0_VCOCAL_OVRD_15,VCO calibration code override enable: Activating (1'b1) this bit allows the VCO code determined during the automatic VCO calibration process to be overridden by the value driven by the VCO calibration code override value field in.." "0,1" newline hexmask.long.byte 0x4 24.--30. 1. "CMN_PLL0_VCOCAL_OVRD_14_8,Reserved" newline hexmask.long.byte 0x4 16.--23. 1. "CMN_PLL0_VCOCAL_OVRD_7_0,VCO calibration code override value: This field is used to override the VCO code determined during the automatic VCO calibration process." newline hexmask.long.word 0x4 3.--15. 1. "CMN_PLL0_VCOCAL_TCTRL_15_3,Reserved" newline bitfld.long 0x4 0.--2. "CMN_PLL0_VCOCAL_TCTRL_2_0,VCO calibration initial time scale control: This field specifies the calibration start time scaling factor applied to the VCO calibration when running the initial step size for the calibration code if not set to 1." "0,1,2,3,4,5,6,7" line.long 0x8 "CMN_PLL0_VCOCAL_ITER_TMR__CMN_PLL0_VCOCAL_INIT_TMR,PLL 0 VCO calibration initialization timer register" rbitfld.long 0x8 30.--31. "CMN_PLL0_VCOCAL_ITER_TMR_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x8 16.--29. 1. "CMN_PLL0_VCOCAL_ITER_TMR_13_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured." newline rbitfld.long 0x8 14.--15. "CMN_PLL0_VCOCAL_INIT_TMR_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x8 0.--13. 1. "CMN_PLL0_VCOCAL_INIT_TMR_13_0,Initialization wait timer value: This is the number of clocks to wait between when the analog VCO calibration circuits are enabled and when the first calibration code is driven to the analog." line.long 0xC "CMN_PLL0_VCOCAL_REFTIM_START,PLL 0 VCO calibration reference clock timer start value register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline rbitfld.long 0xC 14.--15. "CMN_PLL0_VCOCAL_REFTIM_START_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "CMN_PLL0_VCOCAL_REFTIM_START_13_0,PLL VCO calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running VCO calibration." line.long 0x10 "CMN_PLL0_VCOCAL_PLLCNT_START,PLL 0 VCO calibration PLL clock counter start value register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" newline rbitfld.long 0x10 14.--15. "CMN_PLL0_VCOCAL_PLLCNT_START_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x10 0.--13. 1. "CMN_PLL0_VCOCAL_PLLCNT_START_13_0,PLL VCO calibration PLL clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running VCO calibration." group.long 0x120++0x37 line.long 0x0 "CMN_PLL0_FRACDIVL_M0__CMN_PLL0_INTDIV_M0,PLL 0 feedback divider integer register mode 0" hexmask.long.word 0x0 16.--31. 1. "CMN_PLL0_FRACDIVL_M0_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal." newline hexmask.long.byte 0x0 9.--15. 1. "CMN_PLL0_INTDIV_M0_15_9,Reserved" newline hexmask.long.word 0x0 0.--8. 1. "CMN_PLL0_INTDIV_M0_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal." line.long 0x4 "CMN_PLL0_HIGH_THR_M0__CMN_PLL0_FRACDIVH_M0,PLL 0 feedback divider fractional high register mode 0" hexmask.long.byte 0x4 25.--31. 1. "CMN_PLL0_HIGH_THR_M0_15_9,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "CMN_PLL0_HIGH_THR_M0_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal." newline hexmask.long.word 0x4 3.--15. 1. "CMN_PLL0_FRACDIVH_M0_15_3,Reserved" newline bitfld.long 0x4 0.--2. "CMN_PLL0_FRACDIVH_M0_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal." "0,1,2,3,4,5,6,7" line.long 0x8 "CMN_PLL0_DSM_FBH_OVRD_M0__CMN_PLL0_DSM_DIAG_M0,PLL 0 delta sigma modulator diagnostics register mode 0" hexmask.long.byte 0x8 25.--31. 1. "CMN_PLL0_DSM_FBH_OVRD_M0_15_9,Reserved" newline hexmask.long.word 0x8 16.--24. 1. "CMN_PLL0_DSM_FBH_OVRD_M0_8_0,PLL feedback divider high override value : When enabled by the PLL feedback divider override enable bit in the PLL 0 delta sigma modulator diagnostics register mode 0 on page 102 the value in this field will be used to.." newline bitfld.long 0x8 15. "CMN_PLL0_DSM_DIAG_M0_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal." "0,1" newline bitfld.long 0x8 14. "CMN_PLL0_DSM_DIAG_M0_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 0 delta sigma modulator feedback divider value high override register mode 0 on page 102 and PLL 0 delta sigma.." "0,1" newline hexmask.long.word 0x8 4.--13. 1. "CMN_PLL0_DSM_DIAG_M0_13_4,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "CMN_PLL0_DSM_DIAG_M0_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll0_fb_div_high and cmnda_pll0_fb_div_low signals." line.long 0xC "CMN_PLL0_DSM_FBL_OVRD_M0,PLL 0 delta sigma modulator feedback divider value low override register mode 0" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 9.--15. 1. "CMN_PLL0_DSM_FBL_OVRD_M0_15_9,Reserved" newline hexmask.long.word 0xC 0.--8. 1. "CMN_PLL0_DSM_FBL_OVRD_M0_8_0,PLL feedback divider low override value : When enabled by the PLL feedback divider override enable bit in the PLL 0 delta sigma modulator diagnostics register mode 0 on page 102 the value in this field will be used to.." line.long 0x10 "CMN_PLL0_SS_CTRL2_M0__CMN_PLL0_SS_CTRL1_M0,PLL 0 spread spectrum control register 1 mode 0" rbitfld.long 0x10 31. "CMN_PLL0_SS_CTRL2_M0_15,Reserved" "0,1" newline hexmask.long.word 0x10 16.--30. 1. "CMN_PLL0_SS_CTRL2_M0_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator." newline hexmask.long.word 0x10 2.--15. 1. "CMN_PLL0_SS_CTRL1_M0_15_2,Reserved" newline bitfld.long 0x10 1. "CMN_PLL0_SS_CTRL1_M0_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator." "0,1" newline bitfld.long 0x10 0. "CMN_PLL0_SS_CTRL1_M0_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place." "0,1" line.long 0x14 "CMN_PLL0_SS_CTRL4_M0__CMN_PLL0_SS_CTRL3_M0,PLL 0 spread spectrum control register 3 mode 0" hexmask.long.word 0x14 23.--31. 1. "CMN_PLL0_SS_CTRL4_M0_15_7,Reserved" newline hexmask.long.byte 0x14 16.--22. 1. "CMN_PLL0_SS_CTRL4_M0_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator." newline hexmask.long.word 0x14 7.--15. 1. "CMN_PLL0_SS_CTRL3_M0_15_7,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "CMN_PLL0_SS_CTRL3_M0_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator." line.long 0x18 "CMN_PLL0_LOCK_REFCNT_IDLE__CMN_PLL0_LOCK_REFCNT_START,PLL 0 lock reference counter start value register" hexmask.long.byte 0x18 28.--31. 1. "CMN_PLL0_LOCK_REFCNT_IDLE_15_12,Reserved" newline hexmask.long.word 0x18 16.--27. 1. "CMN_PLL0_LOCK_REFCNT_IDLE_11_0,PLL lock reference counter idle value : This is the value used by the PLL lock detection logic to specify the number of reference clocks between each phase of counting PLL clocks." newline hexmask.long.byte 0x18 12.--15. 1. "CMN_PLL0_LOCK_REFCNT_START_15_12,Reserved" newline hexmask.long.word 0x18 0.--11. 1. "CMN_PLL0_LOCK_REFCNT_START_11_0,PLL lock reference counter start value : This is the value that is loaded into the PLL lock detect reference counter as the starting point for that counter when checking for PLL lock." line.long 0x1C "CMN_PLL0_LOCK_PLLCNT_THR__CMN_PLL0_LOCK_PLLCNT_START,PLL 0 lock PLL counter start value register" hexmask.long.byte 0x1C 28.--31. 1. "CMN_PLL0_LOCK_PLLCNT_THR_15_12,Reserved" newline hexmask.long.word 0x1C 16.--27. 1. "CMN_PLL0_LOCK_PLLCNT_THR_11_0,PLL lock counter threshold value : This is the value used by the PLL lock detection logic to determine if the PLL has locked." newline hexmask.long.byte 0x1C 12.--15. 1. "CMN_PLL0_LOCK_PLLCNT_START_15_12,Reserved" newline hexmask.long.word 0x1C 0.--11. 1. "CMN_PLL0_LOCK_PLLCNT_START_11_0,PLL lock PLL counter start value : This is the value that is loaded into the PLL lock detect PLL counter as the starting point for that counter when checking for PLL lock." line.long 0x20 "CMN_PLL0_FRACDIVL_M1__CMN_PLL0_INTDIV_M1,PLL 0 feedback divider integer register mode 1" hexmask.long.word 0x20 16.--31. 1. "CMN_PLL0_FRACDIVL_M1_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal." newline hexmask.long.byte 0x20 9.--15. 1. "CMN_PLL0_INTDIV_M1_15_9,Reserved" newline hexmask.long.word 0x20 0.--8. 1. "CMN_PLL0_INTDIV_M1_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal." line.long 0x24 "CMN_PLL0_HIGH_THR_M1__CMN_PLL0_FRACDIVH_M1,PLL 0 feedback divider fractional high register mode 1" hexmask.long.byte 0x24 25.--31. 1. "CMN_PLL0_HIGH_THR_M1_15_9,Reserved" newline hexmask.long.word 0x24 16.--24. 1. "CMN_PLL0_HIGH_THR_M1_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal." newline hexmask.long.word 0x24 3.--15. 1. "CMN_PLL0_FRACDIVH_M1_15_3,Reserved" newline bitfld.long 0x24 0.--2. "CMN_PLL0_FRACDIVH_M1_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal." "0,1,2,3,4,5,6,7" line.long 0x28 "CMN_PLL0_DSM_FBH_OVRD_M1__CMN_PLL0_DSM_DIAG_M1,PLL 0 delta sigma modulator diagnostics register mode 1" hexmask.long.byte 0x28 25.--31. 1. "CMN_PLL0_DSM_FBH_OVRD_M1_15_9,Reserved" newline hexmask.long.word 0x28 16.--24. 1. "CMN_PLL0_DSM_FBH_OVRD_M1_8_0,PLL feedback divider high override value : When enabled by the PLL feedback divider override enable bit in the PLL 0 delta sigma modulator diagnostics register mode 0 on page 102 the value in this field will be used to.." newline bitfld.long 0x28 15. "CMN_PLL0_DSM_DIAG_M1_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal." "0,1" newline bitfld.long 0x28 14. "CMN_PLL0_DSM_DIAG_M1_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 0 delta sigma modulator feedback divider value high override register mode 0 on page 102 and PLL 0 delta sigma.." "0,1" newline hexmask.long.word 0x28 4.--13. 1. "CMN_PLL0_DSM_DIAG_M1_13_4,Reserved" newline hexmask.long.byte 0x28 0.--3. 1. "CMN_PLL0_DSM_DIAG_M1_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll0_fb_div_high and cmnda_pll0_fb_div_low signals." line.long 0x2C "CMN_PLL0_DSM_FBL_OVRD_M1,PLL 0 delta sigma modulator feedback divider value low override register mode 1" hexmask.long.word 0x2C 16.--31. 1. "RESERVED" newline hexmask.long.byte 0x2C 9.--15. 1. "CMN_PLL0_DSM_FBL_OVRD_M1_15_9,Reserved" newline hexmask.long.word 0x2C 0.--8. 1. "CMN_PLL0_DSM_FBL_OVRD_M1_8_0,PLL feedback divider low override value : When enabled by the PLL feedback divider override enable bit in the PLL 0 delta sigma modulator diagnostics register mode 0 on page 102 the value in this field will be used to.." line.long 0x30 "CMN_PLL0_SS_CTRL2_M1__CMN_PLL0_SS_CTRL1_M1,PLL 0 spread spectrum control register 1 mode 1" rbitfld.long 0x30 31. "CMN_PLL0_SS_CTRL2_M1_15,Reserved" "0,1" newline hexmask.long.word 0x30 16.--30. 1. "CMN_PLL0_SS_CTRL2_M1_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator." newline hexmask.long.word 0x30 2.--15. 1. "CMN_PLL0_SS_CTRL1_M1_15_2,Reserved" newline bitfld.long 0x30 1. "CMN_PLL0_SS_CTRL1_M1_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator." "0,1" newline bitfld.long 0x30 0. "CMN_PLL0_SS_CTRL1_M1_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place." "0,1" line.long 0x34 "CMN_PLL0_SS_CTRL4_M1__CMN_PLL0_SS_CTRL3_M1,PLL 0 spread spectrum control register 3 mode 1" hexmask.long.word 0x34 23.--31. 1. "CMN_PLL0_SS_CTRL4_M1_15_7,Reserved" newline hexmask.long.byte 0x34 16.--22. 1. "CMN_PLL0_SS_CTRL4_M1_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator." newline hexmask.long.word 0x34 7.--15. 1. "CMN_PLL0_SS_CTRL3_M1_15_7,Reserved" newline hexmask.long.byte 0x34 0.--6. 1. "CMN_PLL0_SS_CTRL3_M1_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator." group.long 0x180++0x13 line.long 0x0 "CMN_PLL1_VCOCAL_START__CMN_PLL1_VCOCAL_CTRL,PLL 1 VCO calibration control register" rbitfld.long 0x0 31. "CMN_PLL1_VCOCAL_START_15,Reserved" "0,1" newline bitfld.long 0x0 28.--30. "CMN_PLL1_VCOCAL_START_14_12,VCO calibration initial step size control: This field specifies the initial step size for the VCO calibration state machine." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "CMN_PLL1_VCOCAL_START_11_8,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "CMN_PLL1_VCOCAL_START_7_0,VCO calibration code starting point value: This field specifies the starting VCO code that is used by the VCO calibration state machine." newline bitfld.long 0x0 15. "CMN_PLL1_VCOCAL_CTRL_15,Start VCO calibration: Activating (1'b1) this bit will start a VCO calibration process." "0,1" newline rbitfld.long 0x0 14. "CMN_PLL1_VCOCAL_CTRL_14,VCO calibration process done: This bit will be set to 1'b1 when the VCO calibration process is complete." "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "CMN_PLL1_VCOCAL_CTRL_13_8,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "CMN_PLL1_VCOCAL_CTRL_7_0,VCO calibration code: This is the calibration code that was determined by the VCO calibration process." line.long 0x4 "CMN_PLL1_VCOCAL_OVRD__CMN_PLL1_VCOCAL_TCTRL,PLL 1 VCO calibration timer control register" bitfld.long 0x4 31. "CMN_PLL1_VCOCAL_OVRD_15,VCO calibration code override enable: Activating (1'b1) this bit allows the VCO code determined during the automatic VCO calibration process to be overridden by the value driven by the VCO calibration code override value field in.." "0,1" newline hexmask.long.byte 0x4 24.--30. 1. "CMN_PLL1_VCOCAL_OVRD_14_8,Reserved" newline hexmask.long.byte 0x4 16.--23. 1. "CMN_PLL1_VCOCAL_OVRD_7_0,VCO calibration code override value: This field is used to override the VCO code determined during the automatic VCO calibration process." newline hexmask.long.word 0x4 3.--15. 1. "CMN_PLL1_VCOCAL_TCTRL_15_3,Reserved" newline bitfld.long 0x4 0.--2. "CMN_PLL1_VCOCAL_TCTRL_2_0,VCO calibration initial time scale control: This field specifies the calibration start time scaling factor applied to the VCO calibration when running the initial step size for the calibration code if not set to 1." "0,1,2,3,4,5,6,7" line.long 0x8 "CMN_PLL1_VCOCAL_ITER_TMR__CMN_PLL1_VCOCAL_INIT_TMR,PLL 1 VCO calibration initialization timer register" rbitfld.long 0x8 30.--31. "CMN_PLL1_VCOCAL_ITER_TMR_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x8 16.--29. 1. "CMN_PLL1_VCOCAL_ITER_TMR_13_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured." newline rbitfld.long 0x8 14.--15. "CMN_PLL1_VCOCAL_INIT_TMR_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x8 0.--13. 1. "CMN_PLL1_VCOCAL_INIT_TMR_13_0,Initialization wait timer value: This is the number of clocks to wait between when the analog VCO calibration circuits are enabled and when the first calibration code is driven to the analog." line.long 0xC "CMN_PLL1_VCOCAL_REFTIM_START,PLL 1 VCO calibration reference clock timer start value register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline rbitfld.long 0xC 14.--15. "CMN_PLL1_VCOCAL_REFTIM_START_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "CMN_PLL1_VCOCAL_REFTIM_START_13_0,PLL VCO calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running VCO calibration." line.long 0x10 "CMN_PLL1_VCOCAL_PLLCNT_START,PLL 1 VCO calibration PLL clock counter start value register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" newline rbitfld.long 0x10 14.--15. "CMN_PLL1_VCOCAL_PLLCNT_START_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x10 0.--13. 1. "CMN_PLL1_VCOCAL_PLLCNT_START_13_0,PLL VCO calibration PLL clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running VCO calibration." group.long 0x1A0++0x1F line.long 0x0 "CMN_PLL1_FRACDIVL_M0__CMN_PLL1_INTDIV_M0,PLL 1 feedback divider integer register mode 0" hexmask.long.word 0x0 16.--31. 1. "CMN_PLL1_FRACDIVL_M0_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal." newline hexmask.long.byte 0x0 9.--15. 1. "CMN_PLL1_INTDIV_M0_15_9,Reserved" newline hexmask.long.word 0x0 0.--8. 1. "CMN_PLL1_INTDIV_M0_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal." line.long 0x4 "CMN_PLL1_HIGH_THR_M0__CMN_PLL1_FRACDIVH_M0,PLL 1 feedback divider fractional high register mode 0" hexmask.long.byte 0x4 25.--31. 1. "CMN_PLL1_HIGH_THR_M0_15_9,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "CMN_PLL1_HIGH_THR_M0_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal." newline hexmask.long.word 0x4 3.--15. 1. "CMN_PLL1_FRACDIVH_M0_15_3,Reserved" newline bitfld.long 0x4 0.--2. "CMN_PLL1_FRACDIVH_M0_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal." "0,1,2,3,4,5,6,7" line.long 0x8 "CMN_PLL1_DSM_FBH_OVRD_M0__CMN_PLL1_DSM_DIAG_M0,PLL 1 delta sigma modulator diagnostics register mode 0" hexmask.long.byte 0x8 25.--31. 1. "CMN_PLL1_DSM_FBH_OVRD_M0_15_9,Reserved" newline hexmask.long.word 0x8 16.--24. 1. "CMN_PLL1_DSM_FBH_OVRD_M0_8_0,PLL feedback divider high override value : When enabled by the PLL feedback divider override enable bit in the PLL 1 delta sigma modulator diagnostics register mode 0 on page 111 the value in this field will be used to.." newline bitfld.long 0x8 15. "CMN_PLL1_DSM_DIAG_M0_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal." "0,1" newline bitfld.long 0x8 14. "CMN_PLL1_DSM_DIAG_M0_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 1 delta sigma modulator feedback divider value high override register mode 0 on page 111 and PLL 1 delta sigma.." "0,1" newline hexmask.long.word 0x8 4.--13. 1. "CMN_PLL1_DSM_DIAG_M0_13_4,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "CMN_PLL1_DSM_DIAG_M0_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll1_fb_div_high and cmnda_pll1_fb_div_low signals." line.long 0xC "CMN_PLL1_DSM_FBL_OVRD_M0,PLL 1 delta sigma modulator feedback divider value low override register mode 0" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 9.--15. 1. "CMN_PLL1_DSM_FBL_OVRD_M0_15_9,Reserved" newline hexmask.long.word 0xC 0.--8. 1. "CMN_PLL1_DSM_FBL_OVRD_M0_8_0,PLL feedback divider low override value : When enabled by the PLL feedback divider override enable bit in the PLL 1 delta sigma modulator diagnostics register mode 0 on page 111 the value in this field will be used to.." line.long 0x10 "CMN_PLL1_SS_CTRL2_M0__CMN_PLL1_SS_CTRL1_M0,PLL 1 spread spectrum control register 1 mode 0" rbitfld.long 0x10 31. "CMN_PLL1_SS_CTRL2_M0_15,Reserved" "0,1" newline hexmask.long.word 0x10 16.--30. 1. "CMN_PLL1_SS_CTRL2_M0_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator." newline hexmask.long.word 0x10 2.--15. 1. "CMN_PLL1_SS_CTRL1_M0_15_2,Reserved" newline bitfld.long 0x10 1. "CMN_PLL1_SS_CTRL1_M0_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator." "0,1" newline bitfld.long 0x10 0. "CMN_PLL1_SS_CTRL1_M0_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place." "0,1" line.long 0x14 "CMN_PLL1_SS_CTRL4_M0__CMN_PLL1_SS_CTRL3_M0,PLL 1 spread spectrum control register 3 mode 0" hexmask.long.word 0x14 23.--31. 1. "CMN_PLL1_SS_CTRL4_M0_15_7,Reserved" newline hexmask.long.byte 0x14 16.--22. 1. "CMN_PLL1_SS_CTRL4_M0_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator." newline hexmask.long.word 0x14 7.--15. 1. "CMN_PLL1_SS_CTRL3_M0_15_7,Reserved" newline hexmask.long.byte 0x14 0.--6. 1. "CMN_PLL1_SS_CTRL3_M0_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator." line.long 0x18 "CMN_PLL1_LOCK_REFCNT_IDLE__CMN_PLL1_LOCK_REFCNT_START,PLL 1 lock reference counter start value register" hexmask.long.byte 0x18 28.--31. 1. "CMN_PLL1_LOCK_REFCNT_IDLE_15_12,Reserved" newline hexmask.long.word 0x18 16.--27. 1. "CMN_PLL1_LOCK_REFCNT_IDLE_11_0,PLL lock reference counter idle value : This is the value used by the PLL lock detection logic to specify the number of reference clocks between each phase of counting PLL clocks." newline hexmask.long.byte 0x18 12.--15. 1. "CMN_PLL1_LOCK_REFCNT_START_15_12,Reserved" newline hexmask.long.word 0x18 0.--11. 1. "CMN_PLL1_LOCK_REFCNT_START_11_0,PLL lock reference counter start value : This is the value that is loaded into the PLL lock detect reference counter as the starting point for that counter when checking for PLL lock." line.long 0x1C "CMN_PLL1_LOCK_PLLCNT_THR__CMN_PLL1_LOCK_PLLCNT_START,PLL 1 lock PLL counter start value register" hexmask.long.byte 0x1C 28.--31. 1. "CMN_PLL1_LOCK_PLLCNT_THR_15_12,Reserved" newline hexmask.long.word 0x1C 16.--27. 1. "CMN_PLL1_LOCK_PLLCNT_THR_11_0,PLL lock counter threshold value : This is the value used by the PLL lock detection logic to determine if the PLL has locked." newline hexmask.long.byte 0x1C 12.--15. 1. "CMN_PLL1_LOCK_PLLCNT_START_15_12,Reserved" newline hexmask.long.word 0x1C 0.--11. 1. "CMN_PLL1_LOCK_PLLCNT_START_11_0,PLL lock PLL counter start value : This is the value that is loaded into the PLL lock detect PLL counter as the starting point for that counter when checking for PLL lock." group.long 0x200++0xB line.long 0x0 "CMN_TXPUCAL_OVRD__CMN_TXPUCAL_CTRL,TX pull-up resistor calibration control register" bitfld.long 0x0 31. "CMN_TXPUCAL_OVRD_15,Resistor code override enable: Activation (1'b1) of this register bit allows the resistor codes determined during the automatic resistor calibration process to be overridden." "0,1" newline bitfld.long 0x0 30. "CMN_TXPUCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_rescal_en_tx_useg enable and the cmnda_rescal_clk_tx_useg clock." "0,1" newline hexmask.long.byte 0x0 23.--29. 1. "CMN_TXPUCAL_OVRD_13_7,Reserved" newline hexmask.long.byte 0x0 16.--22. 1. "CMN_TXPUCAL_OVRD_6_0,Resistor code override value: These bits are used to override the resistor code determined during the automatic resistor calibration process." newline bitfld.long 0x0 15. "CMN_TXPUCAL_CTRL_15,Start resistor calibration: Activating (1'b1) this bit will start the resistor calibration process." "0,1" newline rbitfld.long 0x0 14. "CMN_TXPUCAL_CTRL_14,Resistor calibration process done: This bit will be set to 1'b1 when the resistor calibration process is complete." "0,1" newline rbitfld.long 0x0 13. "CMN_TXPUCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1" newline rbitfld.long 0x0 12. "CMN_TXPUCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_rescal_comp_tx_useg)." "0,1" newline hexmask.long.byte 0x0 7.--11. 1. "CMN_TXPUCAL_CTRL_11_7,Reserved" newline hexmask.long.byte 0x0 0.--6. 1. "CMN_TXPUCAL_CTRL_6_0,Resistor calibration code: This is the calibration code that was determined by the resistor calibration process." line.long 0x4 "CMN_TXPUCAL_TUNE__CMN_TXPUCAL_START,TX pull-up resistor calibration start register" hexmask.long.word 0x4 23.--31. 1. "CMN_TXPUCAL_TUNE_15_7,Reserved" newline hexmask.long.byte 0x4 16.--22. 1. "CMN_TXPUCAL_TUNE_6_0,Resistor calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled." newline bitfld.long 0x4 15. "CMN_TXPUCAL_START_15,Resistor calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in." "0,1" newline hexmask.long.byte 0x4 7.--14. 1. "CMN_TXPUCAL_START_14_7,Reserved" newline hexmask.long.byte 0x4 0.--6. 1. "CMN_TXPUCAL_START_6_0,Start resistor calibration code: This is the calibration code that the resistor calibration process starts with when automatic calibration is run." line.long 0x8 "CMN_TXPUCAL_ITER_TMR__CMN_TXPUCAL_INIT_TMR,TX pull-up resistor calibration initialization timer register" hexmask.long.word 0x8 23.--31. 1. "CMN_TXPUCAL_ITER_TMR_15_7,Reserved" newline hexmask.long.byte 0x8 16.--22. 1. "CMN_TXPUCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.word 0x8 7.--15. 1. "CMN_TXPUCAL_INIT_TMR_15_7,Reserved" newline hexmask.long.byte 0x8 0.--6. 1. "CMN_TXPUCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor.." group.long 0x210++0xB line.long 0x0 "CMN_TXPDCAL_OVRD__CMN_TXPDCAL_CTRL,TX pull-down resistor calibration control register" bitfld.long 0x0 31. "CMN_TXPDCAL_OVRD_15,Resistor code override enable: Activation (1'b1) of this register bit allows the resistor codes determined during the automatic resistor calibration process to be overridden." "0,1" newline bitfld.long 0x0 30. "CMN_TXPDCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_rescal_en_tx_dseg enable and the cmnda_rescal_clk_tx_dseg clock." "0,1" newline hexmask.long.byte 0x0 23.--29. 1. "CMN_TXPDCAL_OVRD_13_7,Reserved" newline hexmask.long.byte 0x0 16.--22. 1. "CMN_TXPDCAL_OVRD_6_0,Resistor code override value: These bits are used to override the resistor code determined during the automatic resistor calibration process." newline bitfld.long 0x0 15. "CMN_TXPDCAL_CTRL_15,Start resistor calibration: Activating (1'b1) this bit will start the resistor calibration process." "0,1" newline rbitfld.long 0x0 14. "CMN_TXPDCAL_CTRL_14,Resistor calibration process done: This bit will be set to 1'b1 when the resistor calibration process is complete." "0,1" newline rbitfld.long 0x0 13. "CMN_TXPDCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1" newline rbitfld.long 0x0 12. "CMN_TXPDCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_rescal_comp_tx_dseg)." "0,1" newline hexmask.long.byte 0x0 7.--11. 1. "CMN_TXPDCAL_CTRL_11_7,Reserved" newline hexmask.long.byte 0x0 0.--6. 1. "CMN_TXPDCAL_CTRL_6_0,Resistor calibration code: This is the calibration code that was determined by the resistor calibration process." line.long 0x4 "CMN_TXPDCAL_TUNE__CMN_TXPDCAL_START,TX pull-down resistor calibration start register" hexmask.long.word 0x4 23.--31. 1. "CMN_TXPDCAL_TUNE_15_7,Reserved" newline hexmask.long.byte 0x4 16.--22. 1. "CMN_TXPDCAL_TUNE_6_0,Resistor calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled." newline bitfld.long 0x4 15. "CMN_TXPDCAL_START_15,Resistor calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in." "0,1" newline hexmask.long.byte 0x4 7.--14. 1. "CMN_TXPDCAL_START_14_7,Reserved" newline hexmask.long.byte 0x4 0.--6. 1. "CMN_TXPDCAL_START_6_0,Start resistor calibration code: This is the calibration code that the resistor calibration process starts with when automatic calibration is run." line.long 0x8 "CMN_TXPDCAL_ITER_TMR__CMN_TXPDCAL_INIT_TMR,TX pull-down resistor calibration initialization timer register" hexmask.long.word 0x8 23.--31. 1. "CMN_TXPDCAL_ITER_TMR_15_7,Reserved" newline hexmask.long.byte 0x8 16.--22. 1. "CMN_TXPDCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.word 0x8 7.--15. 1. "CMN_TXPDCAL_INIT_TMR_15_7,Reserved" newline hexmask.long.byte 0x8 0.--6. 1. "CMN_TXPDCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor.." group.long 0x220++0xB line.long 0x0 "CMN_RXCAL_OVRD__CMN_RXCAL_CTRL,RX resistor calibration control register" bitfld.long 0x0 31. "CMN_RXCAL_OVRD_15,Resistor code override enable: Activation (1'b1) of this register bit allows the resistor codes determined during the automatic resistor calibration process to be overridden." "0,1" newline bitfld.long 0x0 30. "CMN_RXCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_rescal_en_rx enable and the cmnda_rescal_clk_rx clock." "0,1" newline hexmask.long.word 0x0 21.--29. 1. "CMN_RXCAL_OVRD_13_5,Reserved" newline hexmask.long.byte 0x0 16.--20. 1. "CMN_RXCAL_OVRD_4_0,Resistor code override value: These bits are used to override the resistor code determined during the automatic resistor calibration process." newline bitfld.long 0x0 15. "CMN_RXCAL_CTRL_15,Start resistor calibration: Activating (1'b1) this bit will start the resistor calibration process." "0,1" newline rbitfld.long 0x0 14. "CMN_RXCAL_CTRL_14,Resistor calibration process done: This bit will be set to 1'b1 when the resistor calibration process is complete." "0,1" newline rbitfld.long 0x0 13. "CMN_RXCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1" newline rbitfld.long 0x0 12. "CMN_RXCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_rescal_comp_rx)." "0,1" newline hexmask.long.byte 0x0 5.--11. 1. "CMN_RXCAL_CTRL_11_5,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "CMN_RXCAL_CTRL_4_0,Resistor calibration code: This is the calibration code that was determined by the resistor calibration process." line.long 0x4 "CMN_RXCAL_TUNE__CMN_RXCAL_START,RX resistor calibration start register" hexmask.long.word 0x4 21.--31. 1. "CMN_RXCAL_TUNE_15_5,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "CMN_RXCAL_TUNE_4_0,Resistor calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled." newline bitfld.long 0x4 15. "CMN_RXCAL_START_15,Resistor calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in." "0,1" newline hexmask.long.word 0x4 5.--14. 1. "CMN_RXCAL_START_14_5,Reserved" newline hexmask.long.byte 0x4 0.--4. 1. "CMN_RXCAL_START_4_0,Start resistor calibration code: This is the calibration code that the resistor calibration process starts with when automatic calibration is run." line.long 0x8 "CMN_RXCAL_ITER_TMR__CMN_RXCAL_INIT_TMR,RX resistor calibration initialization timer register" hexmask.long.byte 0x8 28.--31. 1. "CMN_RXCAL_ITER_TMR_15_12,Reserved" newline hexmask.long.word 0x8 16.--27. 1. "CMN_RXCAL_ITER_TMR_11_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.byte 0x8 12.--15. 1. "CMN_RXCAL_INIT_TMR_15_12,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "CMN_RXCAL_INIT_TMR_11_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor selection.." group.long 0x240++0x13 line.long 0x0 "CMN_SD_CAL_START__CMN_SD_CAL_CTRL,Signal detect clock calibration control register" rbitfld.long 0x0 31. "CMN_SD_CAL_START_15,Reserved" "0,1" newline bitfld.long 0x0 28.--30. "CMN_SD_CAL_START_14_12,Calibration initial step size control: This field specifies the initial step size for the calibration state machine." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 21.--27. 1. "CMN_SD_CAL_START_11_5,Reserved" newline hexmask.long.byte 0x0 16.--20. 1. "CMN_SD_CAL_START_4_0,Calibration code starting point value: This field specifies the starting code that is used by the calibration state machine." newline bitfld.long 0x0 15. "CMN_SD_CAL_CTRL_15,Start calibration: Activating (1'b1) this bit will start a calibration process." "0,1" newline rbitfld.long 0x0 14. "CMN_SD_CAL_CTRL_14,Calibration process done: This bit will be set to 1'b1 when the calibration process is complete." "0,1" newline hexmask.long.word 0x0 5.--13. 1. "CMN_SD_CAL_CTRL_13_5,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "CMN_SD_CAL_CTRL_4_0,Calibration code: This is the calibration code that was determined by the calibration process." line.long 0x4 "CMN_SD_CAL_OVRD__CMN_SD_CAL_TCTRL,Signal detect clock calibration timer control register" bitfld.long 0x4 31. "CMN_SD_CAL_OVRD_15,Calibration code override enable: Activating (1'b1) this bit allows the code determined during the automatic calibration process to be overridden by the value driven by the calibration code override value field in this register." "0,1" newline hexmask.long.word 0x4 21.--30. 1. "CMN_SD_CAL_OVRD_14_5,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "CMN_SD_CAL_OVRD_4_0,Calibration code override value: This field is used to override the code determined during the automatic calibration process." newline hexmask.long.word 0x4 3.--15. 1. "CMN_SD_CAL_TCTRL_15_3,Reserved" newline bitfld.long 0x4 0.--2. "CMN_SD_CAL_TCTRL_2_0,Calibration initial time scale control: This field specifies the calibration start time scaling factor applied to the calibration when running the initial step size for the calibration code is not set to 1." "0,1,2,3,4,5,6,7" line.long 0x8 "CMN_SD_CAL_ITER_TMR__CMN_SD_CAL_INIT_TMR,Signal detect clock calibration initialization timer register" hexmask.long.byte 0x8 24.--31. 1. "CMN_SD_CAL_ITER_TMR_15_8,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "CMN_SD_CAL_ITER_TMR_7_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured." newline hexmask.long.byte 0x8 8.--15. 1. "CMN_SD_CAL_INIT_TMR_15_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "CMN_SD_CAL_INIT_TMR_7_0,Initialization wait timer value: This is the number of clocks to wait between when the analog calibration circuits are enabled and when the first calibration code is driven to the analog." line.long 0xC "CMN_SD_CAL_REFTIM_START,Signal detect clock calibration reference clock timer start value register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 8.--15. 1. "CMN_SD_CAL_REFTIM_START_15_8,Reserved" newline hexmask.long.byte 0xC 0.--7. 1. "CMN_SD_CAL_REFTIM_START_7_0,Calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running calibration." line.long 0x10 "CMN_SD_CAL_PLLCNT_START,Signal detect clock calibration PLL clock counter start value register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" newline hexmask.long.byte 0x10 10.--15. 1. "CMN_SD_CAL_PLLCNT_START_15_10,Reserved" newline hexmask.long.word 0x10 0.--9. 1. "CMN_SD_CAL_PLLCNT_START_9_0,Calibration feedback clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running calibration." group.long 0x300++0x7 line.long 0x0 "CMN_CMSMT_TEST_CLK_SEL__CMN_CMSMT_CLK_FREQ_MSMT_CTRL,Clock frequency measurement control register" hexmask.long.word 0x0 19.--31. 1. "CMN_CMSMT_TEST_CLK_SEL_15_3,Reserved" newline bitfld.long 0x0 16.--18. "CMN_CMSMT_TEST_CLK_SEL_2_0,Test clock select: This field drives the test_clk_select pin in order to control an external MUX for selecting between multiple test clocks to measure." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "CMN_CMSMT_CLK_FREQ_MSMT_CTRL_15,Run test clock measurement: Activating (1'b1) this bit will run the test clock measurement process." "0,1" newline rbitfld.long 0x0 14. "CMN_CMSMT_CLK_FREQ_MSMT_CTRL_14,Test clock measurement done: This bit will be set to 1'b1 when the test clock measurement process is complete." "0,1" newline hexmask.long.word 0x0 0.--13. 1. "CMN_CMSMT_CLK_FREQ_MSMT_CTRL_13_0,Reserved" line.long 0x4 "CMN_CMSMT_TEST_CLK_CNT_VALUE__CMN_CMSMT_REF_CLK_TMR_VALUE,Reference clock timer value register" hexmask.long.byte 0x4 28.--31. 1. "CMN_CMSMT_TEST_CLK_CNT_VALUE_15_12,Reserved" newline hexmask.long.word 0x4 16.--27. 1. "CMN_CMSMT_TEST_CLK_CNT_VALUE_11_0,Test clock counter value: When the test clock measurement process is complete the value in this field specifies the number of test clock cycles that were counted in the time specified by the reference clock timer value." newline hexmask.long.byte 0x4 12.--15. 1. "CMN_CMSMT_REF_CLK_TMR_VALUE_15_12,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "CMN_CMSMT_REF_CLK_TMR_VALUE_11_0,Reference clock timer value : This specifies the amount of time in reference clock cycles to count test clock cycles." group.long 0x340++0xF line.long 0x0 "CMN_PDIAG_PLL0_CLK_SEL_M0__CMN_PDIAG_PLL0_CTRL_M0,PLL 0 control register mode 0" bitfld.long 0x0 31. "CMN_PDIAG_PLL0_CLK_SEL_M0_15,PLL 0 clock 1 divider enable: This bit enables the divider used to generate the cmnda_pll0_clk_1 from the PLL high speed clock." "0,1" newline bitfld.long 0x0 28.--30. "CMN_PDIAG_PLL0_CLK_SEL_M0_14_12,PLL 0 clock 1 divider select: This field selects the divider value used to generate the cmnda_pll0_clk_1 from the PLL high speed clock by driving the cmnda_pll0_clk_1_div_sel signal to the analog." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "CMN_PDIAG_PLL0_CLK_SEL_M0_11_8,PLL 0 clock 0 and derived reference clock divider select: This field selects the divider value used to generate the cmnda_pll0_clk_0 and derived reference clock from the PLL high speed clock by driving the.." newline hexmask.long.byte 0x0 18.--23. 1. "CMN_PDIAG_PLL0_CLK_SEL_M0_7_2,Reserved" newline bitfld.long 0x0 16.--17. "CMN_PDIAG_PLL0_CLK_SEL_M0_1_0,PLL 0 clock select: This field selects one of 3 possible high speed output clocks from PLL 0 to drive on the high speed analog clock 0 by driving the cmnda_pll0_clk_sel signal to the analog." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "CMN_PDIAG_PLL0_CTRL_M0_15_12,This field controls the Ring VCO Frequency drift with temperature." newline rbitfld.long 0x0 9.--11. "CMN_PDIAG_PLL0_CTRL_M0_11_9,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "CMN_PDIAG_PLL0_CTRL_M0_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll0_vco_sel signal going into the common analog." "0,1" newline rbitfld.long 0x0 6.--7. "CMN_PDIAG_PLL0_CTRL_M0_7_6,Reserved" "0,1,2,3" newline bitfld.long 0x0 5. "CMN_PDIAG_PLL0_CTRL_M0_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll0_fb_divider_clk by driving the cmnda_pll0_fb_divider_clk_sel signal going into the common analog." "0,1" newline bitfld.long 0x0 4. "CMN_PDIAG_PLL0_CTRL_M0_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll0_div24_sel signal going into the common analog." "0,1" newline rbitfld.long 0x0 2.--3. "CMN_PDIAG_PLL0_CTRL_M0_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CMN_PDIAG_PLL0_CTRL_M0_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD." "0,1,2,3" line.long 0x4 "CMN_PDIAG_PLL0_ITRIM_M0__CMN_PDIAG_PLL0_OVRD_M0,PLL 0 override register mode 0" hexmask.long.byte 0x4 24.--31. 1. "CMN_PDIAG_PLL0_ITRIM_M0_15_8,Reserved" newline hexmask.long.byte 0x4 16.--23. 1. "CMN_PDIAG_PLL0_ITRIM_M0_7_0,PLL VCO bias current trim code: Controls the tank currents in the PLL LC tank circuit." newline hexmask.long.word 0x4 4.--15. 1. "CMN_PDIAG_PLL0_OVRD_M0_15_4,Reserved" newline bitfld.long 0x4 3. "CMN_PDIAG_PLL0_OVRD_M0_3,PLL VCO calibration enable override enable: When active (1'b1) the PLL VCO calibration enable override bit in this register can be used to directly control the enable of the VCO calibration function in the PLL (instead of the.." "0,1" newline bitfld.long 0x4 2. "CMN_PDIAG_PLL0_OVRD_M0_2,PLL VCO calibration enable override: When enabled by the PLL VCO calibration enable override enable bit in this register this bit will directly control the enable of the VCO calibration function in the PLL." "0,1" newline bitfld.long 0x4 1. "CMN_PDIAG_PLL0_OVRD_M0_1,PLL phase lock detect enable : Enables the diagnostic PLL phase lock detect function in the analog." "0,1" newline rbitfld.long 0x4 0. "CMN_PDIAG_PLL0_OVRD_M0_0,PLL phase lock detected : When enabled by the PLL phase lock detect enable bit in this register this bit indicates that a PLL phase lock has been detected." "0,1" line.long 0x8 "CMN_PDIAG_PLL0_CP_IADJ_M0__CMN_PDIAG_PLL0_CP_PADJ_M0,PLL 0 charge pump proportional path adjust register mode 0" hexmask.long.byte 0x8 24.--31. 1. "CMN_PDIAG_PLL0_CP_IADJ_M0_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll0_cp_int_cap_adj signal going to the analog." newline hexmask.long.byte 0x8 16.--23. 1. "CMN_PDIAG_PLL0_CP_IADJ_M0_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll0_cp_int_cur_adj signal going to the analog." newline hexmask.long.byte 0x8 8.--15. 1. "CMN_PDIAG_PLL0_CP_PADJ_M0_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll0_cp_prop_cap_adj signal going to the analog." newline hexmask.long.byte 0x8 0.--7. 1. "CMN_PDIAG_PLL0_CP_PADJ_M0_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll0_cp_prop_cur_adj signal going to the analog." line.long 0xC "CMN_PDIAG_PLL0_CP_TUNE_M0__CMN_PDIAG_PLL0_FILT_PADJ_M0,PLL 0 proportional path filter adjust register mode 0" hexmask.long.word 0xC 18.--31. 1. "CMN_PDIAG_PLL0_CP_TUNE_M0_15_2,Reserved" newline bitfld.long 0xC 16.--17. "CMN_PDIAG_PLL0_CP_TUNE_M0_1_0,PLL charge pump calibration reference voltage tune: Adjusts the charge pump calibration reference voltage by driving the cmnda_pll0_cp_vref_tune signal going to the analog." "0,1,2,3" newline hexmask.long.byte 0xC 12.--15. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M0_15_12,Reserved" newline hexmask.long.byte 0xC 8.--11. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M0_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll0_filt_c_adj signal going to the analog." newline hexmask.long.byte 0xC 4.--7. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M0_7_4,Reserved" newline hexmask.long.byte 0xC 0.--3. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M0_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll0_filt_r_adj signal going to the analog." group.long 0x360++0xF line.long 0x0 "CMN_PDIAG_PLL0_CLK_SEL_M1__CMN_PDIAG_PLL0_CTRL_M1,PLL 0 control register mode 1" bitfld.long 0x0 31. "CMN_PDIAG_PLL0_CLK_SEL_M1_15,PLL 0 clock 1 divider enable: This bit enables the divider used to generate the cmnda_pll0_clk_1 from the PLL high speed clock." "0,1" newline bitfld.long 0x0 28.--30. "CMN_PDIAG_PLL0_CLK_SEL_M1_14_12,PLL 0 clock 1 divider select: This field selects the divider value used to generate the cmnda_pll0_clk_1 from the PLL high speed clock by driving the cmnda_pll0_clk_1_div_sel signal to the analog." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "CMN_PDIAG_PLL0_CLK_SEL_M1_11_8,PLL 0 clock 0 and derived reference clock divider select: This field selects the divider value used to generate the cmnda_pll0_clk_0 and derived reference clock from the PLL high speed clock by driving the.." newline hexmask.long.byte 0x0 18.--23. 1. "CMN_PDIAG_PLL0_CLK_SEL_M1_7_2,Reserved" newline bitfld.long 0x0 16.--17. "CMN_PDIAG_PLL0_CLK_SEL_M1_1_0,PLL 0 clock select: This field selects one of 3 possible high speed output clocks from PLL 0 to drive on the high speed analog clock 0 by driving the cmnda_pll0_clk_sel signal to the analog." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "CMN_PDIAG_PLL0_CTRL_M1_15_12,This field controls the Ring VCO Frequency drift with temperature." newline rbitfld.long 0x0 9.--11. "CMN_PDIAG_PLL0_CTRL_M1_11_9,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "CMN_PDIAG_PLL0_CTRL_M1_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll0_vco_sel signal going into the common analog." "0,1" newline rbitfld.long 0x0 6.--7. "CMN_PDIAG_PLL0_CTRL_M1_7_6,Reserved" "0,1,2,3" newline bitfld.long 0x0 5. "CMN_PDIAG_PLL0_CTRL_M1_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll0_fb_divider_clk driving the cmnda_pll0_fb_divider_clk_sel signal going into the common analog." "0,1" newline bitfld.long 0x0 4. "CMN_PDIAG_PLL0_CTRL_M1_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll0_div24_sel signal going into the common analog." "0,1" newline rbitfld.long 0x0 2.--3. "CMN_PDIAG_PLL0_CTRL_M1_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CMN_PDIAG_PLL0_CTRL_M1_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD." "0,1,2,3" line.long 0x4 "CMN_PDIAG_PLL0_ITRIM_M1__CMN_PDIAG_PLL0_OVRD_M1,PLL 0 override register mode 1" hexmask.long.byte 0x4 24.--31. 1. "CMN_PDIAG_PLL0_ITRIM_M1_15_8,Reserved" newline hexmask.long.byte 0x4 16.--23. 1. "CMN_PDIAG_PLL0_ITRIM_M1_7_0,PLL VCO bias current trim code: Controls the tank currents in the PLL LC tank circuit." newline hexmask.long.word 0x4 4.--15. 1. "CMN_PDIAG_PLL0_OVRD_M1_15_4,Reserved" newline bitfld.long 0x4 3. "CMN_PDIAG_PLL0_OVRD_M1_3,PLL VCO calibration enable override enable: When active (1'b1) the PLL VCO calibration enable override bit in this register can be used to directly control the enable of the VCO calibration function in the PLL (instead of the.." "0,1" newline bitfld.long 0x4 2. "CMN_PDIAG_PLL0_OVRD_M1_2,PLL VCO calibration enable override: When enabled by the PLL VCO calibration enable override enable bit in this register this bit will directly control the enable of the VCO calibration function in the PLL." "0,1" newline bitfld.long 0x4 1. "CMN_PDIAG_PLL0_OVRD_M1_1,PLL phase lock detect enable : Enables the diagnostic PLL phase lock detect function in the analog." "0,1" newline rbitfld.long 0x4 0. "CMN_PDIAG_PLL0_OVRD_M1_0,PLL phase lock detected : When enabled by the PLL phase lock detect enable bit in this register this bit indicates that a PLL phase lock has been detected." "0,1" line.long 0x8 "CMN_PDIAG_PLL0_CP_IADJ_M1__CMN_PDIAG_PLL0_CP_PADJ_M1,PLL 0 charge pump proportional path adjust register mode 1" hexmask.long.byte 0x8 24.--31. 1. "CMN_PDIAG_PLL0_CP_IADJ_M1_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll0_cp_int_cap_adj signal going to the analog." newline hexmask.long.byte 0x8 16.--23. 1. "CMN_PDIAG_PLL0_CP_IADJ_M1_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll0_cp_int_cur_adj signal going to the analog." newline hexmask.long.byte 0x8 8.--15. 1. "CMN_PDIAG_PLL0_CP_PADJ_M1_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll0_cp_prop_cap_adj signal going to the analog." newline hexmask.long.byte 0x8 0.--7. 1. "CMN_PDIAG_PLL0_CP_PADJ_M1_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll0_cp_prop_cur_adj signal going to the analog." line.long 0xC "CMN_PDIAG_PLL0_CP_TUNE_M1__CMN_PDIAG_PLL0_FILT_PADJ_M1,PLL 0 proportional path filter adjust register mode 1" hexmask.long.word 0xC 18.--31. 1. "CMN_PDIAG_PLL0_CP_TUNE_M1_15_2,Reserved" newline bitfld.long 0xC 16.--17. "CMN_PDIAG_PLL0_CP_TUNE_M1_1_0,PLL charge pump calibration reference voltage tune: Adjusts the charge pump calibration reference voltage by driving the cmnda_pll0_cp_vref_tune signal going to the analog." "0,1,2,3" newline hexmask.long.byte 0xC 12.--15. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M1_15_12,Reserved" newline hexmask.long.byte 0xC 8.--11. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M1_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll0_filt_c_adj signal going to the analog." newline hexmask.long.byte 0xC 4.--7. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M1_7_4,Reserved" newline hexmask.long.byte 0xC 0.--3. 1. "CMN_PDIAG_PLL0_FILT_PADJ_M1_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll0_filt_r_adj signal going to the analog." group.long 0x380++0xF line.long 0x0 "CMN_PDIAG_PLL1_CLK_SEL_M0__CMN_PDIAG_PLL1_CTRL_M0,PLL 1 control register mode 0" bitfld.long 0x0 31. "CMN_PDIAG_PLL1_CLK_SEL_M0_15,PLL 1 clock 1 divider enable: This bit enables the divider used to generate the cmnda_pll1_clk_1 from the PLL high speed clock." "0,1" newline bitfld.long 0x0 28.--30. "CMN_PDIAG_PLL1_CLK_SEL_M0_14_12,PLL 1 clock 1 divider select: This field selects the divider value used to generate the cmnda_pll1_clk_1 from the PLL high speed clock by driving the cmnda_pll1_clk_1_div_sel signal to the analog." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "CMN_PDIAG_PLL1_CLK_SEL_M0_11_8,PLL 1 clock 0 and derived reference clock divider select: This field selects the divider value used to generate the cmnda_pll1_clk_0 and derived reference clock from the PLL high speed clock by driving the.." newline hexmask.long.byte 0x0 18.--23. 1. "CMN_PDIAG_PLL1_CLK_SEL_M0_7_2,Reserved" newline bitfld.long 0x0 16.--17. "CMN_PDIAG_PLL1_CLK_SEL_M0_1_0,PLL 1 clock select: This field selects one of 3 possible high speed output clocks from PLL 1 to drive on the high speed analog clock 1 by driving the cmnda_pll1_clk_sel signal to the analog." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "CMN_PDIAG_PLL1_CTRL_M0_15_12,This field controls the Ring VCO Frequency drift with temperature." newline rbitfld.long 0x0 9.--11. "CMN_PDIAG_PLL1_CTRL_M0_11_9,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "CMN_PDIAG_PLL1_CTRL_M0_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll1_vco_sel signal going into the common analog." "0,1" newline rbitfld.long 0x0 6.--7. "CMN_PDIAG_PLL1_CTRL_M0_7_6,Reserved" "0,1,2,3" newline bitfld.long 0x0 5. "CMN_PDIAG_PLL1_CTRL_M0_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll1_fb_divider_clk driving the cmnda_pll1_fb_divider_clk_sel signal going into the common analog." "0,1" newline bitfld.long 0x0 4. "CMN_PDIAG_PLL1_CTRL_M0_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll1_div24_sel signal going into the common analog." "0,1" newline rbitfld.long 0x0 2.--3. "CMN_PDIAG_PLL1_CTRL_M0_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CMN_PDIAG_PLL1_CTRL_M0_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD." "0,1,2,3" line.long 0x4 "CMN_PDIAG_PLL1_ITRIM_M0__CMN_PDIAG_PLL1_OVRD_M0,PLL 1 override register mode 0" hexmask.long.byte 0x4 24.--31. 1. "CMN_PDIAG_PLL1_ITRIM_M0_15_8,Reserved" newline hexmask.long.byte 0x4 16.--23. 1. "CMN_PDIAG_PLL1_ITRIM_M0_7_0,PLL VCO bias current trim code: Controls the tank currents in the PLL LC tank circuit." newline hexmask.long.word 0x4 4.--15. 1. "CMN_PDIAG_PLL1_OVRD_M0_15_4,Reserved" newline bitfld.long 0x4 3. "CMN_PDIAG_PLL1_OVRD_M0_3,PLL VCO calibration enable override enable: When active (1'b1) the PLL VCO calibration enable override bit in this register can be used to directly control the enable of the VCO calibration function in the PLL (instead of the.." "0,1" newline bitfld.long 0x4 2. "CMN_PDIAG_PLL1_OVRD_M0_2,PLL VCO calibration enable override: When enabled by the PLL VCO calibration enable override enable bit in this register this bit will directly control the enable of the VCO calibration function in the PLL." "0,1" newline bitfld.long 0x4 1. "CMN_PDIAG_PLL1_OVRD_M0_1,PLL phase lock detect enable : Enables the diagnostic PLL phase lock detect function in the analog." "0,1" newline rbitfld.long 0x4 0. "CMN_PDIAG_PLL1_OVRD_M0_0,PLL phase lock detected : When enabled by the PLL phase lock detect enable bit in this register this bit indicates that a PLL phase lock has been detected." "0,1" line.long 0x8 "CMN_PDIAG_PLL1_CP_IADJ_M0__CMN_PDIAG_PLL1_CP_PADJ_M0,PLL 1 charge pump proportional path adjust register mode 0" hexmask.long.byte 0x8 24.--31. 1. "CMN_PDIAG_PLL1_CP_IADJ_M0_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll1_cp_int_cap_adj signal going to the analog." newline hexmask.long.byte 0x8 16.--23. 1. "CMN_PDIAG_PLL1_CP_IADJ_M0_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll1_cp_int_cur_adj signal going to the analog." newline hexmask.long.byte 0x8 8.--15. 1. "CMN_PDIAG_PLL1_CP_PADJ_M0_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll1_cp_prop_cap_adj signal going to the analog." newline hexmask.long.byte 0x8 0.--7. 1. "CMN_PDIAG_PLL1_CP_PADJ_M0_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll1_cp_prop_cur_adj signal going to the analog." line.long 0xC "CMN_PDIAG_PLL1_CP_TUNE_M0__CMN_PDIAG_PLL1_FILT_PADJ_M0,PLL 1 proportional path filter adjust register mode 0" hexmask.long.word 0xC 18.--31. 1. "CMN_PDIAG_PLL1_CP_TUNE_M0_15_2,Reserved" newline bitfld.long 0xC 16.--17. "CMN_PDIAG_PLL1_CP_TUNE_M0_1_0,PLL charge pump calibration reference voltage tune: Adjusts the charge pump calibration reference voltage by driving the cmnda_pll1_cp_vref_tune signal going to the analog." "0,1,2,3" newline hexmask.long.byte 0xC 12.--15. 1. "CMN_PDIAG_PLL1_FILT_PADJ_M0_15_12,Reserved" newline hexmask.long.byte 0xC 8.--11. 1. "CMN_PDIAG_PLL1_FILT_PADJ_M0_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll1_filt_c_adj signal going to the analog." newline hexmask.long.byte 0xC 4.--7. 1. "CMN_PDIAG_PLL1_FILT_PADJ_M0_7_4,Reserved" newline hexmask.long.byte 0xC 0.--3. 1. "CMN_PDIAG_PLL1_FILT_PADJ_M0_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll1_filt_r_adj signal going to the analog." group.long 0x3C0++0xB line.long 0x0 "CMN_DIAG_BIAS_OVRD1__CMN_DIAG_BANDGAP_OVRD,Bandgap override register" rbitfld.long 0x0 31. "CMN_DIAG_BIAS_OVRD1_15,Reserved" "0,1" newline bitfld.long 0x0 28.--30. "CMN_DIAG_BIAS_OVRD1_14_12,Receiver resistor calibration current adjust: This field is used to adjust the receiver resistor calibration bias current." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 27. "CMN_DIAG_BIAS_OVRD1_11,Reserved" "0,1" newline bitfld.long 0x0 24.--26. "CMN_DIAG_BIAS_OVRD1_10_8,Transmitter resistor calibration current adjust: This field is used to adjust the transmitter resistor calibration bias current." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 20.--23. 1. "CMN_DIAG_BIAS_OVRD1_7_4,Reserved - spare" newline rbitfld.long 0x0 17.--19. "CMN_DIAG_BIAS_OVRD1_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "CMN_DIAG_BIAS_OVRD1_0,Reserved - spare" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "CMN_DIAG_BANDGAP_OVRD_15_12,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "CMN_DIAG_BANDGAP_OVRD_11_8,Bandgap startup circuit startup count : Identifies the status of the bandgap startup counter." newline rbitfld.long 0x0 5.--7. "CMN_DIAG_BANDGAP_OVRD_7_5,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CMN_DIAG_BANDGAP_OVRD_4,Bandgap startup circuit select : Selects the startup circuit to be used for the bias / bandgap circuits by driving the cmnda_bias_bg_start_sel signal going to the analog." "0,1" newline bitfld.long 0x0 2.--3. "CMN_DIAG_BANDGAP_OVRD_3_2,Bandgap startup circuit sense voltage adjust : This field is used to adjust the bandgap startup circuit sense voltage by driving the cmnda_bias_bg_start_adj signal to the analog." "0,1,2,3" newline bitfld.long 0x0 0.--1. "CMN_DIAG_BANDGAP_OVRD_1_0,Bandgap voltage adjust : This field is used to adjust the bandgap voltage by driving the cmnda_bias_bg_adj signal to the analog." "0,1,2,3" line.long 0x4 "CMN_DIAG_VREG_CTRL__CMN_DIAG_BIAS_OVRD2,Bias override register 2" hexmask.long.word 0x4 17.--31. 1. "CMN_DIAG_VREG_CTRL_15_1,Reserved" newline bitfld.long 0x4 16. "CMN_DIAG_VREG_CTRL_0,Voltage regulator reference voltage select: Selects the reference voltage used for the voltage regulator in common by driving the cmnda_vreg_ref_sel signal to the analog." "0,1" newline hexmask.long.word 0x4 6.--15. 1. "CMN_DIAG_BIAS_OVRD2_15_6,Reserved" newline bitfld.long 0x4 5. "CMN_DIAG_BIAS_OVRD2_5,Bias filter bypass enable override enable: When active (1'b1) the bias filter bypass enable override bit in this register can be used to directly control the bias filter bypass enable function." "0,1" newline bitfld.long 0x4 4. "CMN_DIAG_BIAS_OVRD2_4,Bias filter bypass enable override: When enabled by the bias filter bypass enable override enable bit in this register this bit will directly control the bias filter bypass enable function." "0,1" newline rbitfld.long 0x4 2.--3. "CMN_DIAG_BIAS_OVRD2_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x4 0.--1. "CMN_DIAG_BIAS_OVRD2_1_0,Regulator bandgap reference voltage adjust: This field is used to adjust the regulator bandgap reference voltage by driving the cmnda_bias_vreg_adj signal to the analog." "0,1,2,3" line.long 0x8 "CMN_DIAG_SH_BANDGAP__CMN_DIAG_PM_CTRL,Common process monitor control register" hexmask.long.word 0x8 22.--31. 1. "CMN_DIAG_SH_BANDGAP_15_6,Reserved" newline rbitfld.long 0x8 21. "CMN_DIAG_SH_BANDGAP_5,Bandgap up value: Bandgap calibration up signal value as it is currently captured in the sample and hold latches." "0,1" newline hexmask.long.byte 0x8 16.--20. 1. "CMN_DIAG_SH_BANDGAP_4_0,Bandgap auto zero select value: Bandgap calibration auto zero select signal value as it is currently captured in the sample and hold latches." newline hexmask.long.word 0x8 5.--15. 1. "CMN_DIAG_PM_CTRL_15_5,Reserved" newline bitfld.long 0x8 4. "CMN_DIAG_PM_CTRL_4,Process monitor enable: Enables the analog process monitor by driving the cmnda_pcm_en signal to the analog." "0,1" newline rbitfld.long 0x8 3. "CMN_DIAG_PM_CTRL_3,Reserved" "0,1" newline bitfld.long 0x8 0.--2. "CMN_DIAG_PM_CTRL_2_0,Process monitor mode select: Selects the mode of the analog process monitor by driving the cmnda_pcm_sel signal to the analog." "0,1,2,3,4,5,6,7" rgroup.long 0x3CC++0x3 line.long 0x0 "CMN_DIAG_SH_SDCLK__CMN_DIAG_SH_RESISTOR,Sample and hold resistor calibration code register" hexmask.long.word 0x0 21.--31. 1. "CMN_DIAG_SH_SDCLK_15_5,Reserved" newline hexmask.long.byte 0x0 16.--20. 1. "CMN_DIAG_SH_SDCLK_4_0,Signal detect clock code: Signal detect clock calibration code signal value as it is currently captured in the sample and hold latches." newline bitfld.long 0x0 14.--15. "CMN_DIAG_SH_RESISTOR_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "CMN_DIAG_SH_RESISTOR_13_8,TX resistor code: TX resistor calibration code signal value as it is currently captured in the sample and hold latches." newline hexmask.long.byte 0x0 4.--7. 1. "CMN_DIAG_SH_RESISTOR_7_4,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "CMN_DIAG_SH_RESISTOR_3_0,RX resistor code: RX resistor calibration code signal value as it is currently captured in the sample and hold latches." group.long 0x3D0++0xF line.long 0x0 "CMN_DIAG_ATB_CTRL2__CMN_DIAG_ATB_CTRL1,ATB control register 1" rbitfld.long 0x0 29.--31. "CMN_DIAG_ATB_CTRL2_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27.--28. "CMN_DIAG_ATB_CTRL2_12_11,ATB component type select: These bits specify which component type is currently selected by the ATB as specified below." "0,1,2,3" newline hexmask.long.byte 0x0 22.--26. 1. "CMN_DIAG_ATB_CTRL2_10_6,ATB component sub address: Specifies the sub address of the component being selected." newline hexmask.long.byte 0x0 16.--21. 1. "CMN_DIAG_ATB_CTRL2_5_0,ATB test point address: Specifies the exact point in the selected analog component to be observed." newline hexmask.long.word 0x0 2.--15. 1. "CMN_DIAG_ATB_CTRL1_15_2,Reserved" newline bitfld.long 0x0 1. "CMN_DIAG_ATB_CTRL1_1,Core side ATB enable: When active (1'b) and the ATB enable bit in this register is also active the ATB signals will be driven on the core side ATB signals." "0,1" newline bitfld.long 0x0 0. "CMN_DIAG_ATB_CTRL1_0,ATB enable: When active (1'b1) the ATB test function is enabled." "0,1" line.long 0x4 "CMN_DIAG_ATB_ADC_CTRL1__CMN_DIAG_ATB_ADC_CTRL0,ATB ADC control register 0" rbitfld.long 0x4 30.--31. "CMN_DIAG_ATB_ADC_CTRL1_15_14,Reserved" "0,1,2,3" newline bitfld.long 0x4 29. "CMN_DIAG_ATB_ADC_CTRL1_13,ATB ADC offset correction enable : Enables internal auto generated offset correction mode by driving the cmnda_atba2d_en_off_cor signal to the analog." "0,1" newline bitfld.long 0x4 28. "CMN_DIAG_ATB_ADC_CTRL1_12,ATB ADC force cap values : Forces a positive or negative voltage on the internal cap by driving the cmnda_atba2d_frc_val signal to the analog." "0,1" newline bitfld.long 0x4 27. "CMN_DIAG_ATB_ADC_CTRL1_11,ATB ADC enable manual offset correction : When this signal is active the value in the ATB ADC manual offset correction value field of this register is used to manually control the offset correction by driving the.." "0,1" newline rbitfld.long 0x4 25.--26. "CMN_DIAG_ATB_ADC_CTRL1_10_9,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 20.--24. 1. "CMN_DIAG_ATB_ADC_CTRL1_8_4,ATB ADC manual offset correction value : When the ATB ADC enable manual offset correction bit in this register is active this field is used to manually control the offset correction by driving the cmnda_atba2d_off_adj_byp.." newline hexmask.long.byte 0x4 16.--19. 1. "CMN_DIAG_ATB_ADC_CTRL1_3_0,ATB ADC mode : This field indicates the mode the analog to digital converter is in." newline bitfld.long 0x4 15. "CMN_DIAG_ATB_ADC_CTRL0_15,ATB analog ADC enable: This enables the analog ADC function by driving the cmnda_atba2d_en signal to the analog." "0,1" newline bitfld.long 0x4 14. "CMN_DIAG_ATB_ADC_CTRL0_14,Start ATB ADC process: Activating (1'b1) this bit will start the ATB ADC process." "0,1" newline rbitfld.long 0x4 13. "CMN_DIAG_ATB_ADC_CTRL0_13,ATB ADC process done: This bit will be set to 1'b1 when the ATB ADC process is complete and the data in the ATB ADC code field of this register is considered valid." "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "CMN_DIAG_ATB_ADC_CTRL0_12_8,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "CMN_DIAG_ATB_ADC_CTRL0_7_0,ATB ADC data code: This is the digital code representing the level of the analog ATB signal that was digitized by the analog ADC." line.long 0x8 "CMN_DIAG_RST_DIAG__CMN_DIAG_HSRRSM_CTRL,Common high speed reset release state machine control register" hexmask.long.byte 0x8 28.--31. 1. "CMN_DIAG_RST_DIAG_15_12,Reserved" newline rbitfld.long 0x8 27. "CMN_DIAG_RST_DIAG_11,Current state of the cmn_sd_clk_cal_fb_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 26. "CMN_DIAG_RST_DIAG_10,Current state of the cmn_sd_clk_cal_ref_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 25. "CMN_DIAG_RST_DIAG_9,Current state of the cmn_pll1_dsm_reset_n reset." "0,1" newline rbitfld.long 0x8 24. "CMN_DIAG_RST_DIAG_8,Current state of the cmn_pll0_dsm_reset_n reset." "0,1" newline rbitfld.long 0x8 23. "CMN_DIAG_RST_DIAG_7,Current state of the cmn_pll1_vco_cal_fbdiv_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 22. "CMN_DIAG_RST_DIAG_6,Current state of the cmn_pll1_lock_det_fbdiv_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 21. "CMN_DIAG_RST_DIAG_5,Current state of the cmn_pll1_vco_cal_ref_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 20. "CMN_DIAG_RST_DIAG_4,Current state of the cmn_pll1_lock_det_ref_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 19. "CMN_DIAG_RST_DIAG_3,Current state of the cmn_pll0_vco_cal_fbdiv_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 18. "CMN_DIAG_RST_DIAG_2,Current state of the cmn_pll0_lock_det_fbdiv_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 17. "CMN_DIAG_RST_DIAG_1,Current state of the cmn_pll0_vco_cal_ref_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 16. "CMN_DIAG_RST_DIAG_0,Current state of the cmn_pll0_lock_det_ref_clk_reset_n reset." "0,1" newline hexmask.long.word 0x8 7.--15. 1. "CMN_DIAG_HSRRSM_CTRL_15_7,Reserved" newline bitfld.long 0x8 4.--6. "CMN_DIAG_HSRRSM_CTRL_6_4,Transceiver reset delay : Species the number of PSM clock cycles the transceiver common high speed reset state machine stays in the delay state." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 3. "CMN_DIAG_HSRRSM_CTRL_3,Reserved" "0,1" newline bitfld.long 0x8 0.--2. "CMN_DIAG_HSRRSM_CTRL_2_0,Transmitter reset delay : Species the number of PSM clock cycles the transmitter common high speed reset state machine stays in the delay state." "0,1,2,3,4,5,6,7" line.long 0xC "CMN_DIAG_ACYA__CMN_DIAG_DCYA,Common digital functions cover your alternatives register" hexmask.long.byte 0xC 24.--31. 1. "CMN_DIAG_ACYA_15_8,Reserved" newline hexmask.long.byte 0xC 20.--23. 1. "CMN_DIAG_ACYA_7_4,Reserved - spare" newline hexmask.long.byte 0xC 16.--19. 1. "CMN_DIAG_ACYA_3_0,PLL charge pump proportional gain adjust: Adjusts the charge pump gain for the PLLs to help manage bandwidth." newline hexmask.long.byte 0xC 8.--15. 1. "CMN_DIAG_DCYA_15_8,Reserved" newline hexmask.long.byte 0xC 0.--7. 1. "CMN_DIAG_DCYA_7_0,Reserved - spare" rgroup.long 0x400++0x3 line.long 0x0 "MOD_VER,The Module and Version Register identifies the module identifier and revision of the WIZmodule." bitfld.long 0x0 30.--31. "SCHEME,Module Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,Module BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID." newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version." newline bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision." group.long 0x404++0xF line.long 0x0 "SERDES_CTRL,Sets the SERDES control state." bitfld.long 0x0 31. "POR_EN,The POR_EN allows the system to place the SERDES in a reset state Access to the SERDES registers are ignored." "0,1" newline hexmask.long 0x0 0.--30. 1. "RESERVED" line.long 0x4 "SERDES_TOP_CTRL,The SERDES Top Level Control" bitfld.long 0x4 30.--31. "PMA_CMN_REFCLK_MODE,The PMA common differential reference clock mode - Sets the mode of operation for differential reference clock input." "0,1,2,3" newline bitfld.long 0x4 28.--29. "PMA_CMN_REFCLK_INT_MODE,The PMA common internal reference clock mode - Sets the mode of operation for internal reference clock input." "0,1,2,3" newline bitfld.long 0x4 26.--27. "PMA_CMN_REFCLK_DIG_DIV,The PMA common reference clock digital divide ratio select - Must be set before the de-assertion of apb_preset_n/phy_reset_n." "0,1,2,3" newline bitfld.long 0x4 24.--25. "RESERVED" "0,1,2,3" newline bitfld.long 0x4 23. "PHY_PMA_SUSPEND_OVERRIDE,The PHY PMA common suspend override enable:" "0,1" newline hexmask.long.tbyte 0x4 0.--22. 1. "RESERVED" line.long 0x8 "SERDES_RST,The SERDES Reset Register controls the Phy reset and REFCLK selection for the SERDES." bitfld.long 0x8 31. "PHY_RESET_N,The PHY reset : Asserting this signal low will reset all PHY logic for the entire PHY with the exception of the APB registers and TAP controller." "0,1" newline bitfld.long 0x8 30. "PHY_EN_REFCLK,The PHY reference clock enable: When cmn_refclk_&lt;p/m&gt; is configured as a reference clock output " "0,1" newline bitfld.long 0x8 29. "PLL1_REFCLK_SEL,The PMA common PLL1 reference clock source select -" "0,1" newline bitfld.long 0x8 28. "PLL0_REFCLK_SEL,The PMA common PLL0 reference clock source select -" "0,1" newline bitfld.long 0x8 27. "REFCLK_TERM_DIS,The PMA common differential reference clock termination disable - enables/disables termination for difference reference clock input (cmn_refclk_&lt;p/m&gt;)." "0,1" newline bitfld.long 0x8 25.--26. "RESERVED" "0,1,2,3" newline bitfld.long 0x8 24. "REFCLK_DIG_SEL,The PMA common reference clock select - Selects the reference clock source for the digital logic between cmn_refclk_&lt;p/m&gt; and pma_cmn_refclk_int." "0,1" newline hexmask.long.tbyte 0x8 0.--23. 1. "RESERVED" line.long 0xC "SERDES_TYPEC,The SERDES Type C control register allows the external lanes selection to be swapped." bitfld.long 0xC 31. "LN23_SWAP,LN23_SWAP will swap lanes 2 and 3. That is all control for lane 2 will apply to lane 3 and vice versa. Forbidden to swap lanes in a link. That is if lanes 2 and 3 are used for a single link of PCIe the LN23_SWAP must be 0. Note: This field.." "0,1" newline bitfld.long 0xC 30. "LN10_SWAP,LN10_SWAP will swap lanes 0 and 1. That is all control for lane 0 will apply to lane 1 and vice versa. Forbidden to swap lanes in a link. That is if lanes 0 and 1 are used for a single link of PCIe the LN10_SWAP must be 0. Note: This field.." "0,1" newline hexmask.long 0xC 0.--29. 1. "RESERVED" group.long 0x440++0xF line.long 0x0 "SERDES_IRQSTATUS_RAW_SYS,Return to the . The System Interrupt Raw Status Register holds the raw status of the SERDES power timout interrupts." hexmask.long 0x0 4.--31. 1. "RESERVED" newline bitfld.long 0x0 3. "P3_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 3 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x0 2. "P2_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 2 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x0 1. "P1_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 1 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x0 0. "P0_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 0 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" line.long 0x4 "SERDES_IRQSTATUS_SYS,Return to the . The System Interrupt Status Register holds the masked status for the SERDES power timout interrupts." hexmask.long 0x4 4.--31. 1. "RESERVED" newline bitfld.long 0x4 3. "P3_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 3 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x4 2. "P2_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 2 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x4 1. "P1_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 1 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" newline bitfld.long 0x4 0. "P0_PHY_PWR_TIMEOUT_SYS,Phy Power Timeout occured for lane 0 error. That is the lane power state took too long to occur.. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no.." "0,1" line.long 0x8 "SERDES_IRQENABLE_SET_SYS,Return to the . The System Interrupt Enable Set Register holds the interrupt enable status of the SERDES power timout interrupts." hexmask.long 0x8 4.--31. 1. "RESERVED" newline bitfld.long 0x8 3. "EN_P3_PHY_PWR_TIMEOUT_SYS,Interrupt Enable set for Phy Power Timeout for lane 3 error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "EN_P2_PHY_PWR_TIMEOUT_SYS,Interrupt Enable set for Phy Power Timeout for lane 2 error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "EN_P1_PHY_PWR_TIMEOUT_SYS,Interrupt Enable set for Phy Power Timeout for lane 1 error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "EN_P0_PHY_PWR_TIMEOUT_SYS,Interrupt Enable set for Phy Power Timeout for lane 0 error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" line.long 0xC "SERDES_IRQENABLE_CLR_SYS,Return to the . The System Interrupt Enable Clear Register holds the interrupt enable status of the SERDES power timout interrupts." hexmask.long 0xC 4.--31. 1. "RESERVED" newline bitfld.long 0xC 3. "EN_P3_PHY_PWR_TIMEOUT_SYS,Interrupt Enable clear for Phy Power Timeout for lane 3 error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "EN_P2_PHY_PWR_TIMEOUT_SYS,Interrupt Enable clear for Phy Power Timeout for lane 2 error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "EN_P1_PHY_PWR_TIMEOUT_SYS,Interrupt Enable clear for Phy Power Timeout for lane 1 error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "EN_P0_PHY_PWR_TIMEOUT_SYS,Interrupt Enable clear for Phy Power Timeout for lane 0 error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" group.long 0x480++0x7 line.long 0x0 "LANECTL0,The Lane Control Register sets the lane specific modes of operation." bitfld.long 0x0 31. "P0_ENABLE,The p0_enable is AND'd with the IPx_LNy_reset_n to enable the lane." "0,1" newline bitfld.long 0x0 30. "P0_FORCE_ENABLE,The p0_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane." "0,1" newline bitfld.long 0x0 29. "P0_ALIGN,The p0_align will auto align the RAW interface to 8B10B comma characters." "0,1" newline bitfld.long 0x0 28. "P0_RAW_AUTO_START,The p0_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1" newline bitfld.long 0x0 26.--27. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 24.--25. "P0_STANDARD_MODE,Standard Mode" "0,1,2,3" newline bitfld.long 0x0 22.--23. "P0_FULLRT_DIV,Full Rate divider for 2x MAC speed mode." "0,1,2,3" newline bitfld.long 0x0 20.--21. "P0_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*." "0,1,2,3" newline bitfld.long 0x0 18.--19. "P0_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal." "0,1,2,3" newline hexmask.long.byte 0x0 10.--17. 1. "RESERVED" newline bitfld.long 0x0 8.--9. "P0_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal." "0,1,2,3" newline bitfld.long 0x0 6.--7. "P0_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" line.long 0x4 "LANEDIV0,The Lane Divider Register sets the lane specific dividers of" hexmask.long.word 0x4 23.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 16.--22. 1. "P0_MAC_DIV_SEL0,The reg_p0_mac_div_sel0 controls the divider for lane 0 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" newline hexmask.long.word 0x4 0.--8. 1. "P0_MAC_DIV_SEL1,The reg_p0_mac_div_sel1 controls the divider for lane 0 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*." rgroup.long 0x488++0x7 line.long 0x0 "LANALIGN0,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode." hexmask.long 0x0 6.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--5. 1. "P0_ALIGN_RX_DELAY,The reg_p0_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment." line.long 0x4 "LANESTS0,The lane Status reports the lane state information for debug purposes." hexmask.long 0x4 2.--31. 1. "RESERVED" newline bitfld.long 0x4 1. "P0_MASTER,The reg_p0_master indicates the lane is a base lane for a multi lane link." "0,1" newline bitfld.long 0x4 0. "RESERVED" "0,1" group.long 0x4C0++0x7 line.long 0x0 "LANECTL1,The Lane Control Register sets the lane specific modes of operation." bitfld.long 0x0 31. "P1_ENABLE,The p1_enable is AND'd with the IPx_LNy_reset_n to enable the lane." "0,1" newline bitfld.long 0x0 30. "P1_FORCE_ENABLE,The p1_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane." "0,1" newline bitfld.long 0x0 29. "P1_ALIGN,The p1_align will auto align the RAW interface to 8B10B comma characters." "0,1" newline bitfld.long 0x0 28. "P1_RAW_AUTO_START,The p1_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1" newline bitfld.long 0x0 26.--27. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 24.--25. "P1_STANDARD_MODE,Standard Mode" "0,1,2,3" newline bitfld.long 0x0 22.--23. "P1_FULLRT_DIV,Full Rate divider for 2x MAC speed mode." "0,1,2,3" newline bitfld.long 0x0 20.--21. "P1_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*." "0,1,2,3" newline bitfld.long 0x0 18.--19. "P1_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal." "0,1,2,3" newline hexmask.long.byte 0x0 10.--17. 1. "RESERVED" newline bitfld.long 0x0 8.--9. "P1_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal." "0,1,2,3" newline bitfld.long 0x0 6.--7. "P1_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" line.long 0x4 "LANEDIV1,The Lane Divider Register sets the lane specific dividers of" hexmask.long.word 0x4 23.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 16.--22. 1. "P1_MAC_DIV_SEL0,The reg_p1_mac_div_sel0 controls the divider for lane 1 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" newline hexmask.long.word 0x4 0.--8. 1. "P1_MAC_DIV_SEL1,The reg_p1_mac_div_sel1 controls the divider for lane 1 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*." rgroup.long 0x4C8++0x7 line.long 0x0 "LANALIGN1,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode." hexmask.long 0x0 6.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--5. 1. "P1_ALIGN_RX_DELAY,The reg_p1_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment." line.long 0x4 "LANESTS1,The lane Status reports the lane state information for debug purposes." hexmask.long 0x4 2.--31. 1. "RESERVED" newline bitfld.long 0x4 1. "P1_MASTER,The reg_p1_master indicates the lane is a base lane for a multi lane link." "0,1" newline bitfld.long 0x4 0. "RESERVED" "0,1" group.long 0x500++0x7 line.long 0x0 "LANECTL2,The Lane Control Register sets the lane specific modes of operation." bitfld.long 0x0 31. "P2_ENABLE,The p2_enable is AND'd with the IPx_LNy_reset_n to enable the lane." "0,1" newline bitfld.long 0x0 30. "P2_FORCE_ENABLE,The p2_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane." "0,1" newline bitfld.long 0x0 29. "P2_ALIGN,The p2_align will auto align the RAW interface to 8B10B comma characters." "0,1" newline bitfld.long 0x0 28. "P2_RAW_AUTO_START,The p2_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1" newline bitfld.long 0x0 26.--27. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 24.--25. "P2_STANDARD_MODE,Standard Mode" "0,1,2,3" newline bitfld.long 0x0 22.--23. "P2_FULLRT_DIV,Full Rate divider for 2x MAC speed mode." "0,1,2,3" newline bitfld.long 0x0 20.--21. "P2_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*." "0,1,2,3" newline bitfld.long 0x0 18.--19. "P2_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal." "0,1,2,3" newline hexmask.long.byte 0x0 10.--17. 1. "RESERVED" newline bitfld.long 0x0 8.--9. "P2_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal." "0,1,2,3" newline bitfld.long 0x0 6.--7. "P2_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" line.long 0x4 "LANEDIV2,The Lane Divider Register sets the lane specific dividers of" hexmask.long.word 0x4 23.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 16.--22. 1. "P2_MAC_DIV_SEL0,The reg_p2_mac_div_sel0 controls the divider for lane 2 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" newline hexmask.long.word 0x4 0.--8. 1. "P2_MAC_DIV_SEL1,The reg_p2_mac_div_sel1 controls the divider for lane 2 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*." rgroup.long 0x508++0x7 line.long 0x0 "LANALIGN2,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode." hexmask.long 0x0 6.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--5. 1. "P2_ALIGN_RX_DELAY,The reg_p2_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment." line.long 0x4 "LANESTS2,The lane Status reports the lane state information for debug purposes." hexmask.long 0x4 2.--31. 1. "RESERVED" newline bitfld.long 0x4 1. "P2_MASTER,The reg_p2_master indicates the lane is a base lane for a multi lane link." "0,1" newline bitfld.long 0x4 0. "RESERVED" "0,1" group.long 0x540++0x7 line.long 0x0 "LANECTL3,The Lane Control Register sets the lane specific modes of operation." bitfld.long 0x0 31. "P3_ENABLE,The p3_enable is AND'd with the IPx_LNy_reset_n to enable the lane." "0,1" newline bitfld.long 0x0 30. "P3_FORCE_ENABLE,The p3_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane." "0,1" newline bitfld.long 0x0 29. "P3_ALIGN,The p3_align will auto align the RAW interface to 8B10B comma characters." "0,1" newline bitfld.long 0x0 28. "P3_RAW_AUTO_START,The p3_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1" newline bitfld.long 0x0 26.--27. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 24.--25. "P3_STANDARD_MODE,Standard Mode" "0,1,2,3" newline bitfld.long 0x0 22.--23. "P3_FULLRT_DIV,Full Rate divider for 2x MAC speed mode." "0,1,2,3" newline bitfld.long 0x0 20.--21. "P3_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*." "0,1,2,3" newline bitfld.long 0x0 18.--19. "P3_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal." "0,1,2,3" newline hexmask.long.byte 0x0 10.--17. 1. "RESERVED" newline bitfld.long 0x0 8.--9. "P3_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal." "0,1,2,3" newline bitfld.long 0x0 6.--7. "P3_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" line.long 0x4 "LANEDIV3,The Lane Divider Register sets the lane specific dividers of" hexmask.long.word 0x4 23.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 16.--22. 1. "P3_MAC_DIV_SEL0,The reg_p3_mac_div_sel0 controls the divider for lane 3 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*." newline hexmask.long.byte 0x4 9.--15. 1. "RESERVED" newline hexmask.long.word 0x4 0.--8. 1. "P3_MAC_DIV_SEL1,The reg_p3_mac_div_sel1 controls the divider for lane 3 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*." rgroup.long 0x548++0x7 line.long 0x0 "LANALIGN3,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode." hexmask.long 0x0 6.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--5. 1. "P3_ALIGN_RX_DELAY,The reg_p3_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment." line.long 0x4 "LANESTS3,The lane Status reports the lane state information for debug purposes." hexmask.long 0x4 2.--31. 1. "RESERVED" newline bitfld.long 0x4 1. "P3_MASTER,The reg_p3_master indicates the lane is a base lane for a multi lane link." "0,1" newline bitfld.long 0x4 0. "RESERVED" "0,1" group.long 0x5F8++0x7 line.long 0x0 "DTB_MUX_SEL,The digital test bus mux select determines the value on the test bus." hexmask.long 0x0 5.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--4. 1. "DTB_MUX_SEL" line.long 0x4 "DIAG_TEST,The Diagnostic Test Register allows the system to validate the read and write of all data bits." hexmask.long 0x4 0.--31. 1. "DIAG_REG,Diagnostic register." group.long 0x4000++0x27 line.long 0x0 "XCVR_PSM_RCTRL__XCVR_PSM_CTRL_j,Power state machine control register Offset = 4000h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "XCVR_PSM_RCTRL_15,RX reset active ready : Controls the state the receiver reset is changed to when in the ready power state." "0,1" newline bitfld.long 0x0 30. "XCVR_PSM_RCTRL_14,RX reset active calibration : Controls the state the receiver reset is changed to when in the calibration power state." "0,1" newline bitfld.long 0x0 29. "XCVR_PSM_RCTRL_13,RX reset active A5 : Controls the state the receiver reset is changed to when in the A5 entry power state." "0,1" newline bitfld.long 0x0 28. "XCVR_PSM_RCTRL_12,RX reset active A4 : Controls the state the receiver reset is changed to when in the A4 entry power state." "0,1" newline bitfld.long 0x0 27. "XCVR_PSM_RCTRL_11,RX reset active A3 : Controls the state the receiver reset is changed to when in the A3 entry power state." "0,1" newline bitfld.long 0x0 26. "XCVR_PSM_RCTRL_10,RX reset active A2 : Controls the state the receiver reset is changed to when in the A2 entry power state." "0,1" newline bitfld.long 0x0 25. "XCVR_PSM_RCTRL_9,RX reset active A1 : Controls the state the receiver reset is changed to when in the A1 entry power state." "0,1" newline bitfld.long 0x0 24. "XCVR_PSM_RCTRL_8,RX reset active A0 : Controls the state the receiver reset is changed to when in the A0 entry power state." "0,1" newline bitfld.long 0x0 23. "XCVR_PSM_RCTRL_7,TX reset active ready : Controls the state the transmitter reset is changed to when in the ready power state." "0,1" newline bitfld.long 0x0 22. "XCVR_PSM_RCTRL_6,TX reset active calibration : Controls the state the transmitter reset is changed to when in the calibration power state." "0,1" newline bitfld.long 0x0 21. "XCVR_PSM_RCTRL_5,TX reset active A5 : Controls the state the transmitter reset is changed to when in the A5 entry power state." "0,1" newline bitfld.long 0x0 20. "XCVR_PSM_RCTRL_4,TX reset active A4 : Controls the state the transmitter reset is changed to when in the A4 entry power state." "0,1" newline bitfld.long 0x0 19. "XCVR_PSM_RCTRL_3,TX reset active A3 : Controls the state the transmitter reset is changed to when in the A3 entry power state." "0,1" newline bitfld.long 0x0 18. "XCVR_PSM_RCTRL_2,TX reset active A2 : Controls the state the transmitter reset is changed to when in the A2 entry power state." "0,1" newline bitfld.long 0x0 17. "XCVR_PSM_RCTRL_1,TX reset active A1 : Controls the state the transmitter reset is changed to when in the A1 entry power state." "0,1" newline bitfld.long 0x0 16. "XCVR_PSM_RCTRL_0,TX reset active A0 : Controls the state the transmitter reset is changed to when in the A0 entry power state." "0,1" newline rbitfld.long 0x0 15. "XCVR_PSM_CTRL_15,Reserved" "0,1" newline bitfld.long 0x0 14. "XCVR_PSM_CTRL_14,Bypass A0 in delay from PSM ready : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the PSM ready state to the A0 power state." "0,1" newline bitfld.long 0x0 13. "XCVR_PSM_CTRL_13,Bypass A0 in delay from A5 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A5 to the A0 power state." "0,1" newline bitfld.long 0x0 12. "XCVR_PSM_CTRL_12,Bypass A0 in delay from A4 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A4 to the A0 power state." "0,1" newline bitfld.long 0x0 11. "XCVR_PSM_CTRL_11,Bypass A0 in delay from A3 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A3 to the A0 power state." "0,1" newline bitfld.long 0x0 10. "XCVR_PSM_CTRL_10,Bypass A0 in delay from A2 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A2 to the A0 power state." "0,1" newline bitfld.long 0x0 9. "XCVR_PSM_CTRL_9,Bypass A0 in delay from A1 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A1 to the A0 power state." "0,1" newline rbitfld.long 0x0 8. "XCVR_PSM_CTRL_8,Reserved" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "XCVR_PSM_CTRL_7_1,Reserved" newline bitfld.long 0x0 0. "XCVR_PSM_CTRL_0,Reserved - spare (must remain set to 1'b1)." "0,1" line.long 0x4 "XCVR_PSM_A0IN_TMR__XCVR_PSM_CALIN_TMR_j,PSM calibration in delay timer register Offset = 4004h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 28.--31. 1. "XCVR_PSM_A0IN_TMR_15_12,Reserved" newline hexmask.long.word 0x4 16.--27. 1. "XCVR_PSM_A0IN_TMR_11_0,A0 in delay state timer value : Value used for the timer when the power state machine is in the A0 in delay state unless the timer is bypassed under the control of the bypass A0 bits in the Power state machine control register." newline hexmask.long.byte 0x4 12.--15. 1. "XCVR_PSM_CALIN_TMR_15_12,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "XCVR_PSM_CALIN_TMR_11_0,PSM calibration in delay state timer value : Value used for the timer when the power state machine is in the PSM calibration in delay state." line.long 0x8 "XCVR_PSM_A1IN_TMR__XCVR_PSM_A0BYP_TMR_j,A0 in bypass timer register Offset = 4008h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 22.--31. 1. "XCVR_PSM_A1IN_TMR_15_6,Reserved" newline hexmask.long.byte 0x8 16.--21. 1. "XCVR_PSM_A1IN_TMR_5_0,A1 in delay state timer value : Value used for the timer when the power state machine is in the A1 in delay state." newline hexmask.long.word 0x8 6.--15. 1. "XCVR_PSM_A0BYP_TMR_15_6,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "XCVR_PSM_A0BYP_TMR_5_0,A0 in delay state bypass timer value : Value used for the timer when the power state machine is in the A0 in delay state and the timer is bypassed under the control of the bypass A0 bits in the Power state machine control register." line.long 0xC "XCVR_PSM_A3IN_TMR__XCVR_PSM_A2IN_TMR_j,A2 in delay timer register Offset = 400Ch + (j * 400h); where j = 0h to 3h" hexmask.long.word 0xC 22.--31. 1. "XCVR_PSM_A3IN_TMR_15_6,Reserved" newline hexmask.long.byte 0xC 16.--21. 1. "XCVR_PSM_A3IN_TMR_5_0,A3 in delay state timer value : Value used for the timer when the power state machine is in the A3 in delay state." newline hexmask.long.word 0xC 6.--15. 1. "XCVR_PSM_A2IN_TMR_15_6,Reserved" newline hexmask.long.byte 0xC 0.--5. 1. "XCVR_PSM_A2IN_TMR_5_0,A2 in delay state timer value : Value used for the timer when the power state machine is in the A2 in delay state." line.long 0x10 "XCVR_PSM_A5IN_TMR__XCVR_PSM_A4IN_TMR_j,A4 in delay timer register Offset = 4010h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x10 22.--31. 1. "XCVR_PSM_A5IN_TMR_15_6,Reserved" newline hexmask.long.byte 0x10 16.--21. 1. "XCVR_PSM_A5IN_TMR_5_0,A5 in delay state timer value : Value used for the timer when the power state machine is in the A5 in delay state." newline hexmask.long.word 0x10 6.--15. 1. "XCVR_PSM_A4IN_TMR_15_6,Reserved" newline hexmask.long.byte 0x10 0.--5. 1. "XCVR_PSM_A4IN_TMR_5_0,A4 in delay state timer value : Value used for the timer when the power state machine is in the A4 in delay state." line.long 0x14 "XCVR_PSM_A0OUT_TMR__XCVR_PSM_CALOUT_TMR_j,PSM calibration out delay timer register Offset = 4014h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x14 22.--31. 1. "XCVR_PSM_A0OUT_TMR_15_6,Reserved" newline hexmask.long.byte 0x14 16.--21. 1. "XCVR_PSM_A0OUT_TMR_5_0,A0 out delay state timer value : Value used for the timer when the power state machine is in the A0 out delay state." newline hexmask.long.word 0x14 6.--15. 1. "XCVR_PSM_CALOUT_TMR_15_6,Reserved" newline hexmask.long.byte 0x14 0.--5. 1. "XCVR_PSM_CALOUT_TMR_5_0,PSM calibration out delay state timer value : Value used for the timer when the power state machine is in the PSM calibration out delay state." line.long 0x18 "XCVR_PSM_A2OUT_TMR__XCVR_PSM_A1OUT_TMR_j,A1 out delay timer register Offset = 4018h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x18 22.--31. 1. "XCVR_PSM_A2OUT_TMR_15_6,Reserved" newline hexmask.long.byte 0x18 16.--21. 1. "XCVR_PSM_A2OUT_TMR_5_0,A2 out delay state timer value : Value used for the timer when the power state machine is in the A2 out delay state." newline hexmask.long.word 0x18 6.--15. 1. "XCVR_PSM_A1OUT_TMR_15_6,Reserved" newline hexmask.long.byte 0x18 0.--5. 1. "XCVR_PSM_A1OUT_TMR_5_0,A1 out delay state timer value : Value used for the timer when the power state machine is in the A1 out delay state." line.long 0x1C "XCVR_PSM_A4OUT_TMR__XCVR_PSM_A3OUT_TMR_j,A3 out delay timer register Offset = 401Ch + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x1C 22.--31. 1. "XCVR_PSM_A4OUT_TMR_15_6,Reserved" newline hexmask.long.byte 0x1C 16.--21. 1. "XCVR_PSM_A4OUT_TMR_5_0,A4 out delay state timer value : Value used for the timer when the power state machine is in the A4 out delay state." newline hexmask.long.word 0x1C 6.--15. 1. "XCVR_PSM_A3OUT_TMR_15_6,Reserved" newline hexmask.long.byte 0x1C 0.--5. 1. "XCVR_PSM_A3OUT_TMR_5_0,A3 out delay state timer value : Value used for the timer when the power state machine is in the A3 out delay state." line.long 0x20 "XCVR_PSM_RDY_TMR__XCVR_PSM_A5OUT_TMR_j,A5 out delay timer register Offset = 4020h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x20 22.--31. 1. "XCVR_PSM_RDY_TMR_15_6,Reserved" newline hexmask.long.byte 0x20 16.--21. 1. "XCVR_PSM_RDY_TMR_5_0,Ready delay state timer value : Value used for the timer when the power state machine is in the ready state." newline hexmask.long.word 0x20 6.--15. 1. "XCVR_PSM_A5OUT_TMR_15_6,Reserved" newline hexmask.long.byte 0x20 0.--5. 1. "XCVR_PSM_A5OUT_TMR_5_0,A5 out delay state timer value : Value used for the timer when the power state machine is in the A5 out delay state." line.long 0x24 "XCVR_PSM_ST_0__XCVR_PSM_DIAG_j,Power state machine diagnostic register Offset = 4024h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x24 16.--31. 1. "XCVR_PSM_ST_0_15_0,PSM current state [15:0] : Indicates bits 15:0 of the current state of the power state machine." newline rbitfld.long 0x24 15. "XCVR_PSM_DIAG_15,Reserved" "0,1" newline bitfld.long 0x24 14. "XCVR_PSM_DIAG_14,Force calibration exit acknowledge : Setting this bit to 1'b1 forces the psm_cal_exit_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 13. "XCVR_PSM_DIAG_13,Force A5 exit acknowledge : Setting this bit to 1'b1 forces the psm_a5_exit_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 12. "XCVR_PSM_DIAG_12,Force A4 exit acknowledge : Setting this bit to 1'b1 forces the psm_a4_exit_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 11. "XCVR_PSM_DIAG_11,Force A3 exit acknowledge : Setting this bit to 1'b1 forces the psm_a3_exit_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 10. "XCVR_PSM_DIAG_10,Force A2 exit acknowledge : Setting this bit to 1'b1 forces the psm_a2_exit_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 9. "XCVR_PSM_DIAG_9,Force A1 exit acknowledge : Setting this bit to 1'b1 forces the psm_a1_exit_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 8. "XCVR_PSM_DIAG_8,Force A0 exit acknowledge : Setting this bit to 1'b1 forces the psm_a0_exit_ack pin of the power state machine active." "0,1" newline rbitfld.long 0x24 7. "XCVR_PSM_DIAG_7,Reserved" "0,1" newline bitfld.long 0x24 6. "XCVR_PSM_DIAG_6,Force calibration entry acknowledge : Setting this bit to 1'b1 forces the psm_cal_entry_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 5. "XCVR_PSM_DIAG_5,Force A5 entry acknowledge : Setting this bit to 1'b1 forces the psm_a5_entry_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 4. "XCVR_PSM_DIAG_4,Force A4 entry acknowledge : Setting this bit to 1'b1 forces the psm_a4_entry_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 3. "XCVR_PSM_DIAG_3,Force A3 entry acknowledge : Setting this bit to 1'b1 forces the psm_a3_entry_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 2. "XCVR_PSM_DIAG_2,Force A2 entry acknowledge : Setting this bit to 1'b1 forces the psm_a2_entry_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 1. "XCVR_PSM_DIAG_1,Force A1 entry acknowledge : Setting this bit to 1'b1 forces the psm_a1_entry_ack pin of the power state machine active." "0,1" newline bitfld.long 0x24 0. "XCVR_PSM_DIAG_0,Force A0 entry acknowledge : Setting this bit to 1'b1 forces the psm_a0_entry_ack pin of the power state machine active." "0,1" rgroup.long 0x4028++0x3 line.long 0x0 "XCVR_PSM_ST_1_j,PSM current state register 1 Offset = 4028h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 10.--15. 1. "XCVR_PSM_ST_1_15_10,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "XCVR_PSM_ST_1_9_0,PSM current state [25:16] : Indicates bits 25:16 of the current state of the power state machine." group.long 0x403C++0x3 line.long 0x0 "XCVR_PSM_USER_DEF_CTRL_j,Power state machine user defined control register Offset = 403Ch + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 21.--31. 1. "XCVR_PSM_USER_DEF_CTRL_15_5,Reserved - spare" newline bitfld.long 0x0 20. "XCVR_PSM_USER_DEF_CTRL_4,Force PSM gated clock on: Setting this bit to 1'b1 will force the PSM gated clock on independent of the internal PSM state machine clock gate controls." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "XCVR_PSM_USER_DEF_CTRL_3_0,Reserved - spare" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED" group.long 0x4080++0x7 line.long 0x0 "TX_TXCC_PRE_OVRD__TX_TXCC_CTRL_j,TX coefficient controller control register Offset = 4080h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x0 25.--31. 1. "TX_TXCC_PRE_OVRD_15_9,Reserved" newline bitfld.long 0x0 24. "TX_TXCC_PRE_OVRD_8,Pre-cursor override enable: When enabled the pre-cursor field in this register is used to override the pre-cursor value." "0,1" newline rbitfld.long 0x0 22.--23. "TX_TXCC_PRE_OVRD_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "TX_TXCC_PRE_OVRD_5_0,Pre-cursor override value: When enabled by the pre-cursor override enable bit in this register the value in this field is used to override the pre-cursor value." newline rbitfld.long 0x0 14.--15. "TX_TXCC_CTRL_15_14,Reserved" "0,1,2,3" newline bitfld.long 0x0 12.--13. "TX_TXCC_CTRL_13_12,Margin multiplier rounding control: This field controls the rounding function on the margin multiplier." "0,1,2,3" newline bitfld.long 0x0 10.--11. "TX_TXCC_CTRL_11_10,LF value multiplier rounding control: This field controls the rounding function on the LF value multiplier." "0,1,2,3" newline bitfld.long 0x0 8.--9. "TX_TXCC_CTRL_9_8,Calculated post-emphasis multiplier rounding control: This field controls the rounding function on the calculated post-emphasis multiplier." "0,1,2,3" newline bitfld.long 0x0 6.--7. "TX_TXCC_CTRL_7_6,Calculated pre-emphasis multiplier rounding control: This field controls the rounding function on the pre-emphasis multiplier." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_TXCC_CTRL_5_4,Coefficient calculator multiplier rounding control: This field controls the rounding function on the coefficient calculator multiplier." "0,1,2,3" newline bitfld.long 0x0 3. "TX_TXCC_CTRL_3,De-emphasis control standard mode 3 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x0 2. "TX_TXCC_CTRL_2,De-emphasis control standard mode 2 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b10." "0,1" newline bitfld.long 0x0 1. "TX_TXCC_CTRL_1,De-emphasis control standard mode 1 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b01." "0,1" newline bitfld.long 0x0 0. "TX_TXCC_CTRL_0,De-emphasis control standard mode 0 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b00." "0,1" line.long 0x4 "TX_TXCC_POST_OVRD__TX_TXCC_MAIN_OVRD_j,TX main-cursor override register Offset = 4084h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 25.--31. 1. "TX_TXCC_POST_OVRD_15_9,Reserved" newline bitfld.long 0x4 24. "TX_TXCC_POST_OVRD_8,Post-cursor override enable: When enabled the post-cursor field in this register is used to override the post-cursor value." "0,1" newline rbitfld.long 0x4 22.--23. "TX_TXCC_POST_OVRD_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "TX_TXCC_POST_OVRD_5_0,Post-cursor override value: When enabled by the post-cursor override enable bit in this register the value in this field is used to override the post-cursor value." newline hexmask.long.byte 0x4 9.--15. 1. "TX_TXCC_MAIN_OVRD_15_9,Reserved" newline bitfld.long 0x4 8. "TX_TXCC_MAIN_OVRD_8,Main-cursor override enable: When enabled the main-cursor field in this register is used to override the main-cursor value." "0,1" newline rbitfld.long 0x4 6.--7. "TX_TXCC_MAIN_OVRD_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_TXCC_MAIN_OVRD_5_0,Main-cursor override value: When enabled by the main-cursor override enable bit in this register the value in this field is used to override the main-cursor value." rgroup.long 0x4088++0x3 line.long 0x0 "TX_TXCC_MAIN_CVAL__TX_TXCC_PRE_CVAL_j,TX pre-cursor current value register Offset = 4088h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 22.--31. 1. "TX_TXCC_MAIN_CVAL_15_6,Reserved" newline hexmask.long.byte 0x0 16.--21. 1. "TX_TXCC_MAIN_CVAL_5_0,Main-cursor value: The value in this field indicates the current value of the main-cursor (C0) coefficient." newline hexmask.long.word 0x0 6.--15. 1. "TX_TXCC_PRE_CVAL_15_6,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "TX_TXCC_PRE_CVAL_5_0,Pre-cursor value: The value in this field indicates the current value of the pre-cursor (C-1) coefficient." group.long 0x408C++0x47 line.long 0x0 "TX_TXCC_LF_MULT__TX_TXCC_POST_CVAL_j,TX post-cursor current value register Offset = 408Ch + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x0 24.--31. 1. "TX_TXCC_LF_MULT_15_8,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "TX_TXCC_LF_MULT_7_0,LF multiplier value: The value in this field specifies the multiplier value used to generate the LF value from the FS value." newline hexmask.long.word 0x0 6.--15. 1. "TX_TXCC_POST_CVAL_15_6,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "TX_TXCC_POST_CVAL_5_0,Post-cursor value: The value in this field indicates the current value of the post-cursor (C+1) coefficient." line.long 0x4 "TX_TXCC_CPRE_MULT_01__TX_TXCC_CPRE_MULT_00_j,Calculated pre emphasis multiplier value 00 register Offset = 4090h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 24.--31. 1. "TX_TXCC_CPRE_MULT_01_15_8,Reserved" newline hexmask.long.byte 0x4 16.--23. 1. "TX_TXCC_CPRE_MULT_01_7_0,Calculated pre emphasis multiplier value 01: The value in this field specifies the multiplier value used to generate the calculated pre emphasis value from the FS value when tx_deemphasis[1:0] = 2'b01." newline hexmask.long.byte 0x4 8.--15. 1. "TX_TXCC_CPRE_MULT_00_15_8,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "TX_TXCC_CPRE_MULT_00_7_0,Calculated pre emphasis multiplier value 00: The value in this field specifies the multiplier value used to generate the calculated pre emphasis value from the FS value when tx_deemphasis[1:0] = 2'b00." line.long 0x8 "TX_TXCC_CPRE_MULT_11__TX_TXCC_CPRE_MULT_10_j,Calculated pre emphasis multiplier value 10 register Offset = 4094h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 24.--31. 1. "TX_TXCC_CPRE_MULT_11_15_8,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "TX_TXCC_CPRE_MULT_11_7_0,Calculated pre emphasis multiplier value 11: The value in this field specifies the multiplier value used to generate the calculated pre emphasis value from the FS value when tx_deemphasis[1:0] = 2'b11." newline hexmask.long.byte 0x8 8.--15. 1. "TX_TXCC_CPRE_MULT_10_15_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "TX_TXCC_CPRE_MULT_10_7_0,Calculated pre emphasis multiplier value 10: The value in this field specifies the multiplier value used to generate the calculated pre emphasis value from the FS value when tx_deemphasis[1:0] = 2'b10." line.long 0xC "TX_TXCC_CPOST_MULT_01__TX_TXCC_CPOST_MULT_00_j,Calculated post emphasis multiplier value 00 register Offset = 4098h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0xC 24.--31. 1. "TX_TXCC_CPOST_MULT_01_15_8,Reserved" newline hexmask.long.byte 0xC 16.--23. 1. "TX_TXCC_CPOST_MULT_01_7_0,Calculated post emphasis multiplier value 01: The value in this field specifies the multiplier value used to generate the calculated post emphasis value from the FS value when tx_deemphasis [1:0] = 2'b01." newline hexmask.long.byte 0xC 8.--15. 1. "TX_TXCC_CPOST_MULT_00_15_8,Reserved" newline hexmask.long.byte 0xC 0.--7. 1. "TX_TXCC_CPOST_MULT_00_7_0,Calculated post emphasis multiplier value 00: The value in this field specifies the multiplier value used to generate the calculated post emphasis value from the FS value when tx_deemphasis [1:0] = 2'b00." line.long 0x10 "TX_TXCC_CPOST_MULT_11__TX_TXCC_CPOST_MULT_10_j,Calculated post emphasis multiplier value 10 register Offset = 409Ch + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x10 24.--31. 1. "TX_TXCC_CPOST_MULT_11_15_8,Reserved" newline hexmask.long.byte 0x10 16.--23. 1. "TX_TXCC_CPOST_MULT_11_7_0,Calculated post emphasis multiplier value 11: The value in this field specifies the multiplier value used to generate the calculated post emphasis value from the FS value when tx_deemphasis [1:0] = 2'b11." newline hexmask.long.byte 0x10 8.--15. 1. "TX_TXCC_CPOST_MULT_10_15_8,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "TX_TXCC_CPOST_MULT_10_7_0,Calculated post emphasis multiplier value 10: The value in this field specifies the multiplier value used to generate the calculated post emphasis value from the FS value when tx_deemphasis [1:0] = 2'b10." line.long 0x14 "TX_TXCC_MGNFS_MULT_001__TX_TXCC_MGNFS_MULT_000_j,Margin full swing multiplier value 000 register Offset = 40A0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x14 24.--31. 1. "TX_TXCC_MGNFS_MULT_001_15_8,Reserved" newline hexmask.long.byte 0x14 16.--23. 1. "TX_TXCC_MGNFS_MULT_001_7_0,Margin full swing multiplier value 001: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b001 and tx_low_power_swing_en = 1'b0." newline hexmask.long.byte 0x14 8.--15. 1. "TX_TXCC_MGNFS_MULT_000_15_8,Reserved" newline hexmask.long.byte 0x14 0.--7. 1. "TX_TXCC_MGNFS_MULT_000_7_0,Margin full swing multiplier value 000: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b000 and tx_low_power_swing_en = 1'b0." line.long 0x18 "TX_TXCC_MGNFS_MULT_011__TX_TXCC_MGNFS_MULT_010_j,Margin full swing multiplier value 010 register Offset = 40A4h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x18 24.--31. 1. "TX_TXCC_MGNFS_MULT_011_15_8,Reserved" newline hexmask.long.byte 0x18 16.--23. 1. "TX_TXCC_MGNFS_MULT_011_7_0,Margin full swing multiplier value 011: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b011 and tx_low_power_swing_en = 1'b0." newline hexmask.long.byte 0x18 8.--15. 1. "TX_TXCC_MGNFS_MULT_010_15_8,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "TX_TXCC_MGNFS_MULT_010_7_0,Margin full swing multiplier value 010: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b010 and tx_low_power_swing_en = 1'b0." line.long 0x1C "TX_TXCC_MGNFS_MULT_101__TX_TXCC_MGNFS_MULT_100_j,Margin full swing multiplier value 100 register Offset = 40A8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x1C 24.--31. 1. "TX_TXCC_MGNFS_MULT_101_15_8,Reserved" newline hexmask.long.byte 0x1C 16.--23. 1. "TX_TXCC_MGNFS_MULT_101_7_0,Margin full swing multiplier value 101: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b101 and tx_low_power_swing_en = 1'b0." newline hexmask.long.byte 0x1C 8.--15. 1. "TX_TXCC_MGNFS_MULT_100_15_8,Reserved" newline hexmask.long.byte 0x1C 0.--7. 1. "TX_TXCC_MGNFS_MULT_100_7_0,Margin full swing multiplier value 100: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b100 and tx_low_power_swing_en = 1'b0." line.long 0x20 "TX_TXCC_MGNFS_MULT_111__TX_TXCC_MGNFS_MULT_110_j,Margin full swing multiplier value 110 register Offset = 40ACh + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x20 24.--31. 1. "TX_TXCC_MGNFS_MULT_111_15_8,Reserved" newline hexmask.long.byte 0x20 16.--23. 1. "TX_TXCC_MGNFS_MULT_111_7_0,Margin full swing multiplier value 111: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b111 and tx_low_power_swing_en = 1'b0." newline hexmask.long.byte 0x20 8.--15. 1. "TX_TXCC_MGNFS_MULT_110_15_8,Reserved" newline hexmask.long.byte 0x20 0.--7. 1. "TX_TXCC_MGNFS_MULT_110_7_0,Margin full swing multiplier value 110: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b110 and tx_low_power_swing_en = 1'b0." line.long 0x24 "TX_TXCC_MGNHS_MULT_001__TX_TXCC_MGNHS_MULT_000_j,Margin half swing multiplier value 000 register Offset = 40B0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x24 24.--31. 1. "TX_TXCC_MGNHS_MULT_001_15_8,Reserved" newline hexmask.long.byte 0x24 16.--23. 1. "TX_TXCC_MGNHS_MULT_001_7_0,Margin half swing multiplier value 001: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b001 and tx_low_power_swing_en = 1'b1." newline hexmask.long.byte 0x24 8.--15. 1. "TX_TXCC_MGNHS_MULT_000_15_8,Reserved" newline hexmask.long.byte 0x24 0.--7. 1. "TX_TXCC_MGNHS_MULT_000_7_0,Margin half swing multiplier value 000: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b000 and tx_low_power_swing_en = 1'b1." line.long 0x28 "TX_TXCC_MGNHS_MULT_011__TX_TXCC_MGNHS_MULT_010_j,Margin half swing multiplier value 010 register Offset = 40B4h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x28 24.--31. 1. "TX_TXCC_MGNHS_MULT_011_15_8,Reserved" newline hexmask.long.byte 0x28 16.--23. 1. "TX_TXCC_MGNHS_MULT_011_7_0,Margin half swing multiplier value 011: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b011 and tx_low_power_swing_en = 1'b1." newline hexmask.long.byte 0x28 8.--15. 1. "TX_TXCC_MGNHS_MULT_010_15_8,Reserved" newline hexmask.long.byte 0x28 0.--7. 1. "TX_TXCC_MGNHS_MULT_010_7_0,Margin half swing multiplier value 010: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b010 and tx_low_power_swing_en = 1'b1." line.long 0x2C "TX_TXCC_MGNHS_MULT_101__TX_TXCC_MGNHS_MULT_100_j,Margin half swing multiplier value 100 register Offset = 40B8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x2C 24.--31. 1. "TX_TXCC_MGNHS_MULT_101_15_8,Reserved" newline hexmask.long.byte 0x2C 16.--23. 1. "TX_TXCC_MGNHS_MULT_101_7_0,Margin half swing multiplier value 101: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b101 and tx_low_power_swing_en = 1'b1." newline hexmask.long.byte 0x2C 8.--15. 1. "TX_TXCC_MGNHS_MULT_100_15_8,Reserved" newline hexmask.long.byte 0x2C 0.--7. 1. "TX_TXCC_MGNHS_MULT_100_7_0,Margin half swing multiplier value 100: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b100 and tx_low_power_swing_en = 1'b1." line.long 0x30 "TX_TXCC_MGNHS_MULT_111__TX_TXCC_MGNHS_MULT_110_j,Margin half swing multiplier value 110 register Offset = 40BCh + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x30 24.--31. 1. "TX_TXCC_MGNHS_MULT_111_15_8,Reserved" newline hexmask.long.byte 0x30 16.--23. 1. "TX_TXCC_MGNHS_MULT_111_7_0,Margin half swing multiplier value 111: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b111 and tx_low_power_swing_en = 1'b1." newline hexmask.long.byte 0x30 8.--15. 1. "TX_TXCC_MGNHS_MULT_110_15_8,Reserved" newline hexmask.long.byte 0x30 0.--7. 1. "TX_TXCC_MGNHS_MULT_110_7_0,Margin half swing multiplier value 110: The value in this field specifies the multiplier value used to generate the margin value from the resistor calibration value when tx_vmargin = 3'b110 and tx_low_power_swing_en = 1'b1." line.long 0x34 "TX_TXCC_P1PRE_COEF_MULT__TX_TXCC_P0PRE_COEF_MULT_j,Preset 0 pre emphasis coefficient multiplier value register Offset = 40C0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x34 24.--31. 1. "TX_TXCC_P1PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x34 16.--23. 1. "TX_TXCC_P1PRE_COEF_MULT_7_0,Preset 1 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 1 pre emphasis coefficient value from the FS value." newline hexmask.long.byte 0x34 8.--15. 1. "TX_TXCC_P0PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x34 0.--7. 1. "TX_TXCC_P0PRE_COEF_MULT_7_0,Preset 0 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 0 pre emphasis coefficient value from the FS value." line.long 0x38 "TX_TXCC_P3PRE_COEF_MULT__TX_TXCC_P2PRE_COEF_MULT_j,Preset 2 pre emphasis coefficient multiplier value register Offset = 40C4h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x38 24.--31. 1. "TX_TXCC_P3PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x38 16.--23. 1. "TX_TXCC_P3PRE_COEF_MULT_7_0,Preset 3 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 3 pre emphasis coefficient value from the FS value." newline hexmask.long.byte 0x38 8.--15. 1. "TX_TXCC_P2PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x38 0.--7. 1. "TX_TXCC_P2PRE_COEF_MULT_7_0,Preset 2 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 2 pre emphasis coefficient value from the FS value." line.long 0x3C "TX_TXCC_P5PRE_COEF_MULT__TX_TXCC_P4PRE_COEF_MULT_j,Preset 4 pre emphasis coefficient multiplier value register Offset = 40C8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x3C 24.--31. 1. "TX_TXCC_P5PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x3C 16.--23. 1. "TX_TXCC_P5PRE_COEF_MULT_7_0,Preset 5 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 5 pre emphasis coefficient value from the FS value." newline hexmask.long.byte 0x3C 8.--15. 1. "TX_TXCC_P4PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x3C 0.--7. 1. "TX_TXCC_P4PRE_COEF_MULT_7_0,Preset 4 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 4 pre emphasis coefficient value from the FS value." line.long 0x40 "TX_TXCC_P7PRE_COEF_MULT__TX_TXCC_P6PRE_COEF_MULT_j,Preset 6 pre emphasis coefficient multiplier value register Offset = 40CCh + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x40 24.--31. 1. "TX_TXCC_P7PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x40 16.--23. 1. "TX_TXCC_P7PRE_COEF_MULT_7_0,Preset 7 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 7 pre emphasis coefficient value from the FS value." newline hexmask.long.byte 0x40 8.--15. 1. "TX_TXCC_P6PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x40 0.--7. 1. "TX_TXCC_P6PRE_COEF_MULT_7_0,Preset 6 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 6 pre emphasis coefficient value from the FS value." line.long 0x44 "TX_TXCC_P9PRE_COEF_MULT__TX_TXCC_P8PRE_COEF_MULT_j,Preset 8 pre emphasis coefficient multiplier value register Offset = 40D0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x44 24.--31. 1. "TX_TXCC_P9PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x44 16.--23. 1. "TX_TXCC_P9PRE_COEF_MULT_7_0,Preset 9 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 9 pre emphasis coefficient value from the FS value." newline hexmask.long.byte 0x44 8.--15. 1. "TX_TXCC_P8PRE_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x44 0.--7. 1. "TX_TXCC_P8PRE_COEF_MULT_7_0,Preset 8 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 8 pre emphasis coefficient value from the FS value." group.long 0x40E0++0x13 line.long 0x0 "TX_TXCC_P1POST_COEF_MULT__TX_TXCC_P0POST_COEF_MULT_j,Preset 0 post emphasis coefficient multiplier value register Offset = 40E0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x0 24.--31. 1. "TX_TXCC_P1POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "TX_TXCC_P1POST_COEF_MULT_7_0,Preset 1 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 1 post emphasis coefficient value from the FS value." newline hexmask.long.byte 0x0 8.--15. 1. "TX_TXCC_P0POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "TX_TXCC_P0POST_COEF_MULT_7_0,Preset 0 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 0 post emphasis coefficient value from the FS value." line.long 0x4 "TX_TXCC_P3POST_COEF_MULT__TX_TXCC_P2POST_COEF_MULT_j,Preset 2 post emphasis coefficient multiplier value register Offset = 40E4h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 24.--31. 1. "TX_TXCC_P3POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x4 16.--23. 1. "TX_TXCC_P3POST_COEF_MULT_7_0,Preset 3 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 3 post emphasis coefficient value from the FS value." newline hexmask.long.byte 0x4 8.--15. 1. "TX_TXCC_P2POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "TX_TXCC_P2POST_COEF_MULT_7_0,Preset 2 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 2 post emphasis coefficient value from the FS value." line.long 0x8 "TX_TXCC_P5POST_COEF_MULT__TX_TXCC_P4POST_COEF_MULT_j,Preset 4 post emphasis coefficient multiplier value register Offset = 40E8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 24.--31. 1. "TX_TXCC_P5POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "TX_TXCC_P5POST_COEF_MULT_7_0,Preset 5 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 5 post emphasis coefficient value from the FS value." newline hexmask.long.byte 0x8 8.--15. 1. "TX_TXCC_P4POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "TX_TXCC_P4POST_COEF_MULT_7_0,Preset 4 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 4 post emphasis coefficient value from the FS value." line.long 0xC "TX_TXCC_P7POST_COEF_MULT__TX_TXCC_P6POST_COEF_MULT_j,Preset 6 post emphasis coefficient multiplier value register Offset = 40ECh + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0xC 24.--31. 1. "TX_TXCC_P7POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0xC 16.--23. 1. "TX_TXCC_P7POST_COEF_MULT_7_0,Preset 7 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 7 post emphasis coefficient value from the FS value." newline hexmask.long.byte 0xC 8.--15. 1. "TX_TXCC_P6POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0xC 0.--7. 1. "TX_TXCC_P6POST_COEF_MULT_7_0,Preset 6 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 6 post emphasis coefficient value from the FS value." line.long 0x10 "TX_TXCC_P9POST_COEF_MULT__TX_TXCC_P8POST_COEF_MULT_j,Preset 8 post emphasis coefficient multiplier value register Offset = 40F0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x10 24.--31. 1. "TX_TXCC_P9POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x10 16.--23. 1. "TX_TXCC_P9POST_COEF_MULT_7_0,Preset 9 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 9 post emphasis coefficient value from the FS value." newline hexmask.long.byte 0x10 8.--15. 1. "TX_TXCC_P8POST_COEF_MULT_15_8,Reserved" newline hexmask.long.byte 0x10 0.--7. 1. "TX_TXCC_P8POST_COEF_MULT_7_0,Preset 8 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 8 post emphasis coefficient value from the FS value." group.long 0x4180++0xF line.long 0x0 "DRV_DIAG_LANE_FCM_EN_SWAIT_TMR__DRV_DIAG_LANE_FCM_EN_TO_j,Lane fast common mode enable timeout register Offset = 4180h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 20.--31. 1. "DRV_DIAG_LANE_FCM_EN_SWAIT_TMR_15_4,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "DRV_DIAG_LANE_FCM_EN_SWAIT_TMR_3_0,Lane fast common mode enable sample wait timer value: This specifies the number of reference clock cycles the fast establishment of common mode process will wait between changing the state of the signals controlling the.." newline bitfld.long 0x0 15. "DRV_DIAG_LANE_FCM_EN_TO_15,Bypass fast establishment of common mode enable: When enabled the fast establishment of common mode function will be bypassed." "0,1" newline rbitfld.long 0x0 12.--14. "DRV_DIAG_LANE_FCM_EN_TO_14_12,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--11. 1. "DRV_DIAG_LANE_FCM_EN_TO_11_0,Lane fast common mode enable timeout value: The usage of the value of this field is a function of the state of the bypass fast establishment of common mode enable bit in this register." line.long 0x4 "DRV_DIAG_LANE_FCM_EN_TUNE__DRV_DIAG_LANE_FCM_EN_MGN_TMR_j,Lane fast common mode enable margin timer register Offset = 4184h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 28.--31. 1. "DRV_DIAG_LANE_FCM_EN_TUNE_15_12,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "DRV_DIAG_LANE_FCM_EN_TUNE_11_8,Common mode sense reference DAC voltage initial test: This field sets the common mode detect reference voltage for the common mode detect comparator when the fast establishment of common mode function is checking the.." newline hexmask.long.byte 0x4 20.--23. 1. "DRV_DIAG_LANE_FCM_EN_TUNE_7_4,Common mode sense reference DAC voltage high test: This field sets the common mode detect reference voltage for the common mode detect comparator when the fast establishment of common mode function is waiting for the.." newline hexmask.long.byte 0x4 16.--19. 1. "DRV_DIAG_LANE_FCM_EN_TUNE_3_0,Common mode sense reference DAC voltage low test: This field sets the common mode detect reference voltage for the common mode detect comparator when the fast establishment of common mode function is waiting for the.." newline hexmask.long.byte 0x4 12.--15. 1. "DRV_DIAG_LANE_FCM_EN_MGN_TMR_15_12,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "DRV_DIAG_LANE_FCM_EN_MGN_TMR_11_0,Lane fast common mode enable margin timer value: This specifies the number of reference clock cycles the fast establishment of common mode process will enable all the margin segments for." line.long 0x8 "DRV_DIAG_RCVDET_TUNE__DRV_DIAG_LFPS_CTRL_j,Transmitter LFPS control register Offset = 4188h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 21.--31. 1. "DRV_DIAG_RCVDET_TUNE_15_5,Reserved" newline bitfld.long 0x8 20. "DRV_DIAG_RCVDET_TUNE_4,Receiver detect comparators output and or control: This bit controls how the receiver detect comparators are used to drive the txda_rcvdet_detected_n signal to the digital." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "DRV_DIAG_RCVDET_TUNE_3_0,Receiver detect reference DAC voltage: This field sets the receiver detect reference voltage for the receiver detect comparator." newline hexmask.long.byte 0x8 8.--15. 1. "DRV_DIAG_LFPS_CTRL_15_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "DRV_DIAG_LFPS_CTRL_7_0,LFPS half period clocks: Specifies the number of clock cycles required to implement one half of a LFPS period by the transmitter LFPS controller." line.long 0xC "DRV_DIAG_TX_DRV_j,TX driver diagnostic register Offset = 418Ch + (j * 400h); where j = 0h to 3h" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 8.--15. 1. "DRV_DIAG_TX_DRV_15_8,Reserved" newline bitfld.long 0xC 7. "DRV_DIAG_TX_DRV_7,TX boost enable: Increases the transmitter amplitude for fast data transitions by controlling the txda_drv_boost_en signal going to the analog." "0,1" newline rbitfld.long 0xC 6. "DRV_DIAG_TX_DRV_6,Reserved" "0,1" newline bitfld.long 0xC 4.--5. "DRV_DIAG_TX_DRV_5_4,TX boost tune: Controls the transmitter boost amplitude when the transmitter boost function is enabled using the TX boost enable bit in this register by controlling the txda_drv_boost_tune signal going to the analog." "0,1,2,3" newline rbitfld.long 0xC 2.--3. "DRV_DIAG_TX_DRV_3_2,Reserved" "0,1,2,3" newline bitfld.long 0xC 1. "DRV_DIAG_TX_DRV_1,TX pre-driver pull up control: When the pre-driver is disabled this bit controls the state of the pre-driver output by controlling the txda_drv_predrv_pullup signal going to the analog." "0,1" newline bitfld.long 0xC 0. "DRV_DIAG_TX_DRV_0,TX driver margin type: Selects the margining type the driver will operate in by controlling the txda_drv_margin_type signal going to the analog." "0,1" group.long 0x41C0++0x1F line.long 0x0 "XCVR_DIAG_XCAL_PWRI_OVRD__XCVR_DIAG_PWRI_TMR_j,Transceiver power island control timer register Offset = 41C0h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "XCVR_DIAG_XCAL_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1" newline bitfld.long 0x0 30. "XCVR_DIAG_XCAL_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control.." "0,1" newline rbitfld.long 0x0 28.--29. "XCVR_DIAG_XCAL_PWRI_OVRD_13_12,Reserved" "0,1,2,3" newline bitfld.long 0x0 27. "XCVR_DIAG_XCAL_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine." "0,1" newline rbitfld.long 0x0 26. "XCVR_DIAG_XCAL_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine." "0,1" newline bitfld.long 0x0 25. "XCVR_DIAG_XCAL_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine." "0,1" newline rbitfld.long 0x0 24. "XCVR_DIAG_XCAL_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "XCVR_DIAG_XCAL_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine." newline rbitfld.long 0x0 13.--15. "XCVR_DIAG_PWRI_TMR_15_13,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--12. 1. "XCVR_DIAG_PWRI_TMR_12_8,Power enable phase 2 timer value: This specifies the number of PSM clock cycles the power island control state machines in the transceiver will wait in the power phase 2 enable states in order to allow enough time for the second.." newline rbitfld.long 0x0 5.--7. "XCVR_DIAG_PWRI_TMR_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "XCVR_DIAG_PWRI_TMR_4_0,Power enable phase 1 timer value: This specifies the number of PSM clock cycles the power island control state machines in the transceiver will wait in the power phase 1 enable states in order to allow enough time for the first.." line.long 0x4 "XCVR_DIAG_XDP_PWRI_OVRD__XCVR_DIAG_XCAL_PWRI_STAT_j,Transceiver transceiver calibration power island control status register Offset = 41C4h + (j * 400h); where j = 0h to 3h" bitfld.long 0x4 31. "XCVR_DIAG_XDP_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1" newline bitfld.long 0x4 30. "XCVR_DIAG_XDP_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0,1" newline rbitfld.long 0x4 28.--29. "XCVR_DIAG_XDP_PWRI_OVRD_13_12,Reserved" "0,1,2,3" newline bitfld.long 0x4 27. "XCVR_DIAG_XDP_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine." "0,1" newline rbitfld.long 0x4 26. "XCVR_DIAG_XDP_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine." "0,1" newline bitfld.long 0x4 25. "XCVR_DIAG_XDP_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine." "0,1" newline rbitfld.long 0x4 24. "XCVR_DIAG_XDP_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine." "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "XCVR_DIAG_XDP_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine." newline hexmask.long.byte 0x4 8.--15. 1. "XCVR_DIAG_XCAL_PWRI_STAT_15_8,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "XCVR_DIAG_XCAL_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine." line.long 0x8 "XCVR_DIAG_PLLDRC_CTRL__XCVR_DIAG_XDP_PWRI_STAT_j,Transceiver transceiver data path power island control status register Offset = 41C8h + (j * 400h); where j = 0h to 3h" bitfld.long 0x8 30.--31. "XCVR_DIAG_PLLDRC_CTRL_15_14,Digital PLL clock select standard mode 3: This bit controls which full rate PLL clock is selected when xcvr_standard_mode is set to 2'b11." "?,?,?,3: This bit controls which full rate PLL clock is.." newline bitfld.long 0x8 28.--29. "XCVR_DIAG_PLLDRC_CTRL_13_12,Digital PLL data rate divider standard mode 3 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0,1,2,3" newline bitfld.long 0x8 26.--27. "XCVR_DIAG_PLLDRC_CTRL_11_10,Digital PLL clock select standard mode 2: This bit controls which full rate PLL clock is selected when xcvr_standard_mode is set to 2'b10." "?,?,2: This bit controls which full rate PLL clock is..,?" newline bitfld.long 0x8 24.--25. "XCVR_DIAG_PLLDRC_CTRL_9_8,Digital PLL data rate divider standard mode 2 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0,1,2,3" newline bitfld.long 0x8 22.--23. "XCVR_DIAG_PLLDRC_CTRL_7_6,Digital PLL clock select standard mode 1: This bit controls which full rate PLL clock is selected when xcvr_standard_mode is set to 2'b01." "?,1: This bit controls which full rate PLL clock is..,?,?" newline bitfld.long 0x8 20.--21. "XCVR_DIAG_PLLDRC_CTRL_5_4,Digital PLL data rate divider standard mode 1 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0,1,2,3" newline bitfld.long 0x8 18.--19. "XCVR_DIAG_PLLDRC_CTRL_3_2,Digital PLL clock select standard mode 0: This bit controls which full rate PLL clock is selected when xcvr_standard_mode is set to 2'b00." "0: This bit controls which full rate PLL clock is..,?,?,?" newline bitfld.long 0x8 16.--17. "XCVR_DIAG_PLLDRC_CTRL_1_0,Digital PLL data rate divider standard mode 0 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0,1,2,3" newline hexmask.long.byte 0x8 8.--15. 1. "XCVR_DIAG_XDP_PWRI_STAT_15_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "XCVR_DIAG_XDP_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine." line.long 0xC "XCVR_DIAG_HSCLK_DIV__XCVR_DIAG_HSCLK_SEL_j,Transceiver high speed clock select register Offset = 41CCh + (j * 400h); where j = 0h to 3h" rbitfld.long 0xC 31. "XCVR_DIAG_HSCLK_DIV_15,Reserved" "0,1" newline bitfld.long 0xC 28.--30. "XCVR_DIAG_HSCLK_DIV_14_12,Transceiver clock divider select standard mode 3: This field selects the divider value used to divide the selected analog high speed clock by when generating the transmit and receive clocks when xcvr_standard_mode is set to.." "?,?,?,3: This field selects the divider value used to..,?,?,?,?" newline rbitfld.long 0xC 27. "XCVR_DIAG_HSCLK_DIV_11,Reserved" "0,1" newline bitfld.long 0xC 24.--26. "XCVR_DIAG_HSCLK_DIV_10_8,Transceiver clock divider select standard mode 2: This field selects the divider value used to divide the selected analog high speed clock by when generating the transmit and receive clocks when xcvr_standard_mode is set to.." "?,?,2: This field selects the divider value used to..,?,?,?,?,?" newline rbitfld.long 0xC 23. "XCVR_DIAG_HSCLK_DIV_7,Reserved" "0,1" newline bitfld.long 0xC 20.--22. "XCVR_DIAG_HSCLK_DIV_6_4,Transceiver clock divider select standard mode 1: This field selects the divider value used to divide the selected analog high speed clock by when generating the transmit and receive clocks when xcvr_standard_mode is set to.." "?,1: This field selects the divider value used to..,?,?,?,?,?,?" newline rbitfld.long 0xC 19. "XCVR_DIAG_HSCLK_DIV_3,Reserved" "0,1" newline bitfld.long 0xC 16.--18. "XCVR_DIAG_HSCLK_DIV_2_0,Transceiver clock divider select standard mode 0: This field selects the divider value used to divide the selected analog high speed clock by when generating the transmit and receive clocks when xcvr_standard_mode is set to.." "0: This field selects the divider value used to..,?,?,?,?,?,?,?" newline rbitfld.long 0xC 14.--15. "XCVR_DIAG_HSCLK_SEL_15_14,Reserved" "0,1,2,3" newline bitfld.long 0xC 12.--13. "XCVR_DIAG_HSCLK_SEL_13_12,High speed clock select standard mode 3: This specifies which analog high speed clock is selected when xcvr_standard_mode is set to 2'b11 by driving the xcvrda_clk_sel signal to the analog as specified below." "?,?,?,3: This specifies which analog high speed clock is.." newline rbitfld.long 0xC 10.--11. "XCVR_DIAG_HSCLK_SEL_11_10,Reserved" "0,1,2,3" newline bitfld.long 0xC 8.--9. "XCVR_DIAG_HSCLK_SEL_9_8,High speed clock select standard mode 2: This specifies which analog high speed clock is selected when xcvr_standard_mode is set to 2'b10 by driving the xcvrda_clk_sel signal to the analog as specified below." "?,?,2: This specifies which analog high speed clock is..,?" newline rbitfld.long 0xC 6.--7. "XCVR_DIAG_HSCLK_SEL_7_6,Reserved" "0,1,2,3" newline bitfld.long 0xC 4.--5. "XCVR_DIAG_HSCLK_SEL_5_4,High speed clock select standard mode 1: This specifies which analog high speed clock is selected when xcvr_standard_mode is set to 2'b01 by driving the xcvrda_clk_sel signal to the analog as specified below." "?,1: This specifies which analog high speed clock is..,?,?" newline rbitfld.long 0xC 2.--3. "XCVR_DIAG_HSCLK_SEL_3_2,Reserved" "0,1,2,3" newline bitfld.long 0xC 0.--1. "XCVR_DIAG_HSCLK_SEL_1_0,High speed clock select standard mode 0: This specifies which analog high speed clock is selected when xcvr_standard_mode is set to 2'b00 by driving the xcvrda_clk_sel signal to the analog as specified below." "0: This specifies which analog high speed clock is..,?,?,?" line.long 0x10 "XCVR_DIAG_RXCLK_CTRL__XCVR_DIAG_TXCLK_CTRL_j,TX clock control register Offset = 41D0h + (j * 400h); where j = 0h to 3h" bitfld.long 0x10 31. "XCVR_DIAG_RXCLK_CTRL_15,RX deserializer clock invert: This bit is used to optionally invert the deserializer clock (rxda_des_clk) for diagnostic purposes." "0,1" newline bitfld.long 0x10 30. "XCVR_DIAG_RXCLK_CTRL_14,RX 2x clock enable: This bit enables the receiver 2x clock function by driving the rxda_des_clk_2x_en signal going to the analog." "0,1" newline bitfld.long 0x10 29. "XCVR_DIAG_RXCLK_CTRL_13,RX PI E path clock select: Controls which PI clock drives the E path clocks by driving the rxda_pi_i_drv_e_en signal going to the analog." "0,1" newline hexmask.long.byte 0x10 24.--28. 1. "XCVR_DIAG_RXCLK_CTRL_12_8,Reserved" newline bitfld.long 0x10 23. "XCVR_DIAG_RXCLK_CTRL_7,PI output clock divider enable standard mode 3: This bit controls the rxda_pi_out_clk_div_en to enable the PI output clock divider when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x10 22. "XCVR_DIAG_RXCLK_CTRL_6,PI output clock divider enable standard mode 2: This bit controls the rxda_pi_out_clk_div_en to enable the PI output clock divider when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x10 21. "XCVR_DIAG_RXCLK_CTRL_5,PI output clock divider enable standard mode 1: This bit controls the rxda_pi_out_clk_div_en to enable the PI output clock divider when xcvr_standard_mode is set to 2'b01." "?,1: This bit controls the rxda_pi_out_clk_div_en to.." newline bitfld.long 0x10 20. "XCVR_DIAG_RXCLK_CTRL_4,PI output clock divider enable standard mode 0: This bit controls the rxda_pi_out_clk_div_en to enable the PI output clock divider when xcvr_standard_mode is set to 2'b00." "0: This bit controls the rxda_pi_out_clk_div_en to..,?" newline hexmask.long.byte 0x10 16.--19. 1. "XCVR_DIAG_RXCLK_CTRL_3_0,Reserved" newline bitfld.long 0x10 15. "XCVR_DIAG_TXCLK_CTRL_15,TX serializer clock invert: This bit is used to optionally invert the serializer clock (txda_ser_clk) for diagnostic purposes." "0,1" newline hexmask.long.word 0x10 0.--14. 1. "XCVR_DIAG_TXCLK_CTRL_14_0,Reserved" line.long 0x14 "XCVR_DIAG_PSC_OVRD__XCVR_DIAG_BIDI_CTRL_j,Transceiver bidirectional control register Offset = 41D4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x14 20.--31. 1. "XCVR_DIAG_PSC_OVRD_15_4,Reserved" newline bitfld.long 0x14 19. "XCVR_DIAG_PSC_OVRD_3,Receiver DFE enable mask value standard mode 3: This bit will controls the rx_dfe_eq_enable_std_mask digital signal which can be used to mask off the rxda_dfe_eq_enable signal coming from the power state controller and going into.." "0,1" newline bitfld.long 0x14 18. "XCVR_DIAG_PSC_OVRD_2,Receiver DFE enable mask value standard mode 2: This bit will controls the rx_dfe_eq_enable_std_mask digital signal which can be used to mask off the rxda_dfe_eq_enable signal coming from the power state controller and going into.." "?,?" newline bitfld.long 0x14 17. "XCVR_DIAG_PSC_OVRD_1,Receiver DFE enable mask value standard mode 1: This bit will controls the rx_dfe_eq_enable_std_mask digital signal which can be used to mask off the rxda_dfe_eq_enable signal coming from the power state controller and going into.." "?,1: This bit will controls the.." newline bitfld.long 0x14 16. "XCVR_DIAG_PSC_OVRD_0,Receiver DFE enable mask value standard mode 0: This bit will controls the rx_dfe_eq_enable_std_mask digital signal which can be used to mask off the rxda_dfe_eq_enable signal coming from the power state controller and going into.." "0: This bit will controls the..,?" newline hexmask.long.byte 0x14 8.--15. 1. "XCVR_DIAG_BIDI_CTRL_15_8,Reserved" newline bitfld.long 0x14 7. "XCVR_DIAG_BIDI_CTRL_7,Receiver enable standard mode 3: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the receiver function when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x14 6. "XCVR_DIAG_BIDI_CTRL_6,Receiver enable standard mode 2: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the receiver function when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x14 5. "XCVR_DIAG_BIDI_CTRL_5,Receiver enable standard mode 1: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the receiver function when xcvr_standard_mode is set to 2'b01." "?,1: When bidirectional bumps are implemented in the.." newline bitfld.long 0x14 4. "XCVR_DIAG_BIDI_CTRL_4,Receiver enable standard mode 0: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the receiver function when xcvr_standard_mode is set to 2'b00." "0: When bidirectional bumps are implemented in the..,?" newline bitfld.long 0x14 3. "XCVR_DIAG_BIDI_CTRL_3,Transmitter enable standard mode 3: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the transmitter function when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x14 2. "XCVR_DIAG_BIDI_CTRL_2,Transmitter enable standard mode 2: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the transmitter function when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x14 1. "XCVR_DIAG_BIDI_CTRL_1,Transmitter enable standard mode 1: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the transmitter function when xcvr_standard_mode is set to 2'b01." "?,1: When bidirectional bumps are implemented in the.." newline bitfld.long 0x14 0. "XCVR_DIAG_BIDI_CTRL_0,Transmitter enable standard mode 0: When bidirectional bumps are implemented in the transceiver this bit is a global enable for the transmitter function when xcvr_standard_mode is set to 2'b00." "0: When bidirectional bumps are implemented in the..,?" line.long 0x18 "XCVR_DIAG_XCVR_CLK_CTRL__XCVR_DIAG_RST_DIAG_j,Transceiver control reset diagnostic register Offset = 41D8h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x18 22.--31. 1. "XCVR_DIAG_XCVR_CLK_CTRL_15_6,Reserved" newline hexmask.long.byte 0x18 16.--21. 1. "XCVR_DIAG_XCVR_CLK_CTRL_5_0,Transceiver clock enable delay timer value: This specifies the number of xcvr_psm_clk clock cycles that the transceiver high speed clock reset release state machine will wait between when it drives the analog transceiver clock.." newline hexmask.long.word 0x18 3.--15. 1. "XCVR_DIAG_RST_DIAG_15_3,Reserved" newline rbitfld.long 0x18 2. "XCVR_DIAG_RST_DIAG_2,Current state of the tx_coef_calc_reset_n reset." "0,1" newline rbitfld.long 0x18 1. "XCVR_DIAG_RST_DIAG_1,Current state of the xcvr_psm_reset_n reset." "0,1" newline rbitfld.long 0x18 0. "XCVR_DIAG_RST_DIAG_0,Current state of the xcvr_ref_clk_reset_n reset." "0,1" line.long 0x1C "XCVR_DIAG_DCYA_j,Transceiver digital cover your alternatives register Offset = 41DCh + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x1C 16.--31. 1. "XCVR_DIAG_DCYA_15_0,Reserved - spare" newline hexmask.long.word 0x1C 0.--15. 1. "RESERVED" group.long 0x4200++0xF line.long 0x0 "TX_PSC_A1__TX_PSC_A0_j,Transmitter A0 power state definition register Offset = 4200h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x0 28.--31. 1. "TX_PSC_A1_15_12,Reserved" newline bitfld.long 0x0 27. "TX_PSC_A1_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0x0 26. "TX_PSC_A1_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0x0 25. "TX_PSC_A1_9,LFPS clock gate enable" "0,1" newline bitfld.long 0x0 24. "TX_PSC_A1_8,Reserved - spare" "0,1" newline bitfld.long 0x0 23. "TX_PSC_A1_7,Transmitter low current mode" "0,1" newline bitfld.long 0x0 22. "TX_PSC_A1_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0x0 21. "TX_PSC_A1_5,TX driver common mode enable" "0,1" newline bitfld.long 0x0 20. "TX_PSC_A1_4,TX driver enable" "0,1" newline bitfld.long 0x0 19. "TX_PSC_A1_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0x0 18. "TX_PSC_A1_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0x0 17. "TX_PSC_A1_1,TX pre-driver enable" "0,1" newline bitfld.long 0x0 16. "TX_PSC_A1_0,TX serializer enable" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "TX_PSC_A0_15_12,Reserved" newline bitfld.long 0x0 11. "TX_PSC_A0_11,TX driver common mode enable extend control: Specifies which power states the tx_cmn_mode_en_ext signal is considered valid in and can be used to force the driver to continue to be in the common mode state." "0,1" newline bitfld.long 0x0 10. "TX_PSC_A0_10,Force txda_lfps_sel active: Setting this bit forces the txda_lfps_sel signal going to the analog to be driven active." "0,1" newline bitfld.long 0x0 9. "TX_PSC_A0_9,LFPS clock gate enable: Enables the LFPS clock gate when an LFPS clock is required." "0,1" newline bitfld.long 0x0 8. "TX_PSC_A0_8,Reserved - spare" "0,1" newline bitfld.long 0x0 7. "TX_PSC_A0_7,Transmitter low current mode: Enables a low current consumption mode within the common mode voltage circuit in the driver via the txda_drv_idle_lowi_en signal going to the analog." "0,1" newline bitfld.long 0x0 6. "TX_PSC_A0_6,Transmitter mission mode enable: Enables the analog circuits in the driver required to run in mission mode via the txda_drv_mission_en signal going to the analog." "0,1" newline bitfld.long 0x0 5. "TX_PSC_A0_5,TX driver common mode enable: Enables the common mode voltage circuits in the driver." "0,1" newline bitfld.long 0x0 4. "TX_PSC_A0_4,TX driver enable: Enables the transmitter driver via the H bridge driver controller." "0,1" newline bitfld.long 0x0 3. "TX_PSC_A0_3,TX post-emphasis enable (C+1): Enables the transmitter circuits related to the post-emphasis function." "0,1" newline bitfld.long 0x0 2. "TX_PSC_A0_2,TX pre-emphasis enable (C-1): Enables the transmitter circuits related to the pre-emphasis function." "0,1" newline bitfld.long 0x0 1. "TX_PSC_A0_1,TX pre-driver enable: Enables the transmitter pre-driver driver data selection MUX and receiver detect." "0,1" newline bitfld.long 0x0 0. "TX_PSC_A0_0,TX serializer enable: Enables the serializer and related clock divider circuits." "0,1" line.long 0x4 "TX_PSC_A3__TX_PSC_A2_j,Transmitter A2 power state definition register Offset = 4204h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 28.--31. 1. "TX_PSC_A3_15_12,Reserved" newline bitfld.long 0x4 27. "TX_PSC_A3_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0x4 26. "TX_PSC_A3_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0x4 25. "TX_PSC_A3_9,LFPS clock gate enable" "0,1" newline bitfld.long 0x4 24. "TX_PSC_A3_8,Reserved - spare" "0,1" newline bitfld.long 0x4 23. "TX_PSC_A3_7,Transmitter low current mode" "0,1" newline bitfld.long 0x4 22. "TX_PSC_A3_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0x4 21. "TX_PSC_A3_5,TX driver common mode enable" "0,1" newline bitfld.long 0x4 20. "TX_PSC_A3_4,TX driver enable" "0,1" newline bitfld.long 0x4 19. "TX_PSC_A3_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0x4 18. "TX_PSC_A3_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0x4 17. "TX_PSC_A3_1,TX pre-driver enable" "0,1" newline bitfld.long 0x4 16. "TX_PSC_A3_0,TX serializer enable" "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "TX_PSC_A2_15_12,Reserved" newline bitfld.long 0x4 11. "TX_PSC_A2_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0x4 10. "TX_PSC_A2_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0x4 9. "TX_PSC_A2_9,LFPS clock gate enable" "0,1" newline bitfld.long 0x4 8. "TX_PSC_A2_8,Reserved - spare" "0,1" newline bitfld.long 0x4 7. "TX_PSC_A2_7,Transmitter low current mode" "0,1" newline bitfld.long 0x4 6. "TX_PSC_A2_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0x4 5. "TX_PSC_A2_5,TX driver common mode enable" "0,1" newline bitfld.long 0x4 4. "TX_PSC_A2_4,TX driver enable" "0,1" newline bitfld.long 0x4 3. "TX_PSC_A2_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0x4 2. "TX_PSC_A2_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0x4 1. "TX_PSC_A2_1,TX pre-driver enable" "0,1" newline bitfld.long 0x4 0. "TX_PSC_A2_0,TX serializer enable" "0,1" line.long 0x8 "TX_PSC_A5__TX_PSC_A4_j,Transmitter A4 power state definition register Offset = 4208h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 28.--31. 1. "TX_PSC_A5_15_12,Reserved" newline bitfld.long 0x8 27. "TX_PSC_A5_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0x8 26. "TX_PSC_A5_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0x8 25. "TX_PSC_A5_9,LFPS clock gate enable" "0,1" newline bitfld.long 0x8 24. "TX_PSC_A5_8,Reserved - spare" "0,1" newline bitfld.long 0x8 23. "TX_PSC_A5_7,Transmitter low current mode" "0,1" newline bitfld.long 0x8 22. "TX_PSC_A5_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0x8 21. "TX_PSC_A5_5,TX driver common mode enable" "0,1" newline bitfld.long 0x8 20. "TX_PSC_A5_4,TX driver enable" "0,1" newline bitfld.long 0x8 19. "TX_PSC_A5_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0x8 18. "TX_PSC_A5_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0x8 17. "TX_PSC_A5_1,TX pre-driver enable" "0,1" newline bitfld.long 0x8 16. "TX_PSC_A5_0,TX serializer enable" "0,1" newline hexmask.long.byte 0x8 12.--15. 1. "TX_PSC_A4_15_12,Reserved" newline bitfld.long 0x8 11. "TX_PSC_A4_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0x8 10. "TX_PSC_A4_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0x8 9. "TX_PSC_A4_9,LFPS clock gate enable" "0,1" newline bitfld.long 0x8 8. "TX_PSC_A4_8,Reserved - spare" "0,1" newline bitfld.long 0x8 7. "TX_PSC_A4_7,Transmitter low current mode" "0,1" newline bitfld.long 0x8 6. "TX_PSC_A4_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0x8 5. "TX_PSC_A4_5,TX driver common mode enable" "0,1" newline bitfld.long 0x8 4. "TX_PSC_A4_4,TX driver enable" "0,1" newline bitfld.long 0x8 3. "TX_PSC_A4_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0x8 2. "TX_PSC_A4_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0x8 1. "TX_PSC_A4_1,TX pre-driver enable" "0,1" newline bitfld.long 0x8 0. "TX_PSC_A4_0,TX serializer enable" "0,1" line.long 0xC "TX_PSC_RDY__TX_PSC_CAL_j,Transmitter calibration power state definition register Offset = 420Ch + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0xC 28.--31. 1. "TX_PSC_RDY_15_12,Reserved" newline bitfld.long 0xC 27. "TX_PSC_RDY_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0xC 26. "TX_PSC_RDY_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0xC 25. "TX_PSC_RDY_9,LFPS clock gate enable" "0,1" newline bitfld.long 0xC 24. "TX_PSC_RDY_8,Reserved - spare" "0,1" newline bitfld.long 0xC 23. "TX_PSC_RDY_7,Transmitter low current mode" "0,1" newline bitfld.long 0xC 22. "TX_PSC_RDY_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0xC 21. "TX_PSC_RDY_5,TX driver common mode enable" "0,1" newline bitfld.long 0xC 20. "TX_PSC_RDY_4,TX driver enable" "0,1" newline bitfld.long 0xC 19. "TX_PSC_RDY_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0xC 18. "TX_PSC_RDY_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0xC 17. "TX_PSC_RDY_1,TX pre-driver enable" "0,1" newline bitfld.long 0xC 16. "TX_PSC_RDY_0,TX serializer enable" "0,1" newline hexmask.long.byte 0xC 12.--15. 1. "TX_PSC_CAL_15_12,Reserved" newline bitfld.long 0xC 11. "TX_PSC_CAL_11,TX driver common mode enable extend control" "0,1" newline bitfld.long 0xC 10. "TX_PSC_CAL_10,Force txda_lfps_sel active" "0,1" newline bitfld.long 0xC 9. "TX_PSC_CAL_9,LFPS clock gate enable" "0,1" newline bitfld.long 0xC 8. "TX_PSC_CAL_8,Reserved - spare" "0,1" newline bitfld.long 0xC 7. "TX_PSC_CAL_7,Transmitter low current mode" "0,1" newline bitfld.long 0xC 6. "TX_PSC_CAL_6,Transmitter mission mode enable" "0,1" newline bitfld.long 0xC 5. "TX_PSC_CAL_5,TX driver common mode enable" "0,1" newline bitfld.long 0xC 4. "TX_PSC_CAL_4,TX driver enable" "0,1" newline bitfld.long 0xC 3. "TX_PSC_CAL_3,TX post-emphasis enable (C+1)" "0,1" newline bitfld.long 0xC 2. "TX_PSC_CAL_2,TX pre-emphasis enable (C-1)" "0,1" newline bitfld.long 0xC 1. "TX_PSC_CAL_1,TX pre-driver enable" "0,1" newline bitfld.long 0xC 0. "TX_PSC_CAL_0,TX serializer enable" "0,1" group.long 0x4240++0x7 line.long 0x0 "TX_RCVDET_OVRD__TX_RCVDET_CTRL_j,Transmit receiver detect control register Offset = 4240h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "TX_RCVDET_OVRD_15,Receiver detect override enable: Activation (1'b1) of this register bit enables the tx_rcv_detected output from the receiver detect state machine to be driven directly by the receiver detect override bit in this register." "0,1" newline bitfld.long 0x0 30. "TX_RCVDET_OVRD_14,Receiver detect override: When the receiver detect override enable bit in this register is active (1'b1) this bit will directly control the tx_rcv_detected output from the receiver detect state machine." "0,1" newline hexmask.long.word 0x0 16.--29. 1. "TX_RCVDET_OVRD_13_0,Reserved" newline bitfld.long 0x0 15. "TX_RCVDET_CTRL_15,Start receiver detect: Activating (1'b1) this bit will start the receiver detect process." "0,1" newline rbitfld.long 0x0 14. "TX_RCVDET_CTRL_14,Receiver detect process done: This bit will be set to 1'b1 when the receiver detect process is complete." "0,1" newline rbitfld.long 0x0 13. "TX_RCVDET_CTRL_13,Receiver detected: When the receiver detect process is complete this register bit will indicate the current state of the tx_rcv_detected pin." "0,1" newline hexmask.long.word 0x0 0.--12. 1. "TX_RCVDET_CTRL_12_0,Reserved" line.long 0x4 "TX_RCVDET_ST_TMR__TX_RCVDET_EN_TMR_j,Transmit receiver detect enable timer register Offset = 4244h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "TX_RCVDET_ST_TMR_15_0,Start wait time value: This is the number of clocks the receiver detect state machine waits between driving the txda_rcvdet_start signal active and checking the results on the txda_rcvdet_detected_n signal coming from the analog." newline hexmask.long.word 0x4 0.--15. 1. "TX_RCVDET_EN_TMR_15_0,Enable wait time value: This is the number of clocks the receiver detect state machine waits between driving the txda_rcvdet_en signal active and driving the txda_rcvdet_start signal active going to the analog." group.long 0x4280++0x7 line.long 0x0 "TX_BIST_UDDWR__TX_BIST_CTRL_j,Transmit BIST control register Offset = 4280h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x0 26.--31. 1. "TX_BIST_UDDWR_15_10,Reserved" newline hexmask.long.word 0x0 16.--25. 1. "TX_BIST_UDDWR_9_0,Transmitter BIST user defined data: Writing a data word to this field will result in that data word being placed in the next available position in the transmitter BIST user defined data FIFO." newline hexmask.long.byte 0x0 12.--15. 1. "TX_BIST_CTRL_15_12,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "TX_BIST_CTRL_11_8,Transmitter BIST mode: Controls which mode the BIST will operate in." newline rbitfld.long 0x0 5.--7. "TX_BIST_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "TX_BIST_CTRL_4,Transmitter BIST force error: When this bit transitions from 1'b0 to 1'b1 the transmit BIST controller will force an error to be transmitted from the BIST logic by inverting one of the parallel data bits." "0,1" newline rbitfld.long 0x0 2.--3. "TX_BIST_CTRL_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "TX_BIST_CTRL_1,Transmitter BIST user defined data FIFO clear: Writing a 1'b1 to this bit will clear the transmitter BIST user defined data FIFO." "0,1" newline bitfld.long 0x0 0. "TX_BIST_CTRL_0,Transmitter BIST enable: This bit enables the transmitter BIST function." "0,1" line.long 0x4 "TX_BIST_SEED1__TX_BIST_SEED0_j,Transmit BIST PRBS seed 0 register Offset = 4284h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x4 31. "TX_BIST_SEED1_15,Reserved" "0,1" newline hexmask.long.word 0x4 16.--30. 1. "TX_BIST_SEED1_14_0,Transmitter BIST PRBS seed (30:16): When the BIST is in PRBS mode this field provides a seed for the PRBS such that different lanes can have different BIST patterns." newline hexmask.long.word 0x4 0.--15. 1. "TX_BIST_SEED0_15_0,Transmitter BIST PRBS seed (15:0): When the BIST is in PRBS mode this field provides a seed for the PRBS such that different lanes can have different BIST patterns." group.long 0x43C0++0x7 line.long 0x0 "TX_DIAG_SFIFO_TMR__TX_DIAG_SFIFO_CTRL_j,TX sync FIFO diagnostic control register Offset = 43C0h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x0 30.--31. "TX_DIAG_SFIFO_TMR_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "TX_DIAG_SFIFO_TMR_13_8,FIFO alignment settle delay: This field specifies the number of clocks to wait for a prior change to the enqueue pointer to complete before initiating the check phase of the alignment procedure in the sync FIFO." newline rbitfld.long 0x0 22.--23. "TX_DIAG_SFIFO_TMR_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "TX_DIAG_SFIFO_TMR_5_0,FIFO alignment detect delay: This field specifies the number of clocks to wait in the delay state for each phase of the alignment procedure in the sync FIFO." newline hexmask.long.word 0x0 5.--15. 1. "TX_DIAG_SFIFO_CTRL_15_5,Reserved" newline bitfld.long 0x0 4. "TX_DIAG_SFIFO_CTRL_4,FIFO enqueue pointer bump: This bit can be used to decrement the enqueue pointer relative to the dequeue pointer for diagnostic purposes." "0,1" newline rbitfld.long 0x0 3. "TX_DIAG_SFIFO_CTRL_3,FIFO pointers overlapping: This bit indicates that the current enqueue and dequeue pointers have been detected as overlapping." "0,1" newline rbitfld.long 0x0 2. "TX_DIAG_SFIFO_CTRL_2,FIFO alignment acknowledge: This bit indicates that the FIFO alignment process is complete as initiated either automatically by the hardware of the FIFO alignment enable override bits in this register." "0,1" newline bitfld.long 0x0 1. "TX_DIAG_SFIFO_CTRL_1,FIFO alignment enable override enable: This bit enables the FIFO alignment enable override register to drive the fifo_align_en pin of the FIFO directly for diagnostic purposes." "0,1" newline bitfld.long 0x0 0. "TX_DIAG_SFIFO_CTRL_0,FIFO alignment enable override: When enabled by the FIFO alignment enable override enable bit in this register this bit directly controls the fifo_align_en pin of the FIFO to provide a means of running the FIFO alignment function.." "0,1" line.long 0x4 "TX_DIAG_ELEC_IDLE_j,TX electrical idle diagnostic register Offset = 43C4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 12.--15. 1. "TX_DIAG_ELEC_IDLE_15_12,TX electrical idle exit delay 16 bit data width : This field controls the amount of additional delay added to the electrical idle signal after the sync FIFO when exiting the electrical idle state for 16 bit data width modes." newline hexmask.long.byte 0x4 8.--11. 1. "TX_DIAG_ELEC_IDLE_11_8,TX electrical idle entry delay 16 bit data width : This field controls the amount of additional delay added to the electrical idle signal after the sync FIFO when entering the electrical idle state for 16 bit data width modes." newline hexmask.long.byte 0x4 4.--7. 1. "TX_DIAG_ELEC_IDLE_7_4,TX electrical idle exit delay 20 bit data width : This field controls the amount of additional delay added to the electrical idle signal after the sync FIFO when exiting the electrical idle state for 20 bit data width modes." newline hexmask.long.byte 0x4 0.--3. 1. "TX_DIAG_ELEC_IDLE_3_0,TX electrical idle entry delay 20 bit data width : This field controls the amount of additional delay added to the electrical idle signal after the sync FIFO when entering the electrical idle state for 20 bit data width modes." rgroup.long 0x43C8++0x3 line.long 0x0 "TX_DIAG_RST_DIAG_j,Transmitter control reset diagnostic register Offset = 43C8h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 21.--31. 1. "TX_DIAG_RST_DIAG_15_5,Reserved" newline bitfld.long 0x0 20. "TX_DIAG_RST_DIAG_4,Current state of the txda_tx_clk_reset_n reset." "0,1" newline bitfld.long 0x0 19. "TX_DIAG_RST_DIAG_3,Current state of the tx_dig_reset_n reset." "0,1" newline bitfld.long 0x0 18. "TX_DIAG_RST_DIAG_2,Current state of the tx_sync_fifo_deq_rst_n reset." "0,1" newline bitfld.long 0x0 17. "TX_DIAG_RST_DIAG_1,Current state of the tx_sync_fifo_enq_rst_n reset." "0,1" newline bitfld.long 0x0 16. "TX_DIAG_RST_DIAG_0,Current state of the tx_lfps_reset_n reset." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED" group.long 0x43CC++0x3 line.long 0x0 "TX_DIAG_ACYA__TX_DIAG_DCYA_j,Transmitter digital cover your alternatives register Offset = 43CCh + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 17.--31. 1. "TX_DIAG_ACYA_15_1,Reserved - spare" newline bitfld.long 0x0 16. "TX_DIAG_ACYA_0,HBDC latch control: Controls the state of the latches associated with the H bridge driver controller related signals in the H bridge driver encoder logic digital in the transmitter analog as well as the boost enable and level control.." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "TX_DIAG_DCYA_15_0,Reserved - spare" group.long 0x8000++0xF line.long 0x0 "RX_PSC_A1__RX_PSC_A0_j,Receiver A0 power state definition register Offset = 8000h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x0 29.--31. "RX_PSC_A1_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "RX_PSC_A1_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x0 27. "RX_PSC_A1_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x0 26. "RX_PSC_A1_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x0 25. "RX_PSC_A1_9,Reserved - spare" "0,1" newline bitfld.long 0x0 24. "RX_PSC_A1_8,RX signal detect enable" "0,1" newline bitfld.long 0x0 21.--23. "RX_PSC_A1_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RX_PSC_A1_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x0 19. "RX_PSC_A1_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x0 18. "RX_PSC_A1_2,RX PI enable" "0,1" newline bitfld.long 0x0 17. "RX_PSC_A1_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x0 16. "RX_PSC_A1_0,RX enable" "0,1" newline rbitfld.long 0x0 13.--15. "RX_PSC_A0_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "RX_PSC_A0_12,RX signal detect enable extend control: Specifies which power states the rx_sig_det_en_ext signal is considered valid in and can be used to force the signal detect functions to remain on." "0,1" newline bitfld.long 0x0 11. "RX_PSC_A0_11,RX signal detect filter enable: Enables the receiver signal detect filter function in the digital receiver controller." "0,1" newline bitfld.long 0x0 10. "RX_PSC_A0_10,RX LFPS detect filter enable: Enables the receiver LFPS detect filter function in the digital receiver controller." "0,1" newline bitfld.long 0x0 9. "RX_PSC_A0_9,Reserved - spare" "0,1" newline bitfld.long 0x0 8. "RX_PSC_A0_8,RX signal detect enable: Enables the receiver signal detect function." "0,1" newline bitfld.long 0x0 5.--7. "RX_PSC_A0_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "RX_PSC_A0_4,RX equalizer engine enable: Specifies which power state the REE runs in." "0,1" newline bitfld.long 0x0 3. "RX_PSC_A0_3,RX DFE equalization enable: Enables the receiver DFE equalization circuits via the rxda_dfe_eq_enable signal." "0,1" newline bitfld.long 0x0 2. "RX_PSC_A0_2,RX PI enable: Enables the receiver circuits related to the PI and associated clocking components." "0,1" newline bitfld.long 0x0 1. "RX_PSC_A0_1,RX e path enable (calibration and eye surf only) : Enables the receiver circuits related to the eye plot PI and e path deserializer for calibration and eye surf." "0,1" newline bitfld.long 0x0 0. "RX_PSC_A0_0,RX enable: Enables the receiver circuits related to the CDRLF Sampler FE and Deserializer." "0,1" line.long 0x4 "RX_PSC_A3__RX_PSC_A2_j,Receiver A2 power state definition register Offset = 8004h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x4 29.--31. "RX_PSC_A3_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "RX_PSC_A3_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x4 27. "RX_PSC_A3_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x4 26. "RX_PSC_A3_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x4 25. "RX_PSC_A3_9,Reserved - spare" "0,1" newline bitfld.long 0x4 24. "RX_PSC_A3_8,RX signal detect enable" "0,1" newline bitfld.long 0x4 21.--23. "RX_PSC_A3_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RX_PSC_A3_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x4 19. "RX_PSC_A3_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x4 18. "RX_PSC_A3_2,RX PI enable" "0,1" newline bitfld.long 0x4 17. "RX_PSC_A3_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x4 16. "RX_PSC_A3_0,RX enable" "0,1" newline rbitfld.long 0x4 13.--15. "RX_PSC_A2_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "RX_PSC_A2_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x4 11. "RX_PSC_A2_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x4 10. "RX_PSC_A2_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x4 9. "RX_PSC_A2_9,Reserved - spare" "0,1" newline bitfld.long 0x4 8. "RX_PSC_A2_8,RX signal detect enable" "0,1" newline bitfld.long 0x4 5.--7. "RX_PSC_A2_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "RX_PSC_A2_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x4 3. "RX_PSC_A2_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x4 2. "RX_PSC_A2_2,RX PI enable" "0,1" newline bitfld.long 0x4 1. "RX_PSC_A2_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x4 0. "RX_PSC_A2_0,RX enable" "0,1" line.long 0x8 "RX_PSC_A5__RX_PSC_A4_j,Receiver A4 power state definition register Offset = 8008h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x8 29.--31. "RX_PSC_A5_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "RX_PSC_A5_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x8 27. "RX_PSC_A5_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x8 26. "RX_PSC_A5_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x8 25. "RX_PSC_A5_9,Reserved - spare" "0,1" newline bitfld.long 0x8 24. "RX_PSC_A5_8,RX signal detect enable" "0,1" newline bitfld.long 0x8 21.--23. "RX_PSC_A5_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RX_PSC_A5_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x8 19. "RX_PSC_A5_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x8 18. "RX_PSC_A5_2,RX PI enable" "0,1" newline bitfld.long 0x8 17. "RX_PSC_A5_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x8 16. "RX_PSC_A5_0,RX enable" "0,1" newline rbitfld.long 0x8 13.--15. "RX_PSC_A4_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12. "RX_PSC_A4_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0x8 11. "RX_PSC_A4_11,RX signal detect filter enable" "0,1" newline bitfld.long 0x8 10. "RX_PSC_A4_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0x8 9. "RX_PSC_A4_9,Reserved - spare" "0,1" newline bitfld.long 0x8 8. "RX_PSC_A4_8,RX signal detect enable" "0,1" newline bitfld.long 0x8 5.--7. "RX_PSC_A4_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "RX_PSC_A4_4,RX equalizer engine enable" "0,1" newline bitfld.long 0x8 3. "RX_PSC_A4_3,RX DFE equalization enable." "0,1" newline bitfld.long 0x8 2. "RX_PSC_A4_2,RX PI enable" "0,1" newline bitfld.long 0x8 1. "RX_PSC_A4_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0x8 0. "RX_PSC_A4_0,RX enable" "0,1" line.long 0xC "RX_PSC_RDY__RX_PSC_CAL_j,Receiver calibration power state definition register Offset = 800Ch + (j * 400h); where j = 0h to 3h" rbitfld.long 0xC 29.--31. "RX_PSC_RDY_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 28. "RX_PSC_RDY_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0xC 27. "RX_PSC_RDY_11,RX signal detect filter enable" "0,1" newline bitfld.long 0xC 26. "RX_PSC_RDY_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0xC 25. "RX_PSC_RDY_9,Reserved - spare" "0,1" newline bitfld.long 0xC 24. "RX_PSC_RDY_8,RX signal detect enable" "0,1" newline bitfld.long 0xC 21.--23. "RX_PSC_RDY_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20. "RX_PSC_RDY_4,RX equalizer engine enable" "0,1" newline bitfld.long 0xC 19. "RX_PSC_RDY_3,RX DFE equalization enable." "0,1" newline bitfld.long 0xC 18. "RX_PSC_RDY_2,RX PI enable" "0,1" newline bitfld.long 0xC 17. "RX_PSC_RDY_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0xC 16. "RX_PSC_RDY_0,RX enable" "0,1" newline rbitfld.long 0xC 13.--15. "RX_PSC_CAL_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12. "RX_PSC_CAL_12,RX signal detect enable extend control" "0,1" newline bitfld.long 0xC 11. "RX_PSC_CAL_11,RX signal detect filter enable" "0,1" newline bitfld.long 0xC 10. "RX_PSC_CAL_10,RX LFPS detect filter enable" "0,1" newline bitfld.long 0xC 9. "RX_PSC_CAL_9,Reserved - spare" "0,1" newline bitfld.long 0xC 8. "RX_PSC_CAL_8,RX signal detect enable" "0,1" newline bitfld.long 0xC 5.--7. "RX_PSC_CAL_7_5,Reserved - spare" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "RX_PSC_CAL_4,RX equalizer engine enable" "0,1" newline bitfld.long 0xC 3. "RX_PSC_CAL_3,RX DFE equalization enable." "0,1" newline bitfld.long 0xC 2. "RX_PSC_CAL_2,RX PI enable" "0,1" newline bitfld.long 0xC 1. "RX_PSC_CAL_1,RX e path enable (calibration and eye surf only)" "0,1" newline bitfld.long 0xC 0. "RX_PSC_CAL_0,RX enable" "0,1" group.long 0x8080++0xB line.long 0x0 "RX_SDCAL0_OVRD__RX_SDCAL0_CTRL_j,Signal detect calibration 0 control register Offset = 8080h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "RX_SDCAL0_OVRD_15,Calibration code override enable: Activation (1'b1) of this register bit allows the codes determined during the automatic calibration process to be overridden." "0,1" newline bitfld.long 0x0 30. "RX_SDCAL0_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the rxda_sd_cal_0_en enable and the rxda_sd_cal_0_clk clock." "0,1" newline hexmask.long.word 0x0 21.--29. 1. "RX_SDCAL0_OVRD_13_5,Reserved" newline hexmask.long.byte 0x0 16.--20. 1. "RX_SDCAL0_OVRD_4_0,Calibration code override value: These bits are used to override the calibration code determined during the automatic calibration process." newline bitfld.long 0x0 15. "RX_SDCAL0_CTRL_15,Start calibration: Activating (1'b1) this bit will start the calibration process." "0,1" newline rbitfld.long 0x0 14. "RX_SDCAL0_CTRL_14,Calibration process done: This bit will be set to 1'b1 when the calibration process is complete." "0,1" newline rbitfld.long 0x0 13. "RX_SDCAL0_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1" newline rbitfld.long 0x0 12. "RX_SDCAL0_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (rxda_sd_cal_0_comp)." "0,1" newline hexmask.long.byte 0x0 5.--11. 1. "RX_SDCAL0_CTRL_11_5,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "RX_SDCAL0_CTRL_4_0,Calibration code: This is the calibration code that was determined by the calibration process." line.long 0x4 "RX_SDCAL0_TUNE__RX_SDCAL0_START_j,Signal detect calibration 0 start register Offset = 8084h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 21.--31. 1. "RX_SDCAL0_TUNE_15_5,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "RX_SDCAL0_TUNE_4_0,Calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled." newline bitfld.long 0x4 15. "RX_SDCAL0_START_15,Calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in." "0,1" newline hexmask.long.word 0x4 5.--14. 1. "RX_SDCAL0_START_14_5,Reserved" newline hexmask.long.byte 0x4 0.--4. 1. "RX_SDCAL0_START_4_0,Start calibration code: This is the calibration code that the calibration process starts with when automatic calibration is run." line.long 0x8 "RX_SDCAL0_ITER_TMR__RX_SDCAL0_INIT_TMR_j,Signal detect calibration 0 initialization timer register Offset = 8088h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 25.--31. 1. "RX_SDCAL0_ITER_TMR_15_9,Reserved" newline hexmask.long.word 0x8 16.--24. 1. "RX_SDCAL0_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration code signals going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.byte 0x8 9.--15. 1. "RX_SDCAL0_INIT_TMR_15_9,Reserved" newline hexmask.long.word 0x8 0.--8. 1. "RX_SDCAL0_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first values are placed on the calibration code signals going to the analog." group.long 0x8090++0xB line.long 0x0 "RX_SDCAL1_OVRD__RX_SDCAL1_CTRL_j,Signal detect calibration 1 control register Offset = 8090h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "RX_SDCAL1_OVRD_15,Calibration code override enable: Activation (1'b1) of this register bit allows the calibration code determined during the automatic calibration process to be overridden." "0,1" newline bitfld.long 0x0 30. "RX_SDCAL1_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the rxda_sd_cal_1_en enable and the rxda_sd_cal_1_clk clock." "0,1" newline hexmask.long.word 0x0 21.--29. 1. "RX_SDCAL1_OVRD_13_5,Reserved" newline hexmask.long.byte 0x0 16.--20. 1. "RX_SDCAL1_OVRD_4_0,Calibration code override value: These bits are used to override the calibration code determined during the automatic calibration process." newline bitfld.long 0x0 15. "RX_SDCAL1_CTRL_15,Start calibration: Activating (1'b1) this bit will start the calibration process." "0,1" newline rbitfld.long 0x0 14. "RX_SDCAL1_CTRL_14,Calibration process done: This bit will be set to 1'b1 when the calibration process is complete." "0,1" newline rbitfld.long 0x0 13. "RX_SDCAL1_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1" newline rbitfld.long 0x0 12. "RX_SDCAL1_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (rxda_sd_cal_0_comp)." "0,1" newline hexmask.long.byte 0x0 5.--11. 1. "RX_SDCAL1_CTRL_11_5,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "RX_SDCAL1_CTRL_4_0,Calibration code: This is the calibration code that was determined by the calibration process." line.long 0x4 "RX_SDCAL1_TUNE__RX_SDCAL1_START_j,Signal detect calibration 1 start register Offset = 8094h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 21.--31. 1. "RX_SDCAL1_TUNE_15_5,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "RX_SDCAL1_TUNE_4_0,Calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled." newline bitfld.long 0x4 15. "RX_SDCAL1_START_15,Calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in." "0,1" newline hexmask.long.word 0x4 5.--14. 1. "RX_SDCAL1_START_14_5,Reserved" newline hexmask.long.byte 0x4 0.--4. 1. "RX_SDCAL1_START_4_0,Start calibration code: This is the calibration code that the calibration process starts with when automatic calibration is run." line.long 0x8 "RX_SDCAL1_ITER_TMR__RX_SDCAL1_INIT_TMR_j,Signal detect calibration 1 initialization timer register Offset = 8098h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 25.--31. 1. "RX_SDCAL1_ITER_TMR_15_9,Reserved" newline hexmask.long.word 0x8 16.--24. 1. "RX_SDCAL1_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration code signals going to the analog and when the comparator value coming from the analog circuits can be.." newline hexmask.long.byte 0x8 9.--15. 1. "RX_SDCAL1_INIT_TMR_15_9,Reserved" newline hexmask.long.word 0x8 0.--8. 1. "RX_SDCAL1_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first values are placed on the calibration code signals going to the analog." group.long 0x80B0++0x3 line.long 0x0 "RX_SAMP_DAC_CTRL_j,Sampler error DAC control register Offset = 80B0h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 6.--15. 1. "RX_SAMP_DAC_CTRL_15_6,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "RX_SAMP_DAC_CTRL_5_0,Sampler error DAC value: Specifies the input value to the sampler error DAC." group.long 0x80C0++0x23 line.long 0x0 "RX_SLC_IPP_STAT__RX_SLC_CTRL_j,RX sampler latch calibration control register Offset = 80C0h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x0 31. "RX_SLC_IPP_STAT_15,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "RX_SLC_IPP_STAT_14_8,I even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the I even latch in the analog.." newline rbitfld.long 0x0 23. "RX_SLC_IPP_STAT_7,Reserved" "0,1" newline hexmask.long.byte 0x0 16.--22. 1. "RX_SLC_IPP_STAT_6_0,I odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the I odd latch in the analog.." newline bitfld.long 0x0 15. "RX_SLC_CTRL_15,Start RX sampler latch calibration: Activating (1'b1) this bit will start the RX sampler latch calibration process." "0,1" newline rbitfld.long 0x0 14. "RX_SLC_CTRL_14,RX sampler latch calibration process done: This bit will be set to 1'b1 when the RX sampler latch calibration process is complete." "0,1" newline hexmask.long.word 0x0 2.--13. 1. "RX_SLC_CTRL_13_2,Reserved" newline bitfld.long 0x0 0.--1. "RX_SLC_CTRL_1_0,RX sampler latch calibration scaler: This field specifies the scaler value used for the input data accumulator." "0,1,2,3" line.long 0x4 "RX_SLC_IPM_STAT__RX_SLC_IPP_OVRD_j,RX sampler latch calibration I predictive positive override register Offset = 80C4h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x4 31. "RX_SLC_IPM_STAT_15,Reserved" "0,1" newline hexmask.long.byte 0x4 24.--30. 1. "RX_SLC_IPM_STAT_14_8,I even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the I even latch in the analog.." newline rbitfld.long 0x4 23. "RX_SLC_IPM_STAT_7,Reserved" "0,1" newline hexmask.long.byte 0x4 16.--22. 1. "RX_SLC_IPM_STAT_6_0,I odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the I odd latch in the analog.." newline bitfld.long 0x4 15. "RX_SLC_IPP_OVRD_15,I even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the I even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1" newline hexmask.long.byte 0x4 8.--14. 1. "RX_SLC_IPP_OVRD_14_8,I even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the I even sampler latch." newline bitfld.long 0x4 7. "RX_SLC_IPP_OVRD_7,I odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the I odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "RX_SLC_IPP_OVRD_6_0,I odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the I odd sampler latch." line.long 0x8 "RX_SLC_QPP_STAT__RX_SLC_IPM_OVRD_j,RX sampler latch calibration I predictive negative override register Offset = 80C8h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x8 31. "RX_SLC_QPP_STAT_15,Reserved" "0,1" newline hexmask.long.byte 0x8 24.--30. 1. "RX_SLC_QPP_STAT_14_8,Q even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the Q even latch in the analog.." newline rbitfld.long 0x8 23. "RX_SLC_QPP_STAT_7,Reserved" "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "RX_SLC_QPP_STAT_6_0,Q odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the Q odd latch in the analog.." newline bitfld.long 0x8 15. "RX_SLC_IPM_OVRD_15,I eve latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the I even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "RX_SLC_IPM_OVRD_14_8,I even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the I even sampler latch." newline bitfld.long 0x8 7. "RX_SLC_IPM_OVRD_7,I odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the I odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "RX_SLC_IPM_OVRD_6_0,I odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the I odd sampler latch." line.long 0xC "RX_SLC_QPM_STAT__RX_SLC_QPP_OVRD_j,RX sampler latch calibration Q predictive positive override register Offset = 80CCh + (j * 400h); where j = 0h to 3h" rbitfld.long 0xC 31. "RX_SLC_QPM_STAT_15,Reserved" "0,1" newline hexmask.long.byte 0xC 24.--30. 1. "RX_SLC_QPM_STAT_14_8,Q even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the Q even latch in the analog.." newline rbitfld.long 0xC 23. "RX_SLC_QPM_STAT_7,Reserved" "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "RX_SLC_QPM_STAT_6_0,Q odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the Q odd latch in the analog.." newline bitfld.long 0xC 15. "RX_SLC_QPP_OVRD_15,Q even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the Q even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1" newline hexmask.long.byte 0xC 8.--14. 1. "RX_SLC_QPP_OVRD_14_8,Q even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the Q even sampler latch." newline bitfld.long 0xC 7. "RX_SLC_QPP_OVRD_7,Q odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the Q odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "RX_SLC_QPP_OVRD_6_0,Q odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the Q odd sampler latch." line.long 0x10 "RX_SLC_EPP_STAT__RX_SLC_QPM_OVRD_j,RX sampler latch calibration Q predictive negative override register Offset = 80D0h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x10 31. "RX_SLC_EPP_STAT_15,Reserved" "0,1" newline hexmask.long.byte 0x10 24.--30. 1. "RX_SLC_EPP_STAT_14_8,e even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the e even latch in the analog.." newline rbitfld.long 0x10 23. "RX_SLC_EPP_STAT_7,Reserved" "0,1" newline hexmask.long.byte 0x10 16.--22. 1. "RX_SLC_EPP_STAT_6_0,e odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the e odd latch in the analog.." newline bitfld.long 0x10 15. "RX_SLC_QPM_OVRD_15,Q even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the Q even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1" newline hexmask.long.byte 0x10 8.--14. 1. "RX_SLC_QPM_OVRD_14_8,Q even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the Q even sampler latch." newline bitfld.long 0x10 7. "RX_SLC_QPM_OVRD_7,Q odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the Q odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RX_SLC_QPM_OVRD_6_0,Q odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the Q odd sampler latch." line.long 0x14 "RX_SLC_EPM_STAT__RX_SLC_EPP_OVRD_j,RX sampler latch calibration e predictive positive override register Offset = 80D4h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x14 31. "RX_SLC_EPM_STAT_15,Reserved" "0,1" newline hexmask.long.byte 0x14 24.--30. 1. "RX_SLC_EPM_STAT_14_8,e even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the e even latch in the analog.." newline rbitfld.long 0x14 23. "RX_SLC_EPM_STAT_7,Reserved" "0,1" newline hexmask.long.byte 0x14 16.--22. 1. "RX_SLC_EPM_STAT_6_0,e odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the e odd latch in the analog.." newline bitfld.long 0x14 15. "RX_SLC_EPP_OVRD_15,e even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the e even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1" newline hexmask.long.byte 0x14 8.--14. 1. "RX_SLC_EPP_OVRD_14_8,e even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the e even sampler latch." newline bitfld.long 0x14 7. "RX_SLC_EPP_OVRD_7,e odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the e odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "RX_SLC_EPP_OVRD_6_0,e odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the e odd sampler latch." line.long 0x18 "RX_SLC_INIT_TMR__RX_SLC_EPM_OVRD_j,RX sampler latch calibration e predictive negative override register Offset = 80D8h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x18 16.--31. 1. "RX_SLC_INIT_TMR_15_0,RX sampler latch calibration initialization timer value : This is the value that will be used for the RX sampler latch calibration initialization timer which controls the time the rxda_sampler_latch_cal_en is held active prior to.." newline bitfld.long 0x18 15. "RX_SLC_EPM_OVRD_15,e even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the e even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1" newline hexmask.long.byte 0x18 8.--14. 1. "RX_SLC_EPM_OVRD_14_8,e even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the e even sampler latch." newline bitfld.long 0x18 7. "RX_SLC_EPM_OVRD_7,e odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the e odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1" newline hexmask.long.byte 0x18 0.--6. 1. "RX_SLC_EPM_OVRD_6_0,e odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the e odd sampler latch." line.long 0x1C "RX_SLC_DIAG_CTRL__RX_SLC_RUN_TMR_j,RX sampler latch calibration run timer value register Offset = 80DCh + (j * 400h); where j = 0h to 3h" bitfld.long 0x1C 31. "RX_SLC_DIAG_CTRL_15,Diagnostic control enable : This bit enables the selected RX sampler latch calibration data sub module for diagnostic purposes." "0,1" newline hexmask.long.byte 0x1C 23.--30. 1. "RX_SLC_DIAG_CTRL_14_7,Reserved" newline bitfld.long 0x1C 22. "RX_SLC_DIAG_CTRL_6,Voter override neg : When enabled using the voter override enable bit in this register writing a 1'b1 in this register bit will force the voter in the selected RX sampler latch calibration data sub module to activate the voter neg.." "0,1" newline bitfld.long 0x1C 21. "RX_SLC_DIAG_CTRL_5,Voter override pos : When enabled using the voter override enable bit in this register writing a 1'b1 in this register bit will force the voter in the selected RX sampler latch calibration data sub module to activate the voter pos.." "0,1" newline bitfld.long 0x1C 20. "RX_SLC_DIAG_CTRL_4,Voter override enable : Setting this bit to a 1'b1 will enable the voter override function in the selected RX sampler latch calibration data sub module." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "RX_SLC_DIAG_CTRL_3_0,Diagnostic control override select : Selects the RX sampler latch calibration data sub module to enable for diagnostic and verification purposes." newline hexmask.long.word 0x1C 0.--15. 1. "RX_SLC_RUN_TMR_15_0,RX sampler latch calibration run timer value : This is the value that will be used for the RX sampler latch calibration run timer which controls the run time for each calibration process." line.long 0x20 "RX_SLC_DIS_j,RX sampler latch calibration disable register Offset = 80E0h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x20 16.--31. 1. "RESERVED" newline rbitfld.long 0x20 15. "RX_SLC_DIS_15,Reserved" "0,1" newline bitfld.long 0x20 14. "RX_SLC_DIS_14,e even negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the e even negative coefficient RX sampler latch calibration data sub module." "0,1" newline bitfld.long 0x20 13. "RX_SLC_DIS_13,q even negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the q even negative coefficient RX sampler latch calibration data sub module." "0,1" newline bitfld.long 0x20 12. "RX_SLC_DIS_12,i even negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the i even negative coefficient RX sampler latch calibration data sub module." "0,1" newline rbitfld.long 0x20 11. "RX_SLC_DIS_11,Reserved" "0,1" newline bitfld.long 0x20 10. "RX_SLC_DIS_10,e even positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the e even positive coefficient RX sampler latch calibration data sub module." "0,1" newline bitfld.long 0x20 9. "RX_SLC_DIS_9,q even positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the q even positive coefficient RX sampler latch calibration data sub module." "0,1" newline bitfld.long 0x20 8. "RX_SLC_DIS_8,i even positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the i even positive coefficient RX sampler latch calibration data sub module." "0,1" newline rbitfld.long 0x20 7. "RX_SLC_DIS_7,Reserved" "0,1" newline bitfld.long 0x20 6. "RX_SLC_DIS_6,e odd negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the e odd negative coefficient RX sampler latch calibration data sub module." "0,1" newline bitfld.long 0x20 5. "RX_SLC_DIS_5,q odd negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the q odd negative coefficient RX sampler latch calibration data sub module." "0,1" newline bitfld.long 0x20 4. "RX_SLC_DIS_4,i odd negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the i odd negative coefficient RX sampler latch calibration data sub module." "0,1" newline rbitfld.long 0x20 3. "RX_SLC_DIS_3,Reserved" "0,1" newline bitfld.long 0x20 2. "RX_SLC_DIS_2,e odd positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the e odd positive coefficient RX sampler latch calibration data sub module." "0,1" newline bitfld.long 0x20 1. "RX_SLC_DIS_1,q odd positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the q odd positive coefficient RX sampler latch calibration data sub module." "0,1" newline bitfld.long 0x20 0. "RX_SLC_DIS_0,i odd positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the i odd positive coefficient RX sampler latch calibration data sub module." "0,1" group.long 0x8100++0xB line.long 0x0 "RX_CDRLF_CNFG2__RX_CDRLF_CNFG_j,CDRLF configuration register Offset = 8100h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x0 31. "RX_CDRLF_CNFG2_15,Reserved" "0,1" newline bitfld.long 0x0 30. "RX_CDRLF_CNFG2_14,CDRLF second order loop integrator max clear enable: This signal enables the function in the CDRLF where the second order loop integrator is cleared when it reaches the maximum value." "0,1" newline rbitfld.long 0x0 29. "RX_CDRLF_CNFG2_13,CDRLF fast phase lock locked detected: This register bit is the current status of the fphl_locked pin on the CDRLF and indicates the fast phase lock process is complete." "0,1" newline bitfld.long 0x0 28. "RX_CDRLF_CNFG2_12,CDRLF fast phase lock diagnostic enable: This register bit can control the fphl_start pin on the CDRLF." "0,1" newline bitfld.long 0x0 27. "RX_CDRLF_CNFG2_11,CDRLF fast phase lock enabled by signal detect: When active signal detect will control the fphl_start pin on the CDRLF." "0,1" newline bitfld.long 0x0 26. "RX_CDRLF_CNFG2_10,CDRLF reset on CDRLF PM Accumulator Max: Activating (1'b1) this bit will force the CDRLF to be reset when the PM accumulator in the CDRLF reaches is maximum absolute value (the largest positive or negative value)." "0,1" newline bitfld.long 0x0 25. "RX_CDRLF_CNFG2_9,CDRLF freeze on electrical idle detect: Activating (1'b1) this bit will force the CDRLF to be freeze in its current state when the receiver signal detect detects an electrical idle." "0,1" newline bitfld.long 0x0 24. "RX_CDRLF_CNFG2_8,CDRLF reset on electrical idle detect: Activating (1'b1) this bit will force the CDRLF to be reset when the receiver signal detect detects an electrical idle." "0,1" newline rbitfld.long 0x0 22.--23. "RX_CDRLF_CNFG2_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "RX_CDRLF_CNFG2_5_0,CDRLF second order loop integrator threshold : This value is the maximum magnitude the CDRLF second order loop integrator will be allowed to go to." newline bitfld.long 0x0 15. "RX_CDRLF_CNFG_15,CDLRF reset hold: When active (1'b1) the CDRLF will be held in reset beyond the time that it would normally be released by its asynchronous release signals." "0,1" newline bitfld.long 0x0 12.--14. "RX_CDRLF_CNFG_14_12,CDRLF diagnostic mode control: This field controls the information driven on the rx_pi_val_ln_{15:0}[7:0] signal when in diagnostics mode." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "RX_CDRLF_CNFG_11,CDRLF second order loop disable: Activating (1'b1) this bit will disable the CDRLF second order loop." "0,1" newline hexmask.long.byte 0x0 6.--10. 1. "RX_CDRLF_CNFG_10_6,CDRLF second order loop sigma delta update rate: This is the value that is added to or subtracted from the second order loop accumulator register when the serial data sample clock is detected as being out of phase with the serial data.." newline bitfld.long 0x0 5. "RX_CDRLF_CNFG_5,CDRLF first order loop disable: Activating (1'b1) this bit will disable the CDRLF first order loop." "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "RX_CDRLF_CNFG_4_0,CDRLF first order loop sigma delta update rate: This is the value that is added to or subtracted from the first order loop accumulator register when the serial data sample clock is detected as being out of phase with the serial data on.." line.long 0x4 "RX_CDRLF_MGN_DIAG__RX_CDRLF_CNFG3_j,CDRLF configuration register 3 Offset = 8104h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 19.--31. 1. "RX_CDRLF_MGN_DIAG_15_3,Reserved" newline bitfld.long 0x4 18. "RX_CDRLF_MGN_DIAG_2,CDRLF PI override down : When the CDRLF PI override enable function is enabled writing a 1'b1 to this bit will force a down to be generated in the CDRLF PI interface logic." "0,1" newline bitfld.long 0x4 17. "RX_CDRLF_MGN_DIAG_1,CDRLF PI override up : When the CDRLF PI override enable function is enabled writing a 1'b1 to this bit will force an up to be generated in the CDRLF PI interface logic." "0,1" newline bitfld.long 0x4 16. "RX_CDRLF_MGN_DIAG_0,CDRLF PI override enable : Setting this bit to 1'b1 will enable the CDRLF PI override function which will allow ups and downs to be forced to the CDRLF PI interface logic from the up and down override bits in this register." "0,1" newline hexmask.long.word 0x4 4.--15. 1. "RX_CDRLF_CNFG3_15_4,Reserved" newline bitfld.long 0x4 3. "RX_CDRLF_CNFG3_3,CDRLF data filter enable standard mode 3 : Enables the filter function for the data that feeds into the CDRLF from the deserializer using the rxda_cdrlf_data_filter_en_n signal when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x4 2. "RX_CDRLF_CNFG3_2,CDRLF data filter enable standard mode 2 : Enables the filter function for the data that feeds into the CDRLF from the deserializer using the rxda_cdrlf_data_filter_en_n signal when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x4 1. "RX_CDRLF_CNFG3_1,CDRLF data filter enable standard mode 1 : Enables the filter function for the data that feeds into the CDRLF from the deserializer using the rxda_cdrlf_data_filter_en_n signal when xcvr_standard_mode is set to 2'b01." "?,1: Enables the filter function for the data that.." newline bitfld.long 0x4 0. "RX_CDRLF_CNFG3_0,CDRLF data filter enable standard mode 0 : Enables the filter function for the data that feeds into the CDRLF from the deserializer using the rxda_cdrlf_data_filter_en_n signal when xcvr_standard_mode is set to 2'b00." "0: Enables the filter function for the data that..,?" line.long 0x8 "RX_CDRLF_FPL_TMR1__RX_CDRLF_FPL_TMR0_j,CDRLF fast phase lock timer value register 0 Offset = 8108h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 28.--31. 1. "RX_CDRLF_FPL_TMR1_15_12,Reserved" newline hexmask.long.byte 0x8 24.--27. 1. "RX_CDRLF_FPL_TMR1_11_8,Fast phase lock timer trigger 1 state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the trigger state the first time it is in that state." newline hexmask.long.byte 0x8 20.--23. 1. "RX_CDRLF_FPL_TMR1_7_4,Fast phase lock timer trigger 2 state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the trigger state the second time it is in that state." newline hexmask.long.byte 0x8 16.--19. 1. "RX_CDRLF_FPL_TMR1_3_0,Fast phase lock timer trigger 3 state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the trigger state the third time it is in that state." newline hexmask.long.byte 0x8 8.--15. 1. "RX_CDRLF_FPL_TMR0_15_8,Reserved" newline hexmask.long.byte 0x8 4.--7. 1. "RX_CDRLF_FPL_TMR0_7_4,Fast phase lock timer accumulate state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the accumulate state." newline hexmask.long.byte 0x8 0.--3. 1. "RX_CDRLF_FPL_TMR0_3_0,Fast phase lock timer delay state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the delay state." group.long 0x8120++0x1B line.long 0x0 "RX_SIGDET_HL_DLY_TMR__RX_SIGDET_HL_FILT_TMR_j,Receiver signal detect filter high to low filter timer register Offset = 8120h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 22.--31. 1. "RX_SIGDET_HL_DLY_TMR_15_6,Reserved" newline hexmask.long.byte 0x0 16.--21. 1. "RX_SIGDET_HL_DLY_TMR_5_0,Signal detect filter high to low delay timer value: This is the value loaded into the delay timer in the signal detect high to low filter circuit." newline hexmask.long.word 0x0 6.--15. 1. "RX_SIGDET_HL_FILT_TMR_15_6,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "RX_SIGDET_HL_FILT_TMR_5_0,Signal detect filter high to low filter timer value: This is the value loaded into the filter timer in the signal detect high to low filter circuit." line.long 0x4 "RX_SIGDET_HL_INIT_TMR__RX_SIGDET_HL_MIN_TMR_j,Receiver signal detect filter high to low min timer register Offset = 8124h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 22.--31. 1. "RX_SIGDET_HL_INIT_TMR_15_6,Reserved" newline hexmask.long.byte 0x4 16.--21. 1. "RX_SIGDET_HL_INIT_TMR_5_0,Signal detect init timer value: This is the value loaded into the initialization timer in the signal detect filter high to low filter circuit." newline hexmask.long.word 0x4 6.--15. 1. "RX_SIGDET_HL_MIN_TMR_15_6,Reserved" newline hexmask.long.byte 0x4 0.--5. 1. "RX_SIGDET_HL_MIN_TMR_5_0,Signal detect filter high to low min timer value: This is the value loaded into the min timer in the signal detect high to low filter circuit." line.long 0x8 "RX_SIGDET_LH_DLY_TMR__RX_SIGDET_LH_FILT_TMR_j,Receiver signal detect filter low to high filter timer register Offset = 8128h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 22.--31. 1. "RX_SIGDET_LH_DLY_TMR_15_6,Reserved" newline hexmask.long.byte 0x8 16.--21. 1. "RX_SIGDET_LH_DLY_TMR_5_0,Signal detect filter low to high min timer value: This is the value loaded into the min timer in the signal detect low to high filter circuit." newline hexmask.long.word 0x8 6.--15. 1. "RX_SIGDET_LH_FILT_TMR_15_6,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "RX_SIGDET_LH_FILT_TMR_5_0,Signal detect filter low to high filter timer value: This is the value loaded into the filter timer in the signal detect low to high filter circuit." line.long 0xC "RX_SIGDET_LH_INIT_TMR__RX_SIGDET_LH_MIN_TMR_j,Receiver signal detect filter low to high min timer register Offset = 812Ch + (j * 400h); where j = 0h to 3h" hexmask.long.word 0xC 22.--31. 1. "RX_SIGDET_LH_INIT_TMR_15_6,Reserved" newline hexmask.long.byte 0xC 16.--21. 1. "RX_SIGDET_LH_INIT_TMR_5_0,Signal detect init timer value: This is the value loaded into the initialization timer in the signal detect filter high to low filter circuit." newline hexmask.long.word 0xC 6.--15. 1. "RX_SIGDET_LH_MIN_TMR_15_6,Reserved" newline hexmask.long.byte 0xC 0.--5. 1. "RX_SIGDET_LH_MIN_TMR_5_0,Signal detect filter high to low min timer value: This is the value loaded into the min timer in the signal detect high to low filter circuit." line.long 0x10 "RX_LFPSDET_NS_CNT__RX_LFPSDET_MD_CNT_j,Receiver LFPS detect minimum pulse distance counter register Offset = 8130h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x10 18.--31. 1. "RX_LFPSDET_NS_CNT_15_2,Reserved" newline bitfld.long 0x10 16.--17. "RX_LFPSDET_NS_CNT_1_0,No signal counter value (NS): Specifies the number of clock cycles where pulse_high and pulse_low are inactive before declaring no signal." "0,1,2,3" newline hexmask.long.word 0x10 4.--15. 1. "RX_LFPSDET_MD_CNT_15_4,Reserved" newline hexmask.long.byte 0x10 0.--3. 1. "RX_LFPSDET_MD_CNT_3_0,Minimum pulse distance counter value (MD): Specifies the minimum pulse distance for a valid LFPS sequence." line.long 0x14 "RX_LFPSDET_MP_CNT__RX_LFPSDET_RD_CNT_j,Receiver LFPS detect ramp down counter register Offset = 8134h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x14 19.--31. 1. "RX_LFPSDET_MP_CNT_15_3,Reserved" newline bitfld.long 0x14 16.--18. "RX_LFPSDET_MP_CNT_2_0,Minimum pulse duration (MP): Specifies the minimum number of clock cycles required for a given LFPS pulse to be driven active to be considered part of a valid LFPS burst." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 4.--15. 1. "RX_LFPSDET_RD_CNT_15_4,Reserved" newline hexmask.long.byte 0x14 0.--3. 1. "RX_LFPSDET_RD_CNT_3_0,Ramp down counter value (RD): Species the number of clock cycles that are used in the LFPS detect ramp down process." line.long 0x18 "RX_LFPSDET_DIAG_CTRL_j,Receiver LFPS detect diagnostic control register Offset = 8138h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x18 16.--31. 1. "RESERVED" newline hexmask.long.word 0x18 3.--15. 1. "RX_LFPSDET_DIAG_CTRL_15_3,Reserved" newline bitfld.long 0x18 2. "RX_LFPSDET_DIAG_CTRL_2,Disable pulse none MD check: When active (1'b1) the check that tests if pulse_none is driven inactive while the MD check is being performed will be disabled." "0,1" newline bitfld.long 0x18 1. "RX_LFPSDET_DIAG_CTRL_1,LFPS detect override enable: When active (1'b1) the LFPS detect override bit in this register will drive the LFPS detect output directly." "0,1" newline bitfld.long 0x18 0. "RX_LFPSDET_DIAG_CTRL_0,LFPS detect override: When enabled by the LFPS detect override enable bit in this register this bit will drive the LFPS detect output directly." "0,1" group.long 0x8140++0x3 line.long 0x0 "RX_EYESURF_CTRL_j,Eye surf control register Offset = 8140h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline bitfld.long 0x0 15. "RX_EYESURF_CTRL_15,Eye surf run: Setting this bit to 1'b1 will initiate the eye surf process." "0,1" newline rbitfld.long 0x0 14. "RX_EYESURF_CTRL_14,Eye surf done: When this bit is set to 1'b1 the eye surf process has completed." "0,1" newline hexmask.long.word 0x0 0.--13. 1. "RX_EYESURF_CTRL_13_0,Reserved" group.long 0x8148++0xB line.long 0x0 "RX_EYESURF_TMR_DELHIGH__RX_EYESURF_TMR_DELLOW_j,Eye surf timer delay low register Offset = 8148h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RX_EYESURF_TMR_DELHIGH_15_0,Most significant 16 bits of the delay time: The delay time specifies the number of clock cycles to wait between when a coordinate test point is set and when to start testing the i and e data." newline hexmask.long.word 0x0 0.--15. 1. "RX_EYESURF_TMR_DELLOW_15_0,Least significant 16 bits of the delay time: The delay time specifies the number of clock cycles to wait between when a coordinate test point is set and when to start testing the i and e data." line.long 0x4 "RX_EYESURF_TMR_TESTHIGH__RX_EYESURF_TMR_TESTLOW_j,Eye surf timer test low register Offset = 814Ch + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RX_EYESURF_TMR_TESTHIGH_15_0,Most significant 16 bits of the test time: The test time specifies the number of clock cycles to test the i and e data at a given coordinate test point." newline hexmask.long.word 0x4 0.--15. 1. "RX_EYESURF_TMR_TESTLOW_15_0,Least significant 16 bits of the test time: The test time specifies the number of clock cycles to test the i and e data at a given coordinate test point." line.long 0x8 "RX_EYESURF_EW_COORD__RX_EYESURF_NS_COORD_j,Eye surf north south test point coordinate register Offset = 8150h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 25.--31. 1. "RX_EYESURF_EW_COORD_15_9,Reserved" newline bitfld.long 0x8 24. "RX_EYESURF_EW_COORD_8,Test point coordinate east west direction : Indicates whether the desired test point is in the" "0,1" newline rbitfld.long 0x8 21.--23. "RX_EYESURF_EW_COORD_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "RX_EYESURF_EW_COORD_4_0,Test point coordinate east west offset : Indicates how many steps in the east or west" newline hexmask.long.byte 0x8 9.--15. 1. "RX_EYESURF_NS_COORD_15_9,Reserved" newline bitfld.long 0x8 8. "RX_EYESURF_NS_COORD_8,Test point coordinate north south direction : Indicates whether the desired test point is in the north or the south direction relative to the origin." "0,1" newline rbitfld.long 0x8 7. "RX_EYESURF_NS_COORD_7,Reserved" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "RX_EYESURF_NS_COORD_6_0,Test point coordinate north south offset : Indicates how many steps in the north or south direction the desired test point is relative to the origin." rgroup.long 0x8154++0x3 line.long 0x0 "RX_EYESURF_ERRCNT_j,Eye surf bit error count register Offset = 8154h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "RX_EYESURF_ERRCNT_15_0,Test point bit error count : The total number of bit errors that were detected for a given run of the eye surf function." group.long 0x8160++0x7 line.long 0x0 "RX_BIST_SYNCCNT__RX_BIST_CTRL_j,Receiver BIST control register Offset = 8160h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RX_BIST_SYNCCNT_15_0,Receiver BIST sync count: This field controls the value of the RX BIST sync count." newline hexmask.long.byte 0x0 12.--15. 1. "RX_BIST_CTRL_15_12,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "RX_BIST_CTRL_11_8,Receiver BIST mode: Controls which mode the BIST will operate in." newline rbitfld.long 0x0 5.--7. "RX_BIST_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "RX_BIST_CTRL_4,Receiver BIST error reset: Writing this bit is set to a 1'b1 will hold the error indicators in the receive BIST logic in reset." "0,1" newline rbitfld.long 0x0 2.--3. "RX_BIST_CTRL_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RX_BIST_CTRL_1,Receiver BIST user defined data FIFO clear: Writing a 1'b1 to this bit will clear the receiver BIST user defined data FIFO." "0,1" newline bitfld.long 0x0 0. "RX_BIST_CTRL_0,Receiver BIST enable: This bit enables the receiver BIST function." "0,1" line.long 0x4 "RX_BIST_ERRCNT__RX_BIST_UDDWR_j,Receiver BIST user defined data write register Offset = 8164h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RX_BIST_ERRCNT_15_0,Receiver BIST error count: Indicates the number of BIST errors that have been observed by the receive BIST logic since the last time the BIST error indicator logic was reset or restarted." newline hexmask.long.byte 0x4 10.--15. 1. "RX_BIST_UDDWR_15_10,Reserved" newline hexmask.long.word 0x4 0.--9. 1. "RX_BIST_UDDWR_9_0,Receiver BIST user defined data: Writing a data word to this field will result in that data word being placed in the next available position in the receiver BIST user defined data FIFO." group.long 0x8200++0xB line.long 0x0 "RX_REE_PTXEQSM_EQENM_EVAL__RX_REE_PTXEQSM_CTRL_j,REE PCIe TX equalization control state machine control register Offset = 8200h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "RX_REE_PTXEQSM_EQENM_EVAL_15,Reserved - spare" "0,1" newline bitfld.long 0x0 30. "RX_REE_PTXEQSM_EQENM_EVAL_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 29. "RX_REE_PTXEQSM_EQENM_EVAL_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 28. "RX_REE_PTXEQSM_EQENM_EVAL_12,TX post cursor control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 27. "RX_REE_PTXEQSM_EQENM_EVAL_11,TX pre cursor control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 26. "RX_REE_PTXEQSM_EQENM_EVAL_10,Short channel correction : When set to 1'b1 this function is enabled when the TX equalization general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 25. "RX_REE_PTXEQSM_EQENM_EVAL_9,RX attenuation : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 24. "RX_REE_PTXEQSM_EQENM_EVAL_8,RX VGA gain : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 23. "RX_REE_PTXEQSM_EQENM_EVAL_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 22. "RX_REE_PTXEQSM_EQENM_EVAL_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 21. "RX_REE_PTXEQSM_EQENM_EVAL_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 20. "RX_REE_PTXEQSM_EQENM_EVAL_4,Reserved - spare" "0,1" newline bitfld.long 0x0 19. "RX_REE_PTXEQSM_EQENM_EVAL_3,Reserved - spare" "0,1" newline bitfld.long 0x0 18. "RX_REE_PTXEQSM_EQENM_EVAL_2,RX tap3 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 17. "RX_REE_PTXEQSM_EQENM_EVAL_1,RX tap2 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 16. "RX_REE_PTXEQSM_EQENM_EVAL_0,RX tap1 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RX_REE_PTXEQSM_CTRL_15_0,Reserved" line.long 0x4 "RX_REE_PTXEQSM_PEVAL_TMR__RX_REE_PTXEQSM_EQENM_PEVAL_j,REE PCIe TX equalization control state machine equalization enable mask for PCIe post evaluation equalization register Offset = 8204h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RX_REE_PTXEQSM_PEVAL_TMR_15_0,Run post evaluation equalization timer value : This specifies number of clock cycles the state machine will wait in the Post Evaluation Equalization state." newline bitfld.long 0x4 15. "RX_REE_PTXEQSM_EQENM_PEVAL_15,Reserved - spare" "0,1" newline bitfld.long 0x4 14. "RX_REE_PTXEQSM_EQENM_PEVAL_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 13. "RX_REE_PTXEQSM_EQENM_PEVAL_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 12. "RX_REE_PTXEQSM_EQENM_PEVAL_12,TX post cursor control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 11. "RX_REE_PTXEQSM_EQENM_PEVAL_11,TX pre cursor control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 10. "RX_REE_PTXEQSM_EQENM_PEVAL_10,Short channel correction : When set to 1'b1 this function is enabled when the TX equalization general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 9. "RX_REE_PTXEQSM_EQENM_PEVAL_9,RX attenuation : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 8. "RX_REE_PTXEQSM_EQENM_PEVAL_8,RX VGA gain : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 7. "RX_REE_PTXEQSM_EQENM_PEVAL_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 6. "RX_REE_PTXEQSM_EQENM_PEVAL_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 5. "RX_REE_PTXEQSM_EQENM_PEVAL_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 4. "RX_REE_PTXEQSM_EQENM_PEVAL_4,Reserved - spare" "0,1" newline bitfld.long 0x4 3. "RX_REE_PTXEQSM_EQENM_PEVAL_3,Reserved - spare" "0,1" newline bitfld.long 0x4 2. "RX_REE_PTXEQSM_EQENM_PEVAL_2,RX tap 3 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 1. "RX_REE_PTXEQSM_EQENM_PEVAL_1,RX tap 2 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "?,?" newline bitfld.long 0x4 0. "RX_REE_PTXEQSM_EQENM_PEVAL_0,RX tap 1 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE." "?,1: When set to 1'b1" line.long 0x8 "RX_REE_PTXEQSM_MAX_EVAL_CNT__RX_REE_PTXEQSM_TIMEOUT_TMR_j,REE PCIe TX equalization control state machine time-out timer value register Offset = 8208h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 22.--31. 1. "RX_REE_PTXEQSM_MAX_EVAL_CNT_15_6,Reserved" newline hexmask.long.byte 0x8 16.--21. 1. "RX_REE_PTXEQSM_MAX_EVAL_CNT_5_0,Incremental evaluation counter load value: This is the maximum number of incremental evaluations that will be performed plus one." newline hexmask.long.word 0x8 0.--15. 1. "RX_REE_PTXEQSM_TIMEOUT_TMR_15_0,Time-out timer load value: This specifies the number of clocks to run a PCIe evaluation before a time-out is indicated." group.long 0x8210++0xB line.long 0x0 "RX_REE_GCSM1_EQENM_PH1__RX_REE_GCSM1_CTRL_j,REE general control state machine 1 control register Offset = 8210h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "RX_REE_GCSM1_EQENM_PH1_15,Reserved - spare" "0,1" newline bitfld.long 0x0 30. "RX_REE_GCSM1_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 29. "RX_REE_GCSM1_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 28. "RX_REE_GCSM1_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 27. "RX_REE_GCSM1_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 26. "RX_REE_GCSM1_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 25. "RX_REE_GCSM1_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 24. "RX_REE_GCSM1_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 23. "RX_REE_GCSM1_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 22. "RX_REE_GCSM1_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 21. "RX_REE_GCSM1_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 20. "RX_REE_GCSM1_EQENM_PH1_4,Reserved - spare" "0,1" newline bitfld.long 0x0 19. "RX_REE_GCSM1_EQENM_PH1_3,Reserved - spare" "0,1" newline bitfld.long 0x0 18. "RX_REE_GCSM1_EQENM_PH1_2,RX tap 3 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x0 17. "RX_REE_GCSM1_EQENM_PH1_1,RX tap 2 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "?,?" newline bitfld.long 0x0 16. "RX_REE_GCSM1_EQENM_PH1_0,RX tap 1 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "?,1: When set to 1'b1" newline hexmask.long.word 0x0 4.--15. 1. "RX_REE_GCSM1_CTRL_15_4,Reserved" newline bitfld.long 0x0 3. "RX_REE_GCSM1_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n signal when the equalization mode changes." "0,1" newline bitfld.long 0x0 2. "RX_REE_GCSM1_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously." "0,1" newline bitfld.long 0x0 1. "RX_REE_GCSM1_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization." "0,1" newline bitfld.long 0x0 0. "RX_REE_GCSM1_CTRL_0,Enable: This bit enables the general control state machine function." "0,1" line.long 0x4 "RX_REE_GCSM1_START_TMR__RX_REE_GCSM1_EQENM_PH2_j,REE general control state machine 1 phase 2 equalization enable mask register Offset = 8214h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RX_REE_GCSM1_START_TMR_15_0,Start timer value : The number of clock cycles the state machine will wait in the Start Delay state." newline bitfld.long 0x4 15. "RX_REE_GCSM1_EQENM_PH2_15,Reserved - spare" "0,1" newline bitfld.long 0x4 14. "RX_REE_GCSM1_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 13. "RX_REE_GCSM1_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 12. "RX_REE_GCSM1_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 11. "RX_REE_GCSM1_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 10. "RX_REE_GCSM1_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 9. "RX_REE_GCSM1_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 8. "RX_REE_GCSM1_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 7. "RX_REE_GCSM1_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 6. "RX_REE_GCSM1_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 5. "RX_REE_GCSM1_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 4. "RX_REE_GCSM1_EQENM_PH2_4,Reserved - spare" "0,1" newline bitfld.long 0x4 3. "RX_REE_GCSM1_EQENM_PH2_3,Reserved - spare" "0,1" newline bitfld.long 0x4 2. "RX_REE_GCSM1_EQENM_PH2_2,RX tap 3 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "0,1" newline bitfld.long 0x4 1. "RX_REE_GCSM1_EQENM_PH2_1,RX tap 2 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "?,?" newline bitfld.long 0x4 0. "RX_REE_GCSM1_EQENM_PH2_0,RX tap 1 : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE." "?,1: When set to 1'b1" line.long 0x8 "RX_REE_GCSM1_RUN_PH2_TMR__RX_REE_GCSM1_RUN_PH1_TMR_j,REE general control state machine 1 run phase 1 timer value register Offset = 8218h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 16.--31. 1. "RX_REE_GCSM1_RUN_PH2_TMR_15_0,Run phase 2 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 2 state." newline hexmask.long.word 0x8 0.--15. 1. "RX_REE_GCSM1_RUN_PH1_TMR_15_0,Run phase 1 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 1 state." group.long 0x8220++0xB line.long 0x0 "RX_REE_GCSM2_EQENM_PH1__RX_REE_GCSM2_CTRL_j,REE general control state machine 2 control register Offset = 8220h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "RX_REE_GCSM2_EQENM_PH1_15,Reserved - spare" "0,1" newline bitfld.long 0x0 30. "RX_REE_GCSM2_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 29. "RX_REE_GCSM2_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 28. "RX_REE_GCSM2_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 27. "RX_REE_GCSM2_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 26. "RX_REE_GCSM2_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 25. "RX_REE_GCSM2_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 24. "RX_REE_GCSM2_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 23. "RX_REE_GCSM2_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 22. "RX_REE_GCSM2_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 21. "RX_REE_GCSM2_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 20. "RX_REE_GCSM2_EQENM_PH1_4,Reserved - spare" "0,1" newline bitfld.long 0x0 19. "RX_REE_GCSM2_EQENM_PH1_3,Reserved - spare" "0,1" newline bitfld.long 0x0 18. "RX_REE_GCSM2_EQENM_PH1_2,RX tap 3 : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x0 17. "RX_REE_GCSM2_EQENM_PH1_1,RX tap 2 : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "?,?" newline bitfld.long 0x0 16. "RX_REE_GCSM2_EQENM_PH1_0,RX tap 1 : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "?,1: When set to 1'b1" newline hexmask.long.word 0x0 4.--15. 1. "RX_REE_GCSM2_CTRL_15_4,Reserved" newline bitfld.long 0x0 3. "RX_REE_GCSM2_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n signal when the equalization mode changes." "0,1" newline bitfld.long 0x0 2. "RX_REE_GCSM2_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously." "0,1" newline bitfld.long 0x0 1. "RX_REE_GCSM2_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization." "0,1" newline bitfld.long 0x0 0. "RX_REE_GCSM2_CTRL_0,Enable: This bit enables the general control state machine function." "0,1" line.long 0x4 "RX_REE_GCSM2_START_TMR__RX_REE_GCSM2_EQENM_PH2_j,REE general control state machine 2 phase 2 equalization enable mask register Offset = 8224h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RX_REE_GCSM2_START_TMR_15_0,Start timer value : The number of clock cycles the state machine will wait in the Start Delay state." newline bitfld.long 0x4 15. "RX_REE_GCSM2_EQENM_PH2_15,Reserved - spare" "0,1" newline bitfld.long 0x4 14. "RX_REE_GCSM2_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 13. "RX_REE_GCSM2_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 12. "RX_REE_GCSM2_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 11. "RX_REE_GCSM2_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 10. "RX_REE_GCSM2_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 9. "RX_REE_GCSM2_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 8. "RX_REE_GCSM2_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 7. "RX_REE_GCSM2_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 6. "RX_REE_GCSM2_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 5. "RX_REE_GCSM2_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 4. "RX_REE_GCSM2_EQENM_PH2_4,Reserved - spare" "0,1" newline bitfld.long 0x4 3. "RX_REE_GCSM2_EQENM_PH2_3,Reserved - spare" "0,1" newline bitfld.long 0x4 2. "RX_REE_GCSM2_EQENM_PH2_2,RX tap 3 : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "0,1" newline bitfld.long 0x4 1. "RX_REE_GCSM2_EQENM_PH2_1,RX tap 2 : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "?,?" newline bitfld.long 0x4 0. "RX_REE_GCSM2_EQENM_PH2_0,RX tap 1 : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE." "?,1: When set to 1'b1" line.long 0x8 "RX_REE_GCSM2_RUN_PH2_TMR__RX_REE_GCSM2_RUN_PH1_TMR_j,REE general control state machine 2 run phase 1 timer value register Offset = 8228h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 16.--31. 1. "RX_REE_GCSM2_RUN_PH2_TMR_15_0,Run phase 2 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 2 state." newline hexmask.long.word 0x8 0.--15. 1. "RX_REE_GCSM2_RUN_PH1_TMR_15_0,Run phase 1 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 1 state." group.long 0x8230++0xB line.long 0x0 "RX_REE_PERGCSM_EQENM_PH1__RX_REE_PERGCSM_CTRL_j,REE periodic general control state machine control register Offset = 8230h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "RX_REE_PERGCSM_EQENM_PH1_15,Reserved - spare" "0,1" newline bitfld.long 0x0 30. "RX_REE_PERGCSM_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 29. "RX_REE_PERGCSM_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 28. "RX_REE_PERGCSM_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 27. "RX_REE_PERGCSM_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 26. "RX_REE_PERGCSM_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 25. "RX_REE_PERGCSM_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 24. "RX_REE_PERGCSM_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 23. "RX_REE_PERGCSM_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 22. "RX_REE_PERGCSM_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 21. "RX_REE_PERGCSM_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 20. "RX_REE_PERGCSM_EQENM_PH1_4,Reserved - spare" "0,1" newline bitfld.long 0x0 19. "RX_REE_PERGCSM_EQENM_PH1_3,Reserved - spare" "0,1" newline bitfld.long 0x0 18. "RX_REE_PERGCSM_EQENM_PH1_2,RX tap 3 : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 17. "RX_REE_PERGCSM_EQENM_PH1_1,RX tap 2 : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "?,?" newline bitfld.long 0x0 16. "RX_REE_PERGCSM_EQENM_PH1_0,RX tap 1 : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "?,1: When set to 1'b1" newline hexmask.long.word 0x0 4.--15. 1. "RX_REE_PERGCSM_CTRL_15_4,Reserved" newline bitfld.long 0x0 3. "RX_REE_PERGCSM_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n pin when the equalization mode changes." "0,1" newline bitfld.long 0x0 2. "RX_REE_PERGCSM_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously." "0,1" newline bitfld.long 0x0 1. "RX_REE_PERGCSM_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization." "0,1" newline bitfld.long 0x0 0. "RX_REE_PERGCSM_CTRL_0,Enable: This bit enables the general control state machine function." "0,1" line.long 0x4 "RX_REE_PERGCSM_START_TMR__RX_REE_PERGCSM_EQENM_PH2_j,REE periodic general control state machine phase 2 equalization enable mask register Offset = 8234h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RX_REE_PERGCSM_START_TMR_15_0,Start timer value : The number of clock cycles the state machine will wait in the Start Delay state." newline bitfld.long 0x4 15. "RX_REE_PERGCSM_EQENM_PH2_15,Reserved - spare" "0,1" newline bitfld.long 0x4 14. "RX_REE_PERGCSM_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 13. "RX_REE_PERGCSM_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 12. "RX_REE_PERGCSM_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 11. "RX_REE_PERGCSM_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 10. "RX_REE_PERGCSM_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 9. "RX_REE_PERGCSM_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 8. "RX_REE_PERGCSM_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 7. "RX_REE_PERGCSM_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 6. "RX_REE_PERGCSM_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 5. "RX_REE_PERGCSM_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 4. "RX_REE_PERGCSM_EQENM_PH2_4,Reserved - spare" "0,1" newline bitfld.long 0x4 3. "RX_REE_PERGCSM_EQENM_PH2_3,Reserved - spare" "0,1" newline bitfld.long 0x4 2. "RX_REE_PERGCSM_EQENM_PH2_2,RX tap 3 : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 1. "RX_REE_PERGCSM_EQENM_PH2_1,RX tap 2 : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "?,?" newline bitfld.long 0x4 0. "RX_REE_PERGCSM_EQENM_PH2_0,RX tap 1 : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE." "?,1: When set to 1'b1" line.long 0x8 "RX_REE_PERGCSM_RUN_PH2_TMR__RX_REE_PERGCSM_RUN_PH1_TMR_j,REE periodic general control state machine run phase 1 timer value register Offset = 8238h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 16.--31. 1. "RX_REE_PERGCSM_RUN_PH2_TMR_15_0,Run phase 2 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 2 state." newline hexmask.long.word 0x8 0.--15. 1. "RX_REE_PERGCSM_RUN_PH1_TMR_15_0,Run phase 1 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 1 state." group.long 0x8240++0xB line.long 0x0 "RX_REE_U3GCSM_EQENM_PH1__RX_REE_U3GCSM_CTRL_j,REE USB 3 general control state machine control register Offset = 8240h + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "RX_REE_U3GCSM_EQENM_PH1_15,Reserved - spare" "0,1" newline bitfld.long 0x0 30. "RX_REE_U3GCSM_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 29. "RX_REE_U3GCSM_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 28. "RX_REE_U3GCSM_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 27. "RX_REE_U3GCSM_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 26. "RX_REE_U3GCSM_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 25. "RX_REE_U3GCSM_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 24. "RX_REE_U3GCSM_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 23. "RX_REE_U3GCSM_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 22. "RX_REE_U3GCSM_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 21. "RX_REE_U3GCSM_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 20. "RX_REE_U3GCSM_EQENM_PH1_4,Reserved - spare" "0,1" newline bitfld.long 0x0 19. "RX_REE_U3GCSM_EQENM_PH1_3,Reserved - spare" "0,1" newline bitfld.long 0x0 18. "RX_REE_U3GCSM_EQENM_PH1_2,RX tap 3 : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x0 17. "RX_REE_U3GCSM_EQENM_PH1_1,RX tap 2 : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "?,?" newline bitfld.long 0x0 16. "RX_REE_U3GCSM_EQENM_PH1_0,RX tap 1 : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "?,1: When set to 1'b1" newline hexmask.long.word 0x0 4.--15. 1. "RX_REE_U3GCSM_CTRL_15_4,Reserved" newline bitfld.long 0x0 3. "RX_REE_U3GCSM_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n pin when the equalization mode changes." "0,1" newline bitfld.long 0x0 2. "RX_REE_U3GCSM_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously." "0,1" newline bitfld.long 0x0 1. "RX_REE_U3GCSM_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization." "0,1" newline bitfld.long 0x0 0. "RX_REE_U3GCSM_CTRL_0,Enable: This bit enables the general control state machine function." "0,1" line.long 0x4 "RX_REE_U3GCSM_START_TMR__RX_REE_U3GCSM_EQENM_PH2_j,REE USB 3 general control state machine phase 2 equalization enable mask register Offset = 8244h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RX_REE_U3GCSM_START_TMR_15_0,Start timer value : The number of clock cycles the state machine will wait in the Start Delay state." newline bitfld.long 0x4 15. "RX_REE_U3GCSM_EQENM_PH2_15,Reserved - spare" "0,1" newline bitfld.long 0x4 14. "RX_REE_U3GCSM_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 13. "RX_REE_U3GCSM_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 12. "RX_REE_U3GCSM_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 11. "RX_REE_U3GCSM_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 10. "RX_REE_U3GCSM_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 9. "RX_REE_U3GCSM_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 8. "RX_REE_U3GCSM_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 7. "RX_REE_U3GCSM_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 6. "RX_REE_U3GCSM_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 5. "RX_REE_U3GCSM_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 4. "RX_REE_U3GCSM_EQENM_PH2_4,Reserved - spare" "0,1" newline bitfld.long 0x4 3. "RX_REE_U3GCSM_EQENM_PH2_3,Reserved - spare" "0,1" newline bitfld.long 0x4 2. "RX_REE_U3GCSM_EQENM_PH2_2,RX tap 3 : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "0,1" newline bitfld.long 0x4 1. "RX_REE_U3GCSM_EQENM_PH2_1,RX tap 2 : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "?,?" newline bitfld.long 0x4 0. "RX_REE_U3GCSM_EQENM_PH2_0,RX tap 1 : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE." "?,1: When set to 1'b1" line.long 0x8 "RX_REE_U3GCSM_RUN_PH2_TMR__RX_REE_U3GCSM_RUN_PH1_TMR_j,REE USB 3 general control state machine run phase 1 timer value register Offset = 8248h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 16.--31. 1. "RX_REE_U3GCSM_RUN_PH2_TMR_15_0,Run phase 2 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 2 state." newline hexmask.long.word 0x8 0.--15. 1. "RX_REE_U3GCSM_RUN_PH1_TMR_15_0,Run phase 1 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 1 state." group.long 0x8250++0x3 line.long 0x0 "RX_REE_ANAENSM_DEL_TMR_j,REE analog enable control state machine delay timer value register Offset = 8250h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--15. 1. "RX_REE_ANAENSM_DEL_TMR_15_0,Analog enable delay timer value : The number of clock cycles the state machine will wait in the Analog Enable Delay state." group.long 0x8260++0x17 line.long 0x0 "RX_REE_TXPOST_CODE_CTRL__RX_REE_TXPOST_CTRL_j,REE TX post cursor control register Offset = 8260h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x0 30.--31. "RX_REE_TXPOST_CODE_CTRL_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "RX_REE_TXPOST_CODE_CTRL_13_8,Peaking amp code maximum value: This is the maximum value that the peaking amp code will be allowed to increase to." newline rbitfld.long 0x0 22.--23. "RX_REE_TXPOST_CODE_CTRL_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "RX_REE_TXPOST_CODE_CTRL_5_0,Peaking amp initial code: Initial value the peaking amp code is set to when training starts." newline hexmask.long.byte 0x0 12.--15. 1. "RX_REE_TXPOST_CTRL_15_12,Reserved" newline bitfld.long 0x0 11. "RX_REE_TXPOST_CTRL_11,Peaking amp feedback path enable: Enables the peaking amp feedback path." "0,1" newline bitfld.long 0x0 8.--10. "RX_REE_TXPOST_CTRL_10_8,Peaking amp feedback scaler value: Specifies the amount to scale the peaking amp feedback by." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 7. "RX_REE_TXPOST_CTRL_7,Reserved" "0,1" newline bitfld.long 0x0 4.--6. "RX_REE_TXPOST_CTRL_6_4,Peaking amp integrator accumulator scaler value: Specifies the amount to scale the input to the peaking amp integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "RX_REE_TXPOST_CTRL_3_0,Peaking amp sigma delta accumulator scaler value: Specifies the amount to scale the input to the peaking amp sigma delta accumulator by." line.long 0x4 "RX_REE_TXPOST_LTHR__RX_REE_TXPOST_UTHR_j,REE TX post cursor upper threshold register Offset = 8264h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 25.--31. 1. "RX_REE_TXPOST_LTHR_15_9,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "RX_REE_TXPOST_LTHR_8_0,Peaking amp algorithm lower threshold: This is the lower threshold value used in the peaking amp algorithm." newline hexmask.long.byte 0x4 9.--15. 1. "RX_REE_TXPOST_UTHR_15_9,Reserved" newline hexmask.long.word 0x4 0.--8. 1. "RX_REE_TXPOST_UTHR_8_0,Peaking amp algorithm upper threshold: This is the upper threshold value used in the peaking amp algorithm." line.long 0x8 "RX_REE_TXPOST_COVRD0__RX_REE_TXPOST_IOVRD_j,REE TX post cursor input override register Offset = 8268h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x8 30.--31. "RX_REE_TXPOST_COVRD0_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "RX_REE_TXPOST_COVRD0_13_8,Peaking amp code override value mode 1: Value that will override the peaking amp code when in standard mode 1 when the peaking amp code override enable bit in the REE TX post cursor diagnostics register on page 259 is active." newline rbitfld.long 0x8 22.--23. "RX_REE_TXPOST_COVRD0_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "RX_REE_TXPOST_COVRD0_5_0,Peaking amp code override value mode 0: Value that will override the peaking amp code when in standard mode 0 when the peaking amp code override enable bit in the REE TX post cursor diagnostics register on page 259 is active." newline bitfld.long 0x8 15. "RX_REE_TXPOST_IOVRD_15,Peaking amp tap accumulator input override enable: Setting this bit to a 1'b1 will allow the tap accumulator input in the peaking amp gain algorithm to be overridden by the peaking amp tap accumulator input override field in this.." "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "RX_REE_TXPOST_IOVRD_14_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "RX_REE_TXPOST_IOVRD_7_0,Peaking amp tap accumulator input override : Value that will override the tap accumulator input in the peaking amp gain algorithm when the Peaking amp tap accumulator input override enable bit is active." line.long 0xC "RX_REE_TXPOST_DIAG__RX_REE_TXPOST_COVRD1_j,REE TX post cursor code override 1 register Offset = 826Ch + (j * 400h); where j = 0h to 3h" bitfld.long 0xC 31. "RX_REE_TXPOST_DIAG_15,Peaking amp code override enable: Setting this bit to a 1'b1 will allow the peaking amp code to be overridden by the peaking amp code override value fields in the REE TX post cursor code override 0 register on page 258 and REE TX.." "0,1" newline bitfld.long 0xC 30. "RX_REE_TXPOST_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the peaking amp voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0xC 29. "RX_REE_TXPOST_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the peaking amp voter function to activate the voter pos signal for a single clock cycle." "0,1" newline bitfld.long 0xC 28. "RX_REE_TXPOST_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the peaking amp." "0,1" newline hexmask.long.byte 0xC 24.--27. 1. "RX_REE_TXPOST_DIAG_11_8,Reserved" newline rbitfld.long 0xC 22.--23. "RX_REE_TXPOST_DIAG_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 16.--21. 1. "RX_REE_TXPOST_DIAG_5_0,Current peaking amp integrator accumulator: Current value of the tap integrator accumulator without the unused sign bit." newline rbitfld.long 0xC 14.--15. "RX_REE_TXPOST_COVRD1_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 8.--13. 1. "RX_REE_TXPOST_COVRD1_13_8,Peaking amp code override value mode 3: Value that will override the peaking amp code when in standard mode 3 when the peaking amp code override enable bit in the REE TX post cursor diagnostics register on page 259 is active." newline rbitfld.long 0xC 6.--7. "RX_REE_TXPOST_COVRD1_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "RX_REE_TXPOST_COVRD1_5_0,Peaking amp code override value mode 2: Value that will override the peaking amp code when in standard mode 2 when the peaking amp code override enable bit in the REE TX post cursor diagnostics register on page 259 is active." line.long 0x10 "RX_REE_TXPRE_OVRD__RX_REE_TXPRE_CTRL_j,REE TX pre cursor control register Offset = 8270h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x10 24.--31. 1. "RX_REE_TXPRE_OVRD_15_8,Reserved" newline bitfld.long 0x10 23. "RX_REE_TXPRE_OVRD_7,Tap override enable: Setting this bit to a 1'b1 will enable the tap override field in this register to override the tap integrator accumulator functions." "0,1" newline rbitfld.long 0x10 22. "RX_REE_TXPRE_OVRD_6,Reserved" "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "RX_REE_TXPRE_OVRD_5_0,Tap override value: When the tap override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder." newline hexmask.long.byte 0x10 12.--15. 1. "RX_REE_TXPRE_CTRL_15_12,Reserved" newline bitfld.long 0x10 11. "RX_REE_TXPRE_CTRL_11,Tap coefficient combinational logic zero crossing enable:" "0,1" newline bitfld.long 0x10 10. "RX_REE_TXPRE_CTRL_10,Tap coefficient combinational logic non zero crossing enable:" "0,1" newline bitfld.long 0x10 9. "RX_REE_TXPRE_CTRL_9,Tap coefficient combinational logic bit 0 only enable:" "0,1" newline bitfld.long 0x10 8. "RX_REE_TXPRE_CTRL_8,Receiver DFE tap coefficient disable: This bit disables the rxda_dfe_tap_coef output signal." "0,1" newline rbitfld.long 0x10 7. "RX_REE_TXPRE_CTRL_7,Reserved" "0,1" newline bitfld.long 0x10 4.--6. "RX_REE_TXPRE_CTRL_6_4,Tap integrator accumulator scaler value: Specifies the amount to scale the input to the tap integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--3. 1. "RX_REE_TXPRE_CTRL_3_0,Tap sigma delta accumulator scaler value: Specifies the amount to scale the input to the tap sigma delta accumulator by." line.long 0x14 "RX_REE_TXPRE_DIAG_j,REE TX pre cursor diagnostics register Offset = 8274h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x14 16.--31. 1. "RESERVED" newline rbitfld.long 0x14 15. "RX_REE_TXPRE_DIAG_15,Reserved" "0,1" newline bitfld.long 0x14 14. "RX_REE_TXPRE_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0x14 13. "RX_REE_TXPRE_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter pos signal for a single clock cycle." "0,1" newline bitfld.long 0x14 12. "RX_REE_TXPRE_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the tap." "0,1" newline hexmask.long.byte 0x14 6.--11. 1. "RX_REE_TXPRE_DIAG_11_6,Reserved" newline hexmask.long.byte 0x14 0.--5. 1. "RX_REE_TXPRE_DIAG_5_0,Current tap integrator accumulator: Current value of the tap integrator accumulator." group.long 0x8280++0x17 line.long 0x0 "RX_REE_PEAK_CODE_CTRL__RX_REE_PEAK_CTRL_j,REE peaking amp control register Offset = 8280h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x0 30.--31. "RX_REE_PEAK_CODE_CTRL_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "RX_REE_PEAK_CODE_CTRL_13_8,Peaking amp code maximum value: This is the maximum value that the peaking amp code will be allowed to increase to." newline rbitfld.long 0x0 22.--23. "RX_REE_PEAK_CODE_CTRL_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "RX_REE_PEAK_CODE_CTRL_5_0,Peaking amp initial code: Initial value the peaking amp code is set to when training starts." newline hexmask.long.byte 0x0 12.--15. 1. "RX_REE_PEAK_CTRL_15_12,Reserved" newline bitfld.long 0x0 11. "RX_REE_PEAK_CTRL_11,Peaking amp feedback path enable: Enables the peaking amp feedback path." "0,1" newline bitfld.long 0x0 8.--10. "RX_REE_PEAK_CTRL_10_8,Peaking amp feedback scaler value: Specifies the amount to scale the peaking amp feedback by." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 7. "RX_REE_PEAK_CTRL_7,Reserved" "0,1" newline bitfld.long 0x0 4.--6. "RX_REE_PEAK_CTRL_6_4,Peaking amp integrator accumulator scaler value: Specifies the amount to scale the input to the peaking amp integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "RX_REE_PEAK_CTRL_3_0,Peaking amp sigma delta accumulator scaler value: Specifies the amount to scale the input to the peaking amp sigma delta accumulator by." line.long 0x4 "RX_REE_PEAK_LTHR__RX_REE_PEAK_UTHR_j,REE peaking amp upper threshold register Offset = 8284h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 25.--31. 1. "RX_REE_PEAK_LTHR_15_9,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "RX_REE_PEAK_LTHR_8_0,Peaking amp algorithm lower threshold: This is the lower threshold value used in the peaking amp algorithm." newline hexmask.long.byte 0x4 9.--15. 1. "RX_REE_PEAK_UTHR_15_9,Reserved" newline hexmask.long.word 0x4 0.--8. 1. "RX_REE_PEAK_UTHR_8_0,Peaking amp algorithm upper threshold: This is the upper threshold value used in the peaking amp algorithm." line.long 0x8 "RX_REE_PEAK_COVRD0__RX_REE_PEAK_IOVRD_j,REE peaking amp input override register Offset = 8288h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x8 30.--31. "RX_REE_PEAK_COVRD0_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "RX_REE_PEAK_COVRD0_13_8,Peaking amp code override value mode 1: Value that will override the peaking amp code when in standard mode 1 when the peaking amp code override enable bit in the REE peaking amp diagnostics register on page 264 is active." newline rbitfld.long 0x8 22.--23. "RX_REE_PEAK_COVRD0_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "RX_REE_PEAK_COVRD0_5_0,Peaking amp code override value mode 0: Value that will override the peaking amp code when in standard mode 0 when the peaking amp code override enable bit in the REE peaking amp diagnostics register on page 264 is active." newline bitfld.long 0x8 15. "RX_REE_PEAK_IOVRD_15,Peaking amp tap accumulator input override enable: Setting this bit to a 1'b1 will allow the tap accumulator input in the peaking amp gain algorithm to be overridden by the peaking amp tap accumulator input override field in this.." "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "RX_REE_PEAK_IOVRD_14_8,Reserved" newline hexmask.long.byte 0x8 0.--7. 1. "RX_REE_PEAK_IOVRD_7_0,Peaking amp tap accumulator input override : Value that will override the tap accumulator input in the peaking amp gain algorithm when the Peaking amp tap accumulator input override enable bit is active." line.long 0xC "RX_REE_PEAK_DIAG__RX_REE_PEAK_COVRD1_j,REE peaking amp code override 1 register Offset = 828Ch + (j * 400h); where j = 0h to 3h" bitfld.long 0xC 31. "RX_REE_PEAK_DIAG_15,Peaking amp code override enable: Setting this bit to a 1'b1 will allow the peaking amp code to be overridden by the peaking amp code override value fields in the REE peaking amp code override 0 register on page 263 and REE peaking.." "0,1" newline bitfld.long 0xC 30. "RX_REE_PEAK_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the peaking amp voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0xC 29. "RX_REE_PEAK_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the peaking amp voter function to activate the voter pos signal for a single clock cycle." "0,1" newline bitfld.long 0xC 28. "RX_REE_PEAK_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the peaking amp." "0,1" newline hexmask.long.byte 0xC 24.--27. 1. "RX_REE_PEAK_DIAG_11_8,Reserved" newline rbitfld.long 0xC 22.--23. "RX_REE_PEAK_DIAG_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 16.--21. 1. "RX_REE_PEAK_DIAG_5_0,Current peaking amp integrator accumulator: Current value of the tap integrator accumulator without the unused sign bit." newline rbitfld.long 0xC 14.--15. "RX_REE_PEAK_COVRD1_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 8.--13. 1. "RX_REE_PEAK_COVRD1_13_8,Peaking amp code override value mode 3: Value that will override the peaking amp code when in standard mode 3 when the peaking amp code override enable bit in the REE peaking amp diagnostics register on page 264 is active." newline rbitfld.long 0xC 6.--7. "RX_REE_PEAK_COVRD1_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "RX_REE_PEAK_COVRD1_5_0,Peaking amp code override value mode 2: Value that will override the peaking amp code when in standard mode 2 when the peaking amp code override enable bit in the REE peaking amp diagnostics register on page 264 is active." line.long 0x10 "RX_REE_ATTEN_THR__RX_REE_ATTEN_CTRL_j,REE attenuation control register Offset = 8290h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x10 29.--31. "RX_REE_ATTEN_THR_15_13,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--28. 1. "RX_REE_ATTEN_THR_12_8,Attenuation high threshold value: High threshold value to compare against the VGA gain accumulator value." newline rbitfld.long 0x10 21.--23. "RX_REE_ATTEN_THR_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "RX_REE_ATTEN_THR_4_0,Attenuation low threshold value: Low threshold value to compare against the VGA gain accumulator value." newline hexmask.long.word 0x10 5.--15. 1. "RX_REE_ATTEN_CTRL_15_5,Reserved" newline hexmask.long.byte 0x10 0.--4. 1. "RX_REE_ATTEN_CTRL_4_0,Receiver DFE attenuation maximum value: The maximum value the rxda_dfe_attenuation_bin will increase to." line.long 0x14 "RX_REE_ATTEN_OVRD__RX_REE_ATTEN_CNT_j,REE attenuation counter register Offset = 8294h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x14 25.--31. 1. "RX_REE_ATTEN_OVRD_15_9,Reserved" newline bitfld.long 0x14 24. "RX_REE_ATTEN_OVRD_8,Attenuation override enable: Setting this bit to a 1'b1 will allow the rxda_dfe_attenuation_bin signal to be overridden by the attenuation override value signal in this register." "0,1" newline rbitfld.long 0x14 21.--23. "RX_REE_ATTEN_OVRD_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "RX_REE_ATTEN_OVRD_4_0,Attenuation override value: When enabled by the attenuation override enable bit in this register this value will override the current attenuation value on the rxda_dfe_attenuation_bin output pin and also force a corresponding.." newline hexmask.long.word 0x14 0.--15. 1. "RX_REE_ATTEN_CNT_15_0,Attenuation counter max: Value used to specify the maximum number of consecutive words above or below the specified thresholds which will result in triggering an increase or decrease in the rxda_dfe_attenuation_bin signal." rgroup.long 0x8298++0x3 line.long 0x0 "RX_REE_ATTEN_DIAG_j,REE attenuation diagnostics register Offset = 8298h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.word 0x0 5.--15. 1. "RX_REE_ATTEN_DIAG_15_5,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "RX_REE_ATTEN_DIAG_4_0,Current attenuation value: Current value of the attenuation." group.long 0x82A0++0x33 line.long 0x0 "RX_REE_TAP1_OVRD__RX_REE_TAP1_CTRL_j,REE tap 1 control register Offset = 82A0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x0 24.--31. 1. "RX_REE_TAP1_OVRD_15_8,Reserved" newline bitfld.long 0x0 23. "RX_REE_TAP1_OVRD_7,Tap override enable: Setting this bit to a 1'b1 will enable the tap override field in this register to override the tap integrator accumulator functions." "0,1" newline rbitfld.long 0x0 22. "RX_REE_TAP1_OVRD_6,Reserved" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "RX_REE_TAP1_OVRD_5_0,Tap override value: When the tap override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder." newline hexmask.long.byte 0x0 12.--15. 1. "RX_REE_TAP1_CTRL_15_12,Reserved" newline bitfld.long 0x0 11. "RX_REE_TAP1_CTRL_11,Tap coefficient combinational logic zero crossing enable:" "0,1" newline bitfld.long 0x0 10. "RX_REE_TAP1_CTRL_10,Tap coefficient combinational logic non zero crossing enable:" "0,1" newline bitfld.long 0x0 9. "RX_REE_TAP1_CTRL_9,Tap coefficient combinational logic bit 0 only enable:" "0,1" newline bitfld.long 0x0 8. "RX_REE_TAP1_CTRL_8,Receiver DFE tap coefficient disable: This bit disables the rxda_dfe_tap_coef output signal." "0,1" newline rbitfld.long 0x0 7. "RX_REE_TAP1_CTRL_7,Reserved" "0,1" newline bitfld.long 0x0 4.--6. "RX_REE_TAP1_CTRL_6_4,Tap integrator accumulator scaler value: Specifies the amount to scale the input to the tap integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "RX_REE_TAP1_CTRL_3_0,Tap sigma delta accumulator scaler value: Specifies the amount to scale the input to the tap sigma delta accumulator by." line.long 0x4 "RX_REE_TAP1_DIAG_j,REE tap 1 diagnostics register Offset = 82A4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline rbitfld.long 0x4 15. "RX_REE_TAP1_DIAG_15,Reserved" "0,1" newline bitfld.long 0x4 14. "RX_REE_TAP1_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0x4 13. "RX_REE_TAP1_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter pos signal for a single clock cycle." "0,1" newline bitfld.long 0x4 12. "RX_REE_TAP1_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the tap." "0,1" newline hexmask.long.byte 0x4 6.--11. 1. "RX_REE_TAP1_DIAG_11_6,Reserved" newline hexmask.long.byte 0x4 0.--5. 1. "RX_REE_TAP1_DIAG_5_0,Current tap integrator accumulator: Current value of the tap integrator accumulator." line.long 0x8 "RX_REE_TAP2_OVRD__RX_REE_TAP2_CTRL_j,REE tap 2 control register Offset = 82A8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 24.--31. 1. "RX_REE_TAP2_OVRD_15_8,Reserved" newline bitfld.long 0x8 23. "RX_REE_TAP2_OVRD_7,Tap override enable: Setting this bit to a 1'b1 will enable the tap override field in this register to override the tap integrator accumulator functions." "0,1" newline rbitfld.long 0x8 22. "RX_REE_TAP2_OVRD_6,Reserved" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RX_REE_TAP2_OVRD_5_0,Tap override value: When the tap override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder." newline hexmask.long.byte 0x8 12.--15. 1. "RX_REE_TAP2_CTRL_15_12,Reserved" newline bitfld.long 0x8 11. "RX_REE_TAP2_CTRL_11,Tap coefficient combinational logic zero crossing enable:" "0,1" newline bitfld.long 0x8 10. "RX_REE_TAP2_CTRL_10,Tap coefficient combinational logic non zero crossing enable:" "0,1" newline bitfld.long 0x8 9. "RX_REE_TAP2_CTRL_9,Tap coefficient combinational logic bit 0 only enable:" "0,1" newline bitfld.long 0x8 8. "RX_REE_TAP2_CTRL_8,Receiver DFE tap coefficient disable: This bit disables the rxda_dfe_tap_coef output signal." "0,1" newline rbitfld.long 0x8 7. "RX_REE_TAP2_CTRL_7,Reserved" "0,1" newline bitfld.long 0x8 4.--6. "RX_REE_TAP2_CTRL_6_4,Tap integrator accumulator scaler value: Specifies the amount to scale the input to the tap integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--3. 1. "RX_REE_TAP2_CTRL_3_0,Tap sigma delta accumulator scaler value: Specifies the amount to scale the input to the tap sigma delta accumulator by." line.long 0xC "RX_REE_TAP2_DIAG_j,REE tap 2 diagnostics register Offset = 82ACh + (j * 400h); where j = 0h to 3h" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline rbitfld.long 0xC 15. "RX_REE_TAP2_DIAG_15,Reserved" "0,1" newline bitfld.long 0xC 14. "RX_REE_TAP2_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0xC 13. "RX_REE_TAP2_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter pos signal for a single clock cycle." "0,1" newline bitfld.long 0xC 12. "RX_REE_TAP2_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the tap." "0,1" newline hexmask.long.byte 0xC 6.--11. 1. "RX_REE_TAP2_DIAG_11_6,Reserved" newline hexmask.long.byte 0xC 0.--5. 1. "RX_REE_TAP2_DIAG_5_0,Current tap integrator accumulator: Current value of the tap integrator accumulator." line.long 0x10 "RX_REE_TAP3_OVRD__RX_REE_TAP3_CTRL_j,REE tap 3 control register Offset = 82B0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x10 24.--31. 1. "RX_REE_TAP3_OVRD_15_8,Reserved" newline bitfld.long 0x10 23. "RX_REE_TAP3_OVRD_7,Tap override enable: Setting this bit to a 1'b1 will enable the tap override field in this register to override the tap integrator accumulator functions." "0,1" newline rbitfld.long 0x10 22. "RX_REE_TAP3_OVRD_6,Reserved" "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "RX_REE_TAP3_OVRD_5_0,Tap override value: When the tap override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder." newline hexmask.long.byte 0x10 12.--15. 1. "RX_REE_TAP3_CTRL_15_12,Reserved" newline bitfld.long 0x10 11. "RX_REE_TAP3_CTRL_11,Tap coefficient combinational logic zero crossing enable:" "0,1" newline bitfld.long 0x10 10. "RX_REE_TAP3_CTRL_10,Tap coefficient combinational logic non zero crossing enable:" "0,1" newline bitfld.long 0x10 9. "RX_REE_TAP3_CTRL_9,Tap coefficient combinational logic bit 0 only enable:" "0,1" newline bitfld.long 0x10 8. "RX_REE_TAP3_CTRL_8,Receiver DFE tap coefficient disable: This bit disables the rxda_dfe_tap_coef output signal." "0,1" newline rbitfld.long 0x10 7. "RX_REE_TAP3_CTRL_7,Reserved" "0,1" newline bitfld.long 0x10 4.--6. "RX_REE_TAP3_CTRL_6_4,Tap integrator accumulator scaler value: Specifies the amount to scale the input to the tap integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--3. 1. "RX_REE_TAP3_CTRL_3_0,Tap sigma delta accumulator scaler value: Specifies the amount to scale the input to the tap sigma delta accumulator by." line.long 0x14 "RX_REE_TAP3_DIAG_j,REE tap 3 diagnostics register Offset = 82B4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x14 16.--31. 1. "RESERVED" newline rbitfld.long 0x14 15. "RX_REE_TAP3_DIAG_15,Reserved" "0,1" newline bitfld.long 0x14 14. "RX_REE_TAP3_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0x14 13. "RX_REE_TAP3_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter pos signal for a single clock cycle." "0,1" newline bitfld.long 0x14 12. "RX_REE_TAP3_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the tap." "0,1" newline hexmask.long.byte 0x14 6.--11. 1. "RX_REE_TAP3_DIAG_11_6,Reserved" newline hexmask.long.byte 0x14 0.--5. 1. "RX_REE_TAP3_DIAG_5_0,Current tap integrator accumulator: Current value of the tap integrator accumulator." line.long 0x18 "RX_REE_LFEQ_OVRD__RX_REE_LFEQ_CTRL_j,REE low frequency equalizer control register Offset = 82B8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x18 24.--31. 1. "RX_REE_LFEQ_OVRD_15_8,Reserved" newline bitfld.long 0x18 23. "RX_REE_LFEQ_OVRD_7,Override enable: Setting this bit to a 1'b1 will enable the override field in this register to override the integrator accumulator functions." "0,1" newline rbitfld.long 0x18 22. "RX_REE_LFEQ_OVRD_6,Reserved" "0,1" newline hexmask.long.byte 0x18 16.--21. 1. "RX_REE_LFEQ_OVRD_5_0,Override value: When the override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder." newline hexmask.long.byte 0x18 9.--15. 1. "RX_REE_LFEQ_CTRL_15_9,Reserved" newline bitfld.long 0x18 8. "RX_REE_LFEQ_CTRL_8,Receiver DFE coefficient disable: This bit disables the rxda_dfe_coef output signal." "0,1" newline rbitfld.long 0x18 7. "RX_REE_LFEQ_CTRL_7,Reserved" "0,1" newline bitfld.long 0x18 4.--6. "RX_REE_LFEQ_CTRL_6_4,Integrator accumulator scaler value: Specifies the amount to scale the input to the integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--3. 1. "RX_REE_LFEQ_CTRL_3_0,Sigma delta accumulator scaler value: Specifies the amount to scale the input to the sigma delta accumulator by." line.long 0x1C "RX_REE_LFEQ_DIAG_j,REE low frequency equalizer diagnostics register Offset = 82BCh + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x1C 16.--31. 1. "RESERVED" newline rbitfld.long 0x1C 15. "RX_REE_LFEQ_DIAG_15,Reserved" "0,1" newline bitfld.long 0x1C 14. "RX_REE_LFEQ_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0x1C 13. "RX_REE_LFEQ_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the voter function to activate the voter pos signal for a single cycle." "0,1" newline bitfld.long 0x1C 12. "RX_REE_LFEQ_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter." "0,1" newline hexmask.long.byte 0x1C 6.--11. 1. "RX_REE_LFEQ_DIAG_11_6,Reserved" newline hexmask.long.byte 0x1C 0.--5. 1. "RX_REE_LFEQ_DIAG_5_0,Current integrator accumulator: Current value of the integrator accumulator." line.long 0x20 "RX_REE_VGA_GAIN_OVRD__RX_REE_VGA_GAIN_CTRL_j,REE VGA gain control register Offset = 82C0h + (j * 400h); where j = 0h to 3h" bitfld.long 0x20 31. "RX_REE_VGA_GAIN_OVRD_15,VGA gain target adjust override enable: Setting this bit to a 1'b1 will enable the VGA gain target adjust override field in this register to override the VGA gain target adjust accumulator functions." "0,1" newline rbitfld.long 0x20 29.--30. "RX_REE_VGA_GAIN_OVRD_14_13,Reserved" "0,1,2,3" newline hexmask.long.byte 0x20 24.--28. 1. "RX_REE_VGA_GAIN_OVRD_12_8,VGA gain target adjust override value: When the VGA gain target adjust override enable bit in this register is active the value in this field will override the accumulator value used to drive the vga_gain_tgt_adj signal." newline bitfld.long 0x20 23. "RX_REE_VGA_GAIN_OVRD_7,VGA gain override enable: Setting this bit to a 1'b1 will enable the VGA gain override field in this register to override the VGA gain integrator accumulator functions." "0,1" newline rbitfld.long 0x20 21.--22. "RX_REE_VGA_GAIN_OVRD_6_5,Reserved" "0,1,2,3" newline hexmask.long.byte 0x20 16.--20. 1. "RX_REE_VGA_GAIN_OVRD_4_0,VGA gain override value: When the VGA gain override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder." newline rbitfld.long 0x20 13.--15. "RX_REE_VGA_GAIN_CTRL_15_13,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 8.--12. 1. "RX_REE_VGA_GAIN_CTRL_12_8,VGA gain max: Specifies the maximum value of the VGA gain integrator accumulator and therefore also the maximum number of bits in the rxda_dfe_vga_gain thermometer code that will be set." newline rbitfld.long 0x20 7. "RX_REE_VGA_GAIN_CTRL_7,Reserved" "0,1" newline bitfld.long 0x20 4.--6. "RX_REE_VGA_GAIN_CTRL_6_4,VGA gain integrator accumulator scaler value: Specifies the amount to scale the input to the VGA gain integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 0.--3. 1. "RX_REE_VGA_GAIN_CTRL_3_0,VGA gain sigma delta accumulator scaler value: Specifies the amount to scale the input to the VGA gain sigma delta accumulator by." line.long 0x24 "RX_REE_VGA_GAIN_TGT_DIAG__RX_REE_VGA_GAIN_DIAG_j,REE VGA gain diagnostics register Offset = 82C4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x24 21.--31. 1. "RX_REE_VGA_GAIN_TGT_DIAG_15_5,Reserved" newline hexmask.long.byte 0x24 16.--20. 1. "RX_REE_VGA_GAIN_TGT_DIAG_4_0,Current VGA gain integrator accumulator: Current value of the VGA gain integrator accumulator." newline rbitfld.long 0x24 15. "RX_REE_VGA_GAIN_DIAG_15,Reserved" "0,1" newline bitfld.long 0x24 14. "RX_REE_VGA_GAIN_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the VGA gain voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0x24 13. "RX_REE_VGA_GAIN_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the VGA gain voter function to activate the voter pos signal for a single clock cycle." "0,1" newline bitfld.long 0x24 12. "RX_REE_VGA_GAIN_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the VGA gain." "0,1" newline hexmask.long.byte 0x24 6.--11. 1. "RX_REE_VGA_GAIN_DIAG_11_6,Reserved" newline hexmask.long.byte 0x24 0.--5. 1. "RX_REE_VGA_GAIN_DIAG_5_0,Current VGA gain integrator accumulator: Current value of the VGA gain integrator accumulator." line.long 0x28 "RX_REE_OFF_COR_OVRD__RX_REE_OFF_COR_CTRL_j,REE offset correction control register Offset = 82C8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x28 24.--31. 1. "RX_REE_OFF_COR_OVRD_15_8,Reserved" newline bitfld.long 0x28 23. "RX_REE_OFF_COR_OVRD_7,Offset correction override enable: Setting this bit to a 1'b1 will enable the offset correction override field in this register to override the offset correction integrator accumulator functions." "0,1" newline rbitfld.long 0x28 22. "RX_REE_OFF_COR_OVRD_6,Reserved" "0,1" newline hexmask.long.byte 0x28 16.--21. 1. "RX_REE_OFF_COR_OVRD_5_0,Offset correction override value: When the offset correction override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer.." newline hexmask.long.word 0x28 7.--15. 1. "RX_REE_OFF_COR_CTRL_15_7,Reserved" newline bitfld.long 0x28 4.--6. "RX_REE_OFF_COR_CTRL_6_4,Offset correction integrator accumulator scaler value: Specifies the amount to scale the input to the offset correction integrator accumulator by." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--3. 1. "RX_REE_OFF_COR_CTRL_3_0,Offset correction sigma delta accumulator scaler value: Specifies the amount to scale the input to the offset correction sigma delta accumulator by." line.long 0x2C "RX_REE_OFF_COR_DIAG_j,REE offset correction diagnostics register Offset = 82CCh + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x2C 16.--31. 1. "RESERVED" newline rbitfld.long 0x2C 15. "RX_REE_OFF_COR_DIAG_15,Reserved" "0,1" newline bitfld.long 0x2C 14. "RX_REE_OFF_COR_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the offset correction voter function to activate the voter neg signal for a single clock cycle." "0,1" newline bitfld.long 0x2C 13. "RX_REE_OFF_COR_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the offset correction voter function to activate the voter pos signal for a single clock cycle." "0,1" newline bitfld.long 0x2C 12. "RX_REE_OFF_COR_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the offset correction." "0,1" newline hexmask.long.byte 0x2C 6.--11. 1. "RX_REE_OFF_COR_DIAG_11_6,Reserved" newline hexmask.long.byte 0x2C 0.--5. 1. "RX_REE_OFF_COR_DIAG_5_0,Current offset correction integrator accumulator: Current value of the offset correction integrator accumulator." line.long 0x30 "RX_REE_SC_COR_TCNT__RX_REE_SC_COR_WCNT_j,REE short channel correction valid word counter register Offset = 82D0h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x30 22.--31. 1. "RX_REE_SC_COR_TCNT_15_6,Reserved" newline hexmask.long.byte 0x30 16.--21. 1. "RX_REE_SC_COR_TCNT_5_0,Threshold counter start value : Value used for the starting value when counting the number of bits that are below the error threshold." newline hexmask.long.word 0x30 6.--15. 1. "RX_REE_SC_COR_WCNT_15_6,Reserved" newline hexmask.long.byte 0x30 0.--5. 1. "RX_REE_SC_COR_WCNT_5_0,Valid word counter start value : Value used for the starting value when counting the number of valid words." group.long 0x82E0++0x13 line.long 0x0 "RX_REE_TAP1_CLIP__RX_REE_ADDR_CFG_j,REE adder configuration register Offset = 82E0h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x0 27.--31. 1. "RX_REE_TAP1_CLIP_15_11,Reserved" newline bitfld.long 0x0 24.--26. "RX_REE_TAP1_CLIP_10_8,VGA target gain adjust multiplier: Controls how much to multiply the VGA target gain adjust by when calculating the tap threshold." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 21.--23. "RX_REE_TAP1_CLIP_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "RX_REE_TAP1_CLIP_4_0,Threshold adjust: Controls how much the threshold can be adjusted by after multiplying the VGA target gain adjust multiplier with the VGA target gain adjust." newline hexmask.long.byte 0x0 11.--15. 1. "RX_REE_ADDR_CFG_15_11,Reserved" newline bitfld.long 0x0 10. "RX_REE_ADDR_CFG_10,TX post cursor tap 3 adder enable: Setting this bit to 1'b1 enables the results of tap 3 to be added to the TX post cursor controller input." "0,1" newline bitfld.long 0x0 9. "RX_REE_ADDR_CFG_9,TX post cursor tap 2 adder enable: Setting this bit to 1'b1 enables the results of tap 2 to be added to the TX post cursor controller input." "0,1" newline bitfld.long 0x0 8. "RX_REE_ADDR_CFG_8,TX post cursor tap 1 adder enable: Setting this bit to 1'b1 enables the results of tap 1 to be added to the TX post cursor controller input." "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RX_REE_ADDR_CFG_7_3,Reserved" newline bitfld.long 0x0 2. "RX_REE_ADDR_CFG_2,RX peaking tap 3 adder enable: Setting this bit to 1'b1 enables the results of tap 3 to be added to the RX peaking amp gain input." "0,1" newline bitfld.long 0x0 1. "RX_REE_ADDR_CFG_1,RX peaking tap 2 adder enable: Setting this bit to 1'b1 enables the results of tap 2 to be added to the RX peaking amp gain input." "0,1" newline bitfld.long 0x0 0. "RX_REE_ADDR_CFG_0,RX peaking tap 1 adder enable: Setting this bit to 1'b1 enables the results of tap 1 to be added to the RX peaking amp gain input." "0,1" line.long 0x4 "RX_REE_CTRL_DATA_MASK__RX_REE_TAP2TON_CLIP_j,REE taps 2 and 3 clip control register Offset = 82E4h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x4 31. "RX_REE_CTRL_DATA_MASK_15,Reserved" "0,1" newline rbitfld.long 0x4 30. "RX_REE_CTRL_DATA_MASK_14,Ignore 1010 controller - Note that this is read only." "0,1" newline bitfld.long 0x4 29. "RX_REE_CTRL_DATA_MASK_13,TX equalization evaluator: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data.." "0,1" newline bitfld.long 0x4 28. "RX_REE_CTRL_DATA_MASK_12,TX post cursor control: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data.." "0,1" newline bitfld.long 0x4 27. "RX_REE_CTRL_DATA_MASK_11,TX pre cursor control: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data.." "0,1" newline bitfld.long 0x4 26. "RX_REE_CTRL_DATA_MASK_10,Short channel correction: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data.." "0,1" newline bitfld.long 0x4 25. "RX_REE_CTRL_DATA_MASK_9,RX attenuation: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals by the.." "0,1" newline bitfld.long 0x4 24. "RX_REE_CTRL_DATA_MASK_8,RX VGA gain: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals by the REE." "0,1" newline bitfld.long 0x4 23. "RX_REE_CTRL_DATA_MASK_7,RX offset correction coefficient: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the.." "0,1" newline bitfld.long 0x4 22. "RX_REE_CTRL_DATA_MASK_6,RX peaking amp gain: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals.." "0,1" newline bitfld.long 0x4 21. "RX_REE_CTRL_DATA_MASK_5,RX low frequency equalizer adaptive control: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is.." "0,1" newline rbitfld.long 0x4 20. "RX_REE_CTRL_DATA_MASK_4,Reserved" "0,1" newline rbitfld.long 0x4 19. "RX_REE_CTRL_DATA_MASK_3,Reserved" "0,1" newline bitfld.long 0x4 18. "RX_REE_CTRL_DATA_MASK_2,RX tap 3: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals by the REE." "0,1" newline bitfld.long 0x4 17. "RX_REE_CTRL_DATA_MASK_1,RX tap 2: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals by the REE." "?,?" newline bitfld.long 0x4 16. "RX_REE_CTRL_DATA_MASK_0,RX tap 1: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals by the REE." "?,1: When set to 1'b0" newline hexmask.long.byte 0x4 11.--15. 1. "RX_REE_TAP2TON_CLIP_15_11,Reserved" newline bitfld.long 0x4 8.--10. "RX_REE_TAP2TON_CLIP_10_8,VGA target gain adjust multiplier: Controls how much to multiply the VGA target gain adjust by when calculating the tap threshold." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 5.--7. "RX_REE_TAP2TON_CLIP_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "RX_REE_TAP2TON_CLIP_4_0,Threshold adjust: Controls how much the threshold can be adjusted by after multiplying the VGA target gain adjust multiplier with the VGA target gain adjust." line.long 0x8 "RX_REE_DIAG_CTRL__RX_REE_FIFO_DIAG_j,REE coefficient FIFO diagnostic register Offset = 82E8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 24.--31. 1. "RX_REE_DIAG_CTRL_15_8,Reserved" newline bitfld.long 0x8 23. "RX_REE_DIAG_CTRL_7,Analog tap disable: When this bit is set to 1'b1 the rxda_dfe_tap_1_coef rxda_dfe_tap_2_coef and rxda_dfe_tap_3_coef signals being driven to the analog will be forced to all 0s." "0,1" newline bitfld.long 0x8 22. "RX_REE_DIAG_CTRL_6,Hold periodic equalization while RX idle: When this bit is set to 1'b1 a detection of electrical idle on the receiver (rx_signal_detect is set to 1'b0) will disable the periodic REE general control state machine and as a result.." "0,1" newline bitfld.long 0x8 21. "RX_REE_DIAG_CTRL_5,Hold general control state machine 2 equalization while RX idle: When this bit is set to 1'b1 a detection of electrical idle on the receiver (rx_signal_detect is set to 1'b0) will disable the REE general control state machine 2 and.." "0,1" newline bitfld.long 0x8 20. "RX_REE_DIAG_CTRL_4,Hold general control state machine 1 equalization while RX idle: When this bit is set to 1'b1 a detection of electrical idle on the receiver (rx_signal_detect is set to 1'b0) will disable the REE general control state machine 1 and.." "0,1" newline rbitfld.long 0x8 18.--19. "RX_REE_DIAG_CTRL_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x8 17. "RX_REE_DIAG_CTRL_1,Enable REE control clock on : Enables the REE control clock." "0,1" newline bitfld.long 0x8 16. "RX_REE_DIAG_CTRL_0,Force REE function clock on : When active the REE function clock gate will allow the clock to run." "0,1" newline rbitfld.long 0x8 15. "RX_REE_FIFO_DIAG_15,FIFO underflow : Indicates when a FIFO underflow condition has occurred." "0,1" newline rbitfld.long 0x8 14. "RX_REE_FIFO_DIAG_14,FIFO empty :Indicates that the FIFO is empty." "0,1" newline bitfld.long 0x8 13. "RX_REE_FIFO_DIAG_13,FIFO output dequeue : Writing a 1'b1 to this bit will dequeue the current values from the output of the FIFO." "0,1" newline bitfld.long 0x8 12. "RX_REE_FIFO_DIAG_12,FIFO output override enable : Enables the FIFO output override functions." "0,1" newline rbitfld.long 0x8 11. "RX_REE_FIFO_DIAG_11,FIFO output data pre cursor increment : Current value on the pre cursor increment bit on the FIFO output." "0,1" newline rbitfld.long 0x8 10. "RX_REE_FIFO_DIAG_10,FIFO output data pre cursor decrement : Current value on the pre cursor decrement bit on the FIFO output." "0,1" newline rbitfld.long 0x8 9. "RX_REE_FIFO_DIAG_9,FIFO output data post cursor increment : Current value on the post cursor increment bit on the FIFO output." "0,1" newline rbitfld.long 0x8 8. "RX_REE_FIFO_DIAG_8,FIFO output data post cursor decrement : Current value on the post cursor decrement bit on the FIFO output." "0,1" newline rbitfld.long 0x8 7. "RX_REE_FIFO_DIAG_7,FIFO overflow :Indicates when a FIFO overflow condition has occurred." "0,1" newline rbitfld.long 0x8 6. "RX_REE_FIFO_DIAG_6,FIFO full :Indicates that the FIFO is full." "0,1" newline bitfld.long 0x8 5. "RX_REE_FIFO_DIAG_5,FIFO input enqueue : Writing a 1'b1 to this bit will enqueue the values of the FIFO input data bits in this register to their respective FIFO bits." "0,1" newline bitfld.long 0x8 4. "RX_REE_FIFO_DIAG_4,FIFO input override enable : Enables the FIFO input override functions." "0,1" newline bitfld.long 0x8 3. "RX_REE_FIFO_DIAG_3,FIFO input data pre cursor increment : Pre cursor increment value that will be enqueued to the FIFO by the FIFO input enqueue bit in this register." "0,1" newline bitfld.long 0x8 2. "RX_REE_FIFO_DIAG_2,FIFO input data pre cursor decrement : Pre cursor decrement value that will be enqueued to the FIFO by the FIFO input enqueue bit in this register." "0,1" newline bitfld.long 0x8 1. "RX_REE_FIFO_DIAG_1,FIFO input data post cursor increment : Post cursor increment value that will be enqueued to the FIFO by the FIFO input enqueue bit in this register." "0,1" newline bitfld.long 0x8 0. "RX_REE_FIFO_DIAG_0,FIFO input data post cursor decrement : Post cursor decrement value that will be enqueued to the FIFO by the FIFO input enqueue bit in this register." "0,1" line.long 0xC "RX_REE_SMGM_CTRL1__RX_REE_TXEQEVAL_CTRL_j,REE TX equalization evaluator control register Offset = 82ECh + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0xC 28.--31. 1. "RX_REE_SMGM_CTRL1_15_12,Reserved" newline bitfld.long 0xC 27. "RX_REE_SMGM_CTRL1_11,REE Periodic general control state machine enable standard mode 3: This bit will control if the REE periodic general control state machine will run when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0xC 26. "RX_REE_SMGM_CTRL1_10,REE Periodic general control state machine enable standard mode 2: This bit will control if the REE periodic general control state machine will run when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0xC 25. "RX_REE_SMGM_CTRL1_9,REE Periodic general control state machine enable standard mode 1: This bit will control if the REE periodic general control state machine will run when xcvr_standard_mode is set to 2'b01." "?,1: This bit will control if the REE periodic.." newline bitfld.long 0xC 24. "RX_REE_SMGM_CTRL1_8,REE Periodic general control state machine enable standard mode 0: This bit will control if the REE periodic general control state machine will run when xcvr_standard_mode is set to 2'b00." "0: This bit will control if the REE periodic..,?" newline bitfld.long 0xC 23. "RX_REE_SMGM_CTRL1_7,REE general control state machine 2 enable standard mode 3: This bit will control if the REE general control state machine 2 will run when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0xC 22. "RX_REE_SMGM_CTRL1_6,REE general control state machine 2 enable standard mode 2: This bit will control if the REE general control state machine 2 will run when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0xC 21. "RX_REE_SMGM_CTRL1_5,REE general control state machine 2 enable standard mode 1: This bit will control if the REE general control state machine 2 will run when xcvr_standard_mode is set to 2'b01." "?,1: This bit will control if the REE general control.." newline bitfld.long 0xC 20. "RX_REE_SMGM_CTRL1_4,REE general control state machine 2 enable standard mode 0: This bit will control if the REE general control state machine 2 will run when xcvr_standard_mode is set to 2'b00." "0: This bit will control if the REE general control..,?" newline bitfld.long 0xC 19. "RX_REE_SMGM_CTRL1_3,REE general control state machine 1 enable standard mode 3: This bit will control if the REE general control state machine 1 will run when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0xC 18. "RX_REE_SMGM_CTRL1_2,REE general control state machine 1 enable standard mode 2: This bit will control if the REE general control state machine 1 will run when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0xC 17. "RX_REE_SMGM_CTRL1_1,REE general control state machine 1 enable standard mode 1: This bit will control if the REE general control state machine 1 will run when xcvr_standard_mode is set to 2'b01." "?,1: This bit will control if the REE general control.." newline bitfld.long 0xC 16. "RX_REE_SMGM_CTRL1_0,REE general control state machine 1 enable standard mode 0: This bit will control if the REE general control state machine 1 will run when xcvr_standard_mode is set to 2'b00." "0: This bit will control if the REE general control..,?" newline hexmask.long.word 0xC 2.--15. 1. "RX_REE_TXEQEVAL_CTRL_15_2,Reserved" newline bitfld.long 0xC 1. "RX_REE_TXEQEVAL_CTRL_1,TX equalization evaluation counter reset on gen mode change: Controls if the incremental evaluation counter will be reset to its starting value when changing gen modes." "0,1" newline bitfld.long 0xC 0. "RX_REE_TXEQEVAL_CTRL_0,TX main coefficient direction change control: This bit controls the function of the main coefficient direction change." "0,1" line.long 0x10 "RX_REE_TXEQEVAL_PRE__RX_REE_SMGM_CTRL2_j,REE control state machine gen mode control register 2 Offset = 82F0h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x10 30.--31. "RX_REE_TXEQEVAL_PRE_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x10 24.--29. 1. "RX_REE_TXEQEVAL_PRE_13_8,TX equalization evaluator pre-emphasis increment count: Contains a count of the total number of pre-emphasis increment responses that have taken place during the TX equalization evaluator process." newline rbitfld.long 0x10 22.--23. "RX_REE_TXEQEVAL_PRE_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x10 16.--21. 1. "RX_REE_TXEQEVAL_PRE_5_0,TX equalization evaluator pre-emphasis decrement count: Contains a count of the total number of pre-emphasis decrement responses that have taken place during the TX equalization evaluator process." newline bitfld.long 0x10 15. "RX_REE_SMGM_CTRL2_15,REE PCIe Gen 3 TX equalization state machine E path en standard mode 3: This bit controls if the REE PCIE Gen 3 TX equalization state machine will enable the analog E path when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x10 14. "RX_REE_SMGM_CTRL2_14,REE PCIe Gen 3 TX equalization state machine E path en standard mode 2: This bit controls if the REE PCIE Gen 3 TX equalization state machine will enable the analog E path when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x10 13. "RX_REE_SMGM_CTRL2_13,REE PCIe Gen 3 TX equalization state machine E path en standard mode 1: This bit controls if the REE PCIE Gen 3 TX equalization state machine will enable the analog E path when xcvr_standard_mode is set to 2'b01." "?,1: This bit controls if the REE PCIE Gen 3 TX.." newline bitfld.long 0x10 12. "RX_REE_SMGM_CTRL2_12,REE PCIe Gen 3 TX equalization state machine E path en standard mode 0: This bit controls if the REE PCIE Gen 3 TX equalization state machine will enable the analog E path when xcvr_standard_mode is set to 2'b00." "0: This bit controls if the REE PCIE Gen 3 TX..,?" newline bitfld.long 0x10 11. "RX_REE_SMGM_CTRL2_11,REE Periodic general control state machine E path en standard mode 3: This bit controls if the REE periodic general control state machine will enable the analog E path when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x10 10. "RX_REE_SMGM_CTRL2_10,REE Periodic general control state machine E path en standard mode 2: This bit controls if the REE periodic general control state machine will enable the analog E path when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x10 9. "RX_REE_SMGM_CTRL2_9,REE Periodic general control state machine E path en standard mode 1: This bit controls if the REE periodic general control state machine will enable the analog E path when xcvr_standard_mode is set to 2'b01." "?,1: This bit controls if the REE periodic general.." newline bitfld.long 0x10 8. "RX_REE_SMGM_CTRL2_8,REE Periodic general control state machine E path en standard mode 0: This bit controls if the REE periodic general control state machine will enable the analog E path when xcvr_standard_mode is set to 2'b00." "0: This bit controls if the REE periodic general..,?" newline bitfld.long 0x10 7. "RX_REE_SMGM_CTRL2_7,REE general control state machine 2 E path en standard mode 3: This bit controls if the REE general control state machine 2 will enable the analog E path when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x10 6. "RX_REE_SMGM_CTRL2_6,REE general control state machine 2 E path en standard mode 2: This bit controls if the REE general control state machine 2 will enable the analog E path when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x10 5. "RX_REE_SMGM_CTRL2_5,REE general control state machine 2 E path en standard mode 1: This bit controls if the REE general control state machine 2 will enable the analog E path when xcvr_standard_mode is set to 2'b01." "?,1: This bit controls if the REE general control.." newline bitfld.long 0x10 4. "RX_REE_SMGM_CTRL2_4,REE general control state machine 2 E path en standard mode 0: This bit controls if the REE general control state machine 2 will enable the analog E path when xcvr_standard_mode is set to 2'b00." "0: This bit controls if the REE general control..,?" newline bitfld.long 0x10 3. "RX_REE_SMGM_CTRL2_3,REE general control state machine 1 E path en standard mode 3: This bit controls if the REE general control state machine 1 will enable the analog E path when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x10 2. "RX_REE_SMGM_CTRL2_2,REE general control state machine 1 E path en standard mode 2: This bit controls if the REE general control state machine 1 will enable the analog E path when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x10 1. "RX_REE_SMGM_CTRL2_1,REE general control state machine 1 E path en standard mode 1: This bit controls if the REE general control state machine 1 will enable the analog E path when xcvr_standard_mode is set to 2'b01." "?,1: This bit controls if the REE general control.." newline bitfld.long 0x10 0. "RX_REE_SMGM_CTRL2_0,REE general control state machine 1 E path en standard mode 0: This bit controls if the REE general control state machine 1 will enable the analog E path when xcvr_standard_mode is set to 2'b00." "0: This bit controls if the REE general control..,?" rgroup.long 0x82F4++0x3 line.long 0x0 "RX_REE_TXEQEVAL_POST_j,REE TX equalization evaluator post-emphasis register Offset = 82F4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline bitfld.long 0x0 14.--15. "RX_REE_TXEQEVAL_POST_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "RX_REE_TXEQEVAL_POST_13_8,TX equalization evaluator post-emphasis increment count: Contains a count of the total number of post-emphasis increment responses that have taken place during the TX equalization evaluator process." newline bitfld.long 0x0 6.--7. "RX_REE_TXEQEVAL_POST_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "RX_REE_TXEQEVAL_POST_5_0,TX equalization evaluator post-emphasis decrement count: Contains a count of the total number of post-emphasis decrement responses that have taken place during the TX equalization evaluator process." group.long 0x8380++0x7 line.long 0x0 "XCVR_CMSMT_TEST_CLK_SEL__XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_j,Clock frequency measurement control register Offset = 8380h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 19.--31. 1. "XCVR_CMSMT_TEST_CLK_SEL_15_3,Reserved" newline bitfld.long 0x0 16.--18. "XCVR_CMSMT_TEST_CLK_SEL_2_0,Test clock select: This field drives the test_clk_select pin in order to control an external MUX for selecting between multiple test clocks to measure." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_15,Run test clock measurement: Activating (1'b1) this bit will run the test clock measurement process." "0,1" newline rbitfld.long 0x0 14. "XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_14,Test clock measurement done: This bit will be set to 1'b1 when the test clock measurement process is complete." "0,1" newline hexmask.long.word 0x0 0.--13. 1. "XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_13_0,Reserved" line.long 0x4 "XCVR_CMSMT_TEST_CLK_CNT_VALUE__XCVR_CMSMT_REF_CLK_TMR_VALUE_j,Reference clock timer value register Offset = 8384h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x4 28.--31. 1. "XCVR_CMSMT_TEST_CLK_CNT_VALUE_15_12,Reserved" newline hexmask.long.word 0x4 16.--27. 1. "XCVR_CMSMT_TEST_CLK_CNT_VALUE_11_0,Test clock counter value: When the test clock measurement process is complete the value in this field specifies the number of test clock cycles that were counted in the time specified by the reference clock timer value." newline hexmask.long.byte 0x4 12.--15. 1. "XCVR_CMSMT_REF_CLK_TMR_VALUE_15_12,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "XCVR_CMSMT_REF_CLK_TMR_VALUE_11_0,Reference clock timer value : This specifies the amount of time in reference clock cycles to count test clock cycles." group.long 0x83C0++0x1B line.long 0x0 "RX_DIAG_DFE_AMP_TUNE__RX_DIAG_DFE_CTRL_j,Receiver DFE control register Offset = 83C0h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x0 31. "RX_DIAG_DFE_AMP_TUNE_15,Reserved" "0,1" newline bitfld.long 0x0 28.--30. "RX_DIAG_DFE_AMP_TUNE_14_12,DFE constant gm bias tune: Adjusts the constant gm bias." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "RX_DIAG_DFE_AMP_TUNE_11,DFE VGA constant gm bias enable: Enables the VGA constant gm bias." "0,1" newline bitfld.long 0x0 24.--26. "RX_DIAG_DFE_AMP_TUNE_10_8,DFE VGA amp current adjust: Adjusts the current for the DFE VGA amp using the rxda_vga_current_adj signal as specified below." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "RX_DIAG_DFE_AMP_TUNE_7,DFE peaking constant gm bias enable: Enables the peaking constant gm bias." "0,1" newline bitfld.long 0x0 20.--22. "RX_DIAG_DFE_AMP_TUNE_6_4,DFE peaking amp current adjust: Adjusts the current for the DFE peaking amp using the rxda_peak_current_adj signal as specified below." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19. "RX_DIAG_DFE_AMP_TUNE_3,DFE summing constant gm bias enable: Enables the summing constant gm bias." "0,1" newline bitfld.long 0x0 16.--18. "RX_DIAG_DFE_AMP_TUNE_2_0,DFE summing amp current adjust: Adjusts the current for the DFE summing amp using the rxda_sum_current_adj signal as specified below." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 4.--15. 1. "RX_DIAG_DFE_CTRL_15_4,Reserved" newline bitfld.long 0x0 3. "RX_DIAG_DFE_CTRL_3,Receiver DFE low frequency equalization enable value standard mode 3: This bit controls the rxda_dfe_lfeq_en signal going to the analog which is used to enable the receiver DFE low frequency equalization analog circuits when.." "0,1" newline bitfld.long 0x0 2. "RX_DIAG_DFE_CTRL_2,Receiver DFE low frequency equalization enable value standard mode 2: This bit controls the rxda_dfe_lfeq_en signal going to the analog which is used to enable the receiver DFE low frequency equalization analog circuits when.." "?,?" newline bitfld.long 0x0 1. "RX_DIAG_DFE_CTRL_1,Receiver DFE low frequency equalization enable value standard mode 1: This bit controls the rxda_dfe_lfeq_en signal going to the analog which is used to enable the receiver DFE low frequency equalization analog circuits when.." "?,1: This bit controls the rxda_dfe_lfeq_en signal.." newline bitfld.long 0x0 0. "RX_DIAG_DFE_CTRL_0,Receiver DFE low frequency equalization enable value standard mode 0: This bit controls the rxda_dfe_lfeq_en signal going to the analog which is used to enable the receiver DFE low frequency equalization analog circuits when.." "0: This bit controls the rxda_dfe_lfeq_en signal..,?" line.long 0x4 "RX_DIAG_DFE_AMP_TUNE_3__RX_DIAG_DFE_AMP_TUNE_2_j,DFE amp fine tuning 2 register Offset = 83C4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 20.--31. 1. "RX_DIAG_DFE_AMP_TUNE_3_15_4,Reserved" newline bitfld.long 0x4 19. "RX_DIAG_DFE_AMP_TUNE_3_3,DFE VGA stage 1 boost standard mode 3: This bit enables the active inductors boost function in stage 1 of the VGA for high data rates when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x4 18. "RX_DIAG_DFE_AMP_TUNE_3_2,DFE VGA stage 1 boost standard mode 2: This bit enables the active inductors boost function in stage 1 of the VGA for high data rates when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x4 17. "RX_DIAG_DFE_AMP_TUNE_3_1,DFE VGA stage 1 boost standard mode 1: This bit enables the active inductors boost function in stage 1 of the VGA for high data rates when xcvr_standard_mode is set to 2'b01." "?,1: This bit enables the active inductors boost.." newline bitfld.long 0x4 16. "RX_DIAG_DFE_AMP_TUNE_3_0,DFE VGA stage 1 boost standard mode 0: This bit enables the active inductors boost function in stage 1 of the VGA for high data rates when xcvr_standard_mode is set to 2'b00." "0: This bit enables the active inductors boost..,?" newline rbitfld.long 0x4 14.--15. "RX_DIAG_DFE_AMP_TUNE_2_15_14,Reserved" "0,1,2,3" newline bitfld.long 0x4 12.--13. "RX_DIAG_DFE_AMP_TUNE_2_13_12,Receiver peaking amp common mode adjust: Adjusts the common mode voltage for the receiver peaking amp by driving the rxda_fe_pkamp_cm_adj signal to the analog." "0,1,2,3" newline bitfld.long 0x4 11. "RX_DIAG_DFE_AMP_TUNE_2_11,DFE low frequency equalizer constant gm bias enable: Enables the low frequency equalizer constant gm bias." "0,1" newline bitfld.long 0x4 8.--10. "RX_DIAG_DFE_AMP_TUNE_2_10_8,DFE low frequency equalizer current adjust: Adjusts the current for the DFE low frequency equalizer using the rxda_lfeq_current_adj signal as specified below." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "RX_DIAG_DFE_AMP_TUNE_2_7,DFE peaking amp boost: Enables the active inductors boost function in the peaking amp for high data rates." "0,1" newline bitfld.long 0x4 6. "RX_DIAG_DFE_AMP_TUNE_2_6,Reserved - Spare" "0,1" newline bitfld.long 0x4 5. "RX_DIAG_DFE_AMP_TUNE_2_5,DFE VGA stage 2 boost: Enables the active inductors boost function in stage 2 of the VGA for high data rates." "0,1" newline bitfld.long 0x4 4. "RX_DIAG_DFE_AMP_TUNE_2_4,DFE RX Tap 1 DAC Range Select: Controls the tap 1 DAC range in the analog DFE." "0,1" newline rbitfld.long 0x4 2.--3. "RX_DIAG_DFE_AMP_TUNE_2_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RX_DIAG_DFE_AMP_TUNE_2_1_0,DFE RX amp current adjust: Adjusts the mix of constant-gm and External Current for RX front end amplifiers." "0,1,2,3" line.long 0x8 "RX_DIAG_NQST_CTRL__RX_DIAG_REE_DAC_CTRL_j,REE DAC control register Offset = 83C8h + (j * 400h); where j = 0h to 3h" hexmask.long.byte 0x8 28.--31. 1. "RX_DIAG_NQST_CTRL_15_12,RX nyquist select value standard mode 3: This field specifies the receiver DFE nyquist frequency select value on the rxda_dfe_nqst_sel signal driven to the analog when xcvr_standard_mode is set to 2'b11." newline hexmask.long.byte 0x8 24.--27. 1. "RX_DIAG_NQST_CTRL_11_8,RX nyquist select value standard mode 2: This field specifies the receiver DFE nyquist frequency select value on the rxda_dfe_nqst_sel signal driven to the analog when xcvr_standard_mode is set to 2'b10." newline hexmask.long.byte 0x8 20.--23. 1. "RX_DIAG_NQST_CTRL_7_4,RX nyquist select value standard mode 1: This field specifies the receiver DFE nyquist frequency select value on the rxda_dfe_nqst_sel signal driven to the analog when xcvr_standard_mode is set to 2'b01." newline hexmask.long.byte 0x8 16.--19. 1. "RX_DIAG_NQST_CTRL_3_0,RX nyquist select value standard mode 0: This field specifies the receiver DFE nyquist frequency select value on the rxda_dfe_nqst_sel signal driven to the analog when xcvr_standard_mode is set to 2'b00." newline hexmask.long.word 0x8 3.--15. 1. "RX_DIAG_REE_DAC_CTRL_15_3,Reserved" newline bitfld.long 0x8 2. "RX_DIAG_REE_DAC_CTRL_2,DFE Offset DAC enable: Enables the DFE offset DAC associated with the VGA amp." "0,1" newline bitfld.long 0x8 1. "RX_DIAG_REE_DAC_CTRL_1,DFE Offset DAC attenuation: Adds attenuation to the DFE offset DAC associated with the VGA amp." "0,1" newline bitfld.long 0x8 0. "RX_DIAG_REE_DAC_CTRL_0,DFE DAC attenuation: Adds attenuation to the DFE DACs associated with the summing amp." "0,1" line.long 0xC "RX_DIAG_LFEQ_TUNE_j,Low frequency equalizer tuning register Offset = 83CCh + (j * 400h); where j = 0h to 3h" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 8.--15. 1. "RX_DIAG_LFEQ_TUNE_15_8,Reserved" newline bitfld.long 0xC 6.--7. "RX_DIAG_LFEQ_TUNE_7_6,RX low frequency equalization zero frequency value standard mode 3: This field specifies the receiver zero frequency setting for the low frequency equalization function by driving the rxda_dfe_lfeq_zero_freq signal going into the.." "?,?,?,3: This field specifies the receiver zero frequency.." newline bitfld.long 0xC 4.--5. "RX_DIAG_LFEQ_TUNE_5_4,RX low frequency equalization zero frequency value standard mode 2: This field specifies the receiver zero frequency setting for the low frequency equalization function by driving the rxda_dfe_lfeq_zero_freq signal going into the.." "?,?,2: This field specifies the receiver zero frequency..,?" newline bitfld.long 0xC 2.--3. "RX_DIAG_LFEQ_TUNE_3_2,RX low frequency equalization zero frequency value standard mode 1: This field specifies the receiver zero frequency setting for the low frequency equalization function by driving the rxda_dfe_lfeq_zero_freq signal going into the.." "?,1: This field specifies the receiver zero frequency..,?,?" newline bitfld.long 0xC 0.--1. "RX_DIAG_LFEQ_TUNE_1_0,RX low frequency equalization zero frequency value standard mode 0: This field specifies the receiver zero frequency setting for the low frequency equalization function by driving the rxda_dfe_lfeq_zero_freq signal going into the.." "0: This field specifies the receiver zero frequency..,?,?,?" line.long 0x10 "RX_DIAG_SH_SIGDET__RX_DIAG_SIGDET_TUNE_j,RX signal detect tuning and control register Offset = 83D0h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x10 29.--31. "RX_DIAG_SH_SIGDET_15_13,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 28. "RX_DIAG_SH_SIGDET_12,Signal detect 1 up: Signal detect 1 calibration up signal value as it is currently captured in the sample and hold latches." "0,1" newline hexmask.long.byte 0x10 24.--27. 1. "RX_DIAG_SH_SIGDET_11_8,Signal detect 1 code: Signal detect 1 calibration code signal value as it is currently captured in the sample and hold latches." newline rbitfld.long 0x10 21.--23. "RX_DIAG_SH_SIGDET_7_5,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 20. "RX_DIAG_SH_SIGDET_4,Signal detect 0 up: Signal detect 0 calibration up signal value as it is currently captured in the sample and hold latches." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "RX_DIAG_SH_SIGDET_3_0,Signal detect 0 code: Signal detect 0 calibration code signal value as it is currently captured in the sample and hold latches." newline rbitfld.long 0x10 15. "RX_DIAG_SIGDET_TUNE_15,Reserved" "0,1" newline bitfld.long 0x10 14. "RX_DIAG_SIGDET_TUNE_14,Signal detect calibration half gain select: Controls the resolution of each step in the signal detect calibration code by adjusting the gain of signal detect offset correction by driving the rxda_sd_cal_halfgain signal going to.." "0,1" newline bitfld.long 0x10 12.--13. "RX_DIAG_SIGDET_TUNE_13_12,Signal detect filter function select: Selects which of the two RX signal detect filter functions are enabled." "0,1,2,3" newline hexmask.long.byte 0x10 8.--11. 1. "RX_DIAG_SIGDET_TUNE_11_8,Reserved" newline bitfld.long 0x10 7. "RX_DIAG_SIGDET_TUNE_7,Receiver signal detect invert samplers: Inverts the behavior of the rxda_sd_pulse_high and rxda_sd_pulse_low samplers by driving the rxda_sd_invert_samplers signal to the analog." "0,1" newline bitfld.long 0x10 6. "RX_DIAG_SIGDET_TUNE_6,Receiver signal detect squelch pulse none: Enable the squelch function for the rxda_sd_pulse_none signal by driving the rxda_sd_squelch_pulse_none signal to the analog." "0,1" newline bitfld.long 0x10 5. "RX_DIAG_SIGDET_TUNE_5,Receiver signal detect one comparator mode: Enables one comparator mode as a power reduction option by driving the rxda_sd_onecomp_mode_en signal to the analog." "0,1" newline bitfld.long 0x10 4. "RX_DIAG_SIGDET_TUNE_4,Receiver signal detect DC coupled path enable: Enables a DC coupled path to the signal detect for verification and testability purposes by driving the rxda_sd_dcpath_en signal to the analog." "0,1" newline rbitfld.long 0x10 3. "RX_DIAG_SIGDET_TUNE_3,Reserved" "0,1" newline bitfld.long 0x10 0.--2. "RX_DIAG_SIGDET_TUNE_2_0,Signal detect level: Sets the reference voltage level at which the comparators will detect a signal by driving the rxda_sd_siglvl_n signal going to the analog." "0,1,2,3,4,5,6,7" line.long 0x14 "RX_DIAG_SD_TEST_j,Signal detect test register Offset = 83D4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x14 16.--31. 1. "RESERVED" newline hexmask.long.word 0x14 4.--15. 1. "RX_DIAG_SD_TEST_15_4,Reserved" newline bitfld.long 0x14 3. "RX_DIAG_SD_TEST_3,LFPS detected low test bit: This bit can be used to detect if the rx_lfps_detect is driven to a low state." "0,1" newline bitfld.long 0x14 2. "RX_DIAG_SD_TEST_2,LFPS detected high test bit: This bit can be used to detect if the rx_lfps_detect is driven to a high state." "0,1" newline bitfld.long 0x14 1. "RX_DIAG_SD_TEST_1,Signal detected low test bit: This bit can be used to detect if the rx_signal_detect is driven to a low state." "0,1" newline bitfld.long 0x14 0. "RX_DIAG_SD_TEST_0,Signal detected high test bit: This bit can be used to detect if the rx_signal_detect is driven to a high state." "0,1" line.long 0x18 "RX_DIAG_SH_SLC_IPP__RX_DIAG_SAMP_CTRL_j,RX sampler diagnostic control register Offset = 83D8h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x18 31. "RX_DIAG_SH_SLC_IPP_15,Reserved" "0,1" newline hexmask.long.byte 0x18 24.--30. 1. "RX_DIAG_SH_SLC_IPP_14_8,RX sampler latch calibration I even positive code: RX sampler latch calibration I even positive code signal value as it is currently captured in the sample and hold latches." newline rbitfld.long 0x18 23. "RX_DIAG_SH_SLC_IPP_7,Reserved" "0,1" newline hexmask.long.byte 0x18 16.--22. 1. "RX_DIAG_SH_SLC_IPP_6_0,RX sampler latch calibration I odd positive code: RX sampler latch calibration I odd positive code signal value as it is currently captured in the sample and hold latches." newline hexmask.long.word 0x18 2.--15. 1. "RX_DIAG_SAMP_CTRL_15_2,Reserved" newline bitfld.long 0x18 1. "RX_DIAG_SAMP_CTRL_1,RX sampler latch range extend: Controls the range of the RX sampler calibration by driving the rxda_sampler_latch_cal_range_ext signal to the analog." "0,1" newline bitfld.long 0x18 0. "RX_DIAG_SAMP_CTRL_0,Analog sampler rxda_dfe_0p5ui_mode_en signal control: Selects which delayed I data is to be used to unroll the Q data in the sampler." "0,1" rgroup.long 0x83DC++0xB line.long 0x0 "RX_DIAG_SH_SLC_QPP__RX_DIAG_SH_SLC_IPM_j,Sample and hold RX sampler latch calibration I predictive negative code register Offset = 83DCh + (j * 400h); where j = 0h to 3h" bitfld.long 0x0 31. "RX_DIAG_SH_SLC_QPP_15,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "RX_DIAG_SH_SLC_QPP_14_8,RX sampler latch calibration Q even positive code: RX sampler latch calibration Q even positive code signal value as it is currently captured in the sample and hold latches." newline bitfld.long 0x0 23. "RX_DIAG_SH_SLC_QPP_7,Reserved" "0,1" newline hexmask.long.byte 0x0 16.--22. 1. "RX_DIAG_SH_SLC_QPP_6_0,RX sampler latch calibration Q odd positive code: RX sampler latch calibration Q odd positive code signal value as it is currently captured in the sample and hold latches." newline bitfld.long 0x0 15. "RX_DIAG_SH_SLC_IPM_15,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "RX_DIAG_SH_SLC_IPM_14_8,RX sampler latch calibration I even negative code: RX sampler latch calibration I even negative code signal value as it is currently captured in the sample and hold latches." newline bitfld.long 0x0 7. "RX_DIAG_SH_SLC_IPM_7,Reserved" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "RX_DIAG_SH_SLC_IPM_6_0,RX sampler latch calibration I odd negative code: RX sampler latch calibration I odd negative code signal value as it is currently captured in the sample and hold latches." line.long 0x4 "RX_DIAG_SH_SLC_EPP__RX_DIAG_SH_SLC_QPM_j,Sample and hold RX sampler latch calibration Q predictive negative code register Offset = 83E0h + (j * 400h); where j = 0h to 3h" bitfld.long 0x4 31. "RX_DIAG_SH_SLC_EPP_15,Reserved" "0,1" newline hexmask.long.byte 0x4 24.--30. 1. "RX_DIAG_SH_SLC_EPP_14_8,RX sampler latch calibration E even positive code: RX sampler latch calibration E even positive code signal value as it is currently captured in the sample and hold latches." newline bitfld.long 0x4 23. "RX_DIAG_SH_SLC_EPP_7,Reserved" "0,1" newline hexmask.long.byte 0x4 16.--22. 1. "RX_DIAG_SH_SLC_EPP_6_0,RX sampler latch calibration E odd positive code: RX sampler latch calibration E odd positive code signal value as it is currently captured in the sample and hold latches." newline bitfld.long 0x4 15. "RX_DIAG_SH_SLC_QPM_15,Reserved" "0,1" newline hexmask.long.byte 0x4 8.--14. 1. "RX_DIAG_SH_SLC_QPM_14_8,RX sampler latch calibration Q even negative code: RX sampler latch calibration Q even negative code signal value as it is currently captured in the sample and hold latches." newline bitfld.long 0x4 7. "RX_DIAG_SH_SLC_QPM_7,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "RX_DIAG_SH_SLC_QPM_6_0,RX sampler latch calibration Q odd negative code: RX sampler latch calibration Q odd negative code signal value as it is currently captured in the sample and hold latches." line.long 0x8 "RX_DIAG_SH_SLC_EPM_j,Sample and hold RX sampler latch calibration E predictive negative code register Offset = 83E4h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 16.--31. 1. "RESERVED" newline bitfld.long 0x8 15. "RX_DIAG_SH_SLC_EPM_15,Reserved" "0,1" newline hexmask.long.byte 0x8 8.--14. 1. "RX_DIAG_SH_SLC_EPM_14_8,RX sampler latch calibration E even negative code: RX sampler latch calibration E even negative code signal value as it is currently captured in the sample and hold latches." newline bitfld.long 0x8 7. "RX_DIAG_SH_SLC_EPM_7,Reserved" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "RX_DIAG_SH_SLC_EPM_6_0,RX sampler latch calibration E odd negative code: RX sampler latch calibration E odd negative code signal value as it is currently captured in the sample and hold latches." group.long 0x83E8++0xB line.long 0x0 "RX_DIAG_PI_CAP__RX_DIAG_PI_RATE_j,PI rate selection register Offset = 83E8h + (j * 400h); where j = 0h to 3h" rbitfld.long 0x0 31. "RX_DIAG_PI_CAP_15,Reserved" "0,1" newline bitfld.long 0x0 28.--30. "RX_DIAG_PI_CAP_14_12,PI capacitor selection standard mode 3: This field is used to implement waveform shaping inside the PI CML cells by changing the capacitive loading." "?,?,?,3: This field is used to implement waveform shaping..,?,?,?,?" newline rbitfld.long 0x0 27. "RX_DIAG_PI_CAP_11,Reserved" "0,1" newline bitfld.long 0x0 24.--26. "RX_DIAG_PI_CAP_10_8,PI capacitor selection standard mode 2: This field is used to implement waveform shaping inside the PI CML cells by changing the capacitive loading." "?,?,2: This field is used to implement waveform shaping..,?,?,?,?,?" newline rbitfld.long 0x0 23. "RX_DIAG_PI_CAP_7,Reserved" "0,1" newline bitfld.long 0x0 20.--22. "RX_DIAG_PI_CAP_6_4,PI capacitor selection standard mode 1: This field is used to implement waveform shaping inside the PI CML cells by changing the capacitive loading." "?,1: This field is used to implement waveform shaping..,?,?,?,?,?,?" newline rbitfld.long 0x0 19. "RX_DIAG_PI_CAP_3,Reserved" "0,1" newline bitfld.long 0x0 16.--18. "RX_DIAG_PI_CAP_2_0,PI capacitor selection standard mode 0: This field is used to implement waveform shaping inside the PI CML cells by changing the capacitive loading." "0: This field is used to implement waveform shaping..,?,?,?,?,?,?,?" newline rbitfld.long 0x0 15. "RX_DIAG_PI_RATE_15,Reserved" "0,1" newline bitfld.long 0x0 12.--14. "RX_DIAG_PI_RATE_14_12,PI rate selection standard mode 3: This field is used to scale the power of the CML cells inside the PI to tune it for a given data rate by driving the rxda_pi_rate_sel signal going into the analog when xcvr_standard_mode is set.." "?,?,?,3: This field is used to scale the power of the CML..,?,?,?,?" newline rbitfld.long 0x0 11. "RX_DIAG_PI_RATE_11,Reserved" "0,1" newline bitfld.long 0x0 8.--10. "RX_DIAG_PI_RATE_10_8,PI rate selection standard mode 2: This field is used to scale the power of the CML cells inside the PI to tune it for a given data rate by driving the rxda_pi_rate_sel signal going into the analog when xcvr_standard_mode is set to.." "?,?,2: This field is used to scale the power of the CML..,?,?,?,?,?" newline rbitfld.long 0x0 7. "RX_DIAG_PI_RATE_7,Reserved" "0,1" newline bitfld.long 0x0 4.--6. "RX_DIAG_PI_RATE_6_4,PI rate selection standard mode 1: This field is used to scale the power of the CML cells inside the PI to tune it for a given data rate by driving the rxda_pi_rate_sel signal going into the analog when xcvr_standard_mode is set to.." "?,1: This field is used to scale the power of the CML..,?,?,?,?,?,?" newline rbitfld.long 0x0 3. "RX_DIAG_PI_RATE_3,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "RX_DIAG_PI_RATE_2_0,PI rate selection standard mode 0: This field is used to scale the power of the CML cells inside the PI to tune it for a given data rate by driving the rxda_pi_rate_sel signal going into the analog when xcvr_standard_mode is set to.." "0: This field is used to scale the power of the CML..,?,?,?,?,?,?,?" line.long 0x4 "RX_DIAG_PI_TUNE_j,PI tuning register Offset = 83ECh + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 8.--15. 1. "RX_DIAG_PI_TUNE_15_8,Reserved" newline bitfld.long 0x4 7. "RX_DIAG_PI_TUNE_7,Receiver CML to CMOS rate select value standard mode 3: This bit will drive the rxda_c2c_rate_sel signal going into the analog when xcvr_standard_mode is set to 2'b11." "0,1" newline bitfld.long 0x4 6. "RX_DIAG_PI_TUNE_6,Receiver CML to CMOS rate select value standard mode 2: This bit will drive the rxda_c2c_rate_sel signal going into the analog when xcvr_standard_mode is set to 2'b10." "?,?" newline bitfld.long 0x4 5. "RX_DIAG_PI_TUNE_5,Receiver CML to CMOS rate select value standard mode 1: This bit will drive the rxda_c2c_rate_sel signal going into the analog when xcvr_standard_mode is set to 2'b01." "?,1: This bit will drive the rxda_c2c_rate_sel signal.." newline bitfld.long 0x4 4. "RX_DIAG_PI_TUNE_4,Receiver CML to CMOS rate select value standard mode 0: This bit will drive the rxda_c2c_rate_sel signal going into the analog when xcvr_standard_mode is set to 2'b00." "0: This bit will drive the rxda_c2c_rate_sel signal..,?" newline rbitfld.long 0x4 1.--3. "RX_DIAG_PI_TUNE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "RX_DIAG_PI_TUNE_0,PI current select: Selects either the external based bias or the poly based bias for the PI by driving the rxda_pi_cur_sel signal going into the analog." "0,1" line.long 0x8 "RX_DIAG_RST_DIAG__RX_DIAG_LPBK_CTRL_j,RX loopback controller register Offset = 83F0h + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x8 22.--31. 1. "RX_DIAG_RST_DIAG_15_6,Reserved" newline rbitfld.long 0x8 21. "RX_DIAG_RST_DIAG_5,Current state of the rxda_clk_reset_n reset." "0,1" newline rbitfld.long 0x8 20. "RX_DIAG_RST_DIAG_4,Current state of the rx_dig_reset_n reset." "0,1" newline rbitfld.long 0x8 19. "RX_DIAG_RST_DIAG_3,Current state of the rxda_cdrlf_reset_n reset." "0,1" newline rbitfld.long 0x8 18. "RX_DIAG_RST_DIAG_2,Current state of the rx_ree_fcn_reset_n reset." "0,1" newline rbitfld.long 0x8 17. "RX_DIAG_RST_DIAG_1,Current state of the rx_ree_ctrl_reset_n reset." "0,1" newline rbitfld.long 0x8 16. "RX_DIAG_RST_DIAG_0,Current state of the rx_lfps_det_filter_reset_n reset." "0,1" newline hexmask.long.word 0x8 6.--15. 1. "RX_DIAG_LPBK_CTRL_15_6,Reserved" newline bitfld.long 0x8 4.--5. "RX_DIAG_LPBK_CTRL_5_4,Recovered clock loopback select: Selects which recovered clock to use when recovered clock loopback is enabled." "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "RX_DIAG_LPBK_CTRL_3_0,Attenuation settings: Sets the attenuation for the ISI generation loopback filter as specified below." group.long 0x83FC++0x3 line.long 0x0 "RX_DIAG_ACYA__RX_DIAG_DCYA_j,Receiver digital cover your alternatives register Offset = 83FCh + (j * 400h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RX_DIAG_ACYA_15_0,Reserved - spare" newline hexmask.long.word 0x0 0.--15. 1. "RX_DIAG_DCYA_15_0,Reserved - spare" group.long 0xC000++0x17 line.long 0x0 "PHY_PIPE_CMN_CTRL2__PHY_PIPE_CMN_CTRL1,PIPE common control1 register" hexmask.long.byte 0x0 28.--31. 1. "PHY_PIPE_CMN_CTRL2_15_12,USB SuperSpeed Tx LFPS Stretch : Minimum number of data rate clock cycles in which PMA tx_lfps_en signal is asserted for USB SuperSpeed rate." newline hexmask.long.byte 0x0 24.--27. 1. "PHY_PIPE_CMN_CTRL2_11_8,USB SuperSpeedPlus Tx LFPS Stretch : Minimum number of data rate clock cycles in which PMA tx_lfps_en signal is asserted for USB SuperSpeedPlus rate." newline rbitfld.long 0x0 23. "PHY_PIPE_CMN_CTRL2_7,Reserved" "0,1" newline bitfld.long 0x0 22. "PHY_PIPE_CMN_CTRL2_6,PCIe PCS TX electrical idle pre release:When this bit is set the TX electrical idle release to the PMA is advanced 1" "0,1" newline bitfld.long 0x0 21. "PHY_PIPE_CMN_CTRL2_5,RX equaliser complete mask: When this bit is cleared the PHY will return direction change of 0 when PMA indicates evaluation complete." "0,1" newline bitfld.long 0x0 20. "PHY_PIPE_CMN_CTRL2_4,PCIe PCS EIOS cycle error mask: When this bit is enabled and the pipe rx interface is outputting an EIOS symbol decode errors will be masked out" "0,1" newline bitfld.long 0x0 19. "PHY_PIPE_CMN_CTRL2_3,USB Gen 2 Bit Error Correction Disable: When this bit is high bit error correction on SKP and SDS symbols is disabled." "0,1" newline bitfld.long 0x0 18. "PHY_PIPE_CMN_CTRL2_2,USB PIPE3 Compatibility Mode enable : When this bit is set to 1 USB PIPE3 compatibility mode is enabled." "0,1" newline bitfld.long 0x0 17. "PHY_PIPE_CMN_CTRL2_1,USB Loopback Slave Error Count disable: When this bit is set to 1 disables the error count for US loopback slave such that the error count is not inserted into the BCNT OS." "0,1" newline bitfld.long 0x0 16. "PHY_PIPE_CMN_CTRL2_0,USB Elasticity Buffer Re-align enable: When this bit is set to 1 when Rx for a USB link is initially started the elasticity buffer is re-aligned to its idle point upon seeing 3 consecutive COMMAs (i.e." "0,1" newline rbitfld.long 0x0 13.--15. "PHY_PIPE_CMN_CTRL1_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "PHY_PIPE_CMN_CTRL1_12,PHY APB access timeout: When set an APB read/write request to PHY registers failed (i.e. timed out)." "0,1" newline rbitfld.long 0x0 11. "PHY_PIPE_CMN_CTRL1_11,Reserved" "0,1" newline bitfld.long 0x0 10. "PHY_PIPE_CMN_CTRL1_10,PCIe PCS Comma realign: This field controls the comma alignment state machine to re-align to new bit position without going to loss of sync state." "0,1" newline bitfld.long 0x0 9. "PHY_PIPE_CMN_CTRL1_9,Block alignment clear on EIOS : When set upon receiving a PCIe EIOS 128b/130b block alignment is reset regardless of Rx signal detect from the PMA (applies for PCIe Gen 3 only)." "0,1" newline bitfld.long 0x0 8. "PHY_PIPE_CMN_CTRL1_8,Comma alignment clear on EIOS : When set upon receiving a PCIe EIOS Comma Alignment is reset regardless of Rx signal detect from the PMA (applies for PCIe Gen 1/2 only)." "0,1" newline bitfld.long 0x0 7. "PHY_PIPE_CMN_CTRL1_7,Block alignment ignore Rx SigDetect : When set 128b/13xb block alignment will not be reset due to loss of signal detection from the PMA (applies for PCIe Gen 3 and USB3.1 Gen 2 only)." "0,1" newline bitfld.long 0x0 6. "PHY_PIPE_CMN_CTRL1_6,Comma alignment ignore Rx SigDetect : When set Comma alignment will not be reset due to loss of signal detection from the PMA (applies for PCIe Gen 1/2 and USB3.1 Gen 1 only)." "0,1" newline bitfld.long 0x0 4.--5. "PHY_PIPE_CMN_CTRL1_5_4,Rx signal detect delay : Selects the number of clock cycles of delay to add to the PMA signal detect when the bit alignment blocks should be reset after losing signal." "0,1,2,3" newline rbitfld.long 0x0 2.--3. "PHY_PIPE_CMN_CTRL1_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "PHY_PIPE_CMN_CTRL1_1,RefClk disable override:" "0,1" newline bitfld.long 0x0 0. "PHY_PIPE_CMN_CTRL1_0,PHY RefClk enable input ingnore :" "0,1" line.long 0x4 "PHY_PIPE_COM_LOCK_CFG2__PHY_PIPE_COM_LOCK_CFG1,PIPE comma lock configuration1 register" hexmask.long.byte 0x4 24.--31. 1. "PHY_PIPE_COM_LOCK_CFG2_15_8,PCIe PCS Comma lock count fast: The number of COMMA symbols that needs to be seen in the same bit position for the comma state machine to lock." newline hexmask.long.byte 0x4 16.--23. 1. "PHY_PIPE_COM_LOCK_CFG2_7_0,PCIe PCS Comma lock count: The number of COMMA symbols that needs to be seen in the same bit position for the comma state machine to lock." newline hexmask.long.byte 0x4 12.--15. 1. "PHY_PIPE_COM_LOCK_CFG1_15_12,PCIe PCS Comma unlock count: The number of COMMA symbols that need to be seen in the wrong bit position before the comma alignment state machine will transition to RESYNC or LOS state" newline hexmask.long.word 0x4 0.--11. 1. "PHY_PIPE_COM_LOCK_CFG1_11_0,PCIe PCS Comma full lock count: The number of COMMA symbols that need to be seen in the same bit position for the comma alignment state machine to lock." line.long 0x8 "PHY_PIPE_LANE_DSBL__PHY_PIPE_EIE_LOCK_CFG,PIPE EIEOS lock configuration register" hexmask.long.byte 0x8 24.--31. 1. "PHY_PIPE_LANE_DSBL_15_8,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "PHY_PIPE_LANE_DSBL_7_0,PIPE lane disable: Each bit corresponds to a lane (i.e. bit [0] -X lane 0 bit [1] -X lane 1 etc)." newline hexmask.long.byte 0x8 12.--15. 1. "PHY_PIPE_EIE_LOCK_CFG_15_12,EIE lock count fast: The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4." newline hexmask.long.byte 0x8 8.--11. 1. "PHY_PIPE_EIE_LOCK_CFG_11_8,EIE lock count : The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4." newline hexmask.long.byte 0x8 0.--7. 1. "PHY_PIPE_EIE_LOCK_CFG_7_0,EIE full lock count: The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4." line.long 0xC "PHY_PIPE_RX_ELEC_IDLE_DLY__PHY_PIPE_RCV_DET_INH,PIPE receiver detect inhibit register" hexmask.long.byte 0xC 26.--31. 1. "PHY_PIPE_RX_ELEC_IDLE_DLY_15_10,PCIe PCS L1.x exit Rx electrical idle force fast count : Counter load value to hold PIPE Rx Electrical Idle high upon exit from L1.x." newline hexmask.long.word 0xC 16.--25. 1. "PHY_PIPE_RX_ELEC_IDLE_DLY_9_0,PCIe PCS L1.x exit Rx electrical idle force full count : Counter load value to hold PIPE Rx Electrical Idle high upon exit from L1.x when the PMA common was powered down." newline hexmask.long.word 0xC 0.--15. 1. "PHY_PIPE_RCV_DET_INH_15_0,PCS Receiver Detect Inhibit Counter Load Value: Counter load value to delay receiver detection request to PMA until PMA common mode is within the required range." line.long 0x10 "PHY_ISO_CMN_CTRL,PHY common control signal isolation register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" newline rbitfld.long 0x10 13.--15. "PHY_ISO_CMN_CTRL_15_13,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 12. "PHY_ISO_CMN_CTRL_12,Current value of phy_refclk_reqd PHY output." "0,1" newline rbitfld.long 0x10 9.--11. "PHY_ISO_CMN_CTRL_11_9,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PHY_ISO_CMN_CTRL_8,Drives phy_refclk_en PHY input when in PHY macro and PMA isolation mode." "0,1" newline rbitfld.long 0x10 6.--7. "PHY_ISO_CMN_CTRL_7_6,Reserved" "0,1,2,3" newline bitfld.long 0x10 5. "PHY_ISO_CMN_CTRL_5,Drives phy_pma_suspend_override PHY input when in PHY macro and PMA isolation mode." "0,1" newline bitfld.long 0x10 4. "PHY_ISO_CMN_CTRL_4,Drives refclk_rcvr_pwrdn internal PHY signal when in PHY macro and PMA isolation mode (1 = powers down the reference clock receiver)." "?,1: powers down the reference clock receiver" newline rbitfld.long 0x10 1.--3. "PHY_ISO_CMN_CTRL_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "PHY_ISO_CMN_CTRL_0,Drives phy_reset_n PHY input when in PHY macro and PMA isolation mode." "0,1" line.long 0x14 "PHY_STATE_CHG_TIMEOUT,PHY state change monitor timeout" hexmask.long.word 0x14 16.--31. 1. "RESERVED" newline hexmask.long.word 0x14 0.--15. 1. "PHY_STATE_CHG_TIMEOUT_15_0,State change timeout: Bits [19:4] of the state change timeout (bits [3:0] are zero)." group.long 0xC01C++0xF line.long 0x0 "PHY_AUTO_CFG_SPDUP,PHY speedup control register" hexmask.long.word 0x0 20.--31. 1. "PHY_AUTO_CFG_SPDUP_15_4,Reserved" newline rbitfld.long 0x0 19. "PHY_AUTO_CFG_SPDUP_3,Speedup configuration complete:" "0,1" newline bitfld.long 0x0 18. "PHY_AUTO_CFG_SPDUP_2,Speedup configuration stall:" "0,1" newline bitfld.long 0x0 17. "PHY_AUTO_CFG_SPDUP_1,Speedup configuration enable: If set to 1 upon de-assertion (high) of phy_reset_n the PHY will be configured for simulation speedup." "0,1" newline rbitfld.long 0x0 16. "PHY_AUTO_CFG_SPDUP_0,Reserved" "0,1" newline hexmask.long.word 0x0 2.--15. 1. "PHY_PLL_CFG_15_2,Reserved" newline bitfld.long 0x0 1. "PHY_PLL_CFG_1,PLL configuration:" "0,1" newline bitfld.long 0x0 0. "PHY_PLL_CFG_0,Single link PCIe configuration :" "0,1" line.long 0x4 "PHY_REFCLK_DET_THRES_HIGH__PHY_REFCLK_DET_THRES_LOW,PHY external reference clock detect low threshold register" hexmask.long.word 0x4 16.--31. 1. "PHY_REFCLK_DET_THRES_HIGH_15_0,External Reference Clock Active Detect High Threshold: This is the maximum number of external reference clock cycles which must be counted during the measurement interval to indicate a valid clock detected." newline hexmask.long.word 0x4 0.--15. 1. "PHY_REFCLK_DET_THRES_LOW_15_0,External Reference Clock Active Detect Low Threshold: This is the minimum number of external reference clock cycles which must be counted during the measurement interval to indicate a valid clock detected." line.long 0x8 "PHY_REFCLK_DET_OP_DELAY__PHY_REFCLK_DET_INTERVAL,PHY external reference clock detect measurement interval register" hexmask.long.byte 0x8 24.--31. 1. "PHY_REFCLK_DET_OP_DELAY_15_8,External Reference Clock Active Detect End Delay: This is the number of apb_pclk cycles to wait upon completion of measurement interval before capturing the result (accounts for synchronization delays)." newline hexmask.long.byte 0x8 16.--23. 1. "PHY_REFCLK_DET_OP_DELAY_7_0,External Reference Clock Active Detect Start Delay: This is the number of apb_pclk cycles to wait prior to start of measurement interval (accounts for enable delay of reference clock in PMA)." newline hexmask.long.word 0x8 0.--15. 1. "PHY_REFCLK_DET_INTERVAL_15_0,External Reference Clock Active Detect Measurement Interval: This is the number of apb_pclk cycles in which to count external reference clock cycles." line.long 0xC "PHY_REFCLK_DET_ISO_CTRL,PHY external reference clock detect isolation control register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline rbitfld.long 0xC 13.--15. "PHY_REFCLK_DET_ISO_CTRL_15_13,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 12. "PHY_REFCLK_DET_ISO_CTRL_12,Captures the current value of the pma_cmn_ext_refclk_detected_cfg PHY input." "0,1" newline rbitfld.long 0xC 10.--11. "PHY_REFCLK_DET_ISO_CTRL_11_10,Reserved" "0,1,2,3" newline rbitfld.long 0xC 9. "PHY_REFCLK_DET_ISO_CTRL_9,Current value of pma_cmn_ext_refclk_detected PHY output." "0,1" newline rbitfld.long 0xC 8. "PHY_REFCLK_DET_ISO_CTRL_8,Current value of pma_cmn_ext_refclk_detected_valid PHY output." "0,1" newline hexmask.long.byte 0xC 1.--7. 1. "PHY_REFCLK_DET_ISO_CTRL_7_1,Reserved" newline bitfld.long 0xC 0. "PHY_REFCLK_DET_ISO_CTRL_0,External Reference Clock Active Detect Start: Write with 1 to initiate an external reference clock active detect operation." "0,1" group.long 0xD000++0x17 line.long 0x0 "PHY_PIPE_ISO_TX_LPC_LO__PHY_PIPE_ISO_TX_CTRL_j,PIPE TX control signal isolation register Offset = D000h + (j * 200h); where j = 0h to 3h" rbitfld.long 0x0 30.--31. "PHY_PIPE_ISO_TX_LPC_LO_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "PHY_PIPE_ISO_TX_LPC_LO_13_8,Current value of pipe_tx_local_tx_preset_coefficients [11:6] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1." newline rbitfld.long 0x0 22.--23. "PHY_PIPE_ISO_TX_LPC_LO_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "PHY_PIPE_ISO_TX_LPC_LO_5_0,Current value of pipe_tx_local_tx_preset_coefficients [5:0] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1." newline hexmask.long.byte 0x0 12.--15. 1. "PHY_PIPE_ISO_TX_CTRL_15_12,Drives pipe_tx_data_k PHY input for the associated lane when in PHY macro and PMA isolation modes." newline rbitfld.long 0x0 9.--11. "PHY_PIPE_ISO_TX_CTRL_11_9,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PHY_PIPE_ISO_TX_CTRL_8,Drives pipe_tx_ones_zeros input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x0 5.--7. "PHY_PIPE_ISO_TX_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PHY_PIPE_ISO_TX_CTRL_4,Drives pipe_tx_elec_idle PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1" newline bitfld.long 0x0 3. "PHY_PIPE_ISO_TX_CTRL_3,Drives pipe_tx_128b_enc_byp PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x0 2. "PHY_PIPE_ISO_TX_CTRL_2,Drives pipe_tx_compliance PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x0 0.--1. "PHY_PIPE_ISO_TX_CTRL_1_0,Drives pipe_tx_pattern PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1,2,3" line.long 0x4 "PHY_PCS_ISO_TX_DMPH_LO__PHY_PIPE_ISO_TX_LPC_HI_j,PIPE TX local preset coefficients high isolation register Offset = D004h + (j * 200h); where j = 0h to 3h" rbitfld.long 0x4 30.--31. "PHY_PCS_ISO_TX_DMPH_LO_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 24.--29. 1. "PHY_PCS_ISO_TX_DMPH_LO_13_8,Drives pipe_tx_deemph[11:6] PHY input for the associated lane when in PHY macro and PMA isolation mode." newline rbitfld.long 0x4 22.--23. "PHY_PCS_ISO_TX_DMPH_LO_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "PHY_PCS_ISO_TX_DMPH_LO_5_0,Drives pipe_tx_deemph[5:0] PHY input for the associated lane when in PHY macro and PMA isolation mode." newline rbitfld.long 0x4 15. "PHY_PIPE_ISO_TX_LPC_HI_15,Set upon assertion of pipe_tx_local_tx_coeff_vld PHY output for the associated lane." "0,1" newline rbitfld.long 0x4 13.--14. "PHY_PIPE_ISO_TX_LPC_HI_14_13,Reserved" "0,1,2,3" newline bitfld.long 0x4 12. "PHY_PIPE_ISO_TX_LPC_HI_12,Drives pipe_tx_get_local_preset_coef PHY output for the associated lane when in PHY macro and PMA isolation modes" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "PHY_PIPE_ISO_TX_LPC_HI_11_8,Drives pipe_tx_local_preset_index PHY output for the associated lane when in PHY macro and PMA isolation modes." newline rbitfld.long 0x4 6.--7. "PHY_PIPE_ISO_TX_LPC_HI_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "PHY_PIPE_ISO_TX_LPC_HI_5_0,Current value of pipe_tx_local_tx_preset_coefficients[17:12] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1." line.long 0x8 "PHY_PIPE_ISO_TX_FSLF__PHY_PIPE_ISO_TX_DMPH_HI_j,PIPE TX deemphasis high isolation register Offset = D008h + (j * 200h); where j = 0h to 3h" rbitfld.long 0x8 30.--31. "PHY_PIPE_ISO_TX_FSLF_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "PHY_PIPE_ISO_TX_FSLF_13_8,Current value of pipe_tx_local_fs PHY output for the associated lane." newline rbitfld.long 0x8 22.--23. "PHY_PIPE_ISO_TX_FSLF_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "PHY_PIPE_ISO_TX_FSLF_5_0,Current value of pipe_tx_local_lf PHY output for the associated lane." newline hexmask.long.word 0x8 6.--15. 1. "PHY_PIPE_ISO_TX_DMPH_HI_15_6,Reserved" newline hexmask.long.byte 0x8 0.--5. 1. "PHY_PIPE_ISO_TX_DMPH_HI_5_0,Drives pipe_tx_deemph[17:12] PHY input for the associated lane when in PHY macro and PMA isolation modes." line.long 0xC "PHY_PCS_ISO_TX_DATA_HI__PHY_PCS_ISO_TX_DATA_LO_j,PCS TX PIPE data low isolation register Offset = D00Ch + (j * 200h); where j = 0h to 3h" hexmask.long.word 0xC 16.--31. 1. "PHY_PCS_ISO_TX_DATA_HI_15_0,Drives pipe_tx_data[31:16] PHY input for the associated lane when in PHY macro and PMA isolation mode." newline hexmask.long.word 0xC 0.--15. 1. "PHY_PCS_ISO_TX_DATA_LO_15_0,Drives pipe_tx_data[15:0] PHY input for the associated lane when in PHY macro and PMA isolation mode." line.long 0x10 "PHY_PIPE_ISO_RX_EQ_EVAL__PHY_PCS_ISO_RX_CTRL_j,PCS RX control signal isolation register Offset = D010h + (j * 200h); where j = 0h to 3h" rbitfld.long 0x10 29.--31. "PHY_PIPE_ISO_RX_EQ_EVAL_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 28. "PHY_PIPE_ISO_RX_EQ_EVAL_12,Drives pipe_invalid_request for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x10 27. "PHY_PIPE_ISO_RX_EQ_EVAL_11,pipe_link_eval_dir_change[5:4] bit reversal enable." "0,1" newline bitfld.long 0x10 26. "PHY_PIPE_ISO_RX_EQ_EVAL_10,pipe_link_eval_dir_change[3:2] bit reversal enable." "0,1" newline bitfld.long 0x10 25. "PHY_PIPE_ISO_RX_EQ_EVAL_9,pipe_link_eval_dir_change[1:0] bit reversal enable." "0,1" newline bitfld.long 0x10 24. "PHY_PIPE_ISO_RX_EQ_EVAL_8,Drives pipe_rx_eval PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x10 23. "PHY_PIPE_ISO_RX_EQ_EVAL_7,Reserved" "0,1" newline rbitfld.long 0x10 22. "PHY_PIPE_ISO_RX_EQ_EVAL_6,Captures pipe_phy_status for Rx equalization evaluation PHY output for the associated lane (does not include power state change signaling)." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "PHY_PIPE_ISO_RX_EQ_EVAL_5_0,pipe_link_eval_dir_change PHY output for the associated lane (prior to bit reversal logic) upon completion of Rx equalization evaluation." newline hexmask.long.byte 0x10 12.--15. 1. "PHY_PCS_ISO_RX_CTRL_15_12,Current value of pipe_rx_data_k PHY output for the associated lane when PHY_PCS_ISO_RX_CTRL[5] == 1." newline rbitfld.long 0x10 10.--11. "PHY_PCS_ISO_RX_CTRL_11_10,Reserved" "0,1,2,3" newline bitfld.long 0x10 9. "PHY_PCS_ISO_RX_CTRL_9,Drives pipe_rx_eq_training PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x10 8. "PHY_PCS_ISO_RX_CTRL_8,Drives pipe_rx_termination PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x10 7. "PHY_PCS_ISO_RX_CTRL_7,Drives pipe_rx_polarity PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x10 6. "PHY_PCS_ISO_RX_CTRL_6,Reserved" "0,1" newline rbitfld.long 0x10 5. "PHY_PCS_ISO_RX_CTRL_5,Current value of pipe_rx_valid PHY output for the associated lane." "0,1" newline rbitfld.long 0x10 4. "PHY_PCS_ISO_RX_CTRL_4,Current value of pipe_rx_elec_idle PHY output for the associated lane." "0,1" newline rbitfld.long 0x10 3. "PHY_PCS_ISO_RX_CTRL_3,Current value of pipe_align_detect PHY output for the associated lane." "0,1" newline rbitfld.long 0x10 0.--2. "PHY_PCS_ISO_RX_CTRL_2_0,Current value of pipe_rx_status PHY output for the associated lane." "0,1,2,3,4,5,6,7" line.long 0x14 "PHY_PCS_ISO_LINK_CTRL__PHY_ISO_LINK_CFG_j,PHY link configuration isolation register Offset = D014h + (j * 200h); where j = 0h to 3h" rbitfld.long 0x14 30.--31. "PHY_PCS_ISO_LINK_CTRL_15_14,Reserved" "0,1,2,3" newline rbitfld.long 0x14 29. "PHY_PCS_ISO_LINK_CTRL_13,Current value of phy_l*_ack_l1_x PHY output for the associated lane." "0,1" newline bitfld.long 0x14 28. "PHY_PCS_ISO_LINK_CTRL_12,Drives the phy_l*_ent_l1_x PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x14 27. "PHY_PCS_ISO_LINK_CTRL_11,Drives the phy_l*_rx_elec_idle_det_en PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x14 26. "PHY_PCS_ISO_LINK_CTRL_10,Drives the phy_l*_tx_cmn_mode_en PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x14 24.--25. "PHY_PCS_ISO_LINK_CTRL_9_8,Drives the pipe_l*_rate PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1,2,3" newline rbitfld.long 0x14 23. "PHY_PCS_ISO_LINK_CTRL_7,Reserved" "0,1" newline bitfld.long 0x14 20.--22. "PHY_PCS_ISO_LINK_CTRL_6_4,Drives the pipe_l*_powerdown PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 19. "PHY_PCS_ISO_LINK_CTRL_3,Reserved" "0,1" newline bitfld.long 0x14 18. "PHY_PCS_ISO_LINK_CTRL_2,Drives the pipe_l*_tx_det_rx_lpbk PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x14 17. "PHY_PCS_ISO_LINK_CTRL_1,Captures pipe_l*_phy_status (for power state and rate change) PHY output for the associated lane." "0,1" newline bitfld.long 0x14 16. "PHY_PCS_ISO_LINK_CTRL_0,Drives the phy_l*_reset_n PHY input for the associated lane when in PHY macro and PMA isolation modes." "0,1" newline bitfld.long 0x14 15. "PHY_ISO_LINK_CFG_15,Drives phy_link_cfg_ln_{nnnn} PHY input when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x14 13.--14. "PHY_ISO_LINK_CFG_14_13,Reserved" "0,1,2,3" newline bitfld.long 0x14 12. "PHY_ISO_LINK_CFG_12,Drives pipe_l{nnnn}_32bit_sel PHY input when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x14 10.--11. "PHY_ISO_LINK_CFG_11_10,Reserved" "0,1,2,3" newline bitfld.long 0x14 8.--9. "PHY_ISO_LINK_CFG_9_8,Drives pma_fullrt_div_ln_{nnnn} PHY input when in PHY macro and PMA isolation modes." "0,1,2,3" newline rbitfld.long 0x14 6.--7. "PHY_ISO_LINK_CFG_7_6,Reserved" "0,1,2,3" newline bitfld.long 0x14 5. "PHY_ISO_LINK_CFG_5,Drives pipe_l{nnnn}_pcie_l1_ss_sel PHY input when in PHY macro and PMA isolation mode." "0,1" newline bitfld.long 0x14 4. "PHY_ISO_LINK_CFG_4,Drives pipe_l{nnnn}_eb_mode PHY input when in PHY macro and PMA isolation modes." "0,1" newline rbitfld.long 0x14 2.--3. "PHY_ISO_LINK_CFG_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x14 0.--1. "PHY_ISO_LINK_CFG_1_0,Drives phy_l{nnnn}_mode PHY input when in PHY macro and PMA isolation modes." "0,1,2,3" rgroup.long 0xD018++0x7 line.long 0x0 "PHY_PIPE_ISO_USB_BER_CNT_j,PIPE USB Gen 1 loopback slave BER count register Offset = D018h + (j * 200h); where j = 0h to 3h" hexmask.long.word 0x0 16.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 8.--15. 1. "PHY_PIPE_ISO_USB_BER_CNT_15_8,Reerved" newline hexmask.long.byte 0x0 0.--7. 1. "PHY_PIPE_ISO_USB_BER_CNT_7_0,Current value of USB 3.1 Gen 1 loopback slave Bit Error Count from the PCS." line.long 0x4 "PHY_PCS_ISO_RX_DATA_HI__PHY_PCS_ISO_RX_DATA_LO_j,PCS RX data low isolation register Offset = D01Ch + (j * 200h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "PHY_PCS_ISO_RX_DATA_HI_15_0,Current value of pipe_rx_data[31:16] PHY output." newline hexmask.long.word 0x4 0.--15. 1. "PHY_PCS_ISO_RX_DATA_LO_15_0,Current value of pipe_rx_data[15:0] PHY output." group.long 0xD020++0x7 line.long 0x0 "PHY_ETH_ISO_MAC_CLK_DIV__PHY_ETH_ISO_MAC_CLK_CFG_j,Ethernet MAC clock configuration isolation register Offset = D020h + (j * 200h); where j = 0h to 3h" hexmask.long.word 0x0 23.--31. 1. "PHY_ETH_ISO_MAC_CLK_DIV_15_7,Drives mac_div_sel1 PHY input for the associated lane when in PHY macro and PMA isolation mode." newline hexmask.long.byte 0x0 16.--22. 1. "PHY_ETH_ISO_MAC_CLK_DIV_6_0,Drives mac_div_sel0 PHY input for the associated lane when in PHY macro and PMA isolation mode." newline hexmask.long.word 0x0 2.--15. 1. "PHY_ETH_ISO_MAC_CLK_CFG_15_2,Reserved" newline bitfld.long 0x0 0.--1. "PHY_ETH_ISO_MAC_CLK_CFG_1_0,Drives mac_src_sel PHY input for the associated lane when in PHY macro and PMA isolation mode." "0,1,2,3" line.long 0x4 "PHY_INTERRUPT_STS_j,PHY interrupt status register Offset = D024h + (j * 200h); where j = 0h to 3h" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline bitfld.long 0x4 15. "PHY_INTERRUPT_STS_15,State change monitor enable -" "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "PHY_INTERRUPT_STS_14_11,Reserved" newline rbitfld.long 0x4 8.--10. "PHY_INTERRUPT_STS_10_8,Next power state/data rate - Only valid when one of the interrupt status bits is set." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 7. "PHY_INTERRUPT_STS_7,Reserved" "0,1" newline rbitfld.long 0x4 4.--6. "PHY_INTERRUPT_STS_6_4,Current power state/data rate - Only valid when one of the interrupt status bits is set." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 2.--3. "PHY_INTERRUPT_STS_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x4 1. "PHY_INTERRUPT_STS_1,Data rate state change interrupt status - Set to 1 upon data rate change timeout." "0,1" newline bitfld.long 0x4 0. "PHY_INTERRUPT_STS_0,Power state change interrupt status - Set to 1 upon power state change timeout." "0,1" group.long 0xE000++0xF line.long 0x0 "PHY_PMA_CMN_CTRL2__PHY_PMA_CMN_CTRL1,PMA common control1 register" hexmask.long.byte 0x0 24.--31. 1. "PHY_PMA_CMN_CTRL2_15_8,Reserved" newline rbitfld.long 0x0 23. "PHY_PMA_CMN_CTRL2_7,Current value of cmn_pll1_locked PMA output" "0,1" newline rbitfld.long 0x0 22. "PHY_PMA_CMN_CTRL2_6,Current value of cmn_pll0_locked PMA output" "0,1" newline rbitfld.long 0x0 21. "PHY_PMA_CMN_CTRL2_5,Current value of cmn_pll1_clk_en_ack PMA output" "0,1" newline rbitfld.long 0x0 20. "PHY_PMA_CMN_CTRL2_4,Current value of cmn_pll0_clk_en_ack PMA output" "0,1" newline rbitfld.long 0x0 19. "PHY_PMA_CMN_CTRL2_3,Current value of cmn_pll1_disabled PMA output" "0,1" newline rbitfld.long 0x0 18. "PHY_PMA_CMN_CTRL2_2,Current value of cmn_pll0_disabled PMA output" "0,1" newline rbitfld.long 0x0 17. "PHY_PMA_CMN_CTRL2_1,Current value of cmn_pll1_ready PMA output" "0,1" newline rbitfld.long 0x0 16. "PHY_PMA_CMN_CTRL2_0,Current value of cmn_pll0_ready PMA output" "0,1" newline hexmask.long.word 0x0 7.--15. 1. "PHY_PMA_CMN_CTRL1_15_7,Reserved" newline bitfld.long 0x0 6. "PHY_PMA_CMN_CTRL1_6,Drives cmn_refclk_rcv_out_en PMA input" "0,1" newline rbitfld.long 0x0 5. "PHY_PMA_CMN_CTRL1_5,Current value of cmn_macro_suspend_ack PMA output" "0,1" newline rbitfld.long 0x0 4. "PHY_PMA_CMN_CTRL1_4,Current value of cmn_refclk_active PMA output" "0,1" newline rbitfld.long 0x0 1.--3. "PHY_PMA_CMN_CTRL1_3_1,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 0. "PHY_PMA_CMN_CTRL1_0,Current value of cmn_ready pin PMA output" "0,1" line.long 0x4 "PHY_PMA_PLL_RAW_CTRL__PHY_PMA_SSM_STATE,PMA SSM current state register" hexmask.long.word 0x4 18.--31. 1. "PHY_PMA_PLL_RAW_CTRL_15_2,Reserved" newline bitfld.long 0x4 17. "PHY_PMA_PLL_RAW_CTRL_1,Raw SerDes PLL1 control : When set to 1 cmn_pll1_en PMA input is controlled by PHY logic." "0,1" newline bitfld.long 0x4 16. "PHY_PMA_PLL_RAW_CTRL_0,Raw SerDes PLL0 control : When set to 1 cmn_pll0_en PMA input is controlled by PHY logic." "0,1" newline hexmask.long.byte 0x4 9.--15. 1. "PHY_PMA_SSM_STATE_15_9,Reserved" newline hexmask.long.word 0x4 0.--8. 1. "PHY_PMA_SSM_STATE_8_0,PMA SSM : Current state of the PMA startup state machine." line.long 0x8 "PHY_PMA_ISO_PLL_CTRL0__PHY_PMA_ISO_CMN_CTRL,PMA common control signal isolation register" hexmask.long.byte 0x8 24.--31. 1. "PHY_PMA_ISO_PLL_CTRL0_15_8,Reserved" newline bitfld.long 0x8 23. "PHY_PMA_ISO_PLL_CTRL0_7,Drives cmn_pll1_ref_clk_sel PMA input when in PHY macro or PMA isolation mode." "0,1" newline bitfld.long 0x8 22. "PHY_PMA_ISO_PLL_CTRL0_6,Drives cmn_pll0_ref_clk_sel PMA input when in PHY macro or PMA isolation mode." "0,1" newline bitfld.long 0x8 21. "PHY_PMA_ISO_PLL_CTRL0_5,Drives cmn_pll1_mode_sel PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 20. "PHY_PMA_ISO_PLL_CTRL0_4,Drives cmn_pll0_mode_sel PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 19. "PHY_PMA_ISO_PLL_CTRL0_3,Drives cmn_pll1_clk_en PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 18. "PHY_PMA_ISO_PLL_CTRL0_2,Drives cmn_pll0_clk_en PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 17. "PHY_PMA_ISO_PLL_CTRL0_1,Drives cmn_pll1_en PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 16. "PHY_PMA_ISO_PLL_CTRL0_0,Drives cmn_pll0_en PMA input when in PMA isolation mode" "0,1" newline bitfld.long 0x8 15. "PHY_PMA_ISO_CMN_CTRL_15,Drives cmn_ref_clk_term_en PMA input when in PHY macro or PMA isolation modes" "0,1" newline bitfld.long 0x8 14. "PHY_PMA_ISO_CMN_CTRL_14,Drives cmn_ref_clk_dig_sel PMA input when in PHY macro or PMA isolation modes" "0,1" newline bitfld.long 0x8 12.--13. "PHY_PMA_ISO_CMN_CTRL_13_12,Drives cmn_ref_clk_dig_div PMA input when in PHY macro or PMA isolation modes" "0,1,2,3" newline bitfld.long 0x8 10.--11. "PHY_PMA_ISO_CMN_CTRL_11_10,Drives cmn_ref_clk_int_mode PMA input when in PHY macro and PMA isolation modes." "0,1,2,3" newline bitfld.long 0x8 8.--9. "PHY_PMA_ISO_CMN_CTRL_9_8,Drives cmn_ref_clk0_mode PMA input when in PHY macro and PMA isolation modes." "0,1,2,3" newline rbitfld.long 0x8 7. "PHY_PMA_ISO_CMN_CTRL_7,Current value of cmn_clock_stop_ack PMA output." "0,1" newline bitfld.long 0x8 6. "PHY_PMA_ISO_CMN_CTRL_6,Drives cmn_clock_stop_req PMA input when in PMA isolation mode" "0,1" newline rbitfld.long 0x8 5. "PHY_PMA_ISO_CMN_CTRL_5,Reserved" "0,1" newline bitfld.long 0x8 4. "PHY_PMA_ISO_CMN_CTRL_4,Drives cmn_ref_clk0_clk_gate_en PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 3. "PHY_PMA_ISO_CMN_CTRL_3,Drives cmn_refclk_disable PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x8 2. "PHY_PMA_ISO_CMN_CTRL_2,Drives cmn_macro_suspend_req PMA input when in PMA isolation mode." "0,1" newline rbitfld.long 0x8 1. "PHY_PMA_ISO_CMN_CTRL_1,Reserved" "0,1" newline bitfld.long 0x8 0. "PHY_PMA_ISO_CMN_CTRL_0,Drives cmn_reset_n PMA input when in PMA isolation mode." "0,1" line.long 0xC "PHY_PMA_ISO_PLL_CTRL1,PMA PLL control1 isolation register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 12.--15. 1. "PHY_PMA_ISO_PLL_CTRL1_15_12,Drives cmn_pll1_clk_datart1_div PMA input when in PMA isolation mode" newline hexmask.long.byte 0xC 8.--11. 1. "PHY_PMA_ISO_PLL_CTRL1_11_8,Drives cmn_pll1_clk_datart0_div PMA input when in PMA isolation mode" newline hexmask.long.byte 0xC 4.--7. 1. "PHY_PMA_ISO_PLL_CTRL1_7_4,Drives cmn_pll0_clk_datart1_div PMA input when in PMA isolation mode" newline hexmask.long.byte 0xC 0.--3. 1. "PHY_PMA_ISO_PLL_CTRL1_3_0,Drives cmn_pll0_clk_datart0_div PMA input when in PMA isolation mode" rgroup.long 0xE014++0x7 line.long 0x0 "PHY_PMA_PLL0_SM_STATE,PMA PLL0 State Machine current state register" hexmask.long.byte 0x0 28.--31. 1. "PHY_PMA_PLL0_SM_STATE_15_12,Reserved" newline hexmask.long.word 0x0 16.--27. 1. "PHY_PMA_PLL0_SM_STATE_11_0,Current value of cmn_pllsm0_state[11:0]." newline hexmask.long.word 0x0 0.--15. 1. "RESERVED" line.long 0x4 "PHY_PMA_PLL1_SM_STATE,PMA PLL1 State Machine current state register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 12.--15. 1. "PHY_PMA_PLL1_SM_STATE_15_12,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "PHY_PMA_PLL1_SM_STATE_11_0,Current value of cmn_pllsm1_state[11:0]." group.long 0xE01C++0x3 line.long 0x0 "PHY_PMA_ISOLATION_CTRL,PMA Isolation control register" bitfld.long 0x0 31. "PHY_PMA_ISOLATION_CTRL_15,PHY/PMA isolation enable (isolation_en) - When set enables isolation (PHY or PMA)." "0,1" newline bitfld.long 0x0 30. "PHY_PMA_ISOLATION_CTRL_14,PHY/PMA common isolation enable (cmn_isolation_en) - When in PHY Macro Isolation Mode the PHY common isolation register(s) are selected." "0,1" newline rbitfld.long 0x0 29. "PHY_PMA_ISOLATION_CTRL_13,Reserved" "0,1" newline bitfld.long 0x0 28. "PHY_PMA_ISOLATION_CTRL_12,PHY/PMA isolation mode select (isolation_mode_sel) - When isolation_en is set this bit selects between PHY isolation mode and PMA isolation mode." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "PHY_PMA_ISOLATION_CTRL_11_8,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "PHY_PMA_ISOLATION_CTRL_7_0,PHY/PMA lane isolation enable (ln_isolation_en) - When in PHY Macro Isolation Mode the selected PHY lane(s) isolation registers are selected." newline hexmask.long.word 0x0 0.--15. 1. "RESERVED" group.long 0xF000++0x1B line.long 0x0 "PHY_PMA_XCVR_LPBK__PHY_PMA_XCVR_CTRL_j,PMA transceiver control register Offset = F000h + (j * 200h); where j = 0h to 3h" hexmask.long.byte 0x0 25.--31. 1. "PHY_PMA_XCVR_LPBK_15_9,Reserved" newline bitfld.long 0x0 24. "PHY_PMA_XCVR_LPBK_8,Drives the tx_bist_hold PMA input for all lanes in the associated link (i.e. the bit associated with the master lane of the link drives all lanes in the link)." "0,1" newline rbitfld.long 0x0 22.--23. "PHY_PMA_XCVR_LPBK_7_6,Reserved" "0,1,2,3" newline bitfld.long 0x0 21. "PHY_PMA_XCVR_LPBK_5,Drives the xcvr_lpbk_fe_parallel_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 20. "PHY_PMA_XCVR_LPBK_4,Drives the xcvr_lpbk_ne_parallel_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 19. "PHY_PMA_XCVR_LPBK_3,Drives the xcvr_lpbk_recovered_clk_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 18. "PHY_PMA_XCVR_LPBK_2,Drives the xcvr_lpbk_line_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 17. "PHY_PMA_XCVR_LPBK_1,Drives the xcvr_lpbk_isi_gen_en PMA input for the associated lane." "0,1" newline bitfld.long 0x0 16. "PHY_PMA_XCVR_LPBK_0,Drives the xcvr_lpbk_serial_en PMA input for the associated lane." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "PHY_PMA_XCVR_CTRL_15_9,Reserved" newline bitfld.long 0x0 8. "PHY_PMA_XCVR_CTRL_8,Drives the tx_differential_invert PMA input for the associated lane." "0,1" newline rbitfld.long 0x0 5.--7. "PHY_PMA_XCVR_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 4. "PHY_PMA_XCVR_CTRL_4,Current value of rx_cdrlf_fphl_locked PMA output for the associated lane." "0,1" newline rbitfld.long 0x0 3. "PHY_PMA_XCVR_CTRL_3,Current value of rx_bist_status PMA output for the associated lane." "0,1" newline rbitfld.long 0x0 2. "PHY_PMA_XCVR_CTRL_2,Current value of rx_bist_err_toggle PMA output for the associated lane." "0,1" newline rbitfld.long 0x0 1. "PHY_PMA_XCVR_CTRL_1,Current value of rx_bist_sync PMA output for the associated lane." "0,1" newline bitfld.long 0x0 0. "PHY_PMA_XCVR_CTRL_0,Drives the rx_differential_invert PMA input for the associated lane." "0,1" line.long 0x4 "PHY_PMA_ISO_XCVR_CTRL_j,PMA Transceiver control isolation register Offset = F004h + (j * 200h); where j = 0h to 3h" rbitfld.long 0x4 31. "PHY_PMA_ISO_XCVR_CTRL_15,Current value of xcvr_pll_clk_en_ack PMA output for the associated lane." "0,1" newline rbitfld.long 0x4 30. "PHY_PMA_ISO_XCVR_CTRL_14,Reserved" "0,1" newline bitfld.long 0x4 29. "PHY_PMA_ISO_XCVR_CTRL_13,Drives tx_lfps_en PMA input for the associated lane when in PMA isolation mode." "0,1" newline bitfld.long 0x4 28. "PHY_PMA_ISO_XCVR_CTRL_12,Drives tx_elec_idle PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline rbitfld.long 0x4 27. "PHY_PMA_ISO_XCVR_CTRL_11,Current value of tx_rcv_detected PMA output for the associated lane." "0,1" newline rbitfld.long 0x4 26. "PHY_PMA_ISO_XCVR_CTRL_10,Current value of tx_rcv_detect_done PMA ouptut for the associated lane." "0,1" newline bitfld.long 0x4 25. "PHY_PMA_ISO_XCVR_CTRL_9,Drives tx_rcv_detect_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline bitfld.long 0x4 24. "PHY_PMA_ISO_XCVR_CTRL_8,Drives xcvr_link_reset_n PMA input for the associated lane when in PMA isolation mode." "0,1" newline bitfld.long 0x4 23. "PHY_PMA_ISO_XCVR_CTRL_7,Drives xcvr_pll_clk_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline rbitfld.long 0x4 22. "PHY_PMA_ISO_XCVR_CTRL_6,Reserved" "0,1" newline bitfld.long 0x4 21. "PHY_PMA_ISO_XCVR_CTRL_5,Drives xcvr_lane_suspend PMA input for the associated lane when in PMA isolation mode." "0,1" newline rbitfld.long 0x4 20. "PHY_PMA_ISO_XCVR_CTRL_4,Current value of rx_lfps_detect PMA output for the associated lane." "0,1" newline rbitfld.long 0x4 19. "PHY_PMA_ISO_XCVR_CTRL_3,Current value of rx_signal_detect PMA output for the associated lane." "0,1" newline rbitfld.long 0x4 18. "PHY_PMA_ISO_XCVR_CTRL_2,Reserved" "0,1" newline bitfld.long 0x4 17. "PHY_PMA_ISO_XCVR_CTRL_1,Drives rx_termination PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline rbitfld.long 0x4 16. "PHY_PMA_ISO_XCVR_CTRL_0,Reserved" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "PHY_PMA_PI_POS_15_8,Current value of rx_pi_val PMA output for the associated lane." newline hexmask.long.byte 0x4 0.--7. 1. "PHY_PMA_PI_POS_7_0,Current value of rx_eye_plot_pi_val PMA output for the associated lane." line.long 0x8 "PHY_PMA_ISO_TX_LPC_HI__PHY_PMA_ISO_TX_LPC_LO_j,PMA transmitter local preset coefficient low isolation register Offset = F008h + (j * 200h); where j = 0h to 3h" rbitfld.long 0x8 31. "PHY_PMA_ISO_TX_LPC_HI_15,Current value of tx_local_preset_coef_valid PMA output for the associated lane." "0,1" newline rbitfld.long 0x8 29.--30. "PHY_PMA_ISO_TX_LPC_HI_14_13,Reserved" "0,1,2,3" newline bitfld.long 0x8 28. "PHY_PMA_ISO_TX_LPC_HI_12,Drives tx_get_local_preset_coef PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "PHY_PMA_ISO_TX_LPC_HI_11_8,Drives tx_local_preset_index PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." newline rbitfld.long 0x8 22.--23. "PHY_PMA_ISO_TX_LPC_HI_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "PHY_PMA_ISO_TX_LPC_HI_5_0,Value of tx_local_tx_preset_coef[17:12] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane." newline rbitfld.long 0x8 14.--15. "PHY_PMA_ISO_TX_LPC_LO_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 8.--13. 1. "PHY_PMA_ISO_TX_LPC_LO_13_8,Value of tx_local_tx_preset_coef[11:6] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane." newline rbitfld.long 0x8 6.--7. "PHY_PMA_ISO_TX_LPC_LO_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "PHY_PMA_ISO_TX_LPC_LO_5_0,Value of tx_local_tx_preset_coef[5:0] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane." line.long 0xC "PHY_PMA_ISO_TX_DMPH_HI__PHY_PMA_ISO_TX_DMPH_LO_j,PMA Tx de-emphasis low isolation register Offset = F00Ch + (j * 200h); where j = 0h to 3h" hexmask.long.word 0xC 22.--31. 1. "PHY_PMA_ISO_TX_DMPH_HI_15_6,Reserved" newline hexmask.long.byte 0xC 16.--21. 1. "PHY_PMA_ISO_TX_DMPH_HI_5_0,Drives tx_deemphasis [17:12] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." newline rbitfld.long 0xC 14.--15. "PHY_PMA_ISO_TX_DMPH_LO_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 8.--13. 1. "PHY_PMA_ISO_TX_DMPH_LO_13_8,Drives tx_deemphasis [11:6] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." newline rbitfld.long 0xC 6.--7. "PHY_PMA_ISO_TX_DMPH_LO_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "PHY_PMA_ISO_TX_DMPH_LO_5_0,Drives tx_deemphasis [5:0] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." line.long 0x10 "PHY_PMA_ISO_TX_MGN__PHY_PMA_ISO_TX_FSLF_j,PMA Tx FS/LF isolation register Offset = F010h + (j * 200h); where j = 0h to 3h" hexmask.long.byte 0x10 25.--31. 1. "PHY_PMA_ISO_TX_MGN_15_9,Reserved" newline bitfld.long 0x10 24. "PHY_PMA_ISO_TX_MGN_8,Drives tx_low_power_swing_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline hexmask.long.byte 0x10 19.--23. 1. "PHY_PMA_ISO_TX_MGN_7_3,Reserved" newline bitfld.long 0x10 16.--18. "PHY_PMA_ISO_TX_MGN_2_0,Drives tx_vmargin PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 14.--15. "PHY_PMA_ISO_TX_FSLF_15_14,Reserved" "0,1,2,3" newline hexmask.long.byte 0x10 8.--13. 1. "PHY_PMA_ISO_TX_FSLF_13_8,Current value of tx_local_fs PMA ouptut for the associated lane." newline rbitfld.long 0x10 6.--7. "PHY_PMA_ISO_TX_FSLF_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x10 0.--5. 1. "PHY_PMA_ISO_TX_FSLF_5_0,Current value of tx_local_lf PMA ouptut for the associated lane." line.long 0x14 "PHY_PMA_ISO_PWRST_CTRL__PHY_PMA_ISO_LINK_MODE_j,PMA Isolation mode control register Offset = F014h + (j * 200h); where j = 0h to 3h" bitfld.long 0x14 31. "PHY_PMA_ISO_PWRST_CTRL_15,rx_sig_det_en_ext_ln_{nnnn} PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x14 30. "PHY_PMA_ISO_PWRST_CTRL_14,tx_cmn_mode_en_ext_ln_{nnnn} PMA input when in PMA isolation mode." "0,1" newline hexmask.long.byte 0x14 24.--29. 1. "PHY_PMA_ISO_PWRST_CTRL_13_8,Current value of xcvr_power_state_ack_ln_{nnnn} PMA output." newline rbitfld.long 0x14 22.--23. "PHY_PMA_ISO_PWRST_CTRL_7_6,Reserved" "0,1,2,3" newline hexmask.long.byte 0x14 16.--21. 1. "PHY_PMA_ISO_PWRST_CTRL_5_0,Drives xcvr_power_state_req_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode.." newline bitfld.long 0x14 15. "PHY_PMA_ISO_LINK_MODE_15,tx_reset_n_ln_{nnnn} PMA input when in PMA isolation mode." "0,1" newline bitfld.long 0x14 14. "PHY_PMA_ISO_LINK_MODE_14,rx_reset_n_ln_{nnnn} PMA input when in PMA isolation mode." "0,1" newline hexmask.long.byte 0x14 6.--13. 1. "PHY_PMA_ISO_LINK_MODE_13_6,Reserved" newline bitfld.long 0x14 4.--5. "PHY_PMA_ISO_LINK_MODE_5_4,Drives xcvr_standard_mode_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1,2,3" newline rbitfld.long 0x14 3. "PHY_PMA_ISO_LINK_MODE_3,Reserved" "0,1" newline bitfld.long 0x14 0.--2. "PHY_PMA_ISO_LINK_MODE_2_0,Drives xcvr_data_width_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1,2,3,4,5,6,7" line.long 0x18 "PHY_PMA_ISO_RX_EQ_CTRL_j,PMA RX equalization control isolation register Offset = F018h + (j * 200h); where j = 0h to 3h" rbitfld.long 0x18 30.--31. "PHY_PMA_ISO_RX_EQ_CTRL_15_14,Reserved" "0,1,2,3" newline bitfld.long 0x18 29. "PHY_PMA_ISO_RX_EQ_CTRL_13,Drives rx_eq_training_data_valid PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline bitfld.long 0x18 28. "PHY_PMA_ISO_RX_EQ_CTRL_12,Drives rx_eq_training PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline rbitfld.long 0x18 26.--27. "PHY_PMA_ISO_RX_EQ_CTRL_11_10,Reserved" "0,1,2,3" newline hexmask.long.byte 0x18 20.--25. 1. "PHY_PMA_ISO_RX_EQ_CTRL_9_4,The value of rx_link_eval_fb_dir_change PMA output for the associated lane upon assertion of rx_eq_eval_status to PMA." newline rbitfld.long 0x18 19. "PHY_PMA_ISO_RX_EQ_CTRL_3,The value of rx_eq_eval_complete PMA output for the associated lane upon assertion of rx_eq_eval_status." "0,1" newline bitfld.long 0x18 18. "PHY_PMA_ISO_RX_EQ_CTRL_2,Drives rx_invalid_request PMA input for the associated lane when in PMA isolation mode." "0,1" newline rbitfld.long 0x18 17. "PHY_PMA_ISO_RX_EQ_CTRL_1,Current value of rx_eq_eval_status PMA output for the associated lane." "0,1" newline bitfld.long 0x18 16. "PHY_PMA_ISO_RX_EQ_CTRL_0,Drives rx_eq_eval PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode." "0,1" newline hexmask.long.word 0x18 0.--15. 1. "RESERVED" rgroup.long 0xF01C++0x7 line.long 0x0 "PHY_PMA_ISO_DATA_HI__PHY_PMA_ISO_DATA_LO_j,PMA low data isolation register Offset = F01Ch + (j * 200h); where j = 0h to 3h" hexmask.long.word 0x0 20.--31. 1. "PHY_PMA_ISO_DATA_HI_15_4,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_PMA_ISO_DATA_HI_3_0,Current value of rx_rd[19:16] PMA output for the current lane." newline hexmask.long.word 0x0 0.--15. 1. "PHY_PMA_ISO_DATA_LO_15_0,Current value of rx_rd[15:0] PMA output for the current lane." line.long 0x4 "PHY_PMA_PSM_STATE_HI__PHY_PMA_PSM_STATE_LO_j,PMA PSM current state lower register Offset = F020h + (j * 200h); where j = 0h to 3h" bitfld.long 0x4 29.--31. "PHY_PMA_PSM_STATE_HI_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "PHY_PMA_PSM_STATE_HI_12,Current value of xcvr_psm_ready for the associated lane." "0,1" newline bitfld.long 0x4 26.--27. "PHY_PMA_PSM_STATE_HI_11_10,Reserved" "0,1,2,3" newline hexmask.long.word 0x4 16.--25. 1. "PHY_PMA_PSM_STATE_HI_9_0,Current value of xcvr_psm_state[25:16] for the associated lane - PMA power state machine state." newline hexmask.long.word 0x4 0.--15. 1. "PHY_PMA_PSM_STATE_LO_15_0,Current value of xcvr_psm_state[15:0] for the associated lane - PMA power state machine state." tree.end tree "TIMER" base ad:0x0 tree "TIMER0_CFG" base ad:0x2400000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER1_CFG" base ad:0x2410000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER2_CFG" base ad:0x2420000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER3_CFG" base ad:0x2430000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER4_CFG" base ad:0x2440000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER5_CFG" base ad:0x2450000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER6_CFG" base ad:0x2460000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER7_CFG" base ad:0x2470000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER8_CFG" base ad:0x2480000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER9_CFG" base ad:0x2490000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER10_CFG" base ad:0x24A0000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER11_CFG" base ad:0x24B0000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER12_CFG" base ad:0x24C0000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER13_CFG" base ad:0x24D0000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER14_CFG" base ad:0x24E0000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER15_CFG" base ad:0x24F0000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER16_CFG" base ad:0x2500000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER17_CFG" base ad:0x2510000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER18_CFG" base ad:0x2520000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER19_CFG" base ad:0x2530000 rgroup.long 0x0++0x3 line.long 0x0 "TIMER_TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features. bugs. and compatibility." hexmask.long 0x0 0.--31. 1. "REVISION,IP Revision" group.long 0x10++0x3 line.long 0x0 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface. Some of the timers features described in this section may not be supported on this family of devices. For more information. see . Timers Not Supported.." hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2.--3. "IDLEMODE,Power management req/ack control 0h = Force-idle mode: local target idle state follows (acknowledges) the system clock stop requests unconditionally that is regardless of the IP module internal requirements. Back-up mode for debug only. 1h =.." "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation mode 0h = The timer is frozen in emulation mode (PINSUSPENDN signal active). 1h = The timer runs free regardless of PINSUSPENDN value." "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset Read 0h = Reset done no pending action" "0,1" group.long 0x20++0x27 line.long 0x0 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line (depending on module integration). The.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (that is number 0)." "0,1" line.long 0x4 "TIMER_IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status. mostly for debug." hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x8 "TIMER_IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared. that is..." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0xC "TIMER_IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding *_CLR register." hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0xC 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0xC 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding *_SET register." hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match 0h = Wake-up disabled 1h = Wake-up enabled." "0,1" line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality." hexmask.long.tbyte 0x18 15.--31. 1. "RESERVED,Reserved" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin. 0h = TIMER IO pin functions as PWM output. 1h = TIMER IO pin functions as TRIGGER input." "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) 0h = Single capture: Capture the first enabled capture event in 1h = Capture on second event: Capture the second enabled capture event in" "0,1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin 0h = Pulse modulation 1h = Toggle modulation." "0,1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin 0h = No trigger 1h = Trigger on overflow. 2h = Trigger on overflow and match 3h = Reserved." "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) 0h = No capture 1h = Capture on rising edges of EVENT_CAPTURE pin 2h =.." "0,1,2,3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting 0h = Clear the POTIMERPWM output pin and select positive pulse for pulse mode. 1h = Set the POTIMERPWM output pin and select negative pulse for pulse mode." "0,1" bitfld.long 0x18 6. "CE,Compare enable 0h = Compare mode is disable. 1h = Compare mode is enable." "0,1" newline bitfld.long 0x18 5. "PRE,Prescaler enable 0h = The timer clock input pin clocks the counter. 1h = The divided input pin clocks the counter." "0,1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Autoreload mode 0h = One shot timer 1h = Autoreload timer" "0,1" bitfld.long 0x18 0. "ST,Start/stop timer control 0h = Stop timer: Only the counter is frozen. If one-shot mode selected (AR = 0) this bit is automatically reset by internal logic when the counter is overflowed. 1h = Start timer." "0,1" line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter." hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Value of timer counter" line.long 0x20 "TIMER_TLDR,This register holds the timer load value." hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer counter value loaded on overflow in autoreload mode or on" line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it. The read value of this register is always FFFF FFFFh." hexmask.long 0x24 0.--31. 1. "TTGR_VALUE,Writing to the" rgroup.long 0x48++0x3 line.long 0x0 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for the Read 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for the Read 0h = No negative increment register write pending Read 1h = Negative increment register write pending." "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for the Read 0h = No positive increment register write pending Read 1h = Positive increment register write pending." "0,1" bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" newline bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for theRead 0h = No write pending Read 1h = Write pending." "0,1" group.long 0x4C++0x3 line.long 0x0 "TIMER_TMAR,The register holds the match value to be compared with the counter's value." hexmask.long 0x0 0.--31. 1. "COMPARE_VALUE,Value to be compared to the timer counter" rgroup.long 0x50++0x3 line.long 0x0 "TIMER_TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,First timer counter value captured on an external event trigger" group.long 0x54++0x3 line.long 0x0 "TIMER_TSICR,Timer synchronous interface control register" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values: 0h = The synchronization mechanism is enabled.1h = The synchronization mechanism is disabled." "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used. 0h = When the module is configured in non-posted mode (POSTED = '0') the read operation is executed as.." "0,1" bitfld.long 0x0 2. "POSTED,Posted mode selection. 0h = Posted mode inactive: Delay the command accept output signal. 1h = Posted mode active." "0,1" newline bitfld.long 0x0 1. "SFT,This bit resets the 0h = Reset is inactive. 1h = Reset is asserted." "0,1" rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "TIMER_TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,Second timer counter value captured on an external event trigger" group.long 0x5C++0x13 line.long 0x0 "TIMER_TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,Value of the positive increment" line.long 0x4 "TIMER_TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod.." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INV_VALUE,Value of the negative increment" line.long 0x8 "TIMER_TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,Value of CVR counter" line.long 0xC "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.byte 0xC 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x10 "TIMER_TOWR,This register holds the number of masked overflow interrupts." hexmask.long.byte 0x10 24.--31. 1. "RESERVED,Reads return 0." hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree.end tree "TIMESYNC_INTRTR0_INTR_ROUTER_CFG" base ad:0xA40000 rgroup.long 0x0++0x3 line.long 0x0 "TIMESYNC_INTRTR0_PID,Peripheral identification register. Uniquely identifies the module and its specific revision." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "TIMESYNC_INTRTR0_MUXCNTL_y,Event mux control register. Offset = 4h + (y * 4h); where y = 0h to 2Fh." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "INT_ENABLE,Enable for event output N" "0,1" hexmask.long.word 0x0 6.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "ENABLE,Mux control for event output N" tree.end tree "UART" base ad:0x0 tree "UART0" base ad:0x2800000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART1" base ad:0x2810000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART2" base ad:0x2820000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART3" base ad:0x2830000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART4" base ad:0x2840000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART5" base ad:0x2850000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART6" base ad:0x2860000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART7" base ad:0x2870000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART8" base ad:0x2880000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART9" base ad:0x2890000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree.end tree "USB" base ad:0x0 tree "USB0_ECC_AGGR" base ad:0x2A13000 rgroup.long 0x0++0x3 line.long 0x0 "USB_REV,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "USB_VECTOR,ECC Vector Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "USB_STAT,Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "USB_RESERVED_SVBUS_y,Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "USB_SEC_EOI_REG,EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "USB_SEC_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "USB_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "USB_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "USB_DED_EOI_REG,EOI Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "USB_DED_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "USB_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "USB_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "USB_AGGR_ENABLE_SET,AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "USB_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "USB_AGGR_STATUS_SET,AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "USB_AGGR_STATUS_CLR,AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "USB0_MMR_MMRVBP_USBSS_CMN" base ad:0x4104000 rgroup.long 0x0++0x3 line.long 0x0 "USB3P0SS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,Register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0xF line.long 0x0 "USB3P0SS_W1,Wrapper register containing soft reset. mode selection. and overcurrent indicator." hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 19. "USB2_ONLY_MODE,Selects USB2 only mode." "0,1" bitfld.long 0x0 17.--18. "MODESTRAP,Modestrap input to the Controller." "0,1,2,3" bitfld.long 0x0 16. "OVERCURRENT_N,Overcurrent indicator to the controller. Software writes 0 when overcurrent was detected by external circuitry." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "MODESTRAP_SEL,This bit has to be always set to 1." "0,1" bitfld.long 0x0 8. "OVERCURRENT_SEL,Overcurrent select." "0,1" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "PWRUP_RST_N,Power up reset for the controller." "0,1" line.long 0x4 "USB3P0SS_STATIC_CONFIG,Wrapper register containing static settings. All bits in this register have to be written before setting PWRUP_RST_N bit in register." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 5.--8. 1. "PLL_REF_SEL,Indicates the frequency of the REF_CLOCK input used by the USB PLL." bitfld.long 0x4 3.--4. "RESERVED,Reserved. Always keep at 0x0" "0,1,2,3" bitfld.long 0x4 1.--2. "VBUS_SEL,VBUS select. Always set to 0x1" "0,1,2,3" newline bitfld.long 0x4 0. "LANE_REVERSE,USB2PHY D+/D- reverse selection." "0,1" line.long 0x8 "USB3P0SS_PHY_TEST,Register containing PLL bypass select. BIST control and status" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved bits" bitfld.long 0x8 17. "BIST_MODE,Set for bist mode." "0,1" hexmask.long.byte 0x8 9.--16. 1. "BIST_ERROR_COUNT,Number of bytes that have errors while running BIST." rbitfld.long 0x8 8. "BIST_ERROR,If set this bit indicates that BIST completed with error." "0,1" newline rbitfld.long 0x8 7. "BIST_COMPLETE,If set this bit indicates that the BIST operation is completed." "0,1" bitfld.long 0x8 6. "BIST_ON,Setting this bit starts the BIST operation." "0,1" bitfld.long 0x8 5. "BIST_MODE_EN,BIST Mode Enable." "0,1" hexmask.long.byte 0x8 1.--4. 1. "BIST_MODE_SEL,BIST Mode Selection." newline bitfld.long 0x8 0. "RESERVED,Reserved. Keep at 0x0" "0,1" line.long 0xC "USB3P0SS_DEBUG_CTRL,USB Controller debug selection register" hexmask.long 0xC 5.--31. 1. "RESERVED,Reserved bits" hexmask.long.byte 0xC 0.--4. 1. "DEBUG_SEL,Debug selection to be shown in DEBUG_INFO" rgroup.long 0x14++0x7 line.long 0x0 "USB3P0SS_DEBUG_INFO,USB Controller debug information register" hexmask.long 0x0 0.--31. 1. "DEBUG_INFO,Debug information selected by DEBUG_SEL" line.long 0x4 "USB3P0SS_DEBUG_LINK_STATE,USB Controller debug link state information" bitfld.long 0x4 31. "RESERVED,Reserved bits" "0,1" hexmask.long 0x4 0.--30. 1. "DEBUG_LINK_STATE,Debug link state information" group.long 0x1C++0x3 line.long 0x0 "USB3P0SS_DEVICE_CTRL,Register for device control" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved bits" bitfld.long 0x0 0. "DEV_WAKEUP,Set this bit to trigger device wakeup interrupt on IRQ[7]" "0,1" tree.end tree "USB0_RAMS_INJ_CFG" base ad:0x2A10000 rgroup.long 0x0++0x7 line.long 0x0 "USB_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,Register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "USB_INFO,The Info Register gives the configuration Inforrmation of this module." hexmask.long 0x4 6.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--5. 1. "ENDPOINTS,Total number of Targets supported by this configuration" wgroup.long 0x8++0x3 line.long 0x0 "USB_SFT_RST,The Global Soft Reset Register clears all programmable registers and returns the injector to idle state" hexmask.long 0x0 4.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--3. 1. "KEY,Write 4'b1010 to issue a soft reset." group.long 0x10++0xF line.long 0x0 "USB_BIT1,This register defines the first bit to be flipped when injection is enabled" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "BIT1,First bit to be flipped on an error injection" line.long 0x4 "USB_BIT2,This register defines the second bit to be flipped if 2-bit injection is enabled" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "BIT2,Second bit to be flipped on an error injection if 2-bit injection is chosen." line.long 0x8 "USB_TRGT,This is the target selection register" hexmask.long 0x8 5.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--4. 1. "TRGT,Select which target to interact with." line.long 0xC "USB_CTRL,Controls the injection" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--12. 1. "TRGT,Indicates which target is selected by the" hexmask.long.byte 0xC 3.--7. 1. "RESERVED" rbitfld.long 0xC 2. "DONE,Indicates that the target selected by" "0,1" bitfld.long 0xC 1. "TWOBIT,Write 1 to trigger a 2-bit error in target selected by" "0,1" bitfld.long 0xC 0. "ONEBIT,Write 1 to trigger a 1-bit error in target selected by" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "USB_STATUS,Controls the injection" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 2. "ARMED,Indicates that the target selected by" "0,1" bitfld.long 0x0 0.--1. "RESERVED" "0,1,2,3" tree.end tree.end tree "WKUP" base ad:0x0 tree "WKUP_CBASS0_ERR" base ad:0x4240000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "WKUP_CBASS0_GLB" base ad:0x45B02000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging." hexmask.long 0x0 2.--31. 1. "RESERVED" bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal." hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "WKUP_CBASS_FW0_ERR" base ad:0x4244000 rgroup.long 0x0++0x3 line.long 0x0 "CBASS_PID,The Revision Register contains the major and minor revisions for the module." hexmask.long 0x0 0.--31. 1. "REV,TI internal data." group.long 0x4++0x3 line.long 0x0 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." hexmask.long.word 0x4 0.--15. 1. "RESERVED" line.long 0x8 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.byte 0x10 28.--31. 1. "RESERVED" hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 14.--15. "RESERVED" "0,1,2,3" bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" newline bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED" hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register" hexmask.long 0x8 1.--31. 1. "RESERVED" bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register" hexmask.long 0xC 1.--31. 1. "RESERVED" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "CBASS_EOI,End of Interrupt Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register" tree.end tree "WKUP_CTRL_MMR0_CFG0" base ad:0x43000000 rgroup.long 0x2000++0x3 line.long 0x0 "CTRLMMR_WKUP_PID" bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business unit - Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module functional identifier - CTRL MMR" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL revision number - actual value determined by RTL" newline bitfld.long 0x0 8.--10. "X_MAJOR,Major revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number - actual value determined by RTL" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision number - actual value determined by RTL" rgroup.long 0x2008++0x3 line.long 0x0 "CTRLMMR_WKUP_MMR_CFG1" bitfld.long 0x0 31. "PROXY_EN,Proxy addressing enabled" "0,1" hexmask.long.tbyte 0x0 8.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "PARTITIONS,Indicates present partitions" rgroup.long 0x2014++0x3 line.long 0x0 "CTRLMMR_WKUP_JTAGID" hexmask.long.byte 0x0 28.--31. 1. "VARIANT,Used to indicate new PGs" hexmask.long.word 0x0 12.--27. 1. "PARTNO,Part number for boundary scan" newline hexmask.long.word 0x0 1.--11. 1. "MFG,Indicates manufacturer" bitfld.long 0x0 0. "LSB,Always 1" "0,1" rgroup.long 0x2020++0xF line.long 0x0 "CTRLMMR_WKUP_DIE_ID0" hexmask.long 0x0 0.--31. 1. "DIEID,Contains individual die information" line.long 0x4 "CTRLMMR_WKUP_DIE_ID1" hexmask.long 0x4 0.--31. 1. "DIEID,Contains individual die information" line.long 0x8 "CTRLMMR_WKUP_DIE_ID2" hexmask.long 0x8 0.--31. 1. "DIEID,Contains individual die information" line.long 0xC "CTRLMMR_WKUP_DIE_ID3" hexmask.long 0xC 0.--31. 1. "DIEID,Contains individual die information" group.long 0x2030++0x3 line.long 0x0 "CTRLMMR_WKUP_DEVSTAT" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "MAIN_BOOTMODE,Specifies the device Primary and Backup boot media." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "MCU_BOOTMODE,Indicates MCU boot mode." rgroup.long 0x2034++0xB line.long 0x0 "CTRLMMR_WKUP_BOOTCFG" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--23. 1. "MAIN_BOOTMODE,Specifies the device Primary and Backup boot media as latched at PORz" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "MCU_BOOTMODE,Indicates MCU boot mode as latched at power-on reset. These bits always contain the values latched.Bits 9:8 - Power-on Self Test mode (if" line.long 0x4 "CTRLMMR_WKUP_POST_SEL_STAT" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0.--1. "POST_SEL_STAT,Indicates which POST option was selected at power-up" "0,1,2,3" line.long 0x8 "CTRLMMR_WKUP_POST_OPT" hexmask.long.word 0x8 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 19. "OPT3_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1" newline bitfld.long 0x8 18. "OPT3_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1" bitfld.long 0x8 17. "OPT3_DMSC_LBIST_EN,DMSC LBIST enabled" "0,1" newline bitfld.long 0x8 16. "OPT3_PARALLEL_EN,Selects DMSC/MCU R5 LBIST sequencing" "0,1" hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x8 11. "OPT2_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1" bitfld.long 0x8 10. "OPT2_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1" newline bitfld.long 0x8 9. "OPT2_DMSC_LBIST_EN,DMSC LBIST enabled" "0,1" bitfld.long 0x8 8. "OPT2_PARALLEL_EN,Selects DMSC/MCU R5 LBIST sequencing" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "OPT1_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1" newline bitfld.long 0x8 2. "OPT1_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1" bitfld.long 0x8 1. "OPT1_DMSC_LBIST_EN,DMSC LBIST enabled" "0,1" newline bitfld.long 0x8 0. "OPT1_PARALLEL_EN,Selects DMSC/MCU R5 LBIST sequencing" "0,1" group.long 0x2050++0x3 line.long 0x0 "CTRLMMR_WKUP_RESET_SRC_STAT" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "THERMAL_RST,When set indicates that a VTM Max Temp Thermal reset occurred." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. "DBUGSS_RST,When set indicates that a Debug reset occurred." "0,1" newline bitfld.long 0x0 19. "COLD_OUT_RST,When set indicates that a DMSC Cold reset occurred." "0,1" rbitfld.long 0x0 17.--18. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 16. "WARM_OUT_RST,When set indicates that a DSMC Warm reset occurred." "0,1" hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 11. "PORZ_PIN,When set indicates that a PORz pin reset occurred." "0,1" rbitfld.long 0x0 10. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 9. "RESET_REQZ_PIN,When set indicates that a RESET_REQz pin reset occurred." "0,1" bitfld.long 0x0 8. "MCU_RSTZ_PIN,When set indicates that a MCU_RESETz pin reset occurred." "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "SW_MAIN_POR,When set indicates that a Software MAIN Power-on reset occurred." "0,1" newline rbitfld.long 0x0 2. "RESERVED,Reserved" "0,1" bitfld.long 0x0 1. "SW_MAIN_WARMRST,When set indicates that a Software MAIN Warm reset occurred." "0,1" newline bitfld.long 0x0 0. "SW_MCU_WARMRST,When set indicates that a Software MCU Warm reset occurred." "0,1" rgroup.long 0x2060++0xF line.long 0x0 "CTRLMMR_WKUP_DEVICE_FEATURE0" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "MPU_CLUSTER0_CORE1,MPU Cluster0 Core 1 is enabled when set" "0,1" newline bitfld.long 0x0 0. "MPU_CLUSTER0_CORE0,MPU Cluster0 Core 0 is enabled when set" "0,1" line.long 0x4 "CTRLMMR_WKUP_DEVICE_FEATURE1" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 1. "MCU_CLUSTER0_CORE1,MAIN MCU Cluster0 Core1 is enabled when set" "0,1" newline bitfld.long 0x4 0. "MCU_CLUSTER0_CORE0,MAIN MCU Cluster0 Core0 is enabled when set" "0,1" line.long 0x8 "CTRLMMR_WKUP_DEVICE_FEATURE2" hexmask.long.tbyte 0x8 11.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 10. "CRYPTO_PKA_EN,MCU SA2_UL Crypto Module PKA enabled" "0,1" newline bitfld.long 0x8 9. "CRYPTO_ENCR_EN,MCU SA2_UL Crypto Module AES/3DES/DBRG enabled" "0,1" bitfld.long 0x8 8. "CRYPTO_SHA_EN,MCU SA2_UL Crypto Module SHA/MD5 enabled" "0,1" newline bitfld.long 0x8 7. "AES_AUTH_EN,AES authentication is enabled in MCU_FlashSS and DMSC when set" "0,1" bitfld.long 0x8 6. "HYPERBUS,MCU_Hyperbus is enabled when set" "0,1" newline bitfld.long 0x8 5. "RESERVED,Reserved" "0,1" bitfld.long 0x8 4. "OSPI0,MCU_OSPI0 is enabled when set" "0,1" newline bitfld.long 0x8 3. "MCU_MCAN1,MCU_MCAN1 is enabled when set" "0,1" bitfld.long 0x8 2. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 1. "MCU_MCAN0,MCU_MCAN0 is enabled when set" "0,1" bitfld.long 0x8 0. "MCU_MCAN_FD_MODE,FD mode is supported on MCU_MCAN[1:0] when set" "0,1" line.long 0xC "CTRLMMR_WKUP_DEVICE_FEATURE3" bitfld.long 0xC 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0xC 28. "EMIF0,EMIF0 is enabled when set" "0,1" newline hexmask.long.byte 0xC 22.--27. 1. "RESERVED,Reserved" bitfld.long 0xC 21. "MMC_4B0,4-bit MMC/SD1 is enabled when set" "0,1" newline bitfld.long 0xC 20. "MMC_8B,8-bit MMC/SD0 is enabled when set" "0,1" hexmask.long.word 0xC 9.--19. 1. "RESERVED,Reserved" newline bitfld.long 0xC 8. "SERDES0,10G SERDES0 is enabled when set" "0,1" bitfld.long 0xC 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 5. "PCIE1,PCIe1 is enabled when set" "0,1" hexmask.long.byte 0xC 1.--4. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0. "USB0,USB0 is enabled when set" "0,1" rgroup.long 0x2074++0x7 line.long 0x0 "CTRLMMR_WKUP_DEVICE_FEATURE5" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "MCAN17,MCAN17 is enabled when set" "0,1" newline bitfld.long 0x0 16. "MCAN16,MCAN16 is enabled when set" "0,1" bitfld.long 0x0 15. "MCAN15,MCAN15 is enabled when set" "0,1" newline bitfld.long 0x0 14. "MCAN14,MCAN14 is enabled when set" "0,1" bitfld.long 0x0 13. "MCAN13,MCAN13 is enabled when set" "0,1" newline bitfld.long 0x0 12. "MCAN12,MCAN12 is enabled when set" "0,1" bitfld.long 0x0 11. "MCAN11,MCAN11 is enabled when set" "0,1" newline bitfld.long 0x0 10. "MCAN10,MCAN10 is enabled when set" "0,1" bitfld.long 0x0 9. "MCAN9,MCAN9 is enabled when set" "0,1" newline bitfld.long 0x0 8. "MCAN8,MCAN8 is enabled when set" "0,1" bitfld.long 0x0 7. "MCAN7,MCAN7 is enabled when set" "0,1" newline bitfld.long 0x0 6. "MCAN6,MCAN6 is enabled when set" "0,1" bitfld.long 0x0 5. "MCAN5,MCAN5 is enabled when set" "0,1" newline bitfld.long 0x0 4. "MCAN4,MCAN4 is enabled when set" "0,1" bitfld.long 0x0 3. "MCAN3,MCAN3 is enabled when set" "0,1" newline bitfld.long 0x0 2. "MCAN2,MCAN2 is enabled when set" "0,1" bitfld.long 0x0 1. "MCAN1,MCAN1 is enabled when set" "0,1" newline bitfld.long 0x0 0. "MCAN0,MCAN0 is enabled when set" "0,1" line.long 0x4 "CTRLMMR_WKUP_DEVICE_FEATURE6" hexmask.long.word 0x4 23.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 22. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 21. "RESERVED,Reserved" "0,1" bitfld.long 0x4 20. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x4 10.--19. 1. "RESERVED,Reserved" bitfld.long 0x4 9. "I3C,MAIN domain I3C is enabled when set" "0,1" newline bitfld.long 0x4 8. "MOTOR_PER,Motor control peripherals (eCAP eQEP eHRPWM) are enabled when set" "0,1" bitfld.long 0x4 7. "ATL,Audio tracking logic is enabled when set" "0,1" newline bitfld.long 0x4 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 4. "CPSW5G,4 Channel Q/SGMII Ethernet switch enabled when set" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED,Reserved" rgroup.long 0x2200++0xB line.long 0x0 "CTRLMMR_WKUP_DBG_CBA_ERR_STAT" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 1. "MAIN_DBG_ERR,Main Debug bus segment error" "0,1" newline bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" line.long 0x4 "CTRLMMR_WKUP_FW_CBA_ERR_STAT" hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 2. "MAIN_FW_ERR,MAIN Firewall bus segment error" "0,1" newline bitfld.long 0x4 1. "MCU_FW_ERR,MCU Firewall bus segment error" "0,1" bitfld.long 0x4 0. "WKUP_FW_ERR,WKUP Firewall bus segment error" "0,1" line.long 0x8 "CTRLMMR_WKUP_NONFW_CBA_ERR_STAT" hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 5. "MAIN_INFRA_NONSAFE_CBA_ERR,MAIN Infrastructure non-safe bus segment error" "0,1" newline bitfld.long 0x8 4. "DBG_CBA_ERR,Debug bus aggregated error. See" "0,1" bitfld.long 0x8 3. "WKUP_CBA_ERR,WKUP Data bus segment error" "0,1" newline bitfld.long 0x8 2. "MCU_CBA_ERR,MCU Data bus segment error" "0,1" bitfld.long 0x8 1. "MAIN_INFRA_CBA_ERR,MAIN Infrastructure safe bus segment error" "0,1" newline bitfld.long 0x8 0. "MAIN_CBA_ERR,MAIN Data bus aggregated error. See" "0,1" rgroup.long 0x2210++0x3 line.long 0x0 "CTRLMMR_WKUP_MAIN_CBA_ERR_STAT" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "PULSAR0_SLV_CBA_ERR,MAIN R5 Slave Data bus segment error" "0,1" newline bitfld.long 0x0 16. "PULSAR0_MEM_CBA_ERR,MAIN R5 Memory Data bus segment error" "0,1" bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 13. "IPPHY_SAFE_CBA_ERR,MAIN Phy safe Data bus segment error" "0,1" bitfld.long 0x0 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 11. "MCASP_G0_CBA_ERR,MAIN McASP Group0 Data bus segment error" "0,1" bitfld.long 0x0 10. "IPPHY_CBA_ERR,MAIN Phy non-safe Data bus segment error" "0,1" newline bitfld.long 0x0 8.--9. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 7. "DEBUG_CBA_ERR,MAIN Debug Data bus segment error" "0,1" newline bitfld.long 0x0 6. "HC2_CBA_ERR,MAIN HC2 Data bus segment error" "0,1" bitfld.long 0x0 5. "HC_CFG_CBA_ERR,MAIN HC CFG Data bus segment error" "0,1" newline bitfld.long 0x0 4. "RESERVED,Reserved" "0,1" bitfld.long 0x0 3. "RC_CFG_CBA_ERR,MAIN RC CFG Data bus segment error" "0,1" newline bitfld.long 0x0 2. "RC_CBA_ERR,MAIN RC Data bus segment error" "0,1" bitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" group.long 0x3008++0x1B line.long 0x0 "CTRLMMR_WKUP_LOCK0_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status." "0,1" line.long 0x4 "CTRLMMR_WKUP_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" line.long 0x8 "CTRLMMR_WKUP_INTR_RAW_STAT" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 3. "PROXY_ERR,Proxy violation occurred (attempt to write a Proxy1 claimed register through its Proxy0 address)" "0,1" newline bitfld.long 0x8 2. "LOCK_ERR,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1" bitfld.long 0x8 1. "ADDR_ERR,Address violation occurred (attempt to read or write an invalid register address)" "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)" "0,1" line.long 0xC "CTRLMMR_WKUP_INTR_STAT_CLR" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved" bitfld.long 0xC 3. "EN_PROXY_ERR,Enabled proxy interrupt event status" "0,1" newline bitfld.long 0xC 2. "EN_LOCK_ERR,Enabled lock interrupt event status" "0,1" bitfld.long 0xC 1. "EN_ADDR_ERR,Enabled address interrupt event status" "0,1" newline bitfld.long 0xC 0. "EN_PROT_ERR,Enabled protection interrupt event status" "0,1" line.long 0x10 "CTRLMMR_WKUP_INTR_EN_SET" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 3. "PROXY_ERR_EN_SET,Proxy interrupt enable" "0,1" newline bitfld.long 0x10 2. "LOCK_ERR_EN_SET,Lock interrupt enable" "0,1" bitfld.long 0x10 1. "ADDR_ERR_EN_SET,Address interrupt enable" "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN_SET,Protection interrupt enable" "0,1" line.long 0x14 "CTRLMMR_WKUP_INTR_EN_CLR" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy interrupt disable" "0,1" newline bitfld.long 0x14 2. "LOCK_ERR_EN_CLR,Lock interrupt disable" "0,1" bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Address interrupt disable" "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection interrupt disable" "0,1" line.long 0x18 "CTRLMMR_WKUP_EOI" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x18 0.--7. 1. "VECTOR" rgroup.long 0x3024++0xB line.long 0x0 "CTRLMMR_WKUP_FAULT_ADDR" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address of the faulted access" line.long 0x4 "CTRLMMR_WKUP_FAULT_TYPE" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--5. 1. "TYPE,Type of access which faulted 0h - No fault 1h - User execute access 2h - User write access 4h - User read access 8h - Supervisor execute access 10h - Supervisor write access 20h - Supervisor read access" line.long 0x8 "CTRLMMR_WKUP_FAULT_ATTR" hexmask.long.word 0x8 20.--31. 1. "XID,Transaction ID" hexmask.long.word 0x8 8.--19. 1. "ROUTEID,Route ID" newline hexmask.long.byte 0x8 0.--7. 1. "PRIVID,Privilege ID" group.long 0x3030++0x3 line.long 0x0 "CTRLMMR_WKUP_FAULT_CLR" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "CLEAR,Fault clear" "0,1" group.long 0x3100++0x17 line.long 0x0 "CTRLMMR_WKUP_P0_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_WKUP_P0_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_WKUP_P0_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_WKUP_P0_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_WKUP_P0_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_WKUP_P0_CLAIM5" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x6004++0x7 line.long 0x0 "CTRLMMR_WKUP_MAIN_PWR_CTRL" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "WAKE_EN,When set drives the PMIC_WAKE0 output (low)." "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "PWR_EN,When set drives the PMIC_PWR_EN1 output to turn on the MAIN voltage domain" "0,1" line.long 0x4 "CTRLMMR_WKUP_MCU_PWR_CTRL" hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "WAKE_EN,When set drives the PMIC_WAKE1 output (low)." "0,1" newline hexmask.long.word 0x4 0.--15. 1. "RESERVED,Reserved" group.long 0x6020++0x3 line.long 0x0 "CTRLMMR_WKUP_GPIO_CTRL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "WAKEN,Enables WKUP_GPIO wakeup event operation by controlling the WKUP_GPIO LPSC clockstop_ack behavior. 0h - No WKUP_GPIO wakeup support. WKUP_GPIO vbus clock is gated on clkstop_ack from WKUP_GPIO to LPSC 1h - WKUP_GPIO wakeup enabled. WKUP_GPIO vbus.." "0,1" group.long 0x6030++0x3 line.long 0x0 "CTRLMMR_WKUP_I2C0_CTRL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "HS_MCS_EN,HS Mode master current source enable." "0,1" group.long 0x6084++0x17 line.long 0x0 "CTRLMMR_WKUP_DBOUNCE_CFG1" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--5. 1. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL1 enabled." line.long 0x4 "CTRLMMR_WKUP_DBOUNCE_CFG2" hexmask.long 0x4 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--5. 1. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL2 enabled." line.long 0x8 "CTRLMMR_WKUP_DBOUNCE_CFG3" hexmask.long 0x8 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--5. 1. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL3 enabled." line.long 0xC "CTRLMMR_WKUP_DBOUNCE_CFG4" hexmask.long 0xC 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--5. 1. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL4 enabled." line.long 0x10 "CTRLMMR_WKUP_DBOUNCE_CFG5" hexmask.long 0x10 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x10 0.--5. 1. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL5 enabled." line.long 0x14 "CTRLMMR_WKUP_DBOUNCE_CFG6" hexmask.long 0x14 6.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x14 0.--5. 1. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL6 enabled." group.long 0x7008++0x7 line.long 0x0 "CTRLMMR_WKUP_LOCK1_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status." "0,1" line.long 0x4 "CTRLMMR_WKUP_LOCK1_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers" group.long 0x7100++0x7 line.long 0x0 "CTRLMMR_WKUP_P1_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_WKUP_P1_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0xA000++0x3 line.long 0x0 "CTRLMMR_WKUP_MCU_OBSCLK_CTRL" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "OUT_MUX_SEL,MCU_OBSCLK pin output mux selection." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "CLK_DIV_LD,Load the output divider value" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 8.--11. 1. "CLK_DIV,MCU_OBSCLK pin clock selection output divider" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--3. 1. "CLK_SEL,MCU_OBSCLK pin clock selection 0h - CLK_12M_RC 1h - '0' 2h - MCU_PLL0_HSDIV0_CLKOUT 3h - MCU_PLLCTL_OBSCLK 4h - MCU_PLL1_HSDIV1_CLKOUT 5h - MCU_PLL1_HSDIV2_CLKOUT 6h - MCU_PLL1_HSDIV3_CLKOUT 7h - MCU_PLL1_HSDIV4_CLKOUT 8h - MCU_PLL2_HSDIV0_CLKOUT.." group.long 0xA014++0xB line.long 0x0 "CTRLMMR_WKUP_HFOSC1_CTRL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 7. "PD_C,Oscillator powerdown control. When set oscillator is disabled. Oscillator output is tristated if bp_c=0" "0,1" newline rbitfld.long 0x0 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 4. "BP_C,Oscillator bypass control. When set oscillator is in bypass mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_WKUP_HFOSC0_TRIM" bitfld.long 0x4 31. "TRIM_EN,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1" hexmask.long.byte 0x4 26.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24.--25. "FREQ_RNG,Sets the frequency range of operation based on: 0h - I(AMP) - 3x I(MIRRBIAS) 1h - I(AMP) 2h - I(AMP) 3h - I(AMP) + 3x I(MIRRBIAS)" "0,1,2,3" rbitfld.long 0x4 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 20.--21. "HYST,Sets comparator hysteresis" "0,1,2,3" rbitfld.long 0x4 19. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 16.--18. "I_MULT,AGC AMP current multiplication gain 0h - 3x I(MIRRBIAS) 1h - 4x I(MIRRBIAS) 2h - 5x I(MIRRBIAS) 3h - 6x I(MIRRBIAS) 4h - 7x I(MIRRBIAS) 5h - 8x I(MIRRBIAS) 6h - 9x I(MIRRBIAS) 7h - 10x I(MIRRBIAS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "R_REF,Sets the AMP AGC bias current 0h - 0.00 K-Ohm 1h - 3.1548 K-Ohm 2h - 6.3048 K-Ohm 3h - 9.4548 K-Ohm 4h - 12.6048 K-Ohm 5h - 15.7548 K-Ohm 6h - 18.9048 K-Ohm 7h - 22.0548 K-Ohm" hexmask.long.byte 0x4 4.--7. 1. "I_IBIAS_COMP,Sets the COMP bias current 0h - 40x 1h - 48x 2h - 56x 3h - 64x 4h - 72x 5h - 80x 6h - 88x 7h - 96x 8h - 104x 9h - 112x Ah - 120x Bh - 128x Ch - 136x Dh - 144x Eh - 152x Fh - 160x" newline hexmask.long.byte 0x4 0.--3. 1. "R_IBIAS_REF,Sets the base IBIAS reference 0h - 64 K-Ohm 1h - 72 K-Ohm 2h - 80 K-Ohm 3h - 88 K-Ohm 4h - 96 K-Ohm 5h - 104 K-Ohm 6h - 112 K-Ohm 7h - 120 K-Ohm 8h - 128 K-Ohm 9h - 136 K-Ohm Ah - 144 K-Ohm Bh - 152 K-Ohm Ch - 160 K-Ohm Dh - 168 K-Ohm Eh -.." line.long 0x8 "CTRLMMR_WKUP_HFOSC1_TRIM" bitfld.long 0x8 31. "TRIM_EN,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1" hexmask.long.byte 0x8 26.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "FREQ_RNG,Sets the frequency range of operation based on: 0h - I(AMP) - 3x I(MIRRBIAS) 1h - I(AMP) 2h - I(AMP) 3h - I(AMP) + 3x I(MIRRBIAS)" "0,1,2,3" rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x8 20.--21. "HYST,Sets comparator hysteresis" "0,1,2,3" rbitfld.long 0x8 19. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 16.--18. "I_MULT,AGC AMP current multiplication gain 0h - 3x I(MIRRBIAS) 1h - 4x I(MIRRBIAS) 2h - 5x I(MIRRBIAS) 3h - 6x I(MIRRBIAS) 4h - 7x I(MIRRBIAS) 5h - 8x I(MIRRBIAS) 6h - 9x I(MIRRBIAS) 7h - 10x I(MIRRBIAS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x8 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 8.--13. 1. "R_REF,Sets the AMP AGC bias current 0h - 0.00 K-Ohm 1h - 3.1548 K-Ohm 2h - 6.3048 K-Ohm 3h - 9.4548 K-Ohm 4h - 12.6048 K-Ohm 5h - 15.7548 K-Ohm 6h - 18.9048 K-Ohm 7h - 22.0548 K-Ohm" hexmask.long.byte 0x8 4.--7. 1. "I_IBIAS_COMP,Sets the COMP bias current 0h - 40x 1h - 48x 2h - 56x 3h - 64x 4h - 72x 5h - 80x 6h - 88x 7h - 96x 8h - 104x 9h - 112x Ah - 120x Bh - 128x Ch - 136x Dh - 144x Eh - 152x Fh - 160x" newline hexmask.long.byte 0x8 0.--3. 1. "R_IBIAS_REF,Sets the base IBIAS reference 0h - 64 K-Ohm 1h - 72 K-Ohm 2h - 80 K-Ohm 3h - 88 K-Ohm 4h - 96 K-Ohm 5h - 104 K-Ohm 6h - 112 K-Ohm 7h - 120 K-Ohm 8h - 128 K-Ohm 9h - 136 K-Ohm Ah - 144 K-Ohm Bh - 152 K-Ohm Ch - 160 K-Ohm Dh - 168 K-Ohm Eh -.." group.long 0xA024++0x3 line.long 0x0 "CTRLMMR_WKUP_RC12M_OSC_TRIM" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 6. "TRIMOSC_COARSE_DIR,Coarse adjustment direction. If output is greater than 12.5" "0,1" newline bitfld.long 0x0 3.--5. "TRIMOSC_COARSE,Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TRIMOSC_FINE,Fine adjustment. Decreases the frequency by 250 KHz per value." "0,1,2,3,4,5,6,7" group.long 0xA050++0x3 line.long 0x0 "CTRLMMR_WKUP_MCU_PLL_CLKSEL" bitfld.long 0x0 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x0 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.word 0x0 9.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "CLKLOSS_SWTCH_EN,When set enables automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1" hexmask.long.byte 0x0 0.--7. 1. "RESERVED,Reserved" group.long 0xA060++0x7 line.long 0x0 "CTRLMMR_WKUP_PER_CLKSEL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "MCUPLL_BYPASS,Select the main oscillator clock rather than the PLL generated clock as the functional clock (PLL BYPASS mode)." "0,1" line.long 0x4 "CTRLMMR_WKUP_USART_CLKSEL" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "CLK_SEL,WKUP_USART0 FCLK selection" "0,1" group.long 0xA070++0x3 line.long 0x0 "CTRLMMR_WKUP_GPIO_CLKSEL" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--1. "WAKE_CLK_SEL,WKUP_GPIO clock selection. Must be set to MCU_SYSCLK0/6 whenever WKUP_GPIO VBUS interface is enabled. Other clock source may be selected as a wake up clock for DeepSleep modes after WKUP_GPIO is gated off through LPSC. 0h - MCU_SYSCLK0 / 6.." "0,1,2,3" group.long 0xA080++0x13 line.long 0x0 "CTRLMMR_WKUP_MAIN_PLL0_CLKSEL" bitfld.long 0x0 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x0 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0x0 1.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "CLK_SEL,Selects the clock source for MAIN PLL0" "0,1" line.long 0x4 "CTRLMMR_WKUP_MAIN_PLL1_CLKSEL" bitfld.long 0x4 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x4 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0x4 1.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "CLK_SEL,Selects the clock source for MAIN PLL1" "0,1" line.long 0x8 "CTRLMMR_WKUP_MAIN_PLL2_CLKSEL" bitfld.long 0x8 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x8 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x8 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0x8 1.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x8 0. "CLK_SEL,Selects the clock source for MAIN PLL2" "0,1" line.long 0xC "CTRLMMR_WKUP_MAIN_PLL3_CLKSEL" bitfld.long 0xC 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0xC 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xC 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0xC 1.--22. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0. "CLK_SEL,Selects the clock source for MAIN PLL3" "0,1" line.long 0x10 "CTRLMMR_WKUP_MAIN_PLL4_CLKSEL" bitfld.long 0x10 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x10 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x10 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0x10 5.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x10 4. "XREF_SEL,Selects the alternate clock source for MAIN PLL4" "0,1" rbitfld.long 0x10 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0. "CLK_SEL,Selects the clock source for MAIN PLL4" "0,1" group.long 0xA09C++0x7 line.long 0x0 "CTRLMMR_WKUP_MAIN_PLL7_CLKSEL" bitfld.long 0x0 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x0 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0x0 1.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "CLK_SEL,Selects the clock source for MAIN PLL7" "0,1" line.long 0x4 "CTRLMMR_WKUP_MAIN_PLL8_CLKSEL" bitfld.long 0x4 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x4 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0x4 1.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "CLK_SEL,Selects the clock source for MAIN PLL8" "0,1" group.long 0xA0B0++0x3 line.long 0x0 "CTRLMMR_WKUP_MAIN_PLL12_CLKSEL" bitfld.long 0x0 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x0 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0x0 1.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "CLK_SEL,Selects the clock source for MAIN PLL12" "0,1" group.long 0xA0B8++0x3 line.long 0x0 "CTRLMMR_WKUP_MAIN_PLL14_CLKSEL" bitfld.long 0x0 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1" hexmask.long.byte 0x0 24.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x0 23. "BYP_WARM_RST,PLL bypass mode after warm reset." "0,1" hexmask.long.tbyte 0x0 1.--22. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "CLK_SEL,Selects the clock source for MAIN PLL14" "0,1" group.long 0xA100++0x3 line.long 0x0 "CTRLMMR_WKUP_MAIN_SYSCLK_CTRL" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "SYSCLK1_GATE,When set gates off SYSCLK1 output of the MAIN PLL Controller" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "SYSCLK0_GATE,When set gates off SYSCLK0 (MCLK1) output of the MAIN PLL Controller" "0,1" group.long 0xA110++0x7 line.long 0x0 "CTRLMMR_WKUP_MCU_SPI0_CLKSEL" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_WKUP_MCU_SPI1_CLKSEL" hexmask.long.word 0x4 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1" newline hexmask.long.word 0x4 0.--15. 1. "RESERVED,Reserved" group.long 0xB008++0x7 line.long 0x0 "CTRLMMR_WKUP_LOCK2_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status." "0,1" line.long 0x4 "CTRLMMR_WKUP_LOCK2_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers" group.long 0xB100++0xB line.long 0x0 "CTRLMMR_WKUP_P2_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_WKUP_P2_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_WKUP_P2_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" rgroup.long 0xE280++0x3 line.long 0x0 "CTRLMMR_WKUP_DMSC_LBIST_SIG" hexmask.long 0x0 0.--31. 1. "MISR_SIG,MISR signature" rgroup.long 0xE2C0++0x3 line.long 0x0 "CTRLMMR_WKUP_POST_STAT" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 17. "FPOST_PLL_LOCK_TIMEOUT,Indicates PLL lock timeout for Fast POST mode operation." "0,1" newline bitfld.long 0x0 16. "FPOST_PLL_LOCKLOSS,Indicates if PLL lock was lost during POST" "0,1" bitfld.long 0x0 15. "POST_MCU_PBIST_FAIL,MCU PBIST failed" "0,1" newline hexmask.long.byte 0x0 10.--14. 1. "RESERVED,Reserved" bitfld.long 0x0 9. "POST_MCU_PBIST_TIMEOUT,MCU PBIST timed out" "0,1" newline bitfld.long 0x0 8. "POST_MCU_PBIST_DONE,MCU PBIST done" "0,1" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 5. "POST_MCU_LBIST_TIMEOUT,MCU LBIST timed out" "0,1" bitfld.long 0x0 4. "POST_DMSC_LBIST_TIMEOUT,DMSC LBIST timed out" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "POST_MCU_LBIST_DONE,MCU LBIST done" "0,1" newline bitfld.long 0x0 0. "POST_DMSC_LBIST_DONE,DMSC LBIST done" "0,1" rgroup.long 0xE320++0x3 line.long 0x0 "CTRLMMR_WKUP_FUSE_CRC_STAT" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "CRC_ERR_2,Indicates eFuse CRC error on chain 2" "0,1" newline bitfld.long 0x0 1. "CRC_ERR_1,Indicates eFuse CRC error on chain 1" "0,1" bitfld.long 0x0 0. "RESERVED,Reserved" "0,1" group.long 0xF008++0x7 line.long 0x0 "CTRLMMR_WKUP_LOCK3_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status." "0,1" line.long 0x4 "CTRLMMR_WKUP_LOCK3_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers" group.long 0xF104++0x17 line.long 0x0 "CTRLMMR_WKUP_P3_CLAIM1" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_WKUP_P3_CLAIM2" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_WKUP_P3_CLAIM3" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_WKUP_P3_CLAIM4" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_WKUP_P3_CLAIM5" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_WKUP_P3_CLAIM6" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x13008++0x7 line.long 0x0 "CTRLMMR_WKUP_LOCK4_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status." "0,1" line.long 0x4 "CTRLMMR_WKUP_LOCK4_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition4 registers" group.long 0x13108++0x7 line.long 0x0 "CTRLMMR_WKUP_P4_CLAIM2" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_WKUP_P4_CLAIM3" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x13114++0x3 line.long 0x0 "CTRLMMR_WKUP_P4_CLAIM5" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x1311C++0x3 line.long 0x0 "CTRLMMR_WKUP_P4_CLAIM7" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x1A000++0x3 line.long 0x0 "CTRLMMR_WKUP_POR_CTRL" rbitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 29. "OVRD_SET5,Reserved override set" "0,1" newline bitfld.long 0x0 28. "OVRD_SET4,POKLVB override set" "0,1" bitfld.long 0x0 27. "OVRD_SET3,POKLVA override set" "0,1" newline bitfld.long 0x0 26. "OVRD_SET2,POKHV override set" "0,1" bitfld.long 0x0 25. "OVRD_SET1,BGOK override set" "0,1" newline bitfld.long 0x0 24. "OVRD_SET0,PORHV override set" "0,1" rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 21. "OVRD5,Reserved override enable" "0,1" bitfld.long 0x0 20. "OVRD4,POKLVB override enable" "0,1" newline bitfld.long 0x0 19. "OVRD3,POKLVA override enable" "0,1" bitfld.long 0x0 18. "OVRD2,POKHV override enable" "0,1" newline bitfld.long 0x0 17. "OVRD1,BGOK override enable" "0,1" bitfld.long 0x0 16. "OVRD0,PORHV override enable" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 7. "TRIM_SEL,POR Trim Select" "0,1" newline rbitfld.long 0x0 5.--6. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 4. "MASK_HHV,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED,Reserved" rgroup.long 0x1A004++0x3 line.long 0x0 "CTRLMMR_WKUP_POR_STAT" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "BGOK,Bandgap OK status" "0,1" newline bitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "SOC_POR,POR module status" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED,Reserved" group.long 0x1A010++0x1F line.long 0x0 "CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL" bitfld.long 0x0 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long 0x0 1.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" line.long 0x4 "CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL" bitfld.long 0x4 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x4 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x4 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x4 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x8 "CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL" bitfld.long 0x8 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x8 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x8 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x8 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0xC "CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_UV_CTRL" bitfld.long 0xC 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0xC 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xC 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0xC 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x10 "CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL" bitfld.long 0x10 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x10 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x10 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x10 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x14 "CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL" bitfld.long 0x14 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x14 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x14 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x14 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x18 "CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL" bitfld.long 0x18 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x18 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x18 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x18 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x1C "CTRLMMR_WKUP_POK_VMON_CAP_MCU_GEN_OV_CTRL" bitfld.long 0x1C 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x1C 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." group.long 0x1A070++0x3 line.long 0x0 "CTRLMMR_WKUP_MAIN_VDOM_CTRL" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "MAIN_VD_OFF,MAIN deep sleep isolation enable. This bit should be set prior to powering off the MAIN voltage domain to ensure proper signal isolation." "0,1" group.long 0x1A080++0xF line.long 0x0 "CTRLMMR_WKUP_POR_POKHV_UV_CTRL" bitfld.long 0x0 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x0 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x0 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x4 "CTRLMMR_WKUP_POR_POKLVB_UV_CTRL" bitfld.long 0x4 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x4 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x4 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x4 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x8 "CTRLMMR_WKUP_POR_POKLVA_OV_CTRL" bitfld.long 0x8 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x8 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x8 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x8 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0xC "CTRLMMR_WKUP_POR_BANDGAP_CTRL" hexmask.long.word 0xC 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 16.--19. 1. "BGAPI,Bandgap output current trim bits" newline hexmask.long.byte 0xC 8.--15. 1. "BGAPV,Bandgap output voltage magnitude trim bits" hexmask.long.byte 0xC 0.--7. 1. "BGAPC,Bandgap slope trim bits. Bit7 is used to calculate the offset" group.long 0x1A0A0++0x3 line.long 0x0 "CTRLMMR_WKUP_TEMP_DIODE_TRIM" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--13. 1. "TRIM,Sets the diode non-ideality factor (n) starting from 100th place decimal and going down" rgroup.long 0x1A0B0++0x3 line.long 0x0 "CTRLMMR_WKUP_IO_VOLTAGE_STAT" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "MAIN_CANUART,Indicates the voltage for the CANUART I/O group" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 10. "MAIN_MMC1,Indicates the voltage for the MMC1 I/O group" "0,1" newline bitfld.long 0x0 9. "MAIN_MMC0,Indicates the voltage for the MMC0 I/O group" "0,1" bitfld.long 0x0 8. "MAIN_GEN,Indicates the voltage for the General I/O group" "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 2. "MCU_RGMII,Indicates the voltage for the MCU CPSW2G RGMII I/O group" "0,1" newline bitfld.long 0x0 1. "MCU_FLASH,Indicates the voltage for the MCU Flash I/O group" "0,1" bitfld.long 0x0 0. "MCU_GEN,Indicates the voltage for the MCU General I/O group" "0,1" group.long 0x1A104++0x3 line.long 0x0 "CTRLMMR_WKUP_MAIN_POR_TO_CTRL" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 0.--2. "TIMEOUT_PER,MAIN PORz hardware timeout period. 0h - Immediate 1h - 100 microsec 2h - 200 microsec 3h - 300 microsec 4h - 400 microsec 5h - 500 microsec" "0,1,2,3,4,5,6,7" group.long 0x1A110++0x2F line.long 0x0 "CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL" bitfld.long 0x0 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x0 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x0 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x4 "CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL" bitfld.long 0x4 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x4 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x4 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x4 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x8 "CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL" bitfld.long 0x8 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x8 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x8 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x8 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0xC "CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL" bitfld.long 0xC 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0xC 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xC 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0xC 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x10 "CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL" bitfld.long 0x10 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x10 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x10 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x10 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x14 "CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL" bitfld.long 0x14 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x14 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x14 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x14 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x18 "CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL" bitfld.long 0x18 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x18 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x18 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x18 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x1C "CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL" bitfld.long 0x1C 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x1C 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x20 "CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_UV_CTRL" bitfld.long 0x20 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x20 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x20 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x20 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x24 "CTRLMMR_WKUP_POK_VMON_EXT_MAIN1P8_OV_CTRL" bitfld.long 0x24 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x24 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x24 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x24 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x28 "CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_UV_CTRL" bitfld.long 0x28 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x28 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x28 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x28 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." line.long 0x2C "CTRLMMR_WKUP_POK_VMON_EXT_MAIN3P3_OV_CTRL" bitfld.long 0x2C 31. "HYST_EN,Enable POK hysteresis" "0,1" hexmask.long.tbyte 0x2C 8.--30. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1" hexmask.long.byte 0x2C 0.--6. 1. "POK_TRIM,POK trim bits. These bits are used to trim the comparator threshold voltage." group.long 0x1A160++0x3 line.long 0x0 "CTRLMMR_WKUP_DEEPSLEEP_CTRL" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "FORCE_DS_MAIN,Force all MAIN IOs into deepsleep mode when set" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "FORCE_DS_WKUP,Force all WKUP IOs into deepsleep mode when set" "0,1" group.long 0x1A170++0x7 line.long 0x0 "CTRLMMR_WKUP_POR_RST_CTRL" hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 24. "MAIN_PORZ_DAISYCHAIN_EN,MAIN PORz daisy-chain event enable." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "SW_MAIN_POR,Main Domain software power-on reset. When set to 6h a power-on is issued to the MAIN voltage domain. (Bits will reset to Fh on reset of the Main Domain)" newline rbitfld.long 0x0 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "MAIN_PORZ_DS_STRETCH,DeepSleep mode MAIN PORz stretch." "0,1" newline hexmask.long.word 0x0 1.--11. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "POR_RST_ISO_DONE_Z,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete." "0,1" line.long 0x4 "CTRLMMR_WKUP_MAIN_WARM_RST_CTRL" hexmask.long.word 0x4 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 16.--19. 1. "SW_WARMRST,Main Domain software warm reset. When set to 6h a warm reset is issued to the MAIN voltage domain. (Bits will reset to Fh on reset of the Main Domain)" newline hexmask.long.word 0x4 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "SOC_WARMRST_ISO_DONE_Z,Reset isolation completion (active low). This bit should be cleared only after reset isolation of the MAIN domain is complete." "0,1" rgroup.long 0x1A178++0x3 line.long 0x0 "CTRLMMR_WKUP_RST_STAT" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "MCU_RST_DONE,Indicates MCU domain reset status." "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "MAIN_RST_DONE,Indicates MAIN domain Warm reset status." "0,1" group.long 0x1A17C++0x7 line.long 0x0 "CTRLMMR_WKUP_MCU_WARM_RST_CTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 16.--19. 1. "SW_WARMRST,Chip software warm reset. When set to 6h a warm reset is issued to the device (all voltage domains). (Bits will reset to Fh on reset completion.)" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" line.long 0x4 "CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL" bitfld.long 0x4 31. "PWDB,Power down - active low." "0,1" bitfld.long 0x4 30. "RSTB,Reset - active low. To ensure proper operation rstb must not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings to.." "0,1" newline hexmask.long.word 0x4 19.--29. 1. "RESERVED,Reserved" bitfld.long 0x4 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth 0h - 150 kHz 1h - 125 kHz 2h - 100 kHz 3h - 80 kHz 4h - 60 kHz 5h - 45 kHz 6h - 30 kHz 7h - 15 kHz" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage 0h - 93.5% of VDD 1h - 94.0% of VDD 2h - 94.5% of VDD 3h - 95.0% of VDD 4h - 95.5% of VDD 5h - 96.0% of VDD 6h - 96.5% of VDD 7h - 97.0% of VDD 8h - 97.5% of.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage 0h - 106.5% of VDD 1h - 106.0% of VDD 2h - 105.5% of VDD 3h - 105.0% of VDD 4h - 104.5% of VDD 5h - 104.0% of VDD 6h - 103.5% of VDD 7h - 103.0% of VDD 8h -.." group.long 0x1A190++0xB line.long 0x0 "CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL" bitfld.long 0x0 31. "PWDB,Power down - active low." "0,1" bitfld.long 0x0 30. "RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings.." "0,1" newline hexmask.long.word 0x0 19.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth 0h - 150 kHz 1h - 125 kHz 2h - 100 kHz 3h - 80 kHz 4h - 60 kHz 5h - 45 kHz 6h - 30 kHz 7h - 15 kHz" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage 0h - 93.5% of VDD 1h - 94.0% of VDD 2h - 94.5% of VDD 3h - 95.0% of VDD 4h - 95.5% of VDD 5h - 96.0% of VDD 6h - 96.5% of VDD 7h - 97.0% of VDD 8h - 97.5% of.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage 0h - 106.5% of VDD 1h - 106.0% of VDD 2h - 105.5% of VDD 3h - 105.0% of VDD 4h - 104.5% of VDD 5h - 104.0% of VDD 6h - 103.5% of VDD 7h - 103.0% of VDD 8h -.." line.long 0x4 "CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL" bitfld.long 0x4 31. "PWDB,Power down - active low." "0,1" bitfld.long 0x4 30. "RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings.." "0,1" newline hexmask.long.word 0x4 19.--29. 1. "RESERVED,Reserved" bitfld.long 0x4 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth 0h - 150 kHz 1h - 125 kHz 2h - 100 kHz 3h - 80 kHz 4h - 60 kHz 5h - 45 kHz 6h - 30 kHz 7h - 15 kHz" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage 0h - 93.5% of VDD 1h - 94.0% of VDD 2h - 94.5% of VDD 3h - 95.0% of VDD 4h - 95.5% of VDD 5h - 96.0% of VDD 6h - 96.5% of VDD 7h - 97.0% of VDD 8h - 97.5% of.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage 0h - 106.5% of VDD 1h - 106.0% of VDD 2h - 105.5% of VDD 3h - 105.0% of VDD 4h - 104.5% of VDD 5h - 104.0% of VDD 6h - 103.5% of VDD 7h - 103.0% of VDD 8h -.." line.long 0x8 "CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL" bitfld.long 0x8 31. "PWDB,Power down - active low." "0,1" bitfld.long 0x8 30. "RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings.." "0,1" newline hexmask.long.word 0x8 19.--29. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth 0h - 150 kHz 1h - 125 kHz 2h - 100 kHz 3h - 80 kHz 4h - 60 kHz 5h - 45 kHz 6h - 30 kHz 7h - 15 kHz" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 8.--13. 1. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage 0h - 93.5% of VDD 1h - 94.0% of VDD 2h - 94.5% of VDD 3h - 95.0% of VDD 4h - 95.5% of VDD 5h - 96.0% of VDD 6h - 96.5% of VDD 7h - 97.0% of VDD 8h - 97.5% of.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x8 0.--5. 1. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage 0h - 106.5% of VDD 1h - 106.0% of VDD 2h - 105.5% of VDD 3h - 105.0% of VDD 4h - 104.5% of VDD 5h - 104.0% of VDD 6h - 103.5% of VDD 7h - 103.0% of VDD 8h -.." rgroup.long 0x1A1A0++0x3 line.long 0x0 "CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_CPU_GLDTC_CTRL_rstb bit." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_CPU_GLDTC_CTRL_rstb bit." "0,1" rgroup.long 0x1A1B0++0xB line.long 0x0 "CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit." "0,1" line.long 0x4 "CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDDR_CPU_GLDTC_CTRL_rstb bit." "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDDR_CPU_GLDTC_CTRL_rstb bit." "0,1" line.long 0x8 "CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT" hexmask.long.tbyte 0x8 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 8. "THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDDR_CORE_GLDTC_CTRL_rstb bit." "0,1" newline hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x8 0. "THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDDR_CORE_GLDTC_CTRL_rstb bit." "0,1" group.long 0x1A1C0++0x7 line.long 0x0 "CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL" bitfld.long 0x0 31. "PWDB,Power down - active low." "0,1" bitfld.long 0x0 30. "RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings.." "0,1" newline hexmask.long.word 0x0 19.--29. 1. "RESERVED,Reserved" bitfld.long 0x0 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth 0h - 150 kHz 1h - 125 kHz 2h - 100 kHz 3h - 80 kHz 4h - 60 kHz 5h - 45 kHz 6h - 30 kHz 7h - 15 kHz" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage 0h - 93.5% of VDD 1h - 94.0% of VDD 2h - 94.5% of VDD 3h - 95.0% of VDD 4h - 95.5% of VDD 5h - 96.0% of VDD 6h - 96.5% of VDD 7h - 97.0% of VDD 8h - 97.5% of.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage 0h - 106.5% of VDD 1h - 106.0% of VDD 2h - 105.5% of VDD 3h - 105.0% of VDD 4h - 104.5% of VDD 5h - 104.0% of VDD 6h - 103.5% of VDD 7h - 103.0% of VDD 8h -.." line.long 0x4 "CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL" bitfld.long 0x4 31. "PWDB,Power down - active low." "0,1" bitfld.long 0x4 30. "RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings.." "0,1" newline hexmask.long.word 0x4 19.--29. 1. "RESERVED,Reserved" bitfld.long 0x4 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth 0h - 150 kHz 1h - 125 kHz 2h - 100 kHz 3h - 80 kHz 4h - 60 kHz 5h - 45 kHz 6h - 30 kHz 7h - 15 kHz" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 8.--13. 1. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage 0h - 93.5% of VDD 1h - 94.0% of VDD 2h - 94.5% of VDD 3h - 95.0% of VDD 4h - 95.5% of VDD 5h - 96.0% of VDD 6h - 96.5% of VDD 7h - 97.0% of VDD 8h - 97.5% of.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x4 0.--5. 1. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage 0h - 106.5% of VDD 1h - 106.0% of VDD 2h - 105.5% of VDD 3h - 105.0% of VDD 4h - 104.5% of VDD 5h - 104.0% of VDD 6h - 103.5% of VDD 7h - 103.0% of VDD 8h -.." rgroup.long 0x1A1D0++0x7 line.long 0x0 "CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 8. "THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_MCU_GLDTC_CTRL_rstb bit." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_MCU_GLDTC_CTRL_rstb bit." "0,1" line.long 0x4 "CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT" hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 8. "THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDDR_MCU_GLDTC_CTRL_rstb bit." "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDDR_MCU_GLDTC_CTRL_rstb bit." "0,1" group.long 0x1A200++0x17 line.long 0x0 "CTRLMMR_WKUP_PRG_PP_MCU_CTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 19. "POK_PP_EN,POK ping-pong enable. When set enables automatic switching between undervoltage and overvoltage detection on VDDSHV_WKUP_GENERAL VDDR_MCU and VMON_CAP_MCU_GENERAL POKs. This bit has no effect if the POK's ov_sel bit = 1." "0,1" newline rbitfld.long 0x0 18. "RESERVED,Reserved" "0,1" bitfld.long 0x0 16.--17. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 15. "POK_EN_SEL,Select POK enable source" "0,1" hexmask.long.byte 0x0 11.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "POK_VMON_CAP_MCU_GEN_OV_SEL,Force VMON_CAP_MCU_GENERAL POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" bitfld.long 0x0 9. "POK_VDDR_MCU_OV_SEL,Force VDDR_MCU POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" newline bitfld.long 0x0 8. "POK_VDDSHV_WKUP_GEN_OV_SEL,Force VDDSHV_WKUP_GENERAL POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "POK_VMON_CAP_MCU_GEN_EN,Enable VMON_CAP_MCU_GENERAL POK detection" "0,1" bitfld.long 0x0 1. "POK_VDDR_MCU_EN,Enable VDDR_MCU POK detection" "0,1" newline bitfld.long 0x0 0. "POK_VDDSHV_WKUP_GEN_EN,Enable VDDSHV_WKUP_GENERAL POK detection" "0,1" line.long 0x4 "CTRLMMR_WKUP_PRG_PP_MCU_STAT" bitfld.long 0x4 31. "POK_CLR,When set resets pgood sticky bits for VDDSHV_WKUP_GENERAL VDDR_MCU and VMON_CAP_MCU_GENERAL voltage POK detection." "0,1" hexmask.long.tbyte 0x4 11.--30. 1. "RESERVED,Reserved" newline rbitfld.long 0x4 10. "POK_VMON_CAP_MCU_GEN_OV,VMON_CAP_MCU_GENERAL overvoltage POK" "0,1" rbitfld.long 0x4 9. "POK_VDDR_MCU_OV,VDDR_MCU overvoltage POK" "0,1" newline rbitfld.long 0x4 8. "POK_VDDSHV_WKUP_GEN_OV,VDDSHV_WKUP_GENERAL overvoltage POK" "0,1" hexmask.long.byte 0x4 3.--7. 1. "RESERVED,Reserved" newline rbitfld.long 0x4 2. "POK_VMON_CAP_MCU_GEN_UV,VMON_CAP_MCU_GENERAL undervoltage POK" "0,1" rbitfld.long 0x4 1. "POK_VDDR_MCU_UV,VDDR_MCU undervoltage POK" "0,1" newline rbitfld.long 0x4 0. "POK_VDDSHV_WKUP_GEN_UV,VDDSHV_WKUP_GENERAL undervoltage POK" "0,1" line.long 0x8 "CTRLMMR_WKUP_PRG_PP_POR_CTRL" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reserved" bitfld.long 0x8 16.--17. "DEGLITCH_SEL,Deglitch period for PRG_PP_POR POKs 0h - 5 us 1h - 10 us 2h - 15 us 3h - 20 us" "0,1,2,3" newline bitfld.long 0x8 15. "POK_EN_SEL,Select POK enable source" "0,1" hexmask.long.word 0x8 5.--14. 1. "RESERVED,Reserved" newline bitfld.long 0x8 4. "POK_VDDA_PMIC_IN_UV_EN,Enable VDDA_PMIC_IN undervoltage POK detection" "0,1" bitfld.long 0x8 3. "POK_VDD_MCU_OV_EN,Enable VDD_MCU overvoltage POK detection" "0,1" newline bitfld.long 0x8 2. "POK_VDD_MCU_UV_EN,Enable VDD_MCU undervoltage POK detection" "0,1" bitfld.long 0x8 1. "POK_VDDA_MCU_OV_EN,Enable 1.8V VDDA_MCU overvoltage POK detection" "0,1" newline bitfld.long 0x8 0. "POK_VDDA_MCU_UV_EN,Enable 1.8V VDDA_MCU undervoltage POK detection" "0,1" line.long 0xC "CTRLMMR_WKUP_PRG_PP_POR_STAT" bitfld.long 0xC 31. "POK_CLR,When set resets pgood sticky bits for VDDA_MCU VDD_MCU and VDDA_PMIC_IN voltage POK detection." "0,1" hexmask.long.tbyte 0xC 10.--30. 1. "RESERVED,Reserved" newline rbitfld.long 0xC 9. "POK_VDD_MCU_OV,VDD_MCU overvoltage POK detection" "0,1" rbitfld.long 0xC 8. "POK_VDDA_MCU_OV,1.8V VDDA_MCU overvoltage POK detection" "0,1" newline hexmask.long.byte 0xC 3.--7. 1. "RESERVED,Reserved" rbitfld.long 0xC 2. "POK_VDDA_PMIC_IN_UV,VDDA_PMIC_IN undervoltage POK detection" "0,1" newline rbitfld.long 0xC 1. "POK_VDD_MCU_UV,VDD_MCU undervoltage POK detection" "0,1" rbitfld.long 0xC 0. "POK_VDDA_MCU_UV,1.8V VDDA_MCU undervoltage POK detection" "0,1" line.long 0x10 "CTRLMMR_WKUP_PRG_PP_MAIN_CTRL" hexmask.long.word 0x10 20.--31. 1. "RESERVED,Reserved" bitfld.long 0x10 19. "POK_PP_EN,POK ping-pong enable. When set enables automatic switching between undervoltage and overvoltage detection on VDD_CORE VDD_CPU VDDR_CORE VMON_EXT VMON_EXT_MAIN1P8 and VMON_EXT_MAIN3P3. This bit has no effect if the POK's ov_sel bit = 1." "0,1" newline rbitfld.long 0x10 18. "RESERVED,Reserved" "0,1" bitfld.long 0x10 16.--17. "DEGLITCH_SEL,Deglitch period for PRG_PP_MAIN POKs 0h - 5 us 1h - 10 us 2h - 15 us 3h - 20 us" "0,1,2,3" newline bitfld.long 0x10 15. "POK_EN_SEL,Select POK enable source" "0,1" rbitfld.long 0x10 14. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 13. "POK_VMON_EXT_MAIN3P3_OV_SEL,Force VMON_EXT_MAIN 3.3V POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" bitfld.long 0x10 12. "POK_VMON_EXT_MAIN1P8_OV_SEL,Force VMON_EXT_MAIN 1.8V POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" newline bitfld.long 0x10 11. "POK_VMON_EXT_OV_SEL,Force VMON_EXT POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" bitfld.long 0x10 10. "POK_VDDR_CORE_OV_SEL,Force VDDR_CORE POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" newline bitfld.long 0x10 9. "POK_VDD_CPU_OV_SEL,Force VDD_CPU POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" bitfld.long 0x10 8. "POK_VDD_CORE_OV_SEL,Force VDD_CORE POK overvoltage detection. If this bit is 0 and pok_pp_en bit is also 0 then only undervoltage detection is enabled." "0,1" newline rbitfld.long 0x10 6.--7. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x10 5. "POK_VMON_EXT_MAIN3P3_EN,Enable VMON_EXT_MAIN 3.3V POK detection" "0,1" newline bitfld.long 0x10 4. "POK_VMON_EXT_MAIN1P8_EN,Enable VMON_EXT_MAIN 1.8V POK detection" "0,1" bitfld.long 0x10 3. "POK_VMON_EXT_EN,Enable VMON_EXT POK detection" "0,1" newline bitfld.long 0x10 2. "POK_VDDR_CORE_EN,Enable VDDR_CORE POK detection" "0,1" bitfld.long 0x10 1. "POK_VDD_CPU_EN,Enable VDD_CPU POK detection" "0,1" newline bitfld.long 0x10 0. "POK_VDD_CORE_EN,Enable VDD_CORE POK detection" "0,1" line.long 0x14 "CTRLMMR_WKUP_PRG_PP_MAIN_STAT" bitfld.long 0x14 31. "POK_CLR,When set resets pgood sticky bits for V DD_CORE VDD_CPU VDDR_CORE VMON_EXT VMON_EXT_MAIN1P8 and VMON_EXT_MAIN3P3 voltage POK detection." "0,1" hexmask.long.tbyte 0x14 14.--30. 1. "RESERVED,Reserved" newline rbitfld.long 0x14 13. "POK_VMON_EXT_MAIN3P3_OV,VMON_EXT_MAIN 3.3V overvoltage POK" "0,1" rbitfld.long 0x14 12. "POK_VMON_EXT_MAIN1P8_OV,VMON_EXT_MAIN 1.8V overvoltage POK" "0,1" newline rbitfld.long 0x14 11. "POK_VMON_EXT_OV,VMON_EXT overvoltage POK" "0,1" rbitfld.long 0x14 10. "POK_VDDR_CORE_OV,VDDR_CORE overvoltage POK" "0,1" newline rbitfld.long 0x14 9. "POK_VDD_CPU_OV,VDD_CPU overvoltage POK" "0,1" rbitfld.long 0x14 8. "POK_VDD_CORE_OV,VDD_CORE overvoltage POK" "0,1" newline rbitfld.long 0x14 6.--7. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x14 5. "POK_VMON_EXT_MAIN3P3_UV,VMON_EXT_MAIN 3.3V undervoltage POK" "0,1" newline rbitfld.long 0x14 4. "POK_VMON_EXT_MAIN1P8_UV,VMON_EXT_MAIN 1.8V undervoltage POK" "0,1" rbitfld.long 0x14 3. "POK_VMON_EXT_UV,VMON_EXT undervoltage POK" "0,1" newline rbitfld.long 0x14 2. "POK_VDDR_CORE_UV,VDDR_CORE undervoltage POK" "0,1" rbitfld.long 0x14 1. "POK_VDD_CPU_UV,VDD_CPU undervoltage POK" "0,1" newline rbitfld.long 0x14 0. "POK_VDD_CORE_UV,VDD_CORE undervoltage POK" "0,1" group.long 0x1A280++0xF line.long 0x0 "CTRLMMR_WKUP_CLKGATE_CTRL" hexmask.long 0x0 3.--31. 1. "WKUP_NOGATE_RSVD,WKUP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." bitfld.long 0x0 2. "WKUP_ECC_AGG_NOGATE,WKUP ECC Aggregator clock gate disable" "0,1" newline bitfld.long 0x0 1. "WKUP_FW_CBA_NOGATE,WKUP domain Firewall bus (wkup_fw_cbass) clock gate disable" "0,1" bitfld.long 0x0 0. "WKUP_CBA_NOGATE,WKUP domain Data bus (wkup_cbass) clock gate disable" "0,1" line.long 0x4 "CTRLMMR_WKUP_MCU_CLKGATE_CTRL" hexmask.long.word 0x4 21.--31. 1. "MCU_PER_NOGATE_RSVD,MCU reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." bitfld.long 0x4 20. "MCU_PDMA_G2_NOGATE,MCU domain MCAN1/USART0 PDMA clock gate disable." "0,1" newline bitfld.long 0x4 19. "MCU_PDMA_G0_NOGATE,MCU domain MCAN0/SPI0 PDMA clock gate disable." "0,1" bitfld.long 0x4 18. "MCU_PULSAR_NOGATE,MCU domain Pulsar clock gate disable." "0,1" newline bitfld.long 0x4 17. "MCU_NAV_UDMASS_NOGATE,MCU NavSS UDMA interface clock gate disable." "0,1" bitfld.long 0x4 16. "MCU_NAV_MODSS_NOGATE,MCU NavSS MODSS interface clock gate disable." "0,1" newline hexmask.long.word 0x4 4.--15. 1. "MCU_CBA_NOGATE_RSVD,MCU reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." bitfld.long 0x4 3. "MCU_DBG_CBA_NOGATE,MCU domain Debug bus (mcu_dbg_cbass) clock gate disable." "0,1" newline bitfld.long 0x4 2. "MCU_ECC_AGG_NOGATE,MCU ECC Aggregator clock gate disable" "0,1" bitfld.long 0x4 1. "MCU_FW_CBA_NOGATE,MCU domain Firewall bus (mcu_fw_cbass) clock gate disable." "0,1" newline bitfld.long 0x4 0. "MCU_CBA_NOGATE,MCU domain Data bus (mcu_cbass) clock gate disable." "0,1" line.long 0x8 "CTRLMMR_WKUP_MAIN_CLKGATE_CTRL0" hexmask.long.byte 0x8 24.--31. 1. "MAIN_CBA_NOGATE_RSVD,MAIN CBA reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." bitfld.long 0x8 23. "MAIN_HC_CFG_CBA_NOGATE,MAIN domain HC Configuration bus (hc_cfg_cbass_0) clock gate disable." "0,1" newline bitfld.long 0x8 22. "MAIN_HC_ECC_AGG_NOGATE,MAIN domain HC ECC aggregator (nogate) clock gate disable." "0,1" bitfld.long 0x8 21. "MAIN_HC_FW_CBA_NOGATE,MAIN domain HC Firewall bus (main_hc2_fw_cbass_0) clock gate disable." "0,1" newline bitfld.long 0x8 20. "MAIN_HC_CBA_NOGATE,MAIN domain HC Data bus (hc2_cbass_0) clock gate disable." "0,1" bitfld.long 0x8 19. "MAIN_DBG_DATA_CBA_NOGATE,MAIN domain Debug Data bus (debug_cbass) clock gate disable." "0,1" newline bitfld.long 0x8 18. "MAIN_DBG_CBA_NOGATE,MAIN domain Debug bus (debug_cbass_wrap_main_0) clock gate disable." "0,1" bitfld.long 0x8 17. "MAIN_IP_NOGATE_RSVD,MAIN Interface Peripheral reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." "0,1" newline bitfld.long 0x8 16. "MAIN_IP_MCASP_CBA_NOGATE,MAIN domain Interface Peripheral McASP IP bus (ipphy_mcasp_g0) clock gate disable." "0,1" bitfld.long 0x8 15. "MAIN_IP_NONSAFE_CBA_NOGATE,MAIN domain Interface Peripheral nonsafety IP bus (ipphy_cbass_0) clock gate disable." "0,1" newline bitfld.long 0x8 14. "MAIN_IP_ECC_AGGR_NOGATE,MAIN domain Interface Peripheral ECC aggregator (main_spi0_g0_main_0_ecc_aggr_main_0) clock gate disable." "0,1" bitfld.long 0x8 13. "MAIN_IP_FW_CBA_NOGATE,MAIN domain Interface Peripheral Firewall bus (ipphy_cbass_main_fw_cbass) clock gate disable." "0,1" newline bitfld.long 0x8 12. "MAIN_IP_CBA_NOGATE,MAIN domain Interface Peripheral bus (ipphy_safe_cbass_0) clock gate disable." "0,1" bitfld.long 0x8 11. "MAIN_RC_CFG_CBA_NOGATE,MAIN domain RC Configuration bus (rc_cfg_cbass_0) clock gate disable." "0,1" newline bitfld.long 0x8 10. "MAIN_RC_ECC_AGG_NOGATE,MAIN domain RC ECC aggregator (main_rc_ecc_aggr_main_0) clock gate disable." "0,1" bitfld.long 0x8 9. "MAIN_RC_FW_CBA_NOGATE,MAIN domain RC Firewall bus (rc_cbass_main_fw_cbass) clock gate disable." "0,1" newline bitfld.long 0x8 8. "MAIN_RC_CBA_NOGATE,MAIN domain RC Data bus (rc_cbass_0) clock gate disable." "0,1" bitfld.long 0x8 6.--7. "MAIN_INFRA_NOGATE_RSVD,MAIN Infrastructure reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." "0,1,2,3" newline bitfld.long 0x8 5. "MAIN_PULSAR0_MEM_NOGATE,MAIN domain Pulsar memory bus (pulsar0_mem_cbass) clock gate disable." "0,1" bitfld.long 0x8 4. "MAIN_PULSAR0_SLV_NOGATE,MAIN domain Pulsar slave bus (pulsar0_slv_cbass) clock gate disable." "0,1" newline bitfld.long 0x8 3. "MAIN_INFRA_NONSAFE_CBA_NOGATE,MAIN domain Infrastructure non-safety IP bus (main_infra_non_safe_cbass) clock gate disable." "0,1" bitfld.long 0x8 2. "MAIN_INFRA_ECC_AGG_NOGATE,MAIN domain Infrastructure ECC aggregator (main_infra_ecc_aggr) clock gate disable." "0,1" newline bitfld.long 0x8 1. "MAIN_INFRA_FW_CBA_NOGATE,MAIN domain Infrastructure Firewall bus (main_infra_fw_cbass) clock gate disable." "0,1" bitfld.long 0x8 0. "MAIN_INFRA_CBA_NOGATE,MAIN domain Infrastructure bus (main_infra_cbass) clock gate disable." "0,1" line.long 0xC "CTRLMMR_WKUP_MAIN_CLKGATE_CTRL1" bitfld.long 0xC 31. "MAIN_GMPC_STOG_P2M_NOGATE,MAIN domain GPMC Slave Timeout Gasket output (rc_to_gpmc_stog_p2m_pwr_dis) clock gate disable." "0,1" bitfld.long 0xC 30. "MAIN_STOG_NOGATE_RSVD,MAIN STOG clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." "0,1" newline bitfld.long 0xC 29. "MAIN_IP_STOG_M2P_NOGATE,MAIN domain IP Slave Timeout Gasket output (ipphy_to_ipphy_stog_p2m_pwr_dis) clock gate disable." "0,1" bitfld.long 0xC 28. "MAIN_IP_STOG_P2M_NOGATE,MAIN domain IP Slave Timeout Gasket input (ipphy_to_ipphy_stog_p2m_pwr_dis) clock gate disable." "0,1" newline bitfld.long 0xC 27. "MAIN_INFRA_STOG_M2P_NOGATE,MAIN domain Infrastructure Slave Timeout Gasket output (main_infra_0_mst_stog_p2m_pwr_dis) clock gate disable." "0,1" bitfld.long 0xC 26. "MAIN_INFRA_STOG_P2M_NOGATE,MAIN domain Infrastructure Slave Timeout Gasket input (main_infra_0_mst_stog_p2m_pwr_dis) clock gate disable." "0,1" newline hexmask.long.byte 0xC 21.--25. 1. "MAIN_PDMA_NOGATE_RSVD,MAIN PDMA clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." bitfld.long 0xC 20. "MAIN_PDMA_MCAN_NOGATE,MAIN domain PDMA MCAN clock gate disable." "0,1" newline bitfld.long 0xC 19. "MAIN_PDMA_USART_PSILSS_NOGATE,MAIN domain PDMA USART PSILSS clock gate disable." "0,1" bitfld.long 0xC 18. "MAIN_PDMA_SPI_G1_NOGATE,MAIN domain PDMA SPI_G1 clock gate disable." "0,1" newline bitfld.long 0xC 17. "MAIN_PDMA_SPI_G0_NOGATE,MAIN domain PDMA SPI_G0 clock gate disable." "0,1" bitfld.long 0xC 16. "MAIN_PDMA_SPI_PSILSS_NOGATE,MAIN domain PDMA SPI PSILSS clock gate disable." "0,1" newline hexmask.long.byte 0xC 9.--15. 1. "MAIN_IP1_NOGATE_RSVD,MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." bitfld.long 0xC 8. "MAIN_PULSAR_NOGATE,MAIN domain Pulsar clock gate disable." "0,1" newline bitfld.long 0xC 5.--7. "MAIN_IP0_NOGATE_RSVD,MAIN IP reserved clock gate disable. These bits should remain unchanged (written only with their default value) to maintain compatibility with future devices." "0,1,2,3,4,5,6,7" bitfld.long 0xC 4. "MAIN_NAV_MV_FW_NOGATE,MAIN NavSS Mod/Virt Firewall interface clock gate disable." "0,1" newline bitfld.long 0xC 3. "MAIN_NAV_VIRTSS_NOGATE,MAIN NavSS VIRTSS interface clock gate disable." "0,1" bitfld.long 0xC 2. "MAIN_NAV_NBSS_NOGATE,MAIN NavSS NB interface clock gate disable." "0,1" newline bitfld.long 0xC 1. "MAIN_NAV_UDMASS_NOGATE,Main NavSS UDMA interface clock gate disable." "0,1" bitfld.long 0xC 0. "MAIN_NAV_MODSS_NOGATE,MAIN NavSS MODSS interface clock gate disable." "0,1" group.long 0x1A300++0x3 line.long 0x0 "CTRLMMR_WKUP_CANUART_WAKE_CTRL" hexmask.long 0x0 1.--31. 1. "MW,CANUART IO magic word." bitfld.long 0x0 0. "MW_LOAD_EN,Magic word load enable" "0,1" rgroup.long 0x1A308++0x7 line.long 0x0 "CTRLMMR_WKUP_CANUART_WAKE_STAT0" hexmask.long 0x0 1.--31. 1. "MW_STAT,CANUART magic word status" bitfld.long 0x0 0. "MW_LOAD_STAT,Magic word load status." "0,1" line.long 0x4 "CTRLMMR_WKUP_CANUART_WAKE_STAT1" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "CANUART_IO_MODE,Indicates if CANUART IO wakeup mode is enabled." "0,1" group.long 0x1A310++0x3 line.long 0x0 "CTRLMMR_WKUP_MCU_GEN_WAKE_CTRL" hexmask.long 0x0 1.--31. 1. "MW,MCU_GENERAL IO magic word." bitfld.long 0x0 0. "MW_LOAD_EN,Magic word load enable" "0,1" rgroup.long 0x1A318++0x7 line.long 0x0 "CTRLMMR_WKUP_MCU_GEN_WAKE_STAT0" hexmask.long 0x0 1.--31. 1. "MW_STAT,MCU_GENERAL magic word status" bitfld.long 0x0 0. "MW_LOAD_STAT,Magic word load status." "0,1" line.long 0x4 "CTRLMMR_WKUP_MCU_GEN_WAKE_STAT1" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" bitfld.long 0x4 0. "MCU_GEN_IO_MODE,Indicates if MCU_GENERAL IO wakeup mode is enabled." "0,1" group.long 0x1B008++0x7 line.long 0x0 "CTRLMMR_WKUP_LOCK6_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status." "0,1" line.long 0x4 "CTRLMMR_WKUP_LOCK6_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition6 registers" group.long 0x1B100++0x1B line.long 0x0 "CTRLMMR_WKUP_P6_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_WKUP_P6_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_WKUP_P6_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_WKUP_P6_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x10 "CTRLMMR_WKUP_P6_CLAIM4" hexmask.long 0x10 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x14 "CTRLMMR_WKUP_P6_CLAIM5" hexmask.long 0x14 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x18 "CTRLMMR_WKUP_P6_CLAIM6" hexmask.long 0x18 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" group.long 0x1E000++0x33 line.long 0x0 "CTRLMMR_WKUP_PADCONFIG0" bitfld.long 0x0 31. "LOCK,Lock" "0,1" rbitfld.long 0x0 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x0 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x0 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x0 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x0 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x0 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x4 "CTRLMMR_WKUP_PADCONFIG1" bitfld.long 0x4 31. "LOCK,Lock" "0,1" rbitfld.long 0x4 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x4 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x4 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x4 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x4 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x8 "CTRLMMR_WKUP_PADCONFIG2" bitfld.long 0x8 31. "LOCK,Lock" "0,1" rbitfld.long 0x8 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x8 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x8 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x8 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x8 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x8 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x8 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x8 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xC "CTRLMMR_WKUP_PADCONFIG3" bitfld.long 0xC 31. "LOCK,Lock" "0,1" rbitfld.long 0xC 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xC 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xC 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xC 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xC 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xC 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x10 "CTRLMMR_WKUP_PADCONFIG4" bitfld.long 0x10 31. "LOCK,Lock" "0,1" rbitfld.long 0x10 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x10 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x10 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x10 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x10 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x10 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x10 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x10 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x10 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x10 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x10 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x10 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x10 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x10 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x10 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x10 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x10 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x10 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x10 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x10 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x14 "CTRLMMR_WKUP_PADCONFIG5" bitfld.long 0x14 31. "LOCK,Lock" "0,1" rbitfld.long 0x14 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x14 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x14 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x14 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x14 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x14 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x14 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x14 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x14 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x14 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x14 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x14 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x14 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x14 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x14 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x14 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x14 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x14 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x14 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x14 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x18 "CTRLMMR_WKUP_PADCONFIG6" bitfld.long 0x18 31. "LOCK,Lock" "0,1" rbitfld.long 0x18 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x18 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x18 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x18 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x18 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x18 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x18 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x18 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x18 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x18 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x18 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x18 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x18 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x18 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x18 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x18 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x18 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x18 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x18 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x18 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x18 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x1C "CTRLMMR_WKUP_PADCONFIG7" bitfld.long 0x1C 31. "LOCK,Lock" "0,1" rbitfld.long 0x1C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x1C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x1C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x1C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x1C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x1C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x1C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x1C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x1C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x1C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x1C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x1C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x1C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x1C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x1C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x1C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x1C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x1C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x1C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x1C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x20 "CTRLMMR_WKUP_PADCONFIG8" bitfld.long 0x20 31. "LOCK,Lock" "0,1" rbitfld.long 0x20 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x20 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x20 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x20 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x20 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x20 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x20 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x20 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x20 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x20 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x20 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x20 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x20 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x20 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x20 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x20 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x20 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x20 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x20 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x20 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x20 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x24 "CTRLMMR_WKUP_PADCONFIG9" bitfld.long 0x24 31. "LOCK,Lock" "0,1" rbitfld.long 0x24 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x24 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x24 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x24 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x24 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x24 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x24 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x24 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x24 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x24 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x24 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x24 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x24 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x24 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x24 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x24 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x24 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x24 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x24 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x24 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x28 "CTRLMMR_WKUP_PADCONFIG10" bitfld.long 0x28 31. "LOCK,Lock" "0,1" rbitfld.long 0x28 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x28 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x28 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x28 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x28 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x28 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x28 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x28 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x28 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x28 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x28 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x28 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x28 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x28 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x28 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x28 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x28 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x28 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x28 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x28 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x2C "CTRLMMR_WKUP_PADCONFIG11" bitfld.long 0x2C 31. "LOCK,Lock" "0,1" rbitfld.long 0x2C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x2C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x2C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x2C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x2C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x2C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x2C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x2C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x2C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x2C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x2C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x2C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x2C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x2C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x2C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x2C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x2C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x2C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x2C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x2C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x30 "CTRLMMR_WKUP_PADCONFIG12" bitfld.long 0x30 31. "LOCK,Lock" "0,1" rbitfld.long 0x30 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x30 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x30 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x30 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x30 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x30 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x30 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x30 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x30 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x30 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x30 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x30 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x30 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x30 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x30 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x30 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x30 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x30 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x30 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x30 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x30 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" group.long 0x1E038++0x7 line.long 0x0 "CTRLMMR_WKUP_PADCONFIG14" bitfld.long 0x0 31. "LOCK,Lock" "0,1" rbitfld.long 0x0 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x0 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x0 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x0 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x0 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x0 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x4 "CTRLMMR_WKUP_PADCONFIG15" bitfld.long 0x4 31. "LOCK,Lock" "0,1" rbitfld.long 0x4 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x4 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x4 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x4 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x4 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" group.long 0x1E068++0xEB line.long 0x0 "CTRLMMR_WKUP_PADCONFIG26" bitfld.long 0x0 31. "LOCK,Lock" "0,1" rbitfld.long 0x0 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x0 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x0 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x0 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x0 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x0 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x4 "CTRLMMR_WKUP_PADCONFIG27" bitfld.long 0x4 31. "LOCK,Lock" "0,1" rbitfld.long 0x4 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x4 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x4 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x4 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x4 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x8 "CTRLMMR_WKUP_PADCONFIG28" bitfld.long 0x8 31. "LOCK,Lock" "0,1" rbitfld.long 0x8 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x8 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x8 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x8 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x8 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x8 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x8 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x8 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xC "CTRLMMR_WKUP_PADCONFIG29" bitfld.long 0xC 31. "LOCK,Lock" "0,1" rbitfld.long 0xC 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xC 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xC 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xC 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xC 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xC 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x10 "CTRLMMR_WKUP_PADCONFIG30" bitfld.long 0x10 31. "LOCK,Lock" "0,1" rbitfld.long 0x10 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x10 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x10 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x10 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x10 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x10 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x10 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x10 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x10 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x10 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x10 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x10 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x10 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x10 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x10 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x10 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x10 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x10 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x10 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x10 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x14 "CTRLMMR_WKUP_PADCONFIG31" bitfld.long 0x14 31. "LOCK,Lock" "0,1" rbitfld.long 0x14 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x14 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x14 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x14 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x14 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x14 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x14 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x14 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x14 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x14 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x14 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x14 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x14 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x14 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x14 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x14 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x14 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x14 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x14 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x14 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x18 "CTRLMMR_WKUP_PADCONFIG32" bitfld.long 0x18 31. "LOCK,Lock" "0,1" rbitfld.long 0x18 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x18 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x18 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x18 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x18 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x18 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x18 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x18 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x18 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x18 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x18 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x18 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x18 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x18 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x18 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x18 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x18 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x18 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x18 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x18 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x18 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x1C "CTRLMMR_WKUP_PADCONFIG33" bitfld.long 0x1C 31. "LOCK,Lock" "0,1" rbitfld.long 0x1C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x1C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x1C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x1C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x1C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x1C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x1C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x1C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x1C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x1C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x1C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x1C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x1C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x1C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x1C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x1C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x1C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x1C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x1C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x1C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x20 "CTRLMMR_WKUP_PADCONFIG34" bitfld.long 0x20 31. "LOCK,Lock" "0,1" rbitfld.long 0x20 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x20 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x20 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x20 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x20 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x20 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x20 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x20 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x20 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x20 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x20 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x20 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x20 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x20 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x20 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x20 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x20 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x20 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x20 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x20 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x20 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x20 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x24 "CTRLMMR_WKUP_PADCONFIG35" bitfld.long 0x24 31. "LOCK,Lock" "0,1" rbitfld.long 0x24 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x24 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x24 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x24 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x24 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x24 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x24 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x24 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x24 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x24 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x24 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x24 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x24 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x24 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x24 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x24 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x24 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x24 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x24 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x24 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x28 "CTRLMMR_WKUP_PADCONFIG36" bitfld.long 0x28 31. "LOCK,Lock" "0,1" rbitfld.long 0x28 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x28 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x28 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x28 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x28 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x28 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x28 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x28 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x28 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x28 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x28 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x28 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x28 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x28 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x28 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x28 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x28 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x28 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x28 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x28 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x28 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x2C "CTRLMMR_WKUP_PADCONFIG37" bitfld.long 0x2C 31. "LOCK,Lock" "0,1" rbitfld.long 0x2C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x2C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x2C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x2C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x2C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x2C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x2C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x2C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x2C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x2C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x2C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x2C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x2C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x2C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x2C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x2C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x2C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x2C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x2C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x2C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x2C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x30 "CTRLMMR_WKUP_PADCONFIG38" bitfld.long 0x30 31. "LOCK,Lock" "0,1" rbitfld.long 0x30 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x30 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x30 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x30 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x30 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x30 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x30 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x30 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x30 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x30 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x30 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x30 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x30 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x30 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x30 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x30 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x30 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x30 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x30 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x30 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x30 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x34 "CTRLMMR_WKUP_PADCONFIG39" bitfld.long 0x34 31. "LOCK,Lock" "0,1" rbitfld.long 0x34 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x34 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x34 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x34 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x34 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x34 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x34 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x34 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x34 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x34 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x34 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x34 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x34 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x34 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x34 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x34 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x34 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x34 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x34 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x34 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x34 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x34 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x38 "CTRLMMR_WKUP_PADCONFIG40" bitfld.long 0x38 31. "LOCK,Lock" "0,1" rbitfld.long 0x38 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x38 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x38 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x38 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x38 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x38 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x38 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x38 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x38 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x38 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x38 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x38 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x38 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x38 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x38 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x38 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x38 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x38 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x38 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x38 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x38 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x38 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x3C "CTRLMMR_WKUP_PADCONFIG41" bitfld.long 0x3C 31. "LOCK,Lock" "0,1" rbitfld.long 0x3C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x3C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x3C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x3C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x3C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x3C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x3C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x3C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x3C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x3C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x3C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x3C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x3C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x3C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x3C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x3C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x3C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x3C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x3C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x3C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x3C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x3C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x40 "CTRLMMR_WKUP_PADCONFIG42" bitfld.long 0x40 31. "LOCK,Lock" "0,1" rbitfld.long 0x40 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x40 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x40 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x40 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x40 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x40 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x40 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x40 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x40 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x40 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x40 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x40 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x40 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x40 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x40 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x40 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x40 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x40 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x40 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x40 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x40 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x40 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x44 "CTRLMMR_WKUP_PADCONFIG43" bitfld.long 0x44 31. "LOCK,Lock" "0,1" rbitfld.long 0x44 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x44 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x44 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x44 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x44 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x44 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x44 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x44 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x44 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x44 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x44 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x44 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x44 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x44 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x44 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x44 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x44 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x44 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x44 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x44 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x44 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x44 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x48 "CTRLMMR_WKUP_PADCONFIG44" bitfld.long 0x48 31. "LOCK,Lock" "0,1" rbitfld.long 0x48 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x48 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x48 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x48 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x48 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x48 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x48 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x48 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x48 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x48 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x48 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x48 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x48 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x48 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x48 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x48 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x48 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x48 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x48 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x48 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x48 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x48 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x4C "CTRLMMR_WKUP_PADCONFIG45" bitfld.long 0x4C 31. "LOCK,Lock" "0,1" rbitfld.long 0x4C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x4C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x4C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x4C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x4C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x4C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x4C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x4C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x4C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x4C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x4C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x4C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x4C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x4C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x50 "CTRLMMR_WKUP_PADCONFIG46" bitfld.long 0x50 31. "LOCK,Lock" "0,1" rbitfld.long 0x50 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x50 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x50 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x50 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x50 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x50 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x50 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x50 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x50 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x50 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x50 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x50 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x50 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x50 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x50 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x50 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x50 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x50 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x50 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x50 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x50 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x50 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x54 "CTRLMMR_WKUP_PADCONFIG47" bitfld.long 0x54 31. "LOCK,Lock" "0,1" rbitfld.long 0x54 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x54 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x54 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x54 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x54 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x54 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x54 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x54 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x54 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x54 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x54 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x54 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x54 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x54 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x54 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x54 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x54 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x54 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x54 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x54 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x54 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x54 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x58 "CTRLMMR_WKUP_PADCONFIG48" bitfld.long 0x58 31. "LOCK,Lock" "0,1" rbitfld.long 0x58 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x58 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x58 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x58 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x58 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x58 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x58 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x58 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x58 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x58 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x58 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x58 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x58 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x58 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x58 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x58 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x58 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x58 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x58 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x58 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x58 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x58 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x5C "CTRLMMR_WKUP_PADCONFIG49" bitfld.long 0x5C 31. "LOCK,Lock" "0,1" rbitfld.long 0x5C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x5C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x5C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x5C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x5C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x5C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x5C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x5C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x5C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x5C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x5C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x5C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x5C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x5C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x5C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x5C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x5C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x5C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x5C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x5C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x5C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x5C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x60 "CTRLMMR_WKUP_PADCONFIG50" bitfld.long 0x60 31. "LOCK,Lock" "0,1" rbitfld.long 0x60 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x60 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x60 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x60 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x60 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x60 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x60 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x60 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x60 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x60 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x60 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x60 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x60 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x60 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x60 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x60 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x60 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x60 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x60 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x60 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x60 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x60 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x64 "CTRLMMR_WKUP_PADCONFIG51" bitfld.long 0x64 31. "LOCK,Lock" "0,1" rbitfld.long 0x64 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x64 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x64 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x64 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x64 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x64 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x64 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x64 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x64 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x64 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x64 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x64 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x64 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x64 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x64 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x64 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x64 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x64 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x64 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x64 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x64 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x64 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x68 "CTRLMMR_WKUP_PADCONFIG52" bitfld.long 0x68 31. "LOCK,Lock" "0,1" rbitfld.long 0x68 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x68 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x68 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x68 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x68 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x68 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x68 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x68 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x68 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x68 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x68 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x68 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x68 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x68 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x68 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x68 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x68 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x68 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x68 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x68 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x68 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x68 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x6C "CTRLMMR_WKUP_PADCONFIG53" bitfld.long 0x6C 31. "LOCK,Lock" "0,1" rbitfld.long 0x6C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x6C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x6C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x6C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x6C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x6C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x6C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x6C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x6C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x6C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x6C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x6C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x6C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x6C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x6C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x6C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x6C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x6C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x6C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x6C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x6C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x6C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x70 "CTRLMMR_WKUP_PADCONFIG54" bitfld.long 0x70 31. "LOCK,Lock" "0,1" rbitfld.long 0x70 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x70 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x70 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x70 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x70 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x70 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x70 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x70 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x70 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x70 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x70 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x70 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x70 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x70 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x70 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x70 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x70 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x70 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x70 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x70 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x70 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x70 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x74 "CTRLMMR_WKUP_PADCONFIG55" bitfld.long 0x74 31. "LOCK,Lock" "0,1" rbitfld.long 0x74 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x74 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x74 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x74 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x74 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x74 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x74 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x74 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x74 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x74 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x74 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x74 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x74 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x74 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x74 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x74 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x74 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x74 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x74 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x74 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x74 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x74 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x78 "CTRLMMR_WKUP_PADCONFIG56" bitfld.long 0x78 31. "LOCK,Lock" "0,1" rbitfld.long 0x78 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x78 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x78 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x78 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x78 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x78 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x78 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x78 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x78 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x78 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x78 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x78 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x78 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x78 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x78 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x78 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x78 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x78 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x78 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x78 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x78 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x78 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x7C "CTRLMMR_WKUP_PADCONFIG57" bitfld.long 0x7C 31. "LOCK,Lock" "0,1" rbitfld.long 0x7C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x7C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x7C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x7C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x7C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x7C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x7C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x7C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x7C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x7C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x7C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x7C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x7C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x7C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x7C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x7C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x7C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x7C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x7C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x7C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x7C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x7C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x80 "CTRLMMR_WKUP_PADCONFIG58" bitfld.long 0x80 31. "LOCK,Lock" "0,1" rbitfld.long 0x80 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x80 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x80 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x80 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x80 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x80 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x80 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x80 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x80 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x80 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x80 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x80 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x80 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x80 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x80 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x80 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x80 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x80 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x80 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x80 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x80 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x80 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x84 "CTRLMMR_WKUP_PADCONFIG59" bitfld.long 0x84 31. "LOCK,Lock" "0,1" rbitfld.long 0x84 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x84 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x84 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x84 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x84 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x84 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x84 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x84 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x84 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x84 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x84 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x84 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x84 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x84 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x84 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x84 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x84 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x84 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x84 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x84 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x84 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x84 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x88 "CTRLMMR_WKUP_PADCONFIG60" bitfld.long 0x88 31. "LOCK,Lock" "0,1" rbitfld.long 0x88 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x88 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x88 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x88 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x88 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x88 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x88 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x88 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x88 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x88 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x88 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x88 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x88 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x88 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x88 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x88 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x88 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x88 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x88 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x88 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x88 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x88 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x88 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x8C "CTRLMMR_WKUP_PADCONFIG61" bitfld.long 0x8C 31. "LOCK,Lock" "0,1" rbitfld.long 0x8C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x8C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x8C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x8C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x8C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x8C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x8C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x8C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x8C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x8C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x8C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x8C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x8C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x8C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x8C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x8C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x8C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x8C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x8C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x90 "CTRLMMR_WKUP_PADCONFIG62" bitfld.long 0x90 31. "LOCK,Lock" "0,1" rbitfld.long 0x90 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x90 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x90 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x90 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x90 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x90 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x90 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x90 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x90 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x90 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x90 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x90 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x90 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x90 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x90 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x90 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x90 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x90 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x90 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x90 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x90 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x90 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x90 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x94 "CTRLMMR_WKUP_PADCONFIG63" bitfld.long 0x94 31. "LOCK,Lock" "0,1" rbitfld.long 0x94 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x94 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x94 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x94 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x94 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x94 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x94 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x94 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x94 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x94 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x94 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x94 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x94 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x94 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x94 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x94 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x94 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x94 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x94 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x94 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x94 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x94 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x94 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x98 "CTRLMMR_WKUP_PADCONFIG64" bitfld.long 0x98 31. "LOCK,Lock" "0,1" rbitfld.long 0x98 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x98 29. "WKUP_EN,Wakeup enable" "0,1" rbitfld.long 0x98 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x98 26. "DSOUT_VAL,Deep Sleep output value" "0,1" bitfld.long 0x98 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" newline bitfld.long 0x98 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x98 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x98 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x98 21. "TX_DIS,Driver Disable" "0,1" newline rbitfld.long 0x98 19.--20. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x98 18. "RXACTIVE,Input enable for the Pad" "0,1" newline rbitfld.long 0x98 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x98 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x98 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x98 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x98 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x98 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x98 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x98 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x98 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x98 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x9C "CTRLMMR_WKUP_PADCONFIG65" bitfld.long 0x9C 31. "LOCK,Lock" "0,1" rbitfld.long 0x9C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x9C 29. "WKUP_EN,Wakeup enable" "0,1" rbitfld.long 0x9C 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x9C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" bitfld.long 0x9C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" newline bitfld.long 0x9C 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0x9C 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0x9C 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0x9C 21. "TX_DIS,Driver Disable" "0,1" newline rbitfld.long 0x9C 19.--20. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x9C 18. "RXACTIVE,Input enable for the Pad" "0,1" newline rbitfld.long 0x9C 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x9C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x9C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x9C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x9C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x9C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x9C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x9C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x9C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x9C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xA0 "CTRLMMR_WKUP_PADCONFIG66" bitfld.long 0xA0 31. "LOCK,Lock" "0,1" rbitfld.long 0xA0 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xA0 29. "WKUP_EN,Wakeup enable" "0,1" rbitfld.long 0xA0 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xA0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" bitfld.long 0xA0 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" newline bitfld.long 0xA0 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xA0 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xA0 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xA0 21. "TX_DIS,Driver Disable" "0,1" newline rbitfld.long 0xA0 19.--20. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA0 18. "RXACTIVE,Input enable for the Pad" "0,1" newline rbitfld.long 0xA0 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xA0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xA0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xA0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xA0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xA0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xA0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xA0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xA4 "CTRLMMR_WKUP_PADCONFIG67" bitfld.long 0xA4 31. "LOCK,Lock" "0,1" rbitfld.long 0xA4 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xA4 29. "WKUP_EN,Wakeup enable" "0,1" rbitfld.long 0xA4 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xA4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" bitfld.long 0xA4 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" newline bitfld.long 0xA4 24. "DS_EN,Deep Sleep override control" "0,1" bitfld.long 0xA4 23. "ISO_BYP,Isolation Bypass" "0,1" newline bitfld.long 0xA4 22. "ISO_OVR,Isolation Override" "0,1" bitfld.long 0xA4 21. "TX_DIS,Driver Disable" "0,1" newline rbitfld.long 0xA4 19.--20. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA4 18. "RXACTIVE,Input enable for the Pad" "0,1" newline rbitfld.long 0xA4 16.--17. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xA4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xA4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xA4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xA4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xA4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xA4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xA4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xA8 "CTRLMMR_WKUP_PADCONFIG68" bitfld.long 0xA8 31. "LOCK,Lock" "0,1" rbitfld.long 0xA8 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xA8 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xA8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xA8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xA8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xA8 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xA8 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xA8 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xA8 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xA8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xA8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xA8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xA8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xA8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xA8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xA8 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xA8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xA8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xA8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xA8 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xA8 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xA8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xAC "CTRLMMR_WKUP_PADCONFIG69" bitfld.long 0xAC 31. "LOCK,Lock" "0,1" rbitfld.long 0xAC 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xAC 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xAC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xAC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xAC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xAC 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xAC 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xAC 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xAC 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xAC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xAC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xAC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xAC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xAC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xAC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xAC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xAC 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xAC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xAC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xAC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xAC 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xAC 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xAC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xB0 "CTRLMMR_WKUP_PADCONFIG70" bitfld.long 0xB0 31. "LOCK,Lock" "0,1" rbitfld.long 0xB0 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xB0 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xB0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xB0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xB0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xB0 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xB0 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xB0 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xB0 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xB0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xB0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xB0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xB0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xB0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xB0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xB0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xB0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xB0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xB0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xB0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xB0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xB0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xB4 "CTRLMMR_WKUP_PADCONFIG71" bitfld.long 0xB4 31. "LOCK,Lock" "0,1" rbitfld.long 0xB4 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xB4 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xB4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xB4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xB4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xB4 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xB4 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xB4 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xB4 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xB4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xB4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xB4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xB4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xB4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xB4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xB4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xB4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xB4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xB4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xB4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xB4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xB4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xB8 "CTRLMMR_WKUP_PADCONFIG72" bitfld.long 0xB8 31. "LOCK,Lock" "0,1" rbitfld.long 0xB8 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xB8 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xB8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xB8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xB8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xB8 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xB8 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xB8 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xB8 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xB8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xB8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xB8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xB8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xB8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xB8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xB8 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xB8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xB8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xB8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xB8 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xB8 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xB8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xBC "CTRLMMR_WKUP_PADCONFIG73" bitfld.long 0xBC 31. "LOCK,Lock" "0,1" rbitfld.long 0xBC 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xBC 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xBC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xBC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xBC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xBC 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xBC 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xBC 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xBC 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xBC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xBC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xBC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xBC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xBC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xBC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xBC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xBC 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xBC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xBC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xBC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xBC 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xBC 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xBC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xC0 "CTRLMMR_WKUP_PADCONFIG74" bitfld.long 0xC0 31. "LOCK,Lock" "0,1" rbitfld.long 0xC0 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xC0 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xC0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xC0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC0 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xC0 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xC0 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xC0 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xC0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xC0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xC0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xC0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xC0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xC0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xC0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xC4 "CTRLMMR_WKUP_PADCONFIG75" bitfld.long 0xC4 31. "LOCK,Lock" "0,1" rbitfld.long 0xC4 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xC4 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xC4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xC4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC4 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xC4 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xC4 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xC4 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xC4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xC4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xC4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xC4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xC4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xC4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xC4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xC8 "CTRLMMR_WKUP_PADCONFIG76" bitfld.long 0xC8 31. "LOCK,Lock" "0,1" rbitfld.long 0xC8 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xC8 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xC8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xC8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC8 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xC8 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xC8 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xC8 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xC8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xC8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xC8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xC8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC8 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xC8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xC8 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC8 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xC8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xCC "CTRLMMR_WKUP_PADCONFIG77" bitfld.long 0xCC 31. "LOCK,Lock" "0,1" hexmask.long.tbyte 0xCC 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xCC 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xCC 6.--10. 1. "RESERVED,Reserved" newline bitfld.long 0xCC 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xCC 0.--3. 1. "RESERVED,Reserved" line.long 0xD0 "CTRLMMR_WKUP_PADCONFIG78" bitfld.long 0xD0 31. "LOCK,Lock" "0,1" hexmask.long.tbyte 0xD0 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xD0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD0 6.--10. 1. "RESERVED,Reserved" newline bitfld.long 0xD0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xD0 0.--3. 1. "RESERVED,Reserved" line.long 0xD4 "CTRLMMR_WKUP_PADCONFIG79" bitfld.long 0xD4 31. "LOCK,Lock" "0,1" hexmask.long.tbyte 0xD4 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xD4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD4 6.--10. 1. "RESERVED,Reserved" newline bitfld.long 0xD4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xD4 0.--3. 1. "RESERVED,Reserved" line.long 0xD8 "CTRLMMR_WKUP_PADCONFIG80" bitfld.long 0xD8 31. "LOCK,Lock" "0,1" hexmask.long.tbyte 0xD8 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xD8 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD8 6.--10. 1. "RESERVED,Reserved" newline bitfld.long 0xD8 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xD8 0.--3. 1. "RESERVED,Reserved" line.long 0xDC "CTRLMMR_WKUP_PADCONFIG81" bitfld.long 0xDC 31. "LOCK,Lock" "0,1" hexmask.long.tbyte 0xDC 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xDC 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xDC 6.--10. 1. "RESERVED,Reserved" newline bitfld.long 0xDC 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xDC 0.--3. 1. "RESERVED,Reserved" line.long 0xE0 "CTRLMMR_WKUP_PADCONFIG82" bitfld.long 0xE0 31. "LOCK,Lock" "0,1" hexmask.long.tbyte 0xE0 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xE0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE0 6.--10. 1. "RESERVED,Reserved" newline bitfld.long 0xE0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xE0 0.--3. 1. "RESERVED,Reserved" line.long 0xE4 "CTRLMMR_WKUP_PADCONFIG83" bitfld.long 0xE4 31. "LOCK,Lock" "0,1" hexmask.long.tbyte 0xE4 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xE4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE4 6.--10. 1. "RESERVED,Reserved" newline bitfld.long 0xE4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xE4 0.--3. 1. "RESERVED,Reserved" line.long 0xE8 "CTRLMMR_WKUP_PADCONFIG84" bitfld.long 0xE8 31. "LOCK,Lock" "0,1" hexmask.long.tbyte 0xE8 14.--30. 1. "RESERVED,Reserved" newline bitfld.long 0xE8 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE8 6.--10. 1. "RESERVED,Reserved" newline bitfld.long 0xE8 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xE8 0.--3. 1. "RESERVED,Reserved" group.long 0x1E174++0x1F line.long 0x0 "CTRLMMR_WKUP_PADCONFIG93" bitfld.long 0x0 31. "LOCK,Lock" "0,1" rbitfld.long 0x0 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x0 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x0 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x0 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x0 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x0 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x0 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x0 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x0 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x0 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x0 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x0 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x0 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x0 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x0 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x0 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x0 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x0 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x4 "CTRLMMR_WKUP_PADCONFIG94" bitfld.long 0x4 31. "LOCK,Lock" "0,1" rbitfld.long 0x4 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x4 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x4 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x4 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x4 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x4 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x4 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x4 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x4 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x4 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x4 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x4 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x4 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x4 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x4 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x4 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x4 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x4 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x8 "CTRLMMR_WKUP_PADCONFIG95" bitfld.long 0x8 31. "LOCK,Lock" "0,1" rbitfld.long 0x8 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x8 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x8 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x8 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x8 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x8 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x8 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x8 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x8 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x8 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x8 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x8 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x8 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x8 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x8 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x8 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x8 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x8 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x8 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x8 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x8 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0xC "CTRLMMR_WKUP_PADCONFIG96" bitfld.long 0xC 31. "LOCK,Lock" "0,1" rbitfld.long 0xC 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0xC 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0xC 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0xC 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0xC 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0xC 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0xC 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0xC 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0xC 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0xC 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0xC 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0xC 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0xC 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0xC 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0xC 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0xC 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0xC 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0xC 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0xC 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0xC 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0xC 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x10 "CTRLMMR_WKUP_PADCONFIG97" bitfld.long 0x10 31. "LOCK,Lock" "0,1" rbitfld.long 0x10 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x10 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x10 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x10 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x10 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x10 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x10 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x10 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x10 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x10 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x10 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x10 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x10 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x10 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x10 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x10 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x10 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x10 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x10 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x10 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x10 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x14 "CTRLMMR_WKUP_PADCONFIG98" bitfld.long 0x14 31. "LOCK,Lock" "0,1" rbitfld.long 0x14 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x14 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x14 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x14 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x14 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x14 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x14 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x14 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x14 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x14 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x14 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x14 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x14 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x14 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x14 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x14 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x14 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x14 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x14 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x14 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x18 "CTRLMMR_WKUP_PADCONFIG99" bitfld.long 0x18 31. "LOCK,Lock" "0,1" rbitfld.long 0x18 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x18 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x18 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x18 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x18 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x18 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x18 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x18 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x18 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x18 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x18 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x18 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x18 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x18 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x18 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x18 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x18 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x18 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x18 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x18 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x18 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" line.long 0x1C "CTRLMMR_WKUP_PADCONFIG100" bitfld.long 0x1C 31. "LOCK,Lock" "0,1" rbitfld.long 0x1C 30. "WKUP_EVT,Wakeup event status" "0,1" newline bitfld.long 0x1C 29. "WKUP_EN,Wakeup enable" "0,1" bitfld.long 0x1C 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1" newline bitfld.long 0x1C 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1" bitfld.long 0x1C 26. "DSOUT_VAL,Deep Sleep output value" "0,1" newline bitfld.long 0x1C 25. "DSOUT_DIS,Deep Sleep output enable" "0,1" bitfld.long 0x1C 24. "DS_EN,Deep Sleep override control" "0,1" newline bitfld.long 0x1C 23. "ISO_BYP,Isolation Bypass" "0,1" bitfld.long 0x1C 22. "ISO_OVR,Isolation Override" "0,1" newline bitfld.long 0x1C 21. "TX_DIS,Driver Disable" "0,1" bitfld.long 0x1C 19.--20. "DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "RXACTIVE,Input enable for the Pad" "0,1" bitfld.long 0x1C 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1" newline bitfld.long 0x1C 16. "PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal." "0,1" bitfld.long 0x1C 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1" newline bitfld.long 0x1C 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1" bitfld.long 0x1C 11.--13. "DEBOUNCE_SEL,Selects the debounce period for the pad." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x1C 9.--10. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x1C 8. "WK_LVL_POL,Level Sensitive Wakeup Polarity" "0,1" newline bitfld.long 0x1C 7. "WK_LVL_EN,Level Sensitive Wakeup Enable" "0,1" rbitfld.long 0x1C 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x1C 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select. 0h - Implement GPIO in GPIO_WKUP_0 instance 1h - Implement GPIO in GPIO_WKUP_1 instance" "0,1,2,3" hexmask.long.byte 0x1C 0.--3. 1. "MUXMODE,Pad functional signal mux selection 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 Fh - Mux Mode 15" group.long 0x1F008++0x7 line.long 0x0 "CTRLMMR_WKUP_LOCK7_KICK0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status." "0,1" line.long 0x4 "CTRLMMR_WKUP_LOCK7_KICK1" hexmask.long 0x4 0.--31. 1. "KEY,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers" group.long 0x1F100++0xF line.long 0x0 "CTRLMMR_WKUP_P7_CLAIM0" hexmask.long 0x0 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x4 "CTRLMMR_WKUP_P7_CLAIM1" hexmask.long 0x4 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0x8 "CTRLMMR_WKUP_P7_CLAIM2" hexmask.long 0x8 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" line.long 0xC "CTRLMMR_WKUP_P7_CLAIM3" hexmask.long 0xC 0.--31. 1. "PROXY1_CLAIMED,Proxy1 register claim bit" tree.end tree "WKUP_ESM0_CFG" base ad:0x42080000 rgroup.long 0x0++0x7 line.long 0x0 "ESM_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,Always reads as 1h. Writes have no affect." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit:2h = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID. Always read as the assigned functional ID. Writes have no affect." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom. Special version." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "ESM_INFO,The Info Register gives the configuration information of this ESM." bitfld.long 0x4 31. "LAST_RESET,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1" hexmask.long.word 0x4 16.--30. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Indicates the number of event groups that are pulse (as opposed to level) driven." hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Indicates the total number of groups that exist in the ESM." group.long 0x8++0x3 line.long 0x0 "ESM_EN,The Global Enable Register has the master interrupt mask" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,This field is the global mask for all interrupts. It is reset by the warm reset. The purpose is to leave all of the raw status and per-interrupt enable bits alone so that after a warm reset software may observe the state of the ESM before the warm.." wgroup.long 0xC++0x3 line.long 0x0 "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset field. Writing to this field can cause all of the raw status and all enables to be cleared. This can be used to reset the ESM state after debugging because of a warm reset." group.long 0x10++0xF line.long 0x0 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--7. 1. "STS,This is the raw status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0h." line.long 0x4 "ESM_ERR_STS,Config Error Enable and Clear Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x4 0.--7. 1. "MSK,This is the masked status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0." line.long 0x8 "ESM_ERR_EN_SET,Config Error Enable Set Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x8 0.--7. 1. "MSK,This is the mask enable for errors in the configuration for Group N. If the corresponding bit and the" line.long 0xC "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0xC 0.--7. 1. "MSK,This is the mask clear for errors in the configuration for Group N. If the corresponding bit and the" rgroup.long 0x20++0xF line.long 0x0 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt" hexmask.long.word 0x0 16.--31. 1. "PLS,Indicates what the highest priority low priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." hexmask.long.word 0x0 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for High Priority while.." line.long 0x4 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt" hexmask.long.word 0x4 16.--31. 1. "PLS,Indicates what the highest priority high priority interrupt caused by a pulse number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." hexmask.long.word 0x4 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is. The lowest event has the highest priority. I.e. if Global Events 0 1 2 3 and 4 are pending and Global Event 0 and 1 are configured for high priority while.." line.long 0x8 "ESM_LOW,Shows which groups have outstanding low priority interrupts" hexmask.long 0x8 0.--31. 1. "STS,Indicates which Event Groups have one or more low priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0 bit 1 is for Event Group 1 etc… (bit N is for Event Group N)." line.long 0xC "ESM_HI,Shows which groups have outstanding high priority interrupts" hexmask.long 0xC 0.--31. 1. "STS,Indicates which Event Groups have one or more high priority interrupts pending. This register is bit oriented where bit 0 is for Event Group 0 bit 1 is for Event Group 1 etc… (bit N is for Event Group N)." wgroup.long 0x30++0x3 line.long 0x0 "ESM_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced. Writing the corresponding vector to this field will cause a re-evaluation of interrupts. If when the vector is written there are still pending interrupts a new pulse will be generated. Reads always return 0." group.long 0x40++0x3 line.long 0x0 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output" hexmask.long 0x0 4.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin control key. This field controls behavior of the error pin. Note during reset the field is 0h but the error pin is asserted (active low). Immediately after reset the error pin de-asserts. This field is only reset by a Power-On-Reset (not warm.." rgroup.long 0x44++0x7 line.long 0x0 "ESM_PIN_STS,This register reflects the status of the error_pin_n output" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." bitfld.long 0x0 0. "VAL,This field indicates the status of the error pin as looped back from the I/O. This field reflects the state of the ERR_I pin. Since the ERR_O pin is only affected by Power-On-Reset then the value of this field may be 1h after the release of Warm.." "0,1" line.long 0x4 "ESM_PIN_CNTR,This register shows the current value of the error pin counter" hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,This field indicates the current value of the time interval counter. See" group.long 0x4C++0x3 line.long 0x0 "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Always read as 0h. Writes have no affect." hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,This is the value that will be pre-loaded in to the counter field of the" group.long 0x400++0x1B line.long 0x0 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…)" line.long 0x4 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status of the events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will.." line.long 0x8 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x8 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) If the corresponding bit and the global enable" line.long 0xC "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0xC 0.--31. 1. "MSK,This field is used to disable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) If the corresponding bit and the global enable" line.long 0x10 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x10 0.--31. 1. "MSK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset.." line.long 0x14 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x14 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft.." line.long 0x18 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 3h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG" hexmask.long 0x18 0.--31. 1. "MSK,This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit (Example: bit 0 is event N*32+0 bit 1 is N*32 + 1 etc…) This field is only reset by a Power-On-Reset (not warm reset). A global soft.." tree.end tree "WKUP_GPIO0" base ad:0x42110000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable" group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits " hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits " line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state" hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state" line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits" group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits" line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits" line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits" line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" line.long 0x14 "GPIO_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits " hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits " line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits" group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits" line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits" line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits" line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" line.long 0x14 "GPIO_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits " hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits " line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits" group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits" line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits" line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits" line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" line.long 0x14 "GPIO_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits " hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits " line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits" group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits" line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits" line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits" line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" line.long 0x14 "GPIO_DIR8,Direction Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits " line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits" group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits" line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits" line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits" line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" tree.end tree "WKUP_GPIO1" base ad:0x42100000 rgroup.long 0x0++0x7 line.long 0x0 "GPIO_PID,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "GPIO_PCR,Peripheral Control Register" hexmask.long 0x4 2.--31. 1. "RESERVED" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable" group.long 0x10++0xF line.long 0x0 "GPIO_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits " hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits " line.long 0x4 "GPIO_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x8 "GPIO_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state" hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state" line.long 0xC "GPIO_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x20++0x3 line.long 0x0 "GPIO_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits" group.long 0x24++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits" line.long 0x8 "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits" line.long 0xC "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits" line.long 0x10 "GPIO_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" line.long 0x14 "GPIO_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits " hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits " line.long 0x18 "GPIO_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x48++0x3 line.long 0x0 "GPIO_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits" group.long 0x4C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits" line.long 0x8 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits" line.long 0xC "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits" line.long 0x10 "GPIO_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" line.long 0x14 "GPIO_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits " hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits " line.long 0x18 "GPIO_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x70++0x3 line.long 0x0 "GPIO_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits" group.long 0x74++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits" line.long 0x8 "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits" line.long 0xC "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits" line.long 0x10 "GPIO_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" line.long 0x14 "GPIO_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits " hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits " line.long 0x18 "GPIO_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state" hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state" hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0x98++0x3 line.long 0x0 "GPIO_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits" group.long 0x9C++0x23 line.long 0x0 "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits" hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits" line.long 0x8 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits" line.long 0xC "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits" hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits" line.long 0x10 "GPIO_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" line.long 0x14 "GPIO_DIR8,Direction Register" hexmask.long.word 0x14 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits " line.long 0x18 "GPIO_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state" line.long 0x1C "GPIO_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state" line.long 0x20 "GPIO_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state" rgroup.long 0xC0++0x3 line.long 0x0 "GPIO_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits" group.long 0xC4++0x13 line.long 0x0 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits" line.long 0x4 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits" line.long 0x8 "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits" line.long 0xC "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits" line.long 0x10 "GPIO_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "RESERVED,RESERVED" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" tree.end tree "WKUP_GPIOMUX_INTRTR0_CFG" base ad:0x42200000 rgroup.long 0x0++0x3 line.long 0x0 "WKUP_GPIOMUX_INTRTR0_PID,Peripheral identification register. Uniquely identifies the module and its specific revision." hexmask.long 0x0 0.--31. 1. "REV,TI internal data. Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "WKUP_GPIOMUX_INTRTR0_MUXCNTL_n,Interrupt mux control register. Offset = 4h + (n * 4h); where n = 0h to 1Fh." hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" bitfld.long 0x0 16. "INT_ENABLE,Enable for interrupt output N" "0,1" hexmask.long.word 0x0 7.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x0 0.--6. 1. "ENABLE,Mux control for interrupt output N" tree.end tree "WKUP_I2C0_CFG" base ad:0x42120000 rgroup.long 0x0++0x7 line.long 0x0 "I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "I2C_REVNB_HI,Revision Number register (High)" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "I2C_SYSC,System Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" group.long 0x20++0x2F line.long 0x0 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" line.long 0x4 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" hexmask.long.word 0x8 16.--31. 1. "RESERVED" bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x8 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x8 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x8 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x8 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x8 8. "BF,Bus Free IRQ enabled status" "0,1" bitfld.long 0x8 7. "AERR,Access Error IRQ enabled status" "0,1" newline bitfld.long 0x8 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x8 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x8 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x8 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x8 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0xC "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." hexmask.long.word 0xC 16.--31. 1. "RESERVED" bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0xC 12. "RESERVED,reserved" "0,1" newline bitfld.long 0xC 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0xC 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." hexmask.long.word 0x10 16.--31. 1. "RESERVED" bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x10 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)." hexmask.long.word 0x14 16.--31. 1. "RESERVED" rbitfld.long 0x14 15. "RESERVED,Reserved" "0,1" bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x14 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x14 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x14 4. "RESERVED,Reserved" "0,1" bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." hexmask.long.word 0x18 16.--31. 1. "RESERVED" hexmask.long.word 0x18 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." hexmask.long.word 0x1C 16.--31. 1. "RESERVED" hexmask.long.word 0x1C 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." hexmask.long.word 0x20 16.--31. 1. "RESERVED" hexmask.long.word 0x20 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." hexmask.long.word 0x24 16.--31. 1. "RESERVED" hexmask.long.word 0x24 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." hexmask.long.word 0x28 16.--31. 1. "RESERVED" rbitfld.long 0x28 15. "RESERVED,Reserved" "0,1" bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x28 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x28 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x28 4. "RESERVED,Reserved" "0,1" bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." hexmask.long.word 0x2C 16.--31. 1. "RESERVED" rbitfld.long 0x2C 15. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1" rbitfld.long 0x2C 12. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1" bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1" rbitfld.long 0x2C 7. "RESERVED,Reserved" "0,1" newline bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1" rbitfld.long 0x2C 4. "RESERVED,Reserved" "0,1" bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1" newline bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "I2C_IE,I2C interrupt enable vector (legacy)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" rbitfld.long 0x0 12. "RESERVED,reserved" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" newline bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "0,1" line.long 0x4 "I2C_STAT,I2C interrupt status vector (legacy)." hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" newline bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "I2C_SYSS,System Status register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "I2C_BUF,Buffer Configuration register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "I2C_CNT,Data counter register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "I2C_DATA,Data access register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "I2C_CON,I2C configuration register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" newline bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "I2C_OA,Own address register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 10.--12. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "I2C_SA,Slave address register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.word 0xC 16.--31. 1. "RESERVED" hexmask.long.byte 0xC 8.--15. 1. "RESERVED,Reserved" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x" line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register." hexmask.long.word 0x10 16.--31. 1. "RESERVED" hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "I2C_SCLH,I2C SCL High Time Register." hexmask.long.word 0x14 16.--31. 1. "RESERVED" hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "I2C_SYSTEST,I2C System Test Register." hexmask.long.word 0x18 16.--31. 1. "RESERVED" bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 9.--10. "RESERVED,Reserved" "0,1,2,3" rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.byte 0x4 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED" hexmask.long.byte 0x8 10.--15. 1. "RESERVED,Reserved" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "I2C_ACTOA,I2C Active Own Address Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" newline bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 4.--15. 1. "RESERVED,Reserved" bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" newline bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "WKUP_PLLCTRL0" base ad:0x42010000 rgroup.long 0x0++0x3 line.long 0x0 "PID,Return to the . Peripheral identification register" bitfld.long 0x0 30.--31. "SCHEME,Peripheral identification register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision.Will vary depending on release" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x100++0x3 line.long 0x0 "PLLCTL,Return to the . PLL control register" hexmask.long.tbyte 0x0 10.--31. 1. "RSVD2,Reserved" bitfld.long 0x0 9. "EXCLKSRC,Selects between using bypass clock or an external clock source. 0=bypass clock 1=external clock source" "0: bypass clock,1: external clock source" newline bitfld.long 0x0 8. "CLKMODE,Reference Clock Selection. 1 = clkin_pi is the reference clock 0 = oscin_pi is the reference clock This bit is only applicable when d_clkmodesrc_pi = 1. It is otherwise don't care." "0: oscin_pi is the reference clock This bit is only..,1: clkin_pi is the reference clock" bitfld.long 0x0 7. "PLLSELB,Selects PLL A versus PLL B. 1 = PLL B is selected. PLL A is put in power down (pll_a_pwrdn_po = 1) 0 = PLL A is selected. PLL B is put in power down. (pll_b_pwrdn_po = 1)" "0: PLL A is selected,1: PLL B is selected" newline bitfld.long 0x0 6. "RSVD1,Reserved" "0,1" bitfld.long 0x0 5. "PLLENSRC,PLLEN Mux Control Source 1 = PLLEN Mux is controlled by input pllen_pi. PLLCTL.PLLEN is don't care 0 = PLLEN Mux is controlled by PLLCTL.PLLEN. pllen_pi is don't care" "0: PLLEN Mux is controlled by PLLCTL,1: PLLEN Mux is controlled by input pllen_pi" newline bitfld.long 0x0 4. "PLLDIS,Asserts DISABLE to PLL if Supported 1 = PLL Controller output pll_disable_po = 1. 0 = PLL Controller output pll_disable_po = 0. Chip team must pay attention to the disable signal polarity of the PLL they use. Some PLLs may require PLLDIS=1 to.." "0: PLL Controller output pll_disable_po = 0,1: PLL Controller output pll_disable_po = 1" bitfld.long 0x0 3. "PLLRST,Asserts RESET to PLL if Supported.Controls output pll_reset_po. 1= PLL Controller output pll_reset_po = 1. 0= PLL Controller output pll_reset_po=0. Chip team must pay attention to the reset signal polarity of the PLL they use. Some PLLs require.." "0: PLL Controller output pll_reset_po=0,1: PLL Controller output pll_reset_po = 1" newline bitfld.long 0x0 2. "RSVD,Reserved" "0,1" bitfld.long 0x0 1. "PLLPWRDN,Selects PLL Power Down for the PLL selected by PLLSELB.The PLL not selected by PLLSELB is NOT controlled by PLLPWRDN bit. The not-selected PLL will stay in power down regardless of PLLPWRDN value. 0 = Selected PLL Operational. If PLLSELB=0 (PLLA.." "0: Selected PLL Operational,1: Selected PLL Placed In Power Down State" newline bitfld.long 0x0 0. "PLLEN,PLL Mode Enable This bit controls the multiplexer before the SYSCLK dividers D1 to Dn. 0 = Bypass Mode PreDiv PLL and PostDiv are bypassed. SYSCLK divided down directly from input reference clock refclk. 1 = PLL Mode PLL is used. SYSCLK divided.." "0: Bypass Mode PreDiv,1: PLL Mode PLL is used" group.long 0x118++0x7 line.long 0x0 "PLLDIV1,Return to the . PLL controller divider1 control register" hexmask.long.word 0x0 16.--31. 1. "RSVD1,Reserved" bitfld.long 0x0 15. "DN_EN,Divider Dn Enable 0 = Divider n Disabled. SYSCLKn is also gated before and after divider Dn. 1 = Divider n Enabled" "0: Divider n Disabled,1: Divider n Enabled" newline bitfld.long 0x0 14. "HALF_RATIO,Ratio is in half steps.Example 1: if RATIO = 00000 and HALFRATIO=1 the divider will be /1.5. Example 2: RATIO=10111 and HALFRATIO=1 divider will be /24.5. Example 3: if RATIO=00011 and HALFRATIO=0 divider will be /4. THE HALF RATIO DIVIDER IS.." "?,1: if RATIO = 00000 and HALFRATIO=1 the divider.." hexmask.long.byte 0x0 8.--13. 1. "RSVD,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "RATIO,Divider Dn Ratio (SYSCLKn divider) 00000=/1 00001=/2 00010=/3 00011=/4 00100=/5 00101=/6 00110=/7 00111=/8 01000=/9 01001=/10 01010=/11 01011=/12 01100=/13 01101=/14 01110=/15 01111=/16 10000=/17 10001=/18 10010=/19 10011=/20 10100=/21 10101=/22.." line.long 0x4 "PLLDIV2,Return to the . PLL controller divider2 control register" hexmask.long.word 0x4 16.--31. 1. "RSVD1,Reserved" bitfld.long 0x4 15. "DN_EN,Divider Dn Enable 0 = Divider n Disabled. SYSCLKn is also gated before and after divider Dn. 1 = Divider n Enabled" "0: Divider n Disabled,1: Divider n Enabled" newline bitfld.long 0x4 14. "HALF_RATIO,Ratio is in half steps.Example 1: if RATIO = 00000 and HALFRATIO=1 the divider will be /1.5. Example 2: RATIO=10111 and HALFRATIO=1 divider will be /24.5. Example 3: if RATIO=00011 and HALFRATIO=0 divider will be /4. THE HALF RATIO DIVIDER IS.." "?,1: if RATIO = 00000 and HALFRATIO=1 the divider.." hexmask.long.byte 0x4 8.--13. 1. "RSVD,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "RATIO,Divider Dn Ratio (SYSCLKn divider) 00000=/1 00001=/2 00010=/3 00011=/4 00100=/5 00101=/6 00110=/7 00111=/8 01000=/9 01001=/10 01010=/11 01011=/12 01100=/13 01101=/14 01110=/15 01111=/16 10000=/17 10001=/18 10010=/19 10011=/20 10100=/21 10101=/22.." group.long 0x138++0xF line.long 0x0 "PLLCMD,Return to the . PLL Controller command register" hexmask.long 0x0 2.--31. 1. "RSVD,Reserved" bitfld.long 0x0 1. "OSCPWRDN,iOscillator Power Down Command 1: A write of 1 (doesn't need to be a transition from 0 to 1) to this bit initiates oscillator power down command. 0: A write of 0 to this bit clears the bit to zero but causes no effect. Read from this field.." "0: A write of 0 to this bit clears the bit to zero..,1: A write of 1" newline bitfld.long 0x0 0. "GOSET,GO bit for SYSCLKx phase alignment. GOSET = 1: A write of 1 to this bit signifies that the new divide ratios in PLLDIV[1:n] are taken into account at the nearest possible rising edge to phase align the clocks. The actual SYSCLKx to be aligned are.." "0: A write of 0 to this bit clears the bit to zero..,1: A write of 1 to this bit signifies that the new.." line.long 0x4 "PLLSTAT,Return to the . PLL Controller status register" hexmask.long 0x4 3.--31. 1. "RSVD,Reserved" rbitfld.long 0x4 2. "STABLE,OSCIN Stable This bit shows the status of the rstclk_cnt_done_po signal. It indicates if the rstclk counter has finished counting implying that the OSCIN/CLKIN is stable. The d_rstclk_cnt_pi must be set properly to allow rstclk counter to count.." "0: rstclk counter not done counting,1: OSCIN/CLKIN is assumed to be stable" newline rbitfld.long 0x4 1. "LOCK,PLL Core STATUS This bit returns the lock status of the selected PLL core (if supported by PLL core). For example if PLLSELB=0 (PLLA selected) it reflects the status of pll_a_lock_i. If PLLSELB-1 (PLLB selected) it reflects the status of.." "0: PLL core not locked,1: PLL core locked" rbitfld.long 0x4 0. "GOSET,Reflects the status of GO transition.Read from this register returns the status of the GO operation. Writes to the register are ignored. GOSTAT = 1: This bit goes to 1 as soon as GOSET in PLLCMD is written to. It remains a 1 when GO operation.." "0: No GO operation in progress,1: This bit goes to 1 as soon as GOSET in PLLCMD is.." line.long 0x8 "ALNCTL,Return to the . PLL Controller clock align control register" hexmask.long.word 0x8 16.--31. 1. "RSVD,Reserved" hexmask.long.word 0x8 1.--15. 1. "ALN,SYSCLKx needs to be aligned with other clocks selected in this register. ALNx = 0: Do not need to align SYSCLKx to other clocks. SYSCLKx is left free-running. ALNx = 1: Align SYSCLKx to other clocks selected in this register Software note: This bit.." newline bitfld.long 0x8 0. "ALN1,SYSCLK1 needs to be aligned with other clocks selected in this register. ALN1 = 0: Do not need to align SYSCLK1 to other clocks. SYSCLK1 is left free-running. ALN1 = 1: Align SYSCLK1 to other clocks selected in this register Software note: This bit.." "0: Do not need to align SYSCLK1 to other clocks,1: Align SYSCLK1 to other clocks selected in this.." line.long 0xC "DCHANGE,Return to the . PLLDIV ratio change register" hexmask.long.word 0xC 16.--31. 1. "RSVD,Reserved" hexmask.long.word 0xC 1.--15. 1. "SYS,SYSCLKx divide ratio has been modified.SYSCLKx ratio will be changed during GO operation. SYSx = 0: SYSCLKx ratio has not been modified. When GOSET is set SYSCLKx will not be affected. SYSx = 1: SYSCLKx ratio has been modified. When GOSET is set .." newline rbitfld.long 0xC 0. "SYS1,SYSCLK1 divide ratio has been modified.SYSCLK1 ratio will be changed during GO operation. SYS1 = 0: SYSCLK1 ratio has not been modified. When GOSET is set SYSCLK1 will not be affected. SYS1 = 1: SYSCLK1 ratio has been modified. When GOSET is set .." "0: SYSCLK1 ratio has not been modified,1: SYSCLK1 ratio has been modified" tree.end tree "WKUP_PSC0" base ad:0x42000000 rgroup.long 0x0++0x3 line.long 0x0 "WKUP_PSC0_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module. The WKUP_PSC0_PID stores version information used to identify the module. All bits within this register are read-only.." bitfld.long 0x0 30.--31. "SCHEME,WKUP_PSC0_PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x7 line.long 0x0 "WKUP_PSC0_GBLCTL,This register contains global control to PSC." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control." hexmask.long.byte 0x0 0.--7. 1. "RESERVED" line.long 0x4 "WKUP_PSC0_GBLSTAT,This register shows the PSC global status." hexmask.long.byte 0x4 28.--31. 1. "RESERVED" hexmask.long.word 0x4 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits" hexmask.long.word 0x4 1.--15. 1. "RESERVED" bitfld.long 0x4 0. "OVRIDE,PSC Override Status" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "WKUP_PSC0_INTEVAL,This register has no storage. Read from this register returns 0." hexmask.long.word 0x0 20.--31. 1. "RESERVED" bitfld.long 0x0 19. "GOSET,GOSTAT Interrupt Set" "0,1" bitfld.long 0x0 18. "EPCSET,External Power Control Interrupt Set" "0,1" bitfld.long 0x0 17. "ERRSET,Combined Interrupt Set" "0,1" hexmask.long.word 0x0 3.--16. 1. "RESERVED" bitfld.long 0x0 2. "EPCEV,External Power Control Interrupt Set" "0,1" newline bitfld.long 0x0 1. "ERREV,Re_evaluate Error Interrupt" "0,1" bitfld.long 0x0 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "WKUP_PSC0_MERRPR,This register records pending error conditions for all modules. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "M,Records pending error conditions." group.long 0x50++0x3 line.long 0x0 "WKUP_PSC0_MERRCR,This register has no storage. Read from this register returns 0. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "M,Write of 1 clears the corresponding WKUP_PSC0_MERRPR bit." rgroup.long 0x60++0x3 line.long 0x0 "WKUP_PSC0_PERRPR,This register records pending error conditions for each power domain. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "P,Power Domain n Error Condition." group.long 0x68++0x3 line.long 0x0 "WKUP_PSC0_PERRCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "P,Write of 1 clears the corresponding WKUP_PSC0_PERRPR bit." rgroup.long 0x70++0x3 line.long 0x0 "WKUP_PSC0_EPCPR,This register records pending external power control conditions. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "EPC,External Power Control Intervention Request for Power Domain n" group.long 0x78++0x3 line.long 0x0 "WKUP_PSC0_EPCCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "EPC,Write of 1 clears the corresponding WKUP_PSC0_EPCPR bit" rgroup.long 0x100++0x3 line.long 0x0 "WKUP_PSC0_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor." bitfld.long 0x0 29.--31. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC" hexmask.long.word 0x0 8.--23. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RAILCNT,Indicates the current rail counter value" group.long 0x104++0x7 line.long 0x0 "WKUP_PSC0_RAILCTL,This register is user programmable. It holds the counter values for rail counter. User can select one of the two counter values to be used for each power domain (see WKUP_PSC0_RAILSEL register)." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.byte 0x0 8.--15. 1. "RAILCTR1,Rail Counter Value 1" hexmask.long.byte 0x0 0.--7. 1. "RAILCTR0,Rail Counter Value 0" line.long 0x4 "WKUP_PSC0_RAILSEL,User can use this register to select the counter value (WKUP_PSC0_RAILCTL) for each power domain." hexmask.long 0x4 0.--31. 1. "P,Rail Counter Select for Power Domain" group.long 0x120++0x3 line.long 0x0 "WKUP_PSC0_PTCMD,This is a pseudo-command register with no actual storage. Reads return 0. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "GO,Power Domain n GO Transition" rgroup.long 0x128++0x3 line.long 0x0 "WKUP_PSC0_PTSTAT,This is a status register. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "GOSTAT,Power Domain n Transition Command Status" rgroup.long 0x200++0x3 line.long 0x0 "WKUP_PSC0_PDSTAT_y,This is a status register. One register per power domain. Each register contains the status for the given power domain. Offset = 200h + (y * 4h); where y = 0h to 1h" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" bitfld.long 0x0 11. "EMUIHB,Emulation Alters Domain State" "0,1" bitfld.long 0x0 10. "PWRBAD,Power Bad error" "0,1" bitfld.long 0x0 9. "PORDONE,POR Done Input Status" "0,1" bitfld.long 0x0 8. "PORZ,PORz output actual status" "0,1" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "STATE,Current Power Domain State" group.long 0x300++0x3 line.long 0x0 "WKUP_PSC0_PDCTL_y,This is a control register. One register per power domain. Offset = 300h + (y * 4h); where y = 0h to 1h" bitfld.long 0x0 31. "FORCE,Force Bit" "0,1" bitfld.long 0x0 30. "RESERVED" "0,1" bitfld.long 0x0 29. "PWRSW,Power shorting Switch Control" "0,1" bitfld.long 0x0 28. "ISO,Isolation Cell control" "0,1" hexmask.long.byte 0x0 24.--27. 1. "RESERVED" hexmask.long.byte 0x0 16.--23. 1. "WAKECNT,RAM wake count delay value" newline bitfld.long 0x0 15. "RESERVED" "0,1" bitfld.long 0x0 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10.--11. "RESERVED" "0,1,2,3" bitfld.long 0x0 9. "EMUIHBIE,Emulation alters domain state" "0,1" bitfld.long 0x0 8. "EPCGOOD,External Power Control Power Good Indication" "0,1" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "NEXT,User_Desired Next Power Domain State Current Power Domain State" "0,1" rgroup.long 0x400++0x3 line.long 0x0 "WKUP_PSC0_PDCFG_y,This is a status register. It shows PSC settings for easy debug. Offset = 400h + (y * 4h); where y = 0h to 1h" hexmask.long 0x0 4.--31. 1. "RESERVED" bitfld.long 0x0 3. "ICEPICK,Icepick support" "0,1" bitfld.long 0x0 2. "RESERVED" "0,1" bitfld.long 0x0 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1" bitfld.long 0x0 0. "ALWAYSON,Always on power domain Current Power Domain State" "0,1" rgroup.long 0x600++0x3 line.long 0x0 "WKUP_PSC0_MDCFG_y,This is a constant register showing some PSC settings for easy debug. This register is read only. Offset = 600h + (y * 4h); where y = 0h to 15h" hexmask.long.word 0x0 21.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--20. 1. "PWRDOM,Indicates which power domain this module belongs to" bitfld.long 0x0 15. "AUTOONLY" "0,1" bitfld.long 0x0 14. "RESETISO" "0,1" bitfld.long 0x0 13. "NEXTLOCK" "0,1" bitfld.long 0x0 12. "ASYNC,Async Lpsc" "0,1" newline bitfld.long 0x0 11. "ICEPICK,IcePick support" "0,1" bitfld.long 0x0 10. "PERMDIS,Permanently disable" "0,1" bitfld.long 0x0 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1" bitfld.long 0x0 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7" rgroup.long 0x800++0x3 line.long 0x0 "WKUP_PSC0_MDSTAT_y,This register shows the status of each module. Requires one register per module on the device. Offset = 800h + (y * 4h); where y = 0h to 15h" hexmask.long.word 0x0 18.--31. 1. "RESERVED" bitfld.long 0x0 17. "EMUIHB,Emulation Alters Module State." "0,1" bitfld.long 0x0 16. "EMURST,Emulation Alters Reset" "0,1" bitfld.long 0x0 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. "MCKOUT,Actual modclk output to module Current Power Domain State" "0,1" bitfld.long 0x0 11. "MRSTDONE,Module reset initialization done status" "0,1" newline bitfld.long 0x0 10. "MRSTZ,Module reset actual status" "0,1" bitfld.long 0x0 9. "LRSTDONE,Module local reset initialization done status" "0,1" bitfld.long 0x0 8. "LRSTZ,Module local reset actual status" "0,1" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "STATE,These bits indicate the current module state" group.long 0xA00++0x3 line.long 0x0 "WKUP_PSC0_MDCTL_y,This register provides specific control for the individual module. One register per module on the device. Offset = A00h + (y * 4h); where y = 0h to 15h" bitfld.long 0x0 31. "FORCE,Force Bit" "0,1" hexmask.long.tbyte 0x0 13.--30. 1. "RESERVED" bitfld.long 0x0 12. "RESETISO,Reset Isolation" "0,1" bitfld.long 0x0 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1" bitfld.long 0x0 10. "EMUIHBIE,Emulation Alters Module State." "0,1" bitfld.long 0x0 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1" newline bitfld.long 0x0 8. "LRSTZ,Module local reset control" "0,1" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "NEXT,Module Next State" tree.end tree "WKUP_UART0" base ad:0x42300000 group.long 0x0++0x3 line.long 0x0 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator. stores the most-significant part of the divisor. stores the least-significant part of the divisor." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register. The is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the ." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register. The is a 64-byte FIFO. The local host (LH) writes data to the . The data is placed in the transmit shift register where it is shifted out.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "THR,Transmit holding register" line.long 0x4 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Stores the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "NOT_USED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. interrupt. interrupt. XOFF received and CTS*/RTS* change of state.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "UART_EFR,Enhanced feature register This register enables or disables enhanced features. Most of the enhanced functions apply only to UART modes. but [4] enables write accesses to [5:4]. the TX trigger level. which is also used in IrDA modes." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit" "0,1" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit" "0,1" bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT" "0,1" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit" "0,1" hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit 3 - bit 0. See" group.long 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1. Bits 0 and 3 can be changed only when the baud clock is not running (DLL and DLH set to 0). See for [5:4] setting restriction when [6] = 1. See for [7:6] setting.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "0,1,2,3" bitfld.long 0x0 3. "DMA_MODE,This register is considered if" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT,Read 0h = TX status interrupt inactive" "0,1" bitfld.long 0x0 4. "RESERVED" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT,Read 0h = RX overrun interrupt inactive" "0,1" bitfld.long 0x0 2. "RX_STOP_IT,Read 0h = Receive stop interrupt inactive" "0,1" newline bitfld.long 0x0 1. "THR_IT,Read 0h = THR interrupt inactive" "0,1" bitfld.long 0x0 0. "RHR_IT,Read 0h = RHR interrupt inactive" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART_IIR_UART,Interrupt identification register. The is a read-only register that provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Read 0h = Modem interrupt. Priority = 4" bitfld.long 0x0 0. "IT_PENDING,Read 0h = An interrupt is pending." "0,1" group.long 0xC++0x7 line.long 0x0 "UART_LCR,Line control register [6:0] define transmission and reception parameters. Note: When [6] is set to 1. the TX line is forced to 0 and remains in this state as long as [6] = 1." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit" "0,1" bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format (if" "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" bitfld.long 0x0 3. "PARITY_EN,0h = No parity" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop-bits" "0,1" bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3" line.long 0x4 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR,0h = No action" "0,1" bitfld.long 0x4 5. "XON_EN,0h = Disable XON any function." "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN,0h = Normal operating mode" "0,1" bitfld.long 0x4 3. "CD_STS_CH,0h = In loopback forces DCD* input high and IRQ outputs to inactive state" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH,0h = In loopback forces RI* input high" "0,1" bitfld.long 0x4 1. "RTS,In loopback controls the" "0,1" newline bitfld.long 0x4 0. "DTR,0h = Force DTR* output to inactive (high)." "0,1" group.long 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "RESERVED" bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "THR_EMPTY,Read 0h = Transmit holding register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL,Read 0h = Status FIFO not full" "0,1" bitfld.long 0x0 5. "RX_LAST_BYTE,Read 0h = The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG,Read 0h = No frame-too-long error in frame" "0,1" bitfld.long 0x0 3. "ABORT,Read 0h = No abort pattern error in frame" "0,1" newline bitfld.long 0x0 2. "CRC,Read 0h = No CRC error in frame" "0,1" bitfld.long 0x0 1. "STS_FIFO_E,Read 0h = Status FIFO not empty" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART_LSR_UART,Line status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "RX_FIFO_STS,Read 0h = Normal operation" "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Read 0h = Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 5. "TX_FIFO_E,Read 0h = Transmit hold register (TX FIFO) is not empty." "0,1" newline bitfld.long 0x0 4. "RX_BI,Read 0h = No break condition" "0,1" bitfld.long 0x0 3. "RX_FE,Read 0h = No framing error in data RX FIFO" "0,1" newline bitfld.long 0x0 2. "RX_PE,Read 0h = No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 1. "RX_OE,Read 0h = No overrun error" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Read 0h = No data in the RX FIFO" "0,1" group.long 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" rgroup.long 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only. This register provides information about the current state of the control lines from the modem. data set. or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loopback mode it is equivalent to" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loopback mode it is equivalent to" "0,1" bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input (or" "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input (or" "0,1" bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control. Notes: Trigger levels from 0 to 60 bytes are available with a granularity of 4. (Trigger level = 4.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x4 "UART_SPR,Scratchpad register This read/write register does not control the module. It is a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes." line.long 0x4 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and ). The value of MDR1[2:0] must not be changed.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only" "0,1" bitfld.long 0x4 5. "SCT,Store and control the transmission." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1" bitfld.long 0x4 3. "IR_SLEEP,0h = IrDA/CIR sleep mode disabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,0h = UART 16x mode" "0,1,2,3,4,5,6,7" line.long 0x8 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only. [0] describes the status of the interrupt in UART_IIR[5]. The IRTX_UNDERRUN bit should be read after an UART_IIR[5] TX_STATUS_IT interrupt. The bits [2:1] of this register set the.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate function for" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IrDA transmission status interrupt. When the UART_IIR[5] interrupt occurs the meaning of the interrupt is:" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register IrDA modes only. Reading this register effectively reads frame status information from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Read 1h = Overrun error in RX FIFO when frame at top of RX FIFO was received" "0,1" bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Read 1h = Frame-length too long error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Read 1h = Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 1. "CRC_ERROR,Read 1h = CRC error in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED" "0,1" group.long 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "UART_TXFLH,Transmit frame length register high IrDA modes only. The and registers hold the 13-bit transmit frame length (expressed in bytes). holds the LSBs and holds the MSBs. The frame length value is used if the frame length method of frame closing is.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "UART_RXFLL,Received frame length register low IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and registers to be n +.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high IrDA modes only. The and registers hold the 12-bit receive maximum frame length. holds the LSBs and holds the MSBs. If the intended maximum receive frame length is n bytes. program the and to be n + 3 in SIR.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the and registers (these registers do not physically exist). The LSBs are read from and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register IrDA modes only. The [6] bit selects whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR mode. If only one start flag is required. this is always 0xC0. If n start flags are.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing." "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select" "0,1" hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register UART autobauding mode only. This status register returns the speed. the number of bits by characters. and the type of the parity in UART autobauding mode. In autobauding mode. the input frequency of the UART.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 6.--7. "PARITY_TYPE,Read 0h = No parity identified" "0,1,2,3" newline bitfld.long 0x0 5. "BIT_BY_CHAR,Read 0h = 7-bit character identified" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified" group.long 0x3C++0xF line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 5. "DIS_IR_RX,0h = Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting" "0,1" bitfld.long 0x0 3. "SEND_SIP,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When" "0,1" bitfld.long 0x0 1. "ABORT_EN,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty and" "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" line.long 0x4 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the UART_IIR register. the [1] bit.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" bitfld.long 0x4 7. "RX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger RX level" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1,0h = Disables the granularity of 1 for trigger TX level" "0,1" bitfld.long 0x4 5. "DSR_IT,0h = Disables DSR* interrupt" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE,0h = Disables the wake-up interrupt and clears SSR[1]" "0,1" bitfld.long 0x4 3. "TX_EMPTY_CTL_IT,0h = Normal mode for THR interrupt" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if the" "0,1,2,3" bitfld.long 0x4 0. "DMA_MODE_CTL,0h = The DMA_MODE is set with" "0,1" line.long 0x8 "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST,0h = The DMA counter will not be reset if the corresponding FIFO is reset (through" "0,1" rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS,Read 0h = No falling edge event on RX CTS* and DSR*" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL,Read 0h = TX FIFO is not full." "0,1" line.long 0xC "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only. In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit. Value set into this register must account for the BOF character; therefore. to send only one BOF with no.." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification." rgroup.long 0x50++0x3 line.long 0x0 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned." bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module" group.long 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface. When the feature is enabled. the clock is gated off until an OCP command for this.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Wake-up feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal reset monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system. An event is any activity in the logic that could cause an interrupt and/or an activity that would require.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,0h = Event is not allowed to wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,0h = Event is not allowed to wake up the system." "0,1" line.long 0x4 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple). Examples for CFPS values:" rgroup.long 0x64++0x7 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x4 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" group.long 0x6C++0xB line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS,0h = Enables the RHR interrupt." "0,1" bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "0,1" line.long 0x4 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" line.long 0x8 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,RESERVED" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used." rgroup.long 0x78++0x7 line.long 0x0 "UART_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "UART_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "UART_MDR3,Mode definition register 3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0h = TX: RTS=0 RX: RTS=1. 1h = TX: RTS=1 RX: RTS=0" "0,1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1" bitfld.long 0x0 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies." "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation." "0,1" line.long 0x4 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not. 64-tx_trigger_level will be used without modifying the value of this register." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" rbitfld.long 0x4 6.--7. "RESERVED" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" line.long 0x8 "UART_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1" bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7" line.long 0xC "UART_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1" bitfld.long 0xC 1. "RHR_OVERRUN" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "UART_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED" rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1h = to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" bitfld.long 0x10 2. "TX_RST,Writing 1h = resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing 1h = resets the receiver" "0,1" bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1" line.long 0x14 "UART_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]" line.long 0x1C "UART_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]" line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED" bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1" rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "UART_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit" group.long 0xA4++0xF line.long 0x0 "UART_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit" line.long 0x4 "UART_MAR,Multidrop Address Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "UART_MMR,Multidrop Mask Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "UART_MBR,Multidrop Broadcast Address Register" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "WKUP_VTM0_ECCAGGR_CFG" base ad:0x42810000 rgroup.long 0x0++0x3 line.long 0x0 "WKUP_VTM_REV,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "WKUP_VTM_VECTOR,ECC Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED" newline bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "WKUP_VTM_STAT,Misc Status" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "WKUP_VTM_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets. Offset = 10h + (y * 4h); where y = 0h to 7h" hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "WKUP_VTM_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long 0x0 1.--31. 1. "RESERVED" newline bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "WKUP_VTM_SEC_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 4.--31. 1. "RESERVED" newline bitfld.long 0x4 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "WKUP_VTM_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED" newline bitfld.long 0x0 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "WKUP_VTM_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED" newline bitfld.long 0x0 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "WKUP_VTM_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt.." hexmask.long 0x0 1.--31. 1. "RESERVED" newline bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "WKUP_VTM_DED_STATUS_REG0,Interrupt Status Register 0" hexmask.long 0x4 4.--31. 1. "RESERVED" newline bitfld.long 0x4 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1" newline bitfld.long 0x4 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x4 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "WKUP_VTM_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED" newline bitfld.long 0x0 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "WKUP_VTM_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED" newline bitfld.long 0x0 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1" newline bitfld.long 0x0 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1" newline bitfld.long 0x0 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" group.long 0x200++0xF line.long 0x0 "WKUP_VTM_AGGR_ENABLE_SET,AGGR interrupt enable set Register" hexmask.long 0x0 2.--31. 1. "RESERVED" newline bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "WKUP_VTM_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register" hexmask.long 0x4 2.--31. 1. "RESERVED" newline bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "WKUP_VTM_AGGR_STATUS_SET,AGGR interrupt status set Register" hexmask.long 0x8 4.--31. 1. "RESERVED" newline bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "WKUP_VTM_AGGR_STATUS_CLR,AGGR interrupt status clear Register" hexmask.long 0xC 4.--31. 1. "RESERVED" newline bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "WKUP_VTM0_MMR_VBUSP_CFG1" base ad:0x42040000 rgroup.long 0x0++0x7 line.long 0x0 "WKUP_VTM_PID,VTM Peripheral Identification Register" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL revision number" newline bitfld.long 0x0 8.--10. "X_MAJOR,Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision number" line.long 0x4 "WKUP_VTM_DEVINFO_PWR0,Device specific voltage domain and temp sensor information register." hexmask.long.word 0x4 20.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--19. 1. "VTM_VD_MAP,Core voltage domain cVD global mapping 4-bit code in the context of this SoC." bitfld.long 0x4 13.--15. "RESERVED" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "VD_RTC,RTC voltage domain presence." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "RESERVED" hexmask.long.byte 0x4 4.--7. 1. "TMPSENS_CT,Number of temperature sensors associated with this VTM." hexmask.long.byte 0x4 0.--3. 1. "CVD_CT,Number of core voltage domains in device." group.long 0x100++0x7 line.long 0x0 "WKUP_VTM_VD_DEVINFO_j,Voltage domain a information register. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary. Offset = 100h.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED" bitfld.long 0x0 12. "AVS0_SUP,Indicates VD0 AVS class0 support." "0,1" hexmask.long.byte 0x0 8.--11. 1. "VD_MAP,Indicates the core voltage domain mapping of VTM VD." hexmask.long.byte 0x0 0.--7. 1. "RESERVED" line.long 0x4 "WKUP_VTM_VD_OPPVID_j,Voltage domain a VID actual code used as reference by Firmware to set the various voltage domain supply voltages. Reset defaults are sourced from efuse for each OPP. The default reset values will not be necessarily overwritten. The.." hexmask.long.byte 0x4 24.--31. 1. "OPP_3,OPP 3 default VID." hexmask.long.byte 0x4 16.--23. 1. "OPP_2,OPP 2 default VID." hexmask.long.byte 0x4 8.--15. 1. "OPP_1,OPP 1 default VID." hexmask.long.byte 0x4 0.--7. 1. "OPP_0,OPP 0 default VID." rgroup.long 0x108++0x3 line.long 0x0 "WKUP_VTM_VD_EVT_STAT_j,Voltage domain a event and control status register. Offset = 108h + (j * 20h); where j = 0h to 7h" hexmask.long 0x0 3.--31. 1. "RESERVED" bitfld.long 0x0 2. "LT_TH0_ALERT,This bit reflects the status of the TH0 undertemp alert resulting from the AND of all the similar alerts produced by the temp sensors selected by VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel." "0,1" bitfld.long 0x0 1. "GT_TH2_ALERT,This bit reflects the status of the merged temperature alert resulting from the combination of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel." "0,1" bitfld.long 0x0 0. "GT_TH1_ALERT,This bit reflects the status of the merged temperature alert resulting from the OR of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel." "0,1" group.long 0x10C++0x7 line.long 0x0 "WKUP_VTM_VD_EVT_SEL_SET_j,Voltage domain a event select and control set register. NOTE: This MMR and the companion MMR VTM_VD[a]_EVT_SEL_CLR are linked. which means that they are in fact a single common MMR. with 2 different write addresses/mechanisms..." hexmask.long.byte 0x0 24.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--23. 1. "TSENS_EVT_SEL,In this field we select which of the event contributions of the" hexmask.long.word 0x0 0.--15. 1. "RESERVED" line.long 0x4 "WKUP_VTM_VD_EVT_SEL_CLR_j,Voltage domain a event select and control clear register. NOTE: This MMR and the companion MMR VTM_VD[a]_EVT_SEL_SET are linked. which means that they are in fact a single common MMR. with 2 different write addresses/mechanisms..." hexmask.long.byte 0x4 24.--31. 1. "RESERVED" hexmask.long.byte 0x4 16.--23. 1. "TSENS_EVT_SEL,In this field we select which of the event contributions of the 8-maximum possible temp-monitors controlled by this VTM will contribute to generate the merged event/alerts of this VD." hexmask.long.word 0x4 0.--15. 1. "RESERVED" group.long 0x204++0x7 line.long 0x0 "WKUP_VTM_GT_TH1_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR. are fully linked for write operation. but partially linked for reads. which means that they are in.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt pending bit set for gt_th1_int from VD[7:0]." line.long 0x4 "WKUP_VTM_GT_TH1_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt GT_TH1 per voltage domain. NOTE: This MMR and the companion MMR. are fully linked for write operation. but partially linked for reads. which means that they are in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt masked pending bit for gt_th1_int from VD[7:0]." group.long 0x214++0x7 line.long 0x0 "WKUP_VTM_GT_TH1_INT_EN_SET,Enable set MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR. are linked. which means that they are in fact a single common MMR. with 2 different write addresses/mechanisms. and thus the.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th1_int from VD[7:0]." line.long 0x4 "WKUP_VTM_GT_TH1_INT_EN_CLR,Enable clear MMR for interrupt GT_TH1 for each voltage domain. NOTE: This MMR and the companion MMR. are linked. which means that they are in fact a single common MMR. with 2 different write addresses/mechanisms. and thus the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th1_int from VD[7:0]." group.long 0x224++0x7 line.long 0x0 "WKUP_VTM_GT_TH2_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR. are fully linked for write operation. but partially linked for reads. which means that they are in.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt pending bit set for gt_th2_int from VD[7:0]." line.long 0x4 "WKUP_VTM_GT_TH2_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt GT_TH2 per voltage domain. NOTE: This MMR and the companion MMR. are fully linked for write operation. but partially linked for reads. which means that they are in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enabled pending bit for gt_th2_int from VD[7:0]." group.long 0x234++0x7 line.long 0x0 "WKUP_VTM_GT_TH2_INT_EN_SET,Enable set MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR. are linked. which means that they are in fact a single common MMR. with 2 different write addresses/mechanisms. and thus the.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th2_int from VD[7:0]." line.long 0x4 "WKUP_VTM_GT_TH2_INT_EN_CLR,Enable clear MMR for interrupt GT_TH2 for each voltage domain. NOTE: This MMR and the companion MMR. are linked. which means that they are in fact a single common MMR. with 2 different write addresses/mechanisms. and thus the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th2_int from VD[7:0]." group.long 0x244++0x7 line.long 0x0 "WKUP_VTM_LT_TH0_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR. are fully linked for write operation. but partially linked for reads. which means that they are in.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt pending bit set for lt_th0_int from VD[7:0]." line.long 0x4 "WKUP_VTM_LT_TH0_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt LT_TH0 per voltage domain. NOTE: This MMR and the companion MMR. are fully linked for write operation. but partially linked for reads. which means that they are in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enabled pending status bit for lt_th0_int from VD[7:0]." group.long 0x254++0x7 line.long 0x0 "WKUP_VTM_LT_TH0_INT_EN_SET,Enable set MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR. are linked. which means that they are in fact a single common MMR. with 2 different write addresses/mechanisms. and thus the.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" hexmask.long.byte 0x0 0.--7. 1. "INT_VD,Interrupt enable bit for lt_th0_int from VD[7:0]." line.long 0x4 "WKUP_VTM_LT_TH0_INT_EN_CLR,Enable clear MMR for interrupt LT_TH0 for each voltage domain. NOTE: This MMR and the companion MMR. are linked. which means that they are in fact a single common MMR. with 2 different write addresses/mechanisms. and thus the.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" hexmask.long.byte 0x4 0.--7. 1. "INT_VD,Interrupt enable bit for lt_th0_int from VD[7:0]." group.long 0x300++0x3 line.long 0x0 "WKUP_VTM_TMPSENS_CTRL_j,Temperature Sensor Band-gap control register for sensor a. Offset = 300h + (j * 20h); where j = 0h to 7h" hexmask.long.tbyte 0x0 11.--31. 1. "RESERVED" bitfld.long 0x0 10. "LT_TH0_EN,Enable under-threshold0 event." "0,1" bitfld.long 0x0 9. "GT_TH2_EN,Enable over-threshold2 event." "0,1" bitfld.long 0x0 8. "GT_TH1_EN,Enable over-threshold1 event." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "RESERVED" rgroup.long 0x308++0x3 line.long 0x0 "WKUP_VTM_TMPSENS_STAT_j,Temperature Sensor Band-gap Status register for sensor a. Offset = 308h + (j * 20h); where j = 0h to 7h" hexmask.long.word 0x0 20.--31. 1. "RESERVED" hexmask.long.byte 0x0 16.--19. 1. "VD_MAP,Indicates the core voltage domain placement of the temp sensor." bitfld.long 0x0 15. "MAXT_OUTRG_ALERT,This bit will be driven to a level 1 for a given temperature monitor if it has its corresponding bit maxt_outrg_en = 1 and the temperature reading is reporting to be outside the max temperature supported temp &gt; programmed value." "0,1" bitfld.long 0x0 14. "LT_TH0_ALERT,This field reflects the status of the lt_th0_alert comparator result." "0,1" newline bitfld.long 0x0 13. "GT_TH2_ALERT,This field reflects the status of the gt_th2_alert comparator result." "0,1" bitfld.long 0x0 12. "GT_TH1_ALERT,This field reflects the status of the gt_th1_alert comparator result." "0,1" bitfld.long 0x0 11. "EOC_FC_UPDATE,First time end of conversion." "0,1" bitfld.long 0x0 10. "DATA_VALID,Data_valid signal value from sensor: ADC End of Conversion." "0,1" newline hexmask.long.word 0x0 0.--9. 1. "DATA_OUT,Data_out signal value from sensor: Temperature data from the ADC in monitor." group.long 0x30C++0x7 line.long 0x0 "WKUP_VTM_TMPSENS_TH_j,Temperature Sensor Band-gap Threshold register for sensor a. Offset = 30Ch + (j * 20h); where j = 0h to 7h" hexmask.long.byte 0x0 26.--31. 1. "RESERVED" hexmask.long.word 0x0 16.--25. 1. "TH1_VAL,Threshold point-1 thpt1 temp-value." hexmask.long.byte 0x0 10.--15. 1. "RESERVED" hexmask.long.word 0x0 0.--9. 1. "TH0_VAL,Threshold point-0 thpt0 temp-value." line.long 0x4 "WKUP_VTM_TMPSENS_TH2_j,Temperature Sensor Band-gap Threshold register 2 for sensor a. Offset = 310h + (j * 20h); where j = 0h to 7h" hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--9. 1. "TH2_VAL,Threshold point-2 thpt2 temp-value." tree.end tree "WKUP_VTM0_MMR_VBUSP_CFG2" base ad:0x42040000 group.long 0x10008++0xB line.long 0x0 "WKUP_VTM_CLK_CTRL,VTM clock related control MMR. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary. The e-fuse value is.." bitfld.long 0x0 31. "TSENS_CLK_SEL,Temperature sensor clock source selector." "0,1" hexmask.long 0x0 5.--30. 1. "RESERVED" hexmask.long.byte 0x0 0.--4. 1. "TSENS_CLK_DIV,Temperature sensor clock source divider selector." line.long 0x4 "WKUP_VTM_MISC_CTRL,VTM miscellaneous control bits." hexmask.long 0x4 1.--31. 1. "RESERVED" bitfld.long 0x4 0. "ANY_MAXT_OUTRG_ALERT_EN,This bit when enabled will cause the VTM's output therm_maxtemp_outrange_alert to be driven high if any of the sources for the maxt_outrg_alert is set high." "0,1" line.long 0x8 "WKUP_VTM_MISC_CTRL2,VTM miscellaneous control bits." hexmask.long.byte 0x8 26.--31. 1. "RESERVED" hexmask.long.word 0x8 16.--25. 1. "MAXT_OUTRG_ALERT_THR0,This defines the global max temperature out of range safe sample value." hexmask.long.byte 0x8 10.--15. 1. "RESERVED" hexmask.long.word 0x8 0.--9. 1. "MAXT_OUTRG_ALERT_THR,This defines the global max temperature out of range sample value." group.long 0x10020++0x3 line.long 0x0 "WKUP_VTM_SAMPLE_CTRL,VTM sample related control MMR. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary. The e-fuse value is.." hexmask.long.word 0x0 16.--31. 1. "RESERVED" hexmask.long.word 0x0 0.--15. 1. "SAMPLE_PER_CNT,Temperature sensor sample period count selector." group.long 0x10300++0x7 line.long 0x0 "WKUP_VTM_TMPSENS_CTRL_j,Temperature Sensor Band-gap control register for sensor a. Offset = 300h + (j * 20h); where j = 0h to 7h" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" bitfld.long 0x0 11. "MAXT_OUTRG_EN,Enable out-of-range event." "0,1" hexmask.long.byte 0x0 7.--10. 1. "RESERVED" bitfld.long 0x0 6. "CLRZ,Temp-Monitor control:" "0,1" newline bitfld.long 0x0 5. "SOC,Temp-Monitor control: ADC Start of Conversion." "0,1" bitfld.long 0x0 4. "CONT,Temp-Monitor control: ADC Continuous mode." "0,1" hexmask.long.byte 0x0 0.--3. 1. "RESERVED" line.long 0x4 "WKUP_VTM_TMPSENS_TRIM_j,Temperature Sensor Band-gap trim values register for sensor a. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if.." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED" hexmask.long.byte 0x4 8.--13. 1. "TRIMO,Trim offset bits in the temp sensor." bitfld.long 0x4 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "TRIMG,Trim gain bits in the temp sensor." tree.end tree.end newline AUTOINDENT.OFF